Semiconductor structure and preparation method of semiconductor structure

Abstract

The embodiment of the invention discloses a semiconductor structure and a preparation method of the semiconductor structure. The semiconductor structure comprises a substrate; the surface of the substrate comprises a chip unit; a first oxide layer; the first oxide layer is located on one side of the substrate; an oxygen-doped polycrystalline silicon layer; the oxygen-doped polycrystalline silicon layer is positioned on one side, far away from the substrate, of the first oxide layer; the projection area of the oxygen-doped polycrystalline silicon layer on the substrate is smaller than that of the first oxide layer on the substrate; a silicon nitride layer; the silicon nitride layer is located on the side, away from the substrate, of the oxygen-doped polycrystalline silicon layer; the silicon nitride layer covers the oxygen-doped polycrystalline silicon layer; a second oxide layer; the second oxide layer is located on one side of the silicon nitride layer away from the substrate; the second oxide layer covers the silicon nitride layer. According to the technical scheme, the silicon nitride layer and the second oxide layer are arranged on the side, away from the substrate, of the oxygen-doped polycrystalline silicon layer, the silicon nitride layer covers the oxygen-doped polycrystalline silicon layer, the second oxide layer covers the silicon nitride layer, failure of the oxygen-doped polycrystalline silicon layer is avoided, and the yield and reliability of the semiconductor structure are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Art

[0002] Conventional semiconductor structures are prone to voltage drops because metal, solder paste, copper sheets or molybdenum sheets come into contact with oxygen-doped polysilicon, causing the oxygen-doped polysilicon to fail. Therefore, the oxygen-doped polysilicon needs to be protected.

[0003] The existing technology usually uses a passivation layer to protect oxygen-doped polysilicon, and the conventional passivation layer is usually mainly an oxide layer. However, the oxide layer itself contains sodium ions and potassium ions, and has high requirements for packaging, which will result in a decrease in yield and reliability failure. Summary of the invention

[0004] The present invention provides a semiconductor structure and a method for preparing the semiconductor structure, so as to avoid failure of an oxygen-doped polysilicon layer and improve the yield and reliability of the semiconductor structure.

[0005] According to one aspect of the present invention, a semiconductor structure is provided, the semiconductor structure comprising: a substrate; a surface of the substrate comprising a chip unit;

[0006] A first oxide layer; the first oxide layer is located on one side of the substrate;

[0007] an oxygen-doped polysilicon layer; the oxygen-doped polysilicon layer is located on a side of the first oxide layer away from the substrate; a projected area of ​​the oxygen-doped polysilicon layer on the substrate is smaller than a projected area of ​​the first oxide layer on the substrate;

[0008] Silicon nitride layer; the silicon nitride layer is located on a side of the oxygen-doped polysilicon layer away from the substrate; the silicon nitride layer covers the oxygen-doped polysilicon layer;

[0009] The second oxide layer is located on a side of the silicon nitride layer away from the substrate; the second oxide layer covers the silicon nitride layer.

[0010] Optionally, the chip unit includes a PN junction;

[0011] The first oxide layer is formed by a low pressure chemical vapor deposition process;

[0012] The thickness of the first oxide layer is greater than or equal to 5000 angstroms and less than or equal to 6000 angstroms.

[0013] Optionally, the oxygen-doped polysilicon layer is formed by decomposing silane;

[0014] The thickness of the oxygen-doped polysilicon layer is greater than or equal to 5000 angstroms and less than or equal to 12000 angstroms.

[0015] Optionally, the silicon nitride layer is formed by reacting silicon dichloride and ammonia;

[0016] The thickness of the silicon nitride layer is greater than or equal to 1000 angstroms and less than or equal to 3000 angstroms.

[0017] Optionally, the thickness of the second oxide layer is greater than the thickness of the silicon nitride layer;

[0018] The temperature required to form the second oxide layer is lower than the temperature required to form the first oxide layer.

[0019] Optionally, the silicon nitride layer and the second oxide layer are both insulating layers; and the oxygen-doped polysilicon layer is a semi-insulating layer.

[0020] Optionally, the resistance of the semi-insulating layer is greater than that of the semiconductor and less than that of the insulator; the dielectric constant of the semi-insulating layer is greater than that of the insulator and less than that of the semiconductor.

[0021] Optionally, the semiconductor structure further comprises: a metal layer;

[0022] The metal layer is located on a side of the second oxide layer away from the substrate;

[0023] The metal layer covers a portion of the second oxide layer.

[0024] Optionally, the metal layer includes at least four metal structures; the at least four metal structures include aluminum, titanium, nickel or silver;

[0025] At least four layers of metal structures are deposited in sequence according to a preset order.

[0026] According to another aspect of the present invention, a method for preparing a semiconductor structure is provided, the method for preparing a semiconductor structure comprising:

[0027] Providing a substrate; a surface of the substrate includes a chip unit;

[0028] forming a first oxide layer on one side of the substrate;

[0029] forming an oxygen-doped polysilicon layer on a side of the first oxide layer away from the substrate; wherein a projected area of ​​the oxygen-doped polysilicon layer on the substrate is smaller than a projected area of ​​the first oxide layer on the substrate;

[0030] forming a silicon nitride layer on a side of the oxygen-doped polysilicon layer away from the substrate; the silicon nitride layer covers the oxygen-doped polysilicon layer;

[0031] A second oxide layer is formed on a side of the silicon nitride layer away from the substrate; the second oxide layer covers the silicon nitride layer.

[0032] The technical solution of the embodiment of the present invention is as follows: a first oxide layer is arranged on one side of a substrate, an oxygen-doped polysilicon layer is arranged on a side of the first oxide layer away from the substrate, and a projected area of ​​the oxygen-doped polysilicon layer on the substrate is smaller than a projected area of ​​the first oxide layer on the substrate, a silicon nitride layer is arranged on a side of the oxygen-doped polysilicon layer away from the substrate, and the silicon nitride layer covers the oxygen-doped polysilicon layer, and a second oxide layer is arranged on a side of the silicon nitride layer away from the substrate, and the second oxide layer covers the silicon nitride layer, thereby forming a high-reliability passivation layer to protect the oxygen-doped polysilicon layer, prevent the oxygen-doped polysilicon layer from contacting metal, solder paste, copper sheet or molybdenum sheet and causing failure, and improve the yield and reliability of the semiconductor structure.

[0033] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 is a cross-sectional schematic diagram of a semiconductor structure provided according to an embodiment of the present invention;

[0036] Figure 2 The present invention provides a flow chart of a method for preparing a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0038] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0039] Figure 1 is a cross-sectional schematic diagram of a semiconductor structure provided according to an embodiment of the present invention. Figure 1 As shown, the semiconductor structure includes: a substrate 10; the surface of the substrate 10 includes a chip unit; a first oxide layer 20; the first oxide layer 20 is located on one side of the substrate 10; an oxygen-doped polysilicon layer 30; the oxygen-doped polysilicon layer 30 is located on the side of the first oxide layer 20 away from the substrate 10; the projected area of ​​the oxygen-doped polysilicon layer 30 on the substrate 10 is smaller than the projected area of ​​the first oxide layer 20 on the substrate 10; a silicon nitride layer 40; the silicon nitride layer 40 is located on the side of the oxygen-doped polysilicon layer 30 away from the substrate 10; the silicon nitride layer 40 covers the oxygen-doped polysilicon layer 30; a second oxide layer 50; the second oxide layer 50 is located on the side of the silicon nitride layer 40 away from the substrate 10; the second oxide layer 50 covers the silicon nitride layer 40.

[0040] In an embodiment of the present invention, the material of the substrate 10 includes but is not limited to silicon, silicon carbide or gallium nitride. Exemplarily, in an embodiment of the present invention, the substrate 10 is a silicon substrate. The thickness of the substrate 10 may be 150 microns to 500 microns. The surface of the substrate 10 includes a chip unit. The chip unit may be a PN junction. The substrate 10 in an embodiment of the present invention includes a first conductive type structure 101 and a second conductive type structure 102. When the first conductive type is N-type and the second conductive type is P-type, the first conductive type structure 101 is an N-type substrate and the second conductive type structure 102 is a P-type structure. When the first conductive type is P-type and the second conductive type is N-type, the first conductive type structure 101 is a P-type substrate and the second conductive type structure 102 is an N-type structure. Exemplarily, an N-type silicon wafer with a resistivity of 2Ω*cm-10Ω*cm is selected as the first conductive type structure 101, i.e., an N-type substrate. An oxide layer is grown on both sides of an N-type substrate, and the oxide layer may be a silicon dioxide layer. The oxide layer is patterned to form a boron-doped pattern area on the surface of the N-type substrate. Boron ions are injected into the boron-doped pattern area by an ion implantation process to form a P-type structure. The P-type structure forms a PN junction with the N-type substrate. The oxide layer is etched away by a dry etching process to prevent the formed PN junction from being contaminated by the oxide layer. Similarly, exemplarily, a P-type silicon wafer with a resistivity of 2Ω*cm-10Ω*cm is selected as the first conductive type structure 101, i.e., a P-type substrate. An oxide layer is grown on both sides of a P-type substrate, and the oxide layer is patterned to form a phosphorus-doped pattern area on the surface of the P-type substrate. Phosphorus ions are injected into the phosphorus-doped pattern area by an ion implantation process to form an N-type structure. The N-type structure forms a PN junction with the P-type substrate. The oxide layer is etched away by a dry etching process.

[0041] In the embodiment of the present invention, the first conductivity type is N type and the second conductivity type is P type. An N type substrate is selected and a P type structure is formed on both sides of the N type substrate to improve the utilization rate of the substrate. It should be noted that a P type structure can also be formed on one side of the N type substrate, such as Figure 1 As shown. Ethyl silicate is deposited on the side of the N-type substrate where the P-type structure is formed to form a first oxide layer 20. Ethyl silicate can undergo hydrolysis and polycondensation under appropriate conditions, thereby achieving deposition. Factors affecting the deposition of ethyl silicate include catalysts, temperature, and solvents.

[0042] An oxygen-doped polysilicon layer 30 is disposed on a side of the first oxide layer 20 away from the substrate 10. Figure 1The substrate 10 points to the Y direction of the first oxide layer 20. In the X direction perpendicular to the substrate 10 and pointing to the first oxide layer 20, the size of the first oxide layer 20 covering the substrate 10 is 20 microns to 50 microns. The size of the oxygen-doped polysilicon layer 30 covering the first oxide layer 20 is 10 microns to 25 microns, that is, the size of the first oxide layer 20 covering the substrate 10 is larger than the size of the oxygen-doped polysilicon layer 30 covering the substrate 10.

[0043] A silicon nitride layer 40 is disposed on the side of the oxygen-doped polysilicon layer 30 away from the substrate 10. The silicon nitride layer 40 covers the oxygen-doped polysilicon layer 30 on the side away from the substrate 10 to protect the oxygen-doped polysilicon layer 30. In the X direction perpendicular to the substrate 10 and pointing to the first oxide layer 20, the size of the silicon nitride layer 40 covering the oxygen-doped polysilicon layer 30 is 20 microns to 50 microns.

[0044] A second oxide layer 50 is disposed on the side of the silicon nitride layer 40 away from the substrate 10. In the X direction perpendicular to the substrate 10 and pointing to the first oxide layer 20, the size of the second oxide layer 50 covering the silicon nitride layer 40 is 20 microns to 50 microns. The second oxide layer 50 covers the silicon nitride layer 40, and the silicon nitride layer 40 covers the oxygen-doped polysilicon layer 30, thereby protecting the oxygen-doped polysilicon layer 30, preventing the oxygen-doped polysilicon layer 30 from contacting metal, solder paste, copper sheet or molybdenum sheet and causing failure, thereby improving the yield and reliability of the semiconductor structure.

[0045] The technical solution of the embodiment of the present invention is as follows: a first oxide layer is arranged on one side of a substrate, an oxygen-doped polysilicon layer is arranged on a side of the first oxide layer away from the substrate, and a projected area of ​​the oxygen-doped polysilicon layer on the substrate is smaller than a projected area of ​​the first oxide layer on the substrate, a silicon nitride layer is arranged on a side of the oxygen-doped polysilicon layer away from the substrate, and the silicon nitride layer covers the oxygen-doped polysilicon layer, and a second oxide layer is arranged on a side of the silicon nitride layer away from the substrate, and the second oxide layer covers the silicon nitride layer, thereby forming a high-reliability passivation layer to protect the oxygen-doped polysilicon layer, prevent the oxygen-doped polysilicon layer from contacting metal, solder paste, copper sheet or molybdenum sheet and causing failure, and improve the yield and reliability of the semiconductor structure.

[0046] Based on the technical solution of the above invention embodiment, Figure 1 Optionally, the chip unit includes a PN junction; the first oxide layer 20 is formed by a low pressure chemical vapor deposition process; the thickness of the first oxide layer 20 is greater than or equal to 5000 angstroms and less than or equal to 6000 angstroms.

[0047] In an embodiment of the present invention, a P-type semiconductor and an N-type semiconductor are fabricated on the same semiconductor substrate by processes such as epitaxy, dopant diffusion or ion implantation, and the boundary or interface between the P-type semiconductor material and the N-type semiconductor material is a PN junction. The formed PN junction has unidirectional conductivity. TEOS is deposited on one side of the substrate 10 by a low-pressure chemical vapor deposition process to form a high-density oxide layer, i.e., a first oxide layer 20. When depositing ethyl silicate, 150 mL of tetraethoxysilane (Si(OC2H5)4) and 150 mL of oxygen can be prepared, and the reaction is carried out for 30 min-40 min under a pressure of 100 mTorr-300 mTorr and a temperature of 650°C-750°C to form a first oxide layer 20 with a thickness of 5000 angstroms to 6000 angstroms. The first oxide layer 20 formed by the low-pressure chemical vapor deposition process has the characteristics of high purity and good quality, and is suitable for occasions with high requirements for film quality, such as the preparation of semiconductor devices.

[0048] Based on the technical solution of the above invention embodiment, Figure 1 Optionally, the oxygen-doped polysilicon layer 30 is formed by decomposing silane; the thickness of the oxygen-doped polysilicon layer 30 is greater than or equal to 5000 angstroms and less than or equal to 12000 angstroms.

[0049] In the embodiment of the present invention, when depositing the oxygen-doped polysilicon layer 30, 400 mL of silane (SiH4) and 75 mL of nitrous oxide (N2O) may be prepared, and the reaction may be carried out for 50 min to 90 min at a pressure of 100 mTorr to 300 mTorr and a temperature of 650° C. to 750° C. to form an oxygen-doped polysilicon layer 30 having a thickness of 5000 angstroms to 12000 angstroms. The oxygen-doped polysilicon layer 30 is photolithographically patterned to cover the PN junction by 10 microns to 25 microns.

[0050] Based on the technical solution of the above invention embodiment, Figure 1 Optionally, the silicon nitride layer 40 is formed by reacting silicon dichloromethane and ammonia; the thickness of the silicon nitride layer 40 is greater than or equal to 1000 angstroms and less than or equal to 3000 angstroms.

[0051] In an embodiment of the present invention, when depositing the silicon nitride layer 40, 75 mL of dichlorosilane (SiH2Cl2) and 400 mL of ammonia (NH3) can be prepared, and the reaction can be carried out for 60 min-100 min under the conditions of a pressure of 100 mTorr-300 mTorr and a temperature of 650°C-750°C to form a silicon nitride layer 40 with a thickness of 1000 angstroms to 3000 angstroms.

[0052] Based on the technical solution of the above invention embodiment, Figure 1Optionally, the thickness of the second oxide layer 50 is greater than the thickness of the silicon nitride layer 40 ; and the temperature required to form the second oxide layer 50 is less than the temperature required to form the first oxide layer 20 .

[0053] In an embodiment of the present invention, the second oxide layer 50 is a low-temperature oxide layer. When depositing the second oxide layer 50, 150 mL of silane (SiH4) and 150 mL of oxygen can be prepared, and the reaction is carried out for 50 min-80 min at a pressure of 100 mTorr-300 mTorr and a temperature of 400 ° C-500 ° C to form a second oxide layer 50 with a thickness of 6000 angstroms to 10000 angstroms. The thickness of the second oxide layer 50 is greater than the thickness of the silicon nitride layer 40, and it is easier to form protection for the oxygen-doped polysilicon layer 30. The second oxide layer 50 is formed by low-temperature oxidation, and the first oxide layer 20 is formed by high-temperature oxidation. The stability of the second oxide layer 50 formed by low-temperature oxidation is higher than that of the first oxide layer 20 formed by high-temperature oxidation, which can prevent the oxygen-doped polysilicon layer 30 from failing.

[0054] Based on the technical solution of the above invention embodiment, Figure 1 Optionally, the silicon nitride layer 40 and the second oxide layer 50 are both insulating layers; and the oxygen-doped polysilicon layer 30 is a semi-insulating layer.

[0055] In an embodiment of the present invention, a silicon nitride layer 40 and a second oxide layer 50 are arranged on the side of the oxygen-doped polysilicon layer 30 away from the substrate 10, the second oxide layer 50 covers the silicon nitride layer 40, the silicon nitride layer 40 covers the oxygen-doped polysilicon layer 30, and the silicon nitride layer 40 and the second oxide layer 50 are both insulating layers, which can prevent metal, solder paste, copper sheet or molybdenum sheet from contacting the oxygen-doped polysilicon layer 30 and causing failure of the semi-insulating polysilicon.

[0056] Based on the technical solution of the above-mentioned embodiment of the invention, optionally, the resistance of the semi-insulating layer is greater than that of the semiconductor and less than that of the insulator; the dielectric constant of the semi-insulating layer is greater than that of the insulator and less than that of the semiconductor.

[0057] In the embodiment of the present invention, the oxygen-doped polysilicon layer 30 is a semi-insulating layer, and the oxygen-doped polysilicon layer 30 includes semi-insulating polysilicon. There is no fixed charge in the semi-insulating polysilicon. Semi-insulating semiconductors are materials that are between insulators and semiconductors in terms of resistance and dielectric constant. They are widely used in the manufacture of electronic devices and semiconductor devices, and can be used as isolation layers, buffer layers, and in the manufacture of other semiconductor devices.

[0058] In the embodiment of the present invention, a high-reliability passivation layer is formed by sequentially depositing a first oxide layer 20, an oxygen-doped polysilicon layer 30, a silicon nitride layer 40, and a second oxide layer 50 on one side of a substrate 10. This can avoid failure of semi-insulating polysilicon caused by contact between metal, solder paste, copper sheet, molybdenum sheet and oxygen-doped polysilicon, thereby improving the yield and reliability of the semiconductor structure.

[0059] Based on the technical solution of the above invention embodiment, Figure 1 Optionally, the semiconductor structure further includes: a metal layer 60 ; the metal layer 60 is located on a side of the second oxide layer 50 away from the substrate 10 ; and the metal layer 60 covers a portion of the second oxide layer 50 .

[0060] In the embodiment of the present invention, metal is deposited on the side of the second oxide layer 50 away from the substrate 10 to form a metal layer 60, and in the X direction perpendicular to the substrate 10 and pointing to the first oxide layer 20, the metal layer 60 covers the second oxide layer 50 to a size of 25 microns to 50 microns.

[0061] Based on the technical solution of the above invention embodiment, Figure 1 Optionally, the metal layer 60 includes at least four metal structures; the at least four metal structures include aluminum, titanium, nickel or silver; and the at least four metal structures are deposited sequentially according to a preset order.

[0062] In the embodiment of the present invention, the preset sequence is a preset sequence of depositing metals. Exemplarily, the metal layer 60 is formed in the order of first depositing aluminum, then depositing titanium, nickel, and finally depositing silver. The thickness of the deposited aluminum is 10,000 angstroms, the thickness of the deposited titanium is 900 angstroms, the thickness of the deposited nickel is 4,500 angstroms, and the thickness of the deposited silver is 10,000 angstroms. Metals of corresponding thicknesses are sequentially deposited in the preset sequence to form the metal layer 60, so as to form a good ohmic contact.

[0063] Figure 2 1 is a flow chart of a method for preparing a semiconductor structure according to an embodiment of the present invention. This embodiment can be applied to preparing a semiconductor structure. The method for preparing a semiconductor structure can be performed by a semiconductor structure preparation device. The semiconductor structure preparation device can be implemented in the form of hardware and / or software. Figure 2 As shown, the method for preparing the semiconductor structure includes:

[0064] S110, providing a substrate; a surface of the substrate includes a chip unit.

[0065] Exemplarily, an N-type silicon wafer with a resistivity of 2Ω*cm-10Ω*cm is selected as the N-type substrate. A P-type structure is formed on one side of the N-type substrate, and the P-type structure forms a PN junction with the N-type substrate.

[0066] S120, forming a first oxide layer on one side of the substrate.

[0067] Specifically, a first oxide layer is formed on one side of the substrate by a low-pressure chemical vapor deposition process. Exemplarily, ethyl silicate is deposited on the side of the N-type substrate where a P-type structure is formed to form a first oxide layer. The specific process may be: prepare 150 mL of tetraethoxysilane (Si(OC2H5)4) and 150 mL of oxygen, react for 30 min-40 min at a pressure of 100 mTorr-300 mTorr and a temperature of 650°C-750°C to form a first oxide layer with a thickness of 5000 angstroms to 6000 angstroms. The first oxide layer formed by the low-pressure chemical vapor deposition process has the characteristics of high purity and good quality.

[0068] S130, forming an oxygen-doped polysilicon layer on a side of the first oxide layer away from the substrate; wherein a projected area of ​​the oxygen-doped polysilicon layer on the substrate is smaller than a projected area of ​​the first oxide layer on the substrate.

[0069] Specifically, the oxygen-doped polysilicon layer is formed by decomposing silane. Exemplarily, when depositing the oxygen-doped polysilicon layer, the specific process can be: prepare 400mL of silane (SiH4) and 75mL of nitrous oxide (N2O), react for 50min-90min under the conditions of pressure of 100mTorr-300mTorr and temperature of 650℃-750℃, and form an oxygen-doped polysilicon layer with a thickness of 5000 angstroms to 12000 angstroms.

[0070] S140, forming a silicon nitride layer on a side of the oxygen-doped polysilicon layer away from the substrate; the silicon nitride layer covers the oxygen-doped polysilicon layer.

[0071] Specifically, the silicon nitride layer is formed by reacting dichlorosilane and ammonia. Exemplarily, when depositing the silicon nitride layer, the specific process may be: prepare 75 mL of dichlorosilane and 400 mL of ammonia, react for 60 min to 100 min at a pressure of 100 mTorr to 300 mTorr and a temperature of 650° C. to 750° C., and form a silicon nitride layer with a thickness of 1000 angstroms to 3000 angstroms.

[0072] S150, forming a second oxide layer on a side of the silicon nitride layer away from the substrate; the second oxide layer covers the silicon nitride layer.

[0073] Specifically, the second oxide layer is formed by low temperature oxidation. When depositing the second oxide layer, the specific process can be: prepare 150mL of silane (SiH4) and 150mL of oxygen, react for 50min-80min under the conditions of pressure of 100mTorr-300mTorr and temperature of 400℃-500℃, and form a second oxide layer with a thickness of 6000 angstroms to 10000 angstroms. The thickness of the formed second oxide layer is greater than the thickness of the silicon nitride layer, and it is easier to form protection for the oxygen-doped polysilicon layer.

[0074] After forming the second oxide layer, the process also includes: forming a metal layer in the order of first depositing aluminum, then titanium, nickel, and finally silver. After forming the metal layer, the alloy is formed by reacting for 10-30 minutes at a furnace temperature of 400-530°C. Then, the chip probe station test, blue film pasting, and knife wheel scribing are carried out, and finally the packaging and delivery are completed to complete the preparation and application of the semiconductor structure.

[0075] The technical solution of the embodiment of the present invention forms a first oxide layer on one side of the substrate, forms an oxygen-doped polysilicon layer on the side of the first oxide layer away from the substrate, and the projected area of ​​the oxygen-doped polysilicon layer on the substrate is smaller than the projected area of ​​the first oxide layer on the substrate, forms a silicon nitride layer on the side of the oxygen-doped polysilicon layer away from the substrate, and the silicon nitride layer covers the oxygen-doped polysilicon layer, forms a second oxide layer on the side of the silicon nitride layer away from the substrate, and the second oxide layer covers the silicon nitride layer, thereby forming a high-reliability passivation layer to protect the oxygen-doped polysilicon layer, prevent the oxygen-doped polysilicon layer from contacting metal, solder paste, copper sheet or molybdenum sheet and causing failure, and improve the yield and reliability of the formed semiconductor structure.

[0076] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0077] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: A substrate; a surface of the substrate includes a chip unit; A first oxide layer; the first oxide layer is located on one side of the substrate; an oxygen-doped polysilicon layer; the oxygen-doped polysilicon layer is located on a side of the first oxide layer away from the substrate; a projected area of ​​the oxygen-doped polysilicon layer on the substrate is smaller than a projected area of ​​the first oxide layer on the substrate; A silicon nitride layer; the silicon nitride layer is located on a side of the oxygen-doped polysilicon layer away from the substrate; the silicon nitride layer covers the oxygen-doped polysilicon layer; a second oxide layer; the second oxide layer is located on a side of the silicon nitride layer away from the substrate; and the second oxide layer covers the silicon nitride layer.

2. The semiconductor structure according to claim 1, characterized in that: The chip unit includes a PN junction; The first oxide layer is formed by a low pressure chemical vapor deposition process; The thickness of the first oxide layer is greater than or equal to 5000 angstroms and less than or equal to 6000 angstroms.

3. The semiconductor structure according to claim 1, characterized in that: The oxygen-doped polysilicon layer is formed by decomposing silane; The thickness of the oxygen-doped polysilicon layer is greater than or equal to 5000 angstroms and less than or equal to 12000 angstroms.

4. The semiconductor structure according to claim 1, characterized in that The silicon nitride layer is formed by reacting silicon dichloride and ammonia; The thickness of the silicon nitride layer is greater than or equal to 1000 angstroms and less than or equal to 3000 angstroms.

5. The semiconductor structure according to claim 4, characterized in that: The thickness of the second oxide layer is greater than the thickness of the silicon nitride layer; A temperature required to form the second oxide layer is lower than a temperature required to form the first oxide layer.

6. The semiconductor structure according to claim 1, characterized in that The silicon nitride layer and the second oxide layer are both insulating layers; and the oxygen-doped polysilicon layer is a semi-insulating layer.

7. The semiconductor structure according to claim 6, characterized in that: The resistance of the semi-insulating layer is greater than that of the semiconductor and less than that of the insulator; the dielectric constant of the semi-insulating layer is greater than that of the insulator and less than that of the semiconductor.

8. The semiconductor structure according to claim 1, characterized in that: Also includes: Metal layer; The metal layer is located on a side of the second oxide layer away from the substrate; The metal layer covers a portion of the second oxide layer.

9. The semiconductor structure according to claim 8, characterized in that: The metal layer includes at least four metal structures; the at least four metal structures include aluminum, titanium, nickel or silver; The at least four metal structure layers are deposited sequentially according to a preset order.

10. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate; a surface of the substrate includes a chip unit; forming a first oxide layer on one side of the substrate; forming an oxygen-doped polysilicon layer on a side of the first oxide layer away from the substrate; wherein a projection area of ​​the oxygen-doped polysilicon layer on the substrate is smaller than a projection area of ​​the first oxide layer on the substrate; forming a silicon nitride layer on a side of the oxygen-doped polysilicon layer away from the substrate; The silicon nitride layer covers the oxygen-doped polysilicon layer; A second oxide layer is formed on a side of the silicon nitride layer away from the substrate; the second oxide layer covers the silicon nitride layer.

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