Electronic device and method of manufacturing electronic device

Abstract

An electronic device and a method of manufacturing the electronic device. In one example, a redistribution structure is provided, and the redistribution structure includes a substrate interconnect. A portion of the first cap layer is removed to expose a side of the substrate interconnect. The side of the substrate interconnect is recessed from a side of the first cap layer by a recess height. An electronic component is disposed over the first cap layer. The electronic component includes a second cap layer and a component interconnect. The second cap layer is bonded to the first cap layer. Heat is applied to bond the substrate interconnect to the component interconnect. Other examples, as well as related apparatuses and methods, are also disclosed herein.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly, to electronic devices and methods of making electronic devices. Background Art

[0002] Previous electronic packages and methods for forming electronic packages are inadequate, for example resulting in excessive cost, reduced reliability, relatively low performance, or excessive package size. Other limitations and disadvantages of conventional and traditional methods will be apparent to those skilled in the art by comparing such methods with the present disclosure and with reference to the drawings. Summary of the invention

[0003] One aspect of the present invention is an electronic device comprising: a first electronic component; a dielectric structure defining a through hole extending from an upper side of the dielectric structure to an upper side of the first electronic component; a first interconnect disposed in the through hole, wherein the upper side of the first interconnect is substantially coplanar with the upper side of the dielectric structure; a seed layer located between the first interconnect and the dielectric structure, wherein an end of the seed layer is recessed from the upper side of the dielectric structure and the upper side of the first interconnect; and a cap layer disposed on the dielectric structure and extending to the end of the seed layer between the first interconnect and the dielectric structure.

[0004] In the electronic device according to an aspect of the present invention, the cap layer comprises a height of about 1 nanometer from the dielectric structure.

[0005] In the electronic device according to an aspect of the present invention, the cover layer defines an opening, and the opening exposes the upper side of the first interconnection member for bonding.

[0006] In the electronic device according to an aspect of the present invention, the upper side of the first interconnection member is recessed from the upper side of the cover layer by a recessed height.

[0007] In the electronic device according to an aspect of the present invention, the cover layer includes an L-shaped profile.

[0008] In the electronic device according to an aspect of the present invention, a first height of the cap layer above the end of the seed layer is greater than a second height of the cap layer above the dielectric structure.

[0009] Another aspect of the present invention is a method for manufacturing an electronic device, comprising: providing a redistribution structure including a substrate interconnect; removing a portion of a first cover layer to expose a side of the substrate interconnect, wherein the side of the substrate interconnect is recessed by a recessed height from the side of the first cover layer; providing an electronic component above the first cover layer, wherein the electronic component includes a second cover layer and a component interconnect; bonding the second cover layer to the first cover layer; and applying heat to bond the substrate interconnect to the component interconnect.

[0010] In the method according to another aspect of the present invention, the first cap layer and the second cap layer include an inorganic dielectric material.

[0011] In a method according to another aspect of the invention, the redistribution structure comprises an inter-dielectric, and wherein the first capping layer comprises a thickness of about 1 nanometer measured from an upper side of the inter-dielectric.

[0012] In a method according to another aspect of the present invention, the redistribution structure includes an inter-dielectric, and wherein the redistribution structure includes a seed layer located between the inter-dielectric and the substrate interconnect.

[0013] In the method according to another aspect of the present invention, the first capping layer extends to an end of the seed layer between the substrate interconnection and the inter-dielectric.

[0014] In the method according to another aspect of the present invention, the first cover layer includes an L-shaped profile.

[0015] In a method according to another aspect of the present invention, setting the substrate interconnect includes: setting a conductive material above one side of the inner dielectric of the redistribution structure and filling a through hole defined by the inner dielectric; and removing the conductive material from above the side of the inner dielectric to leave the conductive material protruding above the through hole.

[0016] Another aspect of the present invention is a method for manufacturing an electronic device, characterized in that it includes: providing a first electronic component; providing a dielectric structure above the first electronic component, wherein the sidewalls of the dielectric structure define a through hole extending from the upper side of the dielectric structure to the first electronic component; providing a seed layer above the first electronic component, the upper side of the dielectric structure, and the sidewalls of the dielectric structure; providing a first component interconnect above the seed layer, wherein the first component interconnect fills the through hole and covers the side of the dielectric structure; removing a portion of the first component interconnect to leave a portion recessed from the seed layer. an upper side of the first component interconnect; removing a portion of the seed layer to expose the upper side of the dielectric structure and leaving an end of the seed layer recessed from the dielectric structure and located between the first component interconnect and the dielectric structure; providing a first cap layer over the dielectric structure, the first cap layer extending to the end of the seed layer located between the first component interconnect and the dielectric structure; and removing a portion of the first cap layer to expose the upper side of the first component interconnect, wherein the upper side of the first component interconnect is recessed by a first recess height from the upper side of the first cap layer.

[0017] In the method according to another aspect of the present invention, the first recess height is about 1 nanometer.

[0018] The method according to another aspect of the present invention further includes: setting a redistribution structure, the redistribution structure including a second cover layer and a substrate interconnect located on the inner side of the redistribution structure; bonding the second cover layer to the first cover layer; and applying heat to bond the substrate interconnect to the first component interconnect.

[0019] In the method according to another aspect of the present invention, the first cap layer and the second cap layer include an inorganic dielectric material.

[0020] In the method described in accordance with another aspect of the present invention, setting the redistribution structure further includes: setting the substrate interconnect on the first side of the second cover layer; and removing a portion of the second cover layer to expose the upper side of the substrate interconnect, wherein the upper side of the substrate interconnect is recessed by a recessed height from a second side of the second cover layer opposite to the first side of the second cover layer.

[0021] According to another aspect of the present invention, the method further includes: providing a second electronic component including a second cover layer and a second component interconnect; bonding the second cover layer to the first cover layer; and applying heat to bond the second component interconnect to the first component interconnect.

[0022] According to another aspect of the present invention, the method further includes disposing an encapsulant above the second cover layer and around the sidewalls of the first cover layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A cross-sectional view of an example electronic device is shown.

[0024] Figure 2A to Figure 2L Example methods for manufacturing electronic devices are presented.

[0025] Figure 3 A cross-sectional view of an example electronic device is shown.

[0026] Figure 3A exhibit Figure 3 A magnified view of region A of an example electronic device.

[0027] FIG. 4A to FIG. 4F Example methods for manufacturing electronic devices are presented.

[0028] Figure 4CA exhibit Figure 4C An enlarged view of area A of the electronic device in FIG.

[0029] Figure 4DA exhibit Figure 4D An enlarged view of area A of the electronic device in FIG.

[0030] Figure 4EA exhibit Figure 4E An enlarged view of area A of the electronic device in FIG.

[0031] Figure 4FA exhibit Figure 4F An enlarged view of area A of the electronic device in FIG.

[0032] Figure 5 A cross-sectional view of an example electronic device is shown.

[0033] FIG. 6A to FIG. 6H Example methods for manufacturing electronic devices are presented.

[0034] The following discussion provides various examples of electronic devices and methods of making electronic devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0035] The drawings illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present disclosure. In addition, the elements in the drawings may not be drawn to scale. For example, the size of some elements in the drawings may be enlarged relative to other elements to help improve the understanding of the examples discussed in the present disclosure. The same reference numerals in different drawings represent the same elements.

[0036] The term "or" means any one or more of the items in the list connected by "or". As an example, "x or y" means any one of the three-element set {(x), (y), (x, y)}. As another example, "x, y or z" means any one of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0037] The terms “comprises,” “comprising,” “includes,” and “including” are “open” terms and specify the presence of stated features but do not preclude the presence or addition of one or more other features.

[0038] The terms "first", "second", etc. may be used herein to describe various elements, and the described elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element discussed in the present disclosure may be referred to as a second element without departing from the teachings of the present disclosure.

[0039] Unless otherwise specified, the term "coupled" may be used to describe two elements that are in direct contact with each other or that are indirectly coupled through one or more other elements. For example, if element A is coupled to element B, element A may be in direct contact with element B or indirectly coupled to element B through an intervening element C. Similarly, the terms "above" or "on" may be used to describe two elements that are in direct contact with each other or that are indirectly coupled through one or more other elements. As used herein, the term "coupled" may refer to electrical coupling or mechanical coupling. DETAILED DESCRIPTION

[0040] An example of an electronic device includes a first electronic component and a dielectric structure, the dielectric structure defining a through hole extending from an upper side of the dielectric structure to an upper side of the first electronic component. A first interconnect is disposed in the through hole. An upper side of the first interconnect is substantially coplanar with an upper side of the dielectric structure. A seed layer is disposed between the first interconnect and the dielectric structure. An end of the seed layer is recessed from an upper side of the dielectric structure and an upper side of the first interconnect. A cap layer is disposed on the dielectric structure and extends to an end of the seed layer between the first interconnect and the dielectric structure.

[0041] An example method of manufacturing an electronic device includes providing a redistribution structure including a substrate interconnect. Removing a portion of a first cover layer to expose a side of the substrate interconnect. The side of the substrate interconnect is recessed from a side of the first cover layer by a recess height. Disposing an electronic component over the first cover layer. The electronic component includes a second cover layer and a component interconnect. Bonding the second cover layer to the first cover layer. Applying heat to bond the substrate interconnect to the component interconnect.

[0042] Another example method of manufacturing an electronic device includes providing a first electronic component. A dielectric structure is provided above the first electronic component. A sidewall of the dielectric structure defines a through hole extending from an upper side of the dielectric structure to the first electronic component. A seed layer is provided above the first electronic component, the upper side of the dielectric structure, and the sidewall of the dielectric structure. A first component interconnect is provided above the seed layer. The first component interconnect fills the through hole and covers the side of the dielectric structure. A portion of the first component interconnect is removed to leave an upper side of the first component interconnect recessed from the seed layer. A portion of the seed layer is removed to expose the upper side of the dielectric structure. An end of the seed layer is recessed from the dielectric structure and is located between the first component interconnect and the dielectric structure.

[0043] Other examples are included in the present disclosure. Such examples can be found in the drawings, claims, or description of the present disclosure.

[0044] Various examples of apparatus and methods tend to improve direct copper-copper bonding between interconnects. A thin inorganic capping layer can be deposited on mating surfaces between electronic components or other substrates. The inorganic capping layers can be bonded together and then adjacent interconnects can be bonded by applying heat. The interconnects are recessed or depressed under the capping layer prior to bonding, and the recess height can be controlled during formation based on the thickness of the capping layer. The precise recess depth disclosed herein tends to improve bonding performance by reducing the likelihood of bonding failure caused by recess depths that are too shallow or too deep.

[0045] Reference Figure 1 , shows a cross-sectional view of an example electronic device 100. Figure 1 In the example of , the electronic device 100 may include an electronic component 110 and an electronic component 120. The electronic component 110 may include a dielectric structure 111, a seed layer 112, an interconnect 113, a cap layer 114, a recess 115, and a bonding pad 117. The electronic component 120 may include a dielectric structure 121, a seed layer 122, an interconnect 123, a cap layer 124, a recess 125, and a bonding pad 127.

[0046] In some examples, interconnect 113 and interconnect 123 may be directly bonded together (e.g., in a direct copper-copper bond). A covalent bond may be formed between cap layer 114 and cap layer 124. The bond between interconnect 113 and interconnect 123 may be formed after the bond between cap layer 114 and cap layer 124. The bond between interconnect 113 and interconnect 123 may exhibit grain growth along the boundary or interface between the bonded interconnects. The height or thickness of cap layer 114 or cap layer 124 may be controlled during the formation or deposition of one or more cap layers to improve the reliability of the bond between interconnect 113 and interconnect 123. In the figure, dashed line B represents the bond or interface between interconnect 113 and interconnect 123 and between cap layer 114 and cap layer 124.

[0047] Figure 2A to Figure 2L Demonstrates methods for making example electronic devices such as Figure 1 A cross-sectional view of an example method of an electronic device 100 in FIG. Figure 2A The electronic device 100 is shown in an early stage of manufacture. Figure 2A In the example shown in , a dielectric structure 111 may be disposed on the electronic component 110. The electronic component 110 may include a bonding pad 117 on the front side or active side of the electronic component 110. The bonding pads 117 may be input / output terminals of the electronic component 110 and may be spaced apart from each other in rows or columns over the front side of the electronic component 110. In some examples, the electronic component 110 may include or be referred to as a die, chip, package, or passive component. In some examples, the thickness of the electronic component 110 measured between the front side and the back side of the electronic component 110 may be in the range of about 50 micrometers (μm) to about 800 μm, and the area may be in the range of about 0.5 millimeters (mm)×0.5 mm to about 70 mm×70 mm.

[0048] In some examples, the dielectric structure 111 may be disposed on the front side of the electronic component 110. The dielectric structure 111 may be provided by physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), spin coating, spray coating, dip coating, rod coating, printing, lamination, thermal oxidation, or any other suitable deposition process. In some examples, the dielectric structure 111 may include one or more layers of an organic dielectric material, such as, for example, a photoimageable organic passivation material, PI (polyimide), BCB (benzocyclobutene), PBO (polybenzoxazole), a phenolic resin, or ABF (Ajinomoto deposited film). In some examples, the dielectric structure 111 may include an inorganic dielectric material, such as, for example, SiO 2 、Si 3 N4 , SiCN, SiON or Al 2 O 3 In some examples, the thickness of dielectric structure 111 can be in a range of about 1 μm to about 20 μm.

[0049] Figure 2B The electronic device 100 is shown in a later stage of manufacturing. Figure 2B In the example of , the through hole 111a may be provided in the dielectric structure 111. The through hole 111a may expose at least a portion of the bonding pad 117 located on the front side of the electronic component 110. According to various examples, the through hole 111a may be formed by providing a mask 11 on the upper side of the dielectric structure 111. A portion of the dielectric structure 111 may be exposed by an opening in the mask 11. In some examples, the mask 11 may be a photoresist. The exposed portion of the dielectric structure 111 may be removed by, for example, etching, thereby forming the through hole 111a in the dielectric structure 111. The through hole 111a may be defined by the inner sidewall of the dielectric structure 111. The bonding pad 117 of the electronic component 110 may be exposed from the dielectric structure 111 through the through hole 111a (that is, the dielectric structure 111 may expose the bonding pad 117 of the electronic component 110). After the through hole 111a is formed, the mask 11 may be removed.

[0050] Figure 2C The electronic device 100 is shown in a later stage of manufacturing. Figure 2C In an example of the present invention, the seed layer 112 may be disposed above or cover the electronic component 110 and the dielectric structure 111. The seed layer 112 may have a substantially uniform thickness. The seed layer 112 may be disposed on the bonding pad 117 on the front side of the electronic component 110, on the inner wall of the through hole 111a (i.e., the inner sidewall of the dielectric structure 111), and on the upper side of the dielectric structure 111. The seed layer 112 may be coupled to the bonding pad 117 of the electronic component 110.

[0051] In some examples, the seed layer 112 may be provided by sputtering, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or other suitable deposition processes. The seed layer 112 may include Ti, TiW, or other suitable conductive seed materials. In some examples, the seed layer 112 may have a thickness in a range of about 0.05 μm to about 3 μm.

[0052] Figure 2D The electronic device 100 is shown in a later stage of manufacturing. Figure 2DIn the example shown in , the interconnect material 118 may be provided to fill the through hole 111 and may cover the seed layer 112. In some examples, the interconnect material 118 may be provided by electroplating using the seed layer 112 as a seed for the interconnect material 118. In some examples, an accelerator such as sodium polydisulfide bispropane sulfonate (SPS) may be used during formation to cause the interconnect material 118 to protrude above the through hole 111a. The accelerator may be selectively applied above the through hole 111a. The height of the portion of the interconnect material 118 above the through hole 111a (measured from a plane corresponding to the upper surface of the seed layer 112) may be greater than the height of the portion of the interconnect material 118 on the dielectric structure 111 (measured from the upper surface of the seed layer 112). In some examples, the portion of the interconnect material 118 located on the upper side of the dielectric structure 111 may be removed by chemical mechanical polishing (CMP). In some examples, portions of the interconnect material 118 located on the upper side of the dielectric structure 111 may be removed by etch-back planarization in a post-fabrication stage.

[0053] Figure 2E The electronic device 100 is shown in a later stage of manufacturing. Figure 2E , the interconnect material 118 located on the upper side of the dielectric structure 111 can be removed by isotropic etching. Removing the interconnect material 118 located on the upper side of the dielectric structure 111 using isotropic etching tends to reduce or prevent residual interconnect material 118 from remaining on the upper side of the seed layer 112 located on the dielectric structure 111. In some examples, the interconnect material 118 may protrude above the seed layer 112 in an area corresponding to the via 111a (e.g., in an area within the footprint of the via 111a).

[0054] Figure 2F The electronic device 100 is shown in a later stage of manufacturing. Figure 2F In the example of FIG. 1 , the portion of the interconnect material 118 protruding above the dielectric structure 111 (at Figure 2E ), thereby leaving interconnect 113. In some examples, the protruding portion of interconnect material 118 can be removed by CMP. Interconnect 113 can fill through hole 111a and can be recessed relative to seed layer 112. Interconnect 113 can be coupled to seed layer 112. Interconnect 113 can be coupled to bonding pad 117 of electronic component 110 through seed layer 112. In some examples, interconnect 113 can include copper. In some examples, interconnect 113 can be formed by plating. In some examples, interconnect 113 can be formed by over plating followed by the interconnect material removal step described above.

[0055] According to various examples, the height of the interconnect 113 measured from the front side of the electronic component 110 can be similar or the same as the height of the dielectric structure 111 measured from the front side of the electronic component 110. In some examples, the height of the interconnect 113 can be in the range of about 1 μm to about 20 μm. As a unit of length used herein, the term about can refer to + / -5%, + / -10%, + / -15%, + / -20%, or + / -25%. In some examples, the upper side of the seed layer 112 located on the upper side of the dielectric structure 111 can be coplanar with the upper side of the interconnect 113.

[0056] The seed layer 112 may be interposed between the dielectric structure 111 and the interconnect 113. The seed layer 112 may be interposed between the interconnect 113 and the bonding pad 117 of the electronic component 110.

[0057] Figure 2G The electronic device 100 is shown in a later stage of manufacturing. Figure 2G , a portion of the seed layer 112 covering the upper side of the dielectric structure 111 may be removed. The upper side of the dielectric structure 111 may be exposed after removing the seed layer 112. The seed layer 112 may be removed by, for example, wet etching. In some examples, an upper portion of the seed layer 112 inserted between the dielectric structure 111 and the interconnect 113 may be removed. A recess 115 may be formed by removing an upper portion of the seed layer 112 inserted between the dielectric structure 111 and the interconnect 113. The recess 115 may be defined between the dielectric structure 111 and the interconnect 113. The recess 115 may extend along the sidewall of the interconnect 113 to the end of the seed layer 112. The width of the recess 115 may be similar or the same as the thickness of the seed layer 112. The recess 115 may include a trench surrounding the upper portion of the interconnect 113. In some examples, the depth of the groove 115 measured from the upper side of the interconnect 113 or the upper side of the dielectric structure 111 may be in a range of about 0.01 μm to about 1 μm.

[0058] Figure 2H The electronic device 100 is shown in a later stage of manufacturing. Figure 2H , the cap layer 114 may be disposed over or cover the dielectric structure 111, the seed layer 112, and the interconnect 113. The cap layer 114 may contact the upper side of the dielectric structure 111, the upper side of the seed layer 112, and the upper side of the interconnect 113. The cap layer 114 may fill the groove 115 and may extend to the end of the seed layer 112 between the dielectric structure 111 and the interconnect 113. The cap layer 114 may be inserted between the inner sidewall of the dielectric structure 111 and the interconnect 113.

[0059] In some examples, the cap layer 114 can be provided by PVD, CVD, MOCVD, ALD, LPCVD, PECVD, spin coating, spray coating, dip coating, or rod coating. In some examples, the cap layer 114 can be made of an inorganic material. For example, the cap layer 114 can be SiO 2 、Si 3 N 4 , SiCN, SiON or Al 2 O 3 In some examples, the cap layer 114 may have a thickness in a range of about 1 nanometer (nm) to about 100 nm. The cap layer 114 may also be referred to herein as a nanocap or nanocap layer.

[0060] Fig.2I The electronic device 100 is shown in a later stage of manufacturing. Fig.2I , the upper side of the exposed interconnect 113 may be exposed by removing a portion of the cap layer 114. For example, the mask 12 may be disposed on the upper side of the cap layer 114. The mask 12 may be patterned to expose a portion of the cap layer 114 located on the interconnect 113. The exposed portion of the cap layer 114 may be removed by etching. In some examples, the mask 12 may include a photoresist. The mask 12 may be removed after patterning the cap layer 114 (e.g., after selectively removing a portion of the cap layer 114 to expose the top side of the interconnect 113).

[0061] In some examples, electronic component 110 may include bonding pad 117, dielectric structure 111, seed layer 112, interconnect 113, cap layer 114, and recess 115. The total height of cap layer 114 and dielectric structure 111 may be greater than the total height of interconnect 113 and seed layer 112. The upper side of cap layer 114 may protrude above the upper side of interconnect 113. Interconnect 113 may be recessed or concave relative to cap layer 114.

[0062] The recess height or recess depth may be controlled based on the thickness of the cap layer 114. The thickness of the cap layer 114 tends to be highly controllable or accurate, resulting in improved bonding performance. The increased accuracy of the recess depth may allow for better or more accurate compensation of differences in coefficients of thermal expansion between the dielectric structure 111 and the interconnect 113. The cap layer 114 may fill the recess 115 between the dielectric structure 111 and the interconnect 113. The cap layer 114 may have an L-shaped profile having a portion above the upper side of the dielectric structure 111 and a portion extending into the recess 115 between the dielectric structure 111 and the interconnect 113.

[0063] Figure 2J The electronic device 100 is shown in a later stage of manufacturing. Figure 2JIn the example shown in FIG. 1 , the electronic component 110 may be located above the electronic component 120. The electronic component 120 may include a bonding pad 127, a dielectric structure 121, a seed layer 122, an interconnect 123, a cap layer 124, and a recess 125. The electronic component 120 may have a FIG. 2A to FIG. 2I The electronic component 110 may be manufactured using the same or similar elements, features, materials or manufacturing methods as those shown in the process. The cover layer 114 of the electronic component 110 and the cover layer 124 of the electronic component 120 may be bonded together. Figure 2J , but it is contemplated and understood that electronic component 110 or electronic component 120 may be part of a wafer, a reconstituted wafer, or a redistribution layer (RDL) substrate, and FIG. 2A to FIG. 2I The techniques and structures described in can be used to provide a redistribution structure or other substrate suitable for bonding to the electronic component 110.

[0064] Figure 2K The electronic device 100 is shown in a later stage of manufacturing. Figure 2K In the example shown in , the cover layer 114 of the electronic component 110 and the cover layer 124 of the electronic component 120 can be bonded together. In some examples, the electronic component 110 can be flipped by the pick-and-place equipment so that the cover layer 114 can be located on the upper side of the cover layer 124 of the electronic component 120. The cover layer 114 of the electronic component 110 can be bonded to the cover layer 124 of the electronic component 120 through a hybrid bonding process. For example, the cover layer 114 and the cover layer 124 can undergo surface activation before bonding to each other. The surface activation can enable bonding at low temperatures. For example, in the surface activation of the cap layer 114 and the cap layer 124, hydrogen (H) atoms are generated on the sides of the cap layer 114 and the cap layer 124 by plasma treatment, and during the plasma treatment, oxygen (O) particles separated from water or air are combined with hydrogen (H) on the sides of the cap layer 114 and the cap layer 124 to introduce hydroxyl (OH) groups into the sides of the cap layers 114 and 124. The cap layer 114 and the cap layer 124 having the hydroxyl (OH) groups introduced into the sides can be easily coupled at low temperatures. In some examples, the cap layer 114 and the cap layer 124 can be coupled to each other at a temperature in the range of about 25° C. to about 400° C.

[0065] In some examples, after the cover layer 114 of the electronic component 110 and the cover layer 124 of the electronic component 120 are in contact, the interconnect 113 of the electronic component 110 and the interconnect 123 of the electronic component 120 can be spaced apart from each other to define a gap 116. In some examples, the passive bonding between the cover layer 114 and the cover layer 124 can initially start as a Van der Waals bond that develops into a covalent bond over time or temperature. In the case of a fixed bond, the interconnect 113 and the interconnect 123 can be pushed toward each other until the gap 116 is closed and a direct bond is established between the interconnect 113 and the interconnect 123.

[0066] Figure 2L The electronic device 100 is shown in a later stage of manufacturing. Figure 2L In the example shown in , the interconnect 113 of the electronic component 110 is coupled to the interconnect 123 of the electronic component 120. The interconnect 113 and the interconnect 123 may be coupled to each other at a higher temperature than the temperature used to couple the cover layer 114 and the cover layer 124. For example, the interconnect 113 of the electronic component 110 and the interconnect 123 of the electronic component 120 may be coupled to each other by a hybrid bonding process. In some examples, the interconnect 113 and the interconnect 123 may be coupled to each other at a temperature ranging from about 150° C. to about 400° C. Due to the temperature rise, the interconnect 113 of the electronic component 110 and the interconnect 123 of the electronic component 120 may expand as much as the thickness of the cover layers 114 and 124, and thus may contact each other and couple to each other. The thermal expansion coefficient of the interconnect 113 and the interconnect 123 may be greater than the thermal expansion coefficient of the cover layer 114 and the cover layer 124. The gap 116 ( Figure 2K ) can compensate for the thermal expansion of interconnect 113 and interconnect 123.

[0067] When coupled together, interconnect 113 and interconnect 123 may expand to contact each other. Gap 116 compensates for thermal expansion of interconnects 113 and 123, and prevents or reduces the chance of cover layer 114 and cover layer 124 separating from each other. In some examples, direct bonding between interconnect 113 and interconnect 123 may include or be referred to as fusion bonding or welding-free bonding. In some examples, direct bonding may include grain growth of materials of interconnects 113, 123 toward each other. In some examples, direct bonding may be established by pressure of interconnect 113 and interconnect 123 expanding toward each other due to heat, while being fixed by bonding between cover layers 114 and 124.

[0068] Figure 3 A cross-sectional view of an example electronic device 200 is shown. Figure 3A exhibit Figure 3An enlarged view of region A of the electronic device 200 is shown. Figure 3 and Figure 3A In some examples, the electronic device 200 may include a redistribution structure 210 and an electronic component 220. In some examples, the electronic device 200 may include a substrate 230.

[0069] In some examples, the redistribution structure 210 may include a dielectric structure 211, a conductive structure 212, and a substrate capping layer 214. The conductive structure 212 may include a substrate interconnect 213. The dielectric structure 211 may include an inner dielectric 211a and an outer dielectric 211b. The electronic component 220 may include a component interconnect 223 and a component capping layer 224.

[0070] FIG. 4A to FIG. 4F Demonstrates the use of manufacturing example electronic devices such as Figure 3 2 is a cross-sectional view of an example method of an electronic device 200 in FIG. Figure 4A The electronic device 200 is shown in an early stage of manufacture. Figure 4A In the example shown in , the conductive structure 212 and the dielectric structure 211 of the redistribution structure 210 may be disposed on a substrate 230 .

[0071] In some examples, the substrate 230 may include or be referred to as a wafer, a reconstituted wafer, or a removable carrier. For example, the substrate 230 may be a wafer including a plurality of semiconductor dies. The redistribution structure 210 may be formed over the semiconductor die to manufacture electronic devices including, for example, WLP (wafer level packaging) or WLCSP (wafer level chip size packaging). In some examples, the substrate 230 may be a reconstituted wafer including a plurality of known good semiconductor dies that are aggregated and reconstituted (e.g., encapsulated) to form the substrate 230. The redistribution structure 210 may be formed over the semiconductor die and the encapsulation to manufacture electronic devices including, for example, WLFO (wafer level fan-out) devices. In some examples, the substrate 230 may include a removable (or temporary) carrier formed of, for example, silicon, glass, ceramic, or metal. The redistribution structure 210 may be formed on the removable carrier, and the removable carrier may be subsequently removed / separated from the redistribution structure 210 to expose the outward terminals 212b of the conductive structure 212. In some examples, the thickness of substrate 230 may be in a range of about 300 μm to about 2000 μm, and the width of substrate 230 may be in a range of about 100 mm to about 300 mm. As used herein, the term about may refer to + / -5%, + / -10%, + / -15%, + / -20%, or + / -25%. During, when, or after the manufacturing process is completed, substrate 230 may support dielectric structure 211, conductive structure 212, and electronic component 220.

[0072] In some examples, the outer dielectric 211b of the dielectric structure 211 may be disposed above the substrate 230. The outer dielectric 211b may be disposed to cover the substrate 230, and an opening corresponding to the desired position of the outward terminal 212b of the conductive structure 212 may be disposed in the outer dielectric 211b. For example, after a patterned mask (e.g., a photoresist) is disposed on the upper side of the dielectric structure 211, the opening in the outer dielectric 211b may be formed by removing the exposed portion of the outer dielectric 211b through, for example, etching. In some examples, the outer dielectric 211b may include one or more layers of an organic electrically insulating material, such as polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), a resin, or an Ajinomoto built-up film (ABF). In some examples, the outer dielectric 211b may include an inorganic electrically insulating material (e.g., SiO 2 、Si 3 N 4 、SiON、Ta 2 O 5 or Al 2 O 3 ) or other dielectric materials with similar insulation and structural properties. The outer dielectric 211b can be formed by spin coating, spray coating, dip coating, rod coating, PVD, CVD, printing, lamination, or any other suitable deposition process. In some examples, the thickness of the outer dielectric 211b can be in the range of about 3 μm to about 20 μm.

[0073] According to various examples, the conductive pattern 2121 of the conductive structure 212 may be disposed above the upper side of the outer dielectric 211b and in the opening in the outer dielectric 211b. The conductive pattern 2121 may include one or more layers of Al, Ti, TiW, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. In some examples, the conductive pattern 2121 may include or be referred to as a conductive layer, one or more traces, one or more pads, one or more conductive vias, RDL, wiring pattern, or circuit pattern. In some examples, the conductive pattern 2121 may be provided by electroplating. For example, the conductive pattern 2121 may be disposed in a desired pattern by disposing a metal seed layer, the metal seed layer covering the upper side of the outer dielectric 211b, the opening in the outer dielectric 211b, and the portion of the upper side of the substrate 230 exposed by the opening in the outer dielectric 211b. A patterned mask (e.g., a patterned photoresist) may be deposited on the upper side of the seed layer. The conductive material of the conductive pattern 2121 may be deposited on the portion of the seed layer exposed from the patterned mask. After depositing the conductive material of the conductive pattern 2121, the portion of the patterned mask and the seed layer not covered by the conductive pattern 2121 may be removed. The conductive pattern 2121 may also be formed using PVD, CVD, electroless plating or other suitable metal deposition processes. In some examples, the thickness of the conductive pattern 2121 may be in the range of about 3 μm to about 20 μm. In some examples, the lower (or outward) side of the conductive pattern 2121 (e.g., a side that is substantially coplanar with the lower side of the outer dielectric 211b) may provide an outward terminal 212b of the conductive structure 212. The outward terminal 212b may provide an I / O terminal for the redistribution structure 210. In some examples, the spacing of the outward terminal 212b is in the range between 10 μm and 500 μm.

[0074] In some examples, the dielectric 2111 of the dielectric structure 211 may be disposed over the upper side of the outer dielectric 211b and the conductive pattern 2121 using spin coating, spray coating, dip coating, rod coating, PVD, CVD, printing, lamination, or any other suitable deposition process. An opening exposing the conductive pattern 2121 may be disposed in the dielectric 2111. In some examples, the dielectric 2111 may include an organic electrically insulating material, such as one or more layers of PI, BCB, PBO, resin, or ABF. In some examples, the dielectric 2111 may include an inorganic electrically insulating material (e.g., SiO 2 、Si 3 N 4 、SiON、Ta 2 O 5 or Al 2 O 3) or other dielectric materials with similar insulation and structural properties. In some examples, dielectric 2111 may have similar elements, features, materials, or manufacturing methods as outer dielectric 211b as previously described. In some examples, the thickness of dielectric 2111 may be in the range of about 3 μm to about 20 μm.

[0075] According to various examples, a conductive pattern 2122 of the conductive structure 212 may be disposed above the upper side of the dielectric 2111 and the conductive pattern 2121 using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. The conductive pattern 2122 may include one or more layers of Al, Ti, TiW, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. At least a portion of the conductive pattern 2122 may be coupled to the conductive pattern 2121. In some examples, the conductive pattern 2122 may include or be referred to as a conductive layer, one or more traces, one or more pads, one or more conductive vias, RDL, wiring pattern, or circuit pattern. In some examples, the conductive pattern 2122 may have similar elements, features, materials, or manufacturing methods as the conductive pattern 2121 described previously (for example, the conductive pattern 2122 may be formed using a seed layer, a patterned mask, and electrolytic plating). In some examples, the thickness of the conductive pattern 2122 may be in the range of about 3 μm to about 20 μm.

[0076] In some examples, the dielectric 2112 of the dielectric structure 211 may be disposed over the upper side of the dielectric 2111 and the conductive pattern 2122 using spin coating, spray coating, dip coating, rod coating, PVD, CVD, printing, lamination, or any other suitable deposition process. An opening exposing the conductive pattern 2122 may be disposed in the dielectric 2112. In some examples, the dielectric 2112 may include an organic electrically insulating material, such as one or more layers of PI, BCB, PBO, resin, or ABF. In some examples, the dielectric 2112 may include an inorganic electrically insulating material (e.g., SiO 2 、Si 3 N 4 、SiON、Ta 2 O 5 or Al 2 O 3 ) or other dielectric materials with similar insulation and structural properties. In some examples, dielectric 2112 may have similar elements, features, materials, or manufacturing methods as outer dielectric 211b as previously described. In some examples, the thickness of dielectric 2112 may be in the range of about 3 μm to about 20 μm.

[0077] According to various examples, a conductive pattern 2123 of the conductive structure 212 may be disposed above the upper side of the dielectric 2112 and the conductive pattern 2122 using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. The conductive pattern 2123 may include one or more layers of Al, Ti, TiW, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. At least a portion of the conductive pattern 2123 may be coupled to the conductive pattern 2122. In some examples, the conductive pattern 2123 may include or be referred to as a conductive layer, one or more traces, one or more pads, one or more conductive vias, RDL, wiring pattern, or circuit pattern. In some examples, the conductive pattern 2123 may have similar elements, features, materials, or manufacturing methods as the conductive pattern 2121 described previously. In some examples, the thickness of the conductive pattern 2123 may be in the range of about 3 μm to about 20 μm.

[0078] In some examples, the dielectric 2113 of the dielectric structure 211 may be disposed over the upper side of the dielectric 2112 and the conductive pattern 2123 using spin coating, spray coating, dip coating, rod coating, PVD, CVD, printing, lamination, or any other suitable deposition process. An opening exposing the conductive pattern 2123 may be disposed in the dielectric 2113. In some examples, the dielectric 2113 may include an organic electrically insulating material, such as one or more layers of PI, BCB, PBO, resin, or ABF. In some examples, the dielectric 2113 may include an inorganic electrically insulating material (e.g., SiO 2 、Si 3 N 4 、SiON、Ta 2 O 5 or Al 2 O 3 ) or other dielectric materials with similar insulation and structural properties. In some examples, dielectric 2113 may have similar elements, features, materials, or manufacturing methods as outer dielectric 211b as previously described. In some examples, the thickness of dielectric 2113 may be in the range of about 3 μm to about 20 μm.

[0079] According to various examples, a conductive pattern 2124 of the conductive structure 212 may be disposed above the upper side of the dielectric 2113 and the conductive pattern 2123 using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. The conductive pattern 2124 may include one or more layers of Al, Ti, TiW, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. At least a portion of the conductive pattern 2124 may be coupled to the conductive pattern 2123. In some examples, the conductive pattern 2124 may include or be referred to as a conductive layer, one or more traces, one or more pads, one or more conductive vias, RDL, wiring pattern, or circuit pattern. In some examples, the conductive pattern 2123 may have similar elements, features, materials, or manufacturing methods as the conductive pattern 2121 described previously. In some examples, the thickness of the conductive pattern 2124 may be in the range of about 3 μm to about 20 μm.

[0080] In some examples, the inner dielectric 211a of the dielectric structure 211 may be disposed over the upper side of the dielectric 2113 and the conductive pattern 2124 using spin coating, spray coating, dip coating, rod coating, PVD, CVD, printing, lamination, or any other suitable deposition process. An opening exposing the conductive pattern 2124 may be disposed in the inner dielectric 211a. In some examples, the inner dielectric 211a may include an organic electrically insulating material, such as one or more layers of PI, BCB, PBO, resin, or ABF. In some examples, the inner dielectric 211a may include an inorganic electrically insulating material (e.g., SiO 2 、Si 3 N 4 、SiON、Ta 2 O 5 or Al 2 O 3 ) or other dielectric materials with similar insulation and structural properties. In some examples, the inner dielectric 211a may have similar elements, features, materials, or manufacturing methods as the outer dielectric 211b as previously described. In some examples, the thickness of the inner dielectric 211a may be in the range of about 3 μm to about 20 μm.

[0081] Figure 4B The electronic device 200 is shown in a post-manufacturing stage. Figure 4BIn the example shown in , a substrate interconnect 213 of the conductive structure 212 may be disposed in the opening of the inner dielectric 211a using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. In some examples, the substrate interconnect 213 includes copper. The substrate interconnect 213 may also include one or more layers of Al, Ti, TiW, Sn, Ni, Au, Ag, or other suitable conductive materials. In some examples, during the formation of the substrate interconnect 213, the conductive material of the substrate interconnect 213 may be disposed on the upper side of the inner dielectric 211a and in the opening in the inner dielectric 211a. The conductive material of the substrate interconnect 213 located on the upper side of the inner dielectric 211a may be removed by a CMP process, leaving the substrate interconnect 213 filling the opening in the inner dielectric 211a. Due to the CMP process, the upper side of the inner dielectric 211a and the upper side of the substrate interconnect 213 may be coplanar.

[0082] According to various examples, the substrate interconnect 213 may be in contact with or coupled to the conductive pattern 2124. In some examples, the substrate interconnect 213 may have the same Figure 2A to Figure 2L The substrate interconnect 213 may be similar to the interconnect 113 of the electronic component 110 described above. The upper side of the substrate interconnect 213 may be the inward terminal 212a of the conductive structure 212. The inward terminal 212a of the conductive structure 212 may provide an I / O terminal for the redistribution structure 210. In some examples, the thickness of the substrate interconnect 213 may be in the range of about 3 μm to about 20 μm. In some examples, the substrate interconnect 213 may have a pitch of about 1 μm to about 20 μm.

[0083] Although the present disclosure shows that the conductive structure 212 has conductive patterns 2122, 2123, 2124 between the conductive pattern 2121 and the substrate interconnect 213, and the dielectric structure 211 has dielectrics 2111, 2112, 2113 between the outer dielectric 211b and the inner dielectric 211a, it is contemplated and understood that the conductive structure 212 and the dielectric structure 211 of the redistribution structure 210 may include any number of alternating conductive patterns and dielectric layers. For example, the conductive structure 212 may include fewer or additional conductive patterns between the conductive pattern 2121 and the substrate interconnect 213, and the dielectric structure 211 may include fewer or additional dielectric layers between the outer dielectric 211b and the inner dielectric 211a.

[0084] According to various examples, the redistribution structure 210 may be an RDL substrate. The RDL substrate may include one or more conductive layers and one or more dielectric layers, and (a) may be formed layer by layer over an electronic device to be coupled to the RDL substrate, or (b) may be formed layer by layer over a carrier, and may be completely or at least partially removed after the electronic device and the RDL substrate are coupled together. The RDL substrate may be manufactured layer by layer as a wafer-level substrate on a circular wafer in a wafer-level process, and / or may be manufactured layer by layer as a panel-level substrate on a rectangular or square panel carrier in a panel-level process. The RDL substrate may be formed in an additive buildup process, and may include one or more dielectric layers alternately stacked with one or more conductive layers and define corresponding conductive redistribution patterns or traces, which are configured to collectively (a) fan the electrical traces out of the footprint of the electronic device, and / or (b) fan the electrical traces into the footprint of the electronic device. The conductive pattern may be formed using a plating process, such as, for example, an electroplating process or an electroless plating process. The conductive pattern may include a conductive material such as, for example, copper or other plateable metals. The location of the conductive pattern may be obtained using a photopatterning process such as, for example, a photolithography process and a photoresist material used to form a photolithography mask.

[0085] In some instances, the dielectric layer of the RDL substrate may be patterned using a photopatterning process and may include a photolithography mask through which light is passed to expose desired features of the photopattern, such as through holes in the dielectric layer. The dielectric layer may be made of a photodefinable organic dielectric material, such as, for example, PI, BCB, or PBO. Such dielectric materials may be spin-coated or otherwise applied in liquid form, rather than attached in the form of a preformed film. In order to allow the desired photodefined features to be properly formed, such photodefinable dielectric materials may omit structural reinforcements, or may be filler-free, without strands, fabrics, or other particles, and may interfere with light from the photopatterning process. In some instances, such filler-free properties of filler-free dielectric materials may allow the thickness of the resulting dielectric layer to be reduced. Although the photodefinable dielectric materials described above may be organic materials, in some instances, the dielectric material of the RDL substrate may include one or more inorganic dielectric layers. Some examples of one or more inorganic dielectric layers may include silicon nitride (Si 2+). 3 N 4 ), silicon oxide (SiO 2) and / or silicon oxynitride (SiON). The inorganic dielectric layer may be formed by growing one or more inorganic dielectric layers using an oxidation or nitridation process rather than using a photodefined organic dielectric material. Such inorganic dielectric layers may be filler-free, without strands, fabrics, or other different inorganic particles. In some examples, the RDL substrate may omit a permanent core structure or carrier, such as, for example, a dielectric material including bismaleimide triazine (BT) or FR4, and these types of RDL substrates may include or be referred to as coreless substrates. A substrate as disclosed herein may include an RDL substrate.

[0086] Figure 4C and Figure 4CA The electronic device 200 is shown in a late stage of manufacturing. Figure 4CA for Figure 4C An enlarged view of the electronic device 200 at region A in FIG. Figure 4C and Figure 4CA In the example shown in , PVD, CVD, MOCVD, ALD, LPCVD, PECVD, spin coating, spray coating, dip coating, or bar coating can be used to provide a substrate capping layer 214 to cover the upper side of the dielectric structure 211 and the upper side of the conductive structure 212. The substrate capping layer 214 can be located on or in contact with the upper side of the inner dielectric 211a and the upper side of the substrate interconnect 213. In some examples, the substrate capping layer 214 can be formed with the substrate as described above. Figure 2A to Figure 2L The substrate cap layer 214 may be formed with a structure and technique similar to or identical to the cap layer 114 described in . For example, the substrate cap layer 214 may extend into a recess or trench surrounding an upper portion of the substrate interconnect 213. The portion of the substrate cap layer 214 in the recess may be located between the inner sidewall of the inner dielectric 211a and the upper portion of the substrate interconnect 213, and may extend to the top side of the seed layer located between the inner dielectric 211a and the substrate interconnect 213.

[0087] In some examples, the substrate capping layer 214 may be made of an inorganic material, such as an oxide or a nitride. For example, the substrate capping layer 214 may be made of SiO 2 、Si 3 N 4 , SiON or Al 2 O 3In some examples, the inner dielectric 211a may include an organic material (e.g., PI), and the inorganic material of the substrate capping layer 214 may be formed on the surface of the organic material of the inner dielectric 211a. Using an inorganic material for the substrate capping layer 214 and an organic material for one or more of the dielectrics of the dielectric structure 211 tends to reduce manufacturing costs and / or allow the inorganic capping layer to be applied to an RDL substrate that is manufactured in a location where a substrate with an inorganic dielectric layer is not typically provided or by a manufacturer that does not typically provide a substrate with an inorganic dielectric layer. In addition, the thickness of the substrate capping layer 214 tends to be easier to control, thereby making the depth of the recess more accurate and reducing the occurrence of bonding failures. In some examples, the thickness of the substrate capping layer 214 may be in the range of about 1 nanometer to about 100 nanometers. The thinness of the substrate capping layer 214 may also reduce or prevent wrinkles during deposition.

[0088] Figure 4D and Figure 4DA The electronic device 200 is shown in a late stage of manufacturing. Figure 4DA for Figure 4D An enlarged view of the electronic device 200 at region A in FIG. Figure 4D and Figure 4DA In an example of the present invention, a portion of the substrate capping layer 214 may be removed and an upper side of the substrate interconnect 213 may be exposed. For example, a mask may be disposed on an upper side of the substrate capping layer 214. The mask may be patterned to expose a portion of the substrate capping layer 214 located on the substrate interconnect 213. The exposed portion of the substrate capping layer 214 may be removed by etching. The mask, which may be a photoresist in some examples, may be removed after patterning the substrate capping layer 214.

[0089] The redistribution structure 210 may include a dielectric structure 211, a conductive structure 212, a substrate interconnect 213, and a substrate capping layer 214. The substrate capping layer 214 may protrude upward from the substrate interconnect 213. In other words, the substrate interconnect 213 may be recessed or depressed relative to the substrate capping layer 214. The thickness of the substrate capping layer 214 may be selected to compensate for thermal expansion of the substrate interconnect 213 or to compensate for a difference in the thermal expansion coefficient of the dielectric structure 211 and the thermal expansion coefficient of the substrate interconnect 213.

[0090] Figure 4E and Figure 4EA The electronic device 200 is shown in a late stage of manufacturing. Figure 4EA for Figure 4E An enlarged view of the electronic device 200 in area A of FIG. Figure 4E and Figure 4EA In the example shown in , the electronic component 220 may be disposed on an upper side of the redistribution structure 210 .

[0091] Electronic component 220 may include component interconnect 223 and component cover layer 224. Component interconnect 223 may be coupled to a bonding pad of electronic component 220. In some examples, component interconnect 223 may be a bonding pad of electronic component 220. In some examples, component interconnect 223 may include copper. In some examples, component interconnect 223 may be formed by plating. In some examples, a lower side of component interconnect 223 may be coplanar with a lower (e.g., front or active) side of electronic component 220. In some examples, component interconnect 223 of electronic component 220 may have similar or identical elements, features, materials, or manufacturing methods as interconnect 113 of electronic component 110.

[0092] According to various examples, the component cover layer 224 may be located on or in contact with the lower side of the electronic component 220. The component interconnect 223 is exposed from the component cover layer 224. The lower side of the component cover layer 224 may protrude relative to the lower side of the component interconnect 223. In this regard, the component interconnect 223 may be recessed or depressed relative to the component cover layer 224. In some examples, the component cover layer 224 may have similar or identical elements, features, materials, or manufacturing methods as the substrate cover layer 214 of the redistribution structure 210. In some examples, the component cover layer 224 may have similar or identical corresponding elements, features, materials, or manufacturing methods as the cover layer 114 of the electronic component 110. In some examples, the electronic component 220 may include a dielectric structure similar or identical to the dielectric structure 111 of the electronic component 110, and the component interconnect 223 may be coplanar with the dielectric structure. In some examples, electronic component 220 may include a seed layer and a groove that are similar or identical to seed layer 112 and groove 115 , respectively, of electronic component 110 , and component cap layer 224 may extend into the groove and may contact the seed layer.

[0093] In some examples, a pick-and-place device may pick up the electronic component 220 and place the electronic component 220 on the redistribution structure 210, wherein the component cover layer 224 of the electronic component 220 is placed on the upper side of the substrate cover layer 214. After the component cover layer 224 is located on the substrate cover layer 214, the component interconnects 223 of the electronic component 220 and the substrate interconnects 213 of the redistribution structure 210 may be spaced apart from each other to define a gap 216. The component cover layer 224 of the electronic component 220 may be bonded to the substrate cover layer 214 of the redistribution structure 210 through a hybrid bonding process. For example, the component cover layer 224 and the substrate cover layer 214 may undergo surface activation before being coupled together to enable low temperature coupling. The surface activation of the component cover layer 224 and the substrate cover layer 214 may be similar or identical to the surface activation of the cover layer 114 of the electronic component 110 and the cover layer 124 of the electronic component 120. In some examples, the assembly cap layer 224 may be coupled to the substrate cap layer 214 at a temperature in a range of about 25°C to about 400°C.

[0094] Figure 4F and Figure 4FA The electronic device 200 is shown in a late stage of manufacturing. Figure 4FA for Figure 4F An enlarged view of section A of the Figure 4F and Figure 4FA In the example shown in , the component interconnect 223 of the electronic component 220 may be coupled to the substrate interconnect 213 of the redistribution structure 210 .

[0095] The component interconnect 223 may be coupled to the substrate interconnect 213 at a higher temperature than the temperature employed during coupling the component cap layer 224 to the substrate cap layer 214. For example, the component interconnect 223 may be coupled to the substrate interconnect 213 of the redistribution structure 210 through a hybrid bonding process. In some examples, the component interconnect 223 may be coupled to the substrate interconnect 213 at a temperature in a range of about 150° C. to about 400° C. During bonding, the temperature rise may cause thermal expansion of the component interconnect 223 or the substrate interconnect 213. According to various examples, the thermal expansion coefficients of the component interconnect 223 and the substrate interconnect 213 may be greater than the thermal expansion coefficients of the component cap layer 224 and the substrate cap layer 214. The gap created by the thickness of the component cover layer 224 and the substrate cover layer 214 can be configured to allow thermal expansion of the component interconnect 223 or the substrate interconnect 213 and cause contact and coupling between the component interconnect 223 and the substrate interconnect 213 without separating the component cover layer 224 from the substrate cover layer 214 (or destroying the bond therebetween).

[0096] The electronic device 200 and the redistribution structure 210 can be coupled to each other by low temperature hybrid bonding. When coupled together, the component interconnect 223 and the substrate interconnect 213 can expand to contact and couple with each other. The gap created by the thickness of the component cover layer 224 and the substrate cover layer 214 can prevent or reduce the occurrence of the substrate cover layer 214 and the component cover layer 224 being separated from each other due to the thermal expansion of the substrate interconnect 213 or the component interconnect 223. In some examples, the direct bonding between the substrate interconnect 213 and the component interconnect 223 may include or be referred to as a fusion bonding or a welding-free bonding. In some examples, the direct bonding may include the materials of the substrate interconnect 213 or the component interconnect 223 growing grains with each other. In some examples, the direct bonding may be established by the pressure of the substrate interconnect 213 and the component interconnect 223 expanding toward each other due to heat, while being fixed by the bonding between the substrate cover layer 214 and the component cover layer 224.

[0097] Figure 5 A cross-sectional view of an example electronic device 300 is shown. Figure 5 In some examples, the electronic device 300 may include a redistribution structure 210 and an electronic component 220. In some examples, the electronic device 300 may include an encapsulant 310 and an external interconnect 320.

[0098] The redistribution structure 210 may include a dielectric structure 211, a conductive structure 212, and a substrate capping layer 214. The dielectric structure 211 may include an inner dielectric 211a and an outer dielectric 211b. The conductive structure 212 may include a substrate interconnect 213. The electronic component 220 may include a component interconnect 223 and a component capping layer 224.

[0099] FIG. 6A to FIG. 6H Demonstrates the use of manufacturing example electronic devices such as Figure 5 A cross-sectional view of an example method of an electronic device 300 in FIG. Fig. 6A The electronic device 300 is shown in an early stage of manufacture. Fig. 6A In the example shown in FIG. 1 , the substrate cover layer 214 may be disposed on the upper side of the carrier substrate C. The substrate cover layer 214 may have Figure 4C The substrate cap layer 214 shown in FIG. 2 may be similar or identical elements, features, materials, or manufacturing methods to those shown in FIG.

[0100] In some examples, the carrier substrate C may include silicon or other semiconductor materials. In some examples, the carrier substrate C may include glass or a metal plate. In some examples, the carrier substrate C may include a core or coreless substrate that includes various dielectric materials, such as inorganic dielectric materials (e.g., Si 3 N 4 、SiO 2, SiON, SiN, oxide, nitride, etc.) and / or one or more layers of any of organic dielectric materials (e.g., polymers, PI, BCB, PBO, BT, molding materials, phenolic resins, epoxy resins, etc.). In some examples, the carrier substrate C may include a temporary bonding layer such that the temporary bonding layer is located between the substrate cover layer 214 and the carrier substrate C. As described in further detail below, the temporary bonding layer may allow the carrier substrate C to be separated from the substrate cover layer 214.

[0101] Figure 6B The electronic device 300 is shown in a later stage of manufacturing. Figure 6B In the example shown in FIG. 2 , a redistribution structure 210 including a conductive structure 212 and a dielectric structure 211 may be disposed on a substrate cap layer 214 and a substrate carrier C. Figure 6B As shown in FIG. 1B, the substrate interconnect 213 and the inner dielectric 211a may be disposed on the upper side of the substrate capping layer 214. For example, the substrate interconnect 213 and the inner dielectric 211a may be close to the substrate carrier C, and the outward terminal 212b and the outer dielectric 211b may be away from the substrate carrier C.

[0102] The substrate interconnects 213 may be disposed on the substrate capping layer 214 in a desired pattern (eg, rows or columns). In some examples, the thickness of the substrate interconnects 213 may be in a range of about 3 μm to about 20 μm. The dielectric structures 211 and the conductive structures 212 may have respective Figure 4A The dielectric structure 211 and the conductive structure 212 shown in FIG. 2 may have similar or identical elements, features, materials, or manufacturing methods.

[0103] In some examples, the substrate interconnect 213 and the inner dielectric 211a may be first formed on the substrate cap layer 214 and the substrate carrier C, and the subsequent dielectric of the dielectric structure 211 and the conductive pattern of the conductive structure 212 may be formed on or after the substrate interconnect 213 and the inner dielectric 211a. Providing the substrate cap layer 214, the substrate interconnect 213, and the inner dielectric 211a on the substrate carrier C may increase the flatness (or planarity) of the substrate cap layer 214, the substrate interconnect 213, or the inner dielectric 211a. For example, providing the substrate cap layer 214, the substrate interconnect 213, and the inner dielectric 211a on the substrate carrier C may reduce the probability of grooves or non-uniformity on the side of the substrate cap layer 214 and the side of the substrate interconnect 213 oriented toward the substrate carrier C, thereby improving bonding performance and reducing the possibility of bonding failure.

[0104] Figure 6C The electronic device 300 is shown in a later stage of manufacturing. Figure 6CIn the example shown in FIG. 1 , a removable carrier 330 may be disposed on the outer dielectric 211b of the dielectric structure 211 and the outward terminal 212b of the conductive structure 212. The removable carrier 330 may be formed of, for example, silicon, glass, ceramic, metal, or any other suitable material. The removable carrier 330 may support the dielectric structure 211, the conductive structure 212, the substrate cap layer 214, and the one or more electronic components 220 ( Fig. 6F In some examples, the removable carrier 330 may include a temporary bonding layer such that the temporary bonding layer is located between the redistribution structure 210 and the removable carrier 330. As described in further detail below, the temporary bonding layer may allow the removable carrier 330 to be separated from the outer dielectric 211b and the outward terminals 212b of the redistribution structure 210.

[0105] Fig.6D The electronic device 300 is shown in a later stage of manufacturing. Fig.6D In the embodiment, the electronic device 300 has been rotated 180° so that the movable carrier 330 is located at Fig.6D at the bottom. Fig.6D In the example of FIG. 2 , the carrier substrate C may be separated from the substrate cover layer 214 .

[0106] In some examples, the carrier substrate C may be separated from the substrate cover layer 214 and the redistribution structure 210 (in whole or in part) by, for example, grinding, stripping, or etching. When the carrier substrate C is removed, the substrate cover layer 214 may remain located above the inner dielectric 211a and the substrate interconnect 213. In some examples, the carrier substrate C may include a temporary bonding layer, and the substrate cover layer 214 may be disposed on the temporary bonding layer. The temporary bonding layer may include, for example, a temporary adhesive film, a temporary adhesive tape, or a temporary adhesive coating. In some examples, the temporary bonding layer may be a thermal release tape (film) or an optical release tape (film), wherein the adhesive strength may be weakened or removed by heat or light, respectively. In some examples, the temporary bonding layer may have an adhesive force that is weakened or removed by an external physical or chemical force. The temporary bonding layer may allow the carrier substrate C to be separated from the substrate cover layer 214 before patterning the substrate cover layer 214, as further described below.

[0107] Fig. 6E The electronic device 300 is shown in a later stage of manufacturing. Fig. 6E In the example shown in FIG. 2 , the substrate capping layer 214 may be patterned to expose the upper side of the substrate interconnect 213. The patterning of the substrate capping layer 214 may be similar to Figure 4D The redistribution structure 210 may include a dielectric structure 211 , a conductive structure 212 including a substrate interconnect 213 and an outward terminal 212 b , and a substrate capping layer 214 .

[0108] The substrate capping layer 214 may protrude above the substrate interconnect 213 such that the upper side of the substrate interconnect 213 is recessed or depressed relative to the substrate capping layer 214. By disposing the substrate interconnect 213 and the inner dielectric 211a on the substrate capping layer 214, the upper side of the substrate interconnect 213 and the upper side of the dielectric structure 211 may be formed coplanar with each other, which may eliminate the need for a surface planarization process (e.g., the above-mentioned Figure 4B Eliminating the surface planarization process may simplify the manufacturing process and / or reduce manufacturing costs.

[0109] Fig. 6F and Figure 6G The electronic device 300 is shown in a later stage of manufacturing. Fig. 6F and Figure 6G In the example shown in FIG. 2 , the electronic component 220 and the redistribution structure 210 may be coupled to each other. The coupling of the component cover layer 224 of the electronic component 220 and the substrate cover layer 214 of the redistribution structure 210 may be similar to Figure 4E The coupling of the component cover layer 224 of the electronic component 220 and the substrate cover layer 214 of the redistribution structure 210 shown in FIG. The coupling of the component interconnect 223 of the electronic component 220 and the substrate interconnect 213 of the redistribution structure 210 can be similar to Figure 4F The component interconnects 223 of the electronic component 220 and the substrate interconnects 213 of the redistribution structure 210 shown in FIG. 2 are similar or identical.

[0110] exist Figure 6G In the example shown in , the encapsulant 310 may be disposed over the substrate cover layer 214 and the electronic component 220. The encapsulant 310 may include or be referred to as a package body, a molded body, or a molded part. For example, the encapsulant 310 may include an epoxy molding compound, a resin, a filler-reinforced polymer, a B-stage pressed film, or a gel. The encapsulant 310 may be formed by compression molding, transfer molding, liquid body molding, vacuum lamination, paste printing, or film-assisted molding. Although Figure 6G The encapsulant 310 is shown on the back side of the electronic component 220 , but it is contemplated and understood that in various examples the encapsulant 310 may be coplanar with the back side of the electronic component 220 .

[0111] Figure 6H The electronic device 300 is shown in a later stage of manufacturing. Figure 6HIn the example shown in , the removable carrier 330 can be separated from the outer dielectric 211b and the outward terminal 212b. In some examples, the adhesive strength of the temporary bonding layer of the removable carrier 330 can be removed or reduced by providing heat, light, chemical solution or physical external force, thereby separating the removable carrier 330 from the outer dielectric 211b and the outward terminal 212b. Removing the removable carrier 330 exposes the outer dielectric 211b and the outward terminal 212b.

[0112] According to various examples, the external interconnect 320 may be disposed on the outward terminal 212b. In some examples, an under-bump metallization (UBM) may be disposed between the external interconnect 320 and the outward terminal 212b. The external interconnect 320 may be coupled to the outward terminal 212b. The external interconnect 320 may be coupled to the electronic component 220 through the conductive structure 212 of the redistribution structure 210. In some examples, the external interconnect 320 may include or be referred to as a conductive ball or bump (e.g., a solder ball or solder bump), a conductive pillar or a conductive pillar (e.g., a copper pillar or copper pillar), or a conductive pillar with a solder cap. In some examples, the external interconnect 320 may include tin (NS), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. For example, the external interconnect 320 may be formed by a reflow process after forming a conductive material including solder on the outward terminal 212 b of the conductive structure 212 by a ball drop process. In some examples, the height of the external interconnect 320 may be in a range of about 0.25 mm to about 1.5 mm. In some examples, the external interconnect 320 may be referred to as an external input / output terminal of the electronic device 300. In some examples, a singulation (e.g., sawing or cutting) operation may be performed through the encapsulant 310 and the redistribution structure 210 to provide individual electronic devices 300.

[0113] The apparatus and methods described herein tend to improve bonding performance by controlling the height of the cap layer adjacent to the interconnect. The interconnect may be recessed from the cap layer by a recessed height or depth. The recessed height is controlled by controlling the thickness of the cap layer. The controlled height of the cap layer tends to allow sufficient space to accommodate thermal expansion of the interconnect during bonding. The interconnect may be directly bonded without separating the bonded cap layer or other bonded dielectric. The interconnect has the exact amount of space to expand through thermal expansion or pressure to contact and bond with each other without forcing adjacent cap layers to separate.

[0114] The present disclosure includes reference to certain examples; however, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present disclosure. In addition, modifications may be made to the disclosed examples without departing from the scope of the present disclosure. Therefore, it is intended that the present disclosure is not limited to the disclosed examples, but that the present disclosure will include all examples that fall within the scope of the appended claims.

Claims

1. An electronic device, characterized in that: include: a first electronic component; a dielectric structure defining a through hole extending from an upper side of the dielectric structure to an upper side of the first electronic component; a first interconnect disposed in the through-hole, wherein an upper side of the first interconnect is substantially coplanar with the upper side of the dielectric structure; a seed layer located between the first interconnect and the dielectric structure, wherein an end of the seed layer is recessed from the upper side of the dielectric structure and the upper side of the first interconnect; as well as A cap layer is disposed on the dielectric structure and extends to the end of the seed layer between the first interconnect and the dielectric structure.

2. The electronic device according to claim 1, characterized in that: The cap layer includes a height of approximately 1 nanometer from the dielectric structure.

3. The electronic device according to claim 1, characterized in that: The cap layer defines an opening that exposes the upper side of the first interconnect for bonding.

4. The electronic device according to claim 3, characterized in that: The upper side of the first interconnector is recessed by a recessed height from the upper side of the cover layer.

5. The electronic device according to claim 1, characterized in that: The cover layer includes an L-shaped profile.

6. The electronic device according to claim 1, characterized in that: A first height of the cap layer above the end of the seed layer is greater than a second height of the cap layer above the dielectric structure.

7. A method for manufacturing an electronic device, characterized in that: include: providing a redistribution structure including a substrate interconnect; removing a portion of the first cap layer to expose a side of the substrate interconnect, wherein the side of the substrate interconnect is recessed from the side of the first cap layer by a recessed height; disposing an electronic assembly over the first cover layer, wherein the electronic assembly comprises a second cover layer and an assembly interconnect; bonding the second cover layer to the first cover layer; as well as Heat is applied to bond the substrate interconnect to the component interconnect.

8. The method according to claim 7, characterized in that The first cap layer and the second cap layer include an inorganic dielectric material.

9. The method according to claim 7, characterized in that: The redistribution structure includes an inter-dielectric, and wherein the first capping layer includes a thickness of approximately 1 nanometer measured from an upper side of the inter-dielectric.

10. The method according to claim 7, characterized in that The redistribution structure includes an inter-dielectric, and wherein the redistribution structure includes a seed layer between the inter-dielectric and the substrate interconnect.

11. The method according to claim 10, characterized in that The first cap layer extends to an end of the seed layer between the substrate interconnect and the inner dielectric.

12. The method according to claim 7, characterized in that The first cover layer includes an L-shaped profile.

13. The method according to claim 7, characterized in that Providing the substrate interconnection comprises: Disposing a conductive material over one side of the inter-dielectric of the redistribution structure and filling a via defined by the inter-dielectric; and The conductive material is removed from over the side of the inner dielectric to leave the conductive material protruding over the via.

14. A method for manufacturing an electronic device, characterized in that: include: Disposing a first electronic component; disposing a dielectric structure over the first electronic component, wherein sidewalls of the dielectric structure define a via extending from an upper side of the dielectric structure to the first electronic component; disposing a seed layer over the first electronic component, the upper side of the dielectric structure, and the sidewalls of the dielectric structure; disposing a first component interconnect over the seed layer, wherein the first component interconnect fills the via and covers the side of the dielectric structure; removing a portion of the first component interconnect to leave an upper side of the first component interconnect recessed from the seed layer; removing a portion of the seed layer to expose the upper side of the dielectric structure and leaving an end of the seed layer recessed from the dielectric structure and between the first component interconnect and the dielectric structure; disposing a first cap layer over the dielectric structure, the first cap layer extending to the end of the seed layer between the first component interconnect and the dielectric structure; as well as A portion of the first cover layer is removed to expose the upper side of the first component interconnect, wherein the upper side of the first component interconnect is recessed from the upper side of the first cover layer by a first recessed height.

15. The method according to claim 14, characterized in that The first recess has a height of about 1 nanometer.

16. The method according to claim 14, characterized in that Further including: providing a redistribution structure, the redistribution structure comprising a second cap layer and a substrate interconnection member located inside the redistribution structure; bonding the second cover layer to the first cover layer; as well as Heat is applied to bond the substrate interconnect to the first component interconnect.

17. The method according to claim 16, characterized in that The first cap layer and the second cap layer include an inorganic dielectric material.

18. The method according to claim 16, characterized in that Setting the redistribution structure further comprises: disposing the substrate interconnect on a first side of the second cap layer; and A portion of the second cap layer is removed to expose an upper side of the substrate interconnector, wherein the upper side of the substrate interconnector is recessed by a recess height from a second side of the second cap layer opposite to the first side of the second cap layer.

19. The method according to claim 14, characterized in that Further including: providing a second electronic assembly including a second cover layer and a second assembly interconnect; bonding the second cover layer to the first cover layer; as well as Heat is applied to bond the second component interconnect to the first component interconnect.

20. The method according to claim 16, characterized in that Further comprising disposing an encapsulant over the second cover layer and around the sidewalls of the first cover layer.

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