Modulating drive signal for power converter

Abstract

A circuit (100) includes a high side driver (124) having a high side pendulum control input, a high side drive input, and a high side drive output. The low-side driver (126) has a low-side pendulum control input, a low-side drive input, and a low-side drive output. The drive control circuitry (122) has a high-side drive control output, a low-side drive control output, and a pendulum control output. The high-side drive control output is coupled to the high-side drive input, and the low-side drive control output is coupled to the low-side drive input. The pressure pendulum control output is coupled to at least one of the high side pressure pendulum control input and the low side pressure pendulum control input, and the drive control circuitry (122) is configured to provide a pressure pendulum control signal at the pressure pendulum control output. The high-side and / or low-side drivers (124, 126) are configured to modulate a slew rate of the drive signal at its respective drive output based on the slew control signal.

Description

Technical Field

[0001] The present description relates to modulating a drive signal for a power converter. Background Art

[0002] Power converters are used in a variety of applications to provide electrical power. For example, a switching converter includes an arrangement of switches (such as power transistors) that are configured to convert electrical power from one form to another and provide a regulated voltage at the output terminal. Switching converters are typically designed to maintain a regulated output voltage over a range of operating conditions, including at startup and under a range of load conditions. The trend is to use larger area transistors in switching converters to reduce the resistance of the transistors and achieve faster switching frequencies. In order to reduce switching losses and maintain adequate efficiency at high switching frequencies, the driver can be configured to provide larger di / dt and dv / dt. However, larger di / dt and dv / dt can lead to increased electromagnetic interference (EMI). Summary of the invention

[0003] An example circuit described includes a high-side driver, a low-side driver, and a drive control circuit system. The high-side driver has a high-side slew control input, a high-side drive input, and a high-side drive output. The low-side driver has a low-side slew control input, a low-side drive input, and a low-side drive output. The drive control circuit system has a high-side drive control output, a low-side drive control output, and a slew control output. The high-side drive control output is coupled to the high-side drive input, and the low-side drive control output is coupled to the low-side drive input. The slew control output is coupled to at least one of the high-side slew control input and the low-side slew control input, and the drive control circuit system is configured to provide a slew control signal at the slew control output. At least one of the high-side driver and the low-side driver is configured to modulate the slew rate of the drive signal at its corresponding drive output based on the slew control signal.

[0004] Another example circuit includes a high-side driver configured to provide a high-side drive signal based on a high-side logic signal, wherein the high-side drive signal has a slew rate modulated based on a high-side slew control signal. The circuit also includes a drive control circuit system configured to provide the high-side logic signal, and a slew control logic configured to provide the high-side slew control signal.

[0005] Another example described relates to a system comprising a bridge circuit, a high-side driver and a low-side driver, and a drive control circuit system. The bridge circuit comprises a high-side transistor having a first current terminal, a second current terminal, and a high-side control terminal, wherein the first current terminal is coupled to an input voltage terminal. The bridge circuit also comprises a low-side transistor having a third current terminal, a fourth current terminal, and a low-side control terminal, wherein the third current terminal is coupled to the second current terminal, and the fourth current terminal is coupled to a ground terminal. The high-side driver has a high-side slew control input, a high-side drive input, and a high-side drive output, wherein the high-side drive output is coupled to the high-side control terminal. The low-side driver has a low-side slew control input, a low-side drive input, and a low-side drive output, wherein the low-side drive output is coupled to the low-side control terminal. The drive control circuit system has a high-side drive control output, a low-side drive control output, a low-side slew control output, and a high-side slew control output. The high-side driver control output is coupled to the high-side driver input, the low-side driver control output is coupled to the low-side driver input, the low-side slew control output is coupled to the low-side slew control input, and the high-side slew control output is coupled to the high-side slew control input. At least one of the high-side driver and the low-side driver is configured to modulate a slew rate of a drive signal at its corresponding driver output based on the slew control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of an example power converter circuit.

[0007] Figure 2 is a block diagram of a portion of a power converter circuit illustrating an example high-side driver.

[0008] Figure 3 is a circuit diagram of a portion of a power converter circuit illustrating another example high-side driver.

[0009] Figure 4 is a circuit diagram of a portion of a power converter circuit illustrating another example high-side driver.

[0010] Figure 5 and Figure 6 is a graph of EMI as a function of frequency showing an example comparison between fixed and variable slew rate drive signals under different operating conditions. DETAILED DESCRIPTION

[0011] The present description relates to systems and circuits configured to modulate drive signals for switching power converters, such as for reducing electromagnetic interference (EMI).

[0012] As an example, a circuit includes a high-side driver, a low-side driver and a drive control circuit system. The drive control circuit system is configured to provide a high-side logic signal and a low-side logic signal for controlling the high-side driver and the low-side driver. The high-side driver is configured to provide a high-side drive signal based on the high-side logic signal, and the low-side driver is configured to provide a low-side drive signal based on the low-side logic signal. The circuit may also include a slew control logic, which may be a part of the drive control circuit system or separated therefrom. In one example, the slew control logic is configured to provide a high-side slew control signal, and the high-side drive signal has a slew rate modulated based on the high-side slew control signal. As used herein, the slew rate of each drive signal may refer to the rise time, fall time, or both the rise and fall time of each drive signal. In some examples, the high-side driver is configured to modulate the slew rate of the drive signal in response to the high-side slew control signal within a number of switching cycles. In one example, the slew control logic can provide a high-side slew control signal to cause the high-side driver to change the slew rate through a sequence of different slew rates (e.g., different slew rates for each corresponding switching cycle). In other examples, the slew control logic rate can be configured to randomly determine the slew rate of each switching cycle. The low-side driver can also be configured to modulate the slew rate of the low-side drive signal in response to the low-side slew control signal provided by the slew control logic.

[0013] By actively changing the slew rate of the drive signal during circuit operation, the strength of the gate driver is modified from one switching cycle to another in a controlled manner, thereby generating a switching waveform with different rise and fall times. By modulating the slew rate of the drive signal, the drive signal presents an average slew rate over time. Therefore, the peaks and valleys in the spectrum of the power converter (these peaks and valleys vary based on the slew rate of the voltage at the switch node and based on the slew rate of the current through the transistor of the output stage) can also be averaged over several switching cycles, thereby reducing EMI over time. The scheme described herein can further reduce the EMI generated in the driver circuit system, especially the EMI generated at lower output currents. In addition, this averaging of the rise and fall times over several switching cycles can also reduce the impact of the operating environment and circuit board design, which may vary depending on different usage environments and end-user designs. Therefore, compared with fixed rise and fall times, the scheme described herein provides lower EMI values ​​in the spectrum on average over several cycles and a wide frequency range.

[0014] Figure 1 is a block diagram illustrating an example power converter circuit 100. The power circuit 100 includes a bridge circuit, such as a half-bridge or other power stage topology, having a high-side transistor QHS and a low-side transistor QLS. Figure 1In the example of , the high-side and low-side transistors are implemented as power field effect transistors (FETs), such as n-channel FETs (NFETs). In other examples, different types of transistors may be used, such as p-channel FETs (PFETs), insulated gate bipolar transistors (IGBTs), bipolar junction transistors (BJTs), laterally diffused metal oxide semiconductor (LDMOS) transistors, etc. Transistors QHS and QLS are coupled between first and second voltage terminals, illustrated as input power supply terminal 106 and ground terminal 108. Input power supply terminal 106 may be coupled to an input power supply (e.g., which is configured to provide input voltage VIN) via a parasitic inductance (shown as L1), and ground terminal 108 may be coupled to a ground terminal of circuit 100. Respective output terminals 110 and 112 of transistors QHS and QLS may be coupled together at a switch terminal (SW) 114 of circuit 100. Each of transistors QHS and QLS has a respective control input (e.g., a gate) coupled to respective drive outputs 116 and 118.

[0015] The drive circuit system 120 is configured to control transistors QHS and QLS. The drive circuit system 120 includes a drive control circuit 122, a high-side driver 124, and a low-side driver 126. For improved clarity, Figure 1 Various components of the converter 100 (e.g., error amplifier, pulse width modulation circuitry, filter circuitry, etc.) have been omitted from the drive circuitry 120 of FIG. Figure 1 In the example of , the drive control circuit 122 has a high-side drive control output 128, a low-side drive control output 130, and one or more slew control outputs (illustrated as a high-side slew control output 132 and a low-side slew control output 134). The high-side drive control output 128 is coupled to the high-side drive input of the high-side driver 124, and the low-side drive control output 130 is coupled to the low-side drive input of the low-side driver 126. The high-side slew control output 132 is coupled to the high-side slew control input of the high-side driver 124, and the low-side slew control output 134 is coupled to the low-side slew control input of the low-side driver 126. Figure 1 In the example of FIG. 1 , the circuit 100 includes a high-side slew control output and a low-side slew control output coupled to respective drivers 124 and 126. In other examples, the driver control 122 may provide a slew control output to only one of the high-side driver 124 or the low-side driver 126, or alternatively, provide a common slew control signal to each of the respective drivers 124 and 126.

[0016] The driver control circuit 122 includes a high-side slew control logic 136, a low-side slew control logic 138, and a control loop circuit (also referred to herein as a loop circuit) 140. The high-side slew control logic 136 is configured to provide a high-side slew control signal at an output 132. The low-side slew control logic 138 is configured to provide a low-side slew control signal at an output 134. The loop circuit 140 is configured to receive feedback representing an output voltage (VOUT) provided at an output 142 of the converter circuit 100, and determine a control logic signal for controlling each of the high-side driver 124 and the low-side driver 126. For example, the loop circuit includes an error amplifier configured to compare the feedback signal with a reference signal to generate a high-side logic signal and a low-side logic signal at 128 and 130. The high-side driver 124 is configured to provide a high-side drive signal HS_DRIVE to the control input of the high-side transistor QHS based on the high-side logic signal. As described herein, the high-side driver 124 is also configured to provide a high-side drive signal having a slew rate that is modulated based on the high-side slew control signal provided at 132. The low-side driver can be similarly configured to provide a low-side drive signal LS_DRIVE based on the low-side logic signal provided at 130, wherein the low-side drive signal has a slew rate that is modulated based on the low-side slew control signal 134.

[0017] In one example, the high-side driver 124 includes a circuit system configured to modulate the high-side drive signal HS_DRIVE at 116 by changing the slew rate of the drive signal from a given slew rate during one switching cycle to another slew rate during the next switching cycle based on the slew control signal at 132. During operation, the slew rate of the drive signal at 116 can be changed within a number of switching cycles. In one example, the slew rate can be changed from one cycle to another in a sequence of different slew rates (e.g., a sequence of two, three, four or more slew rates). In another example, the slew rate can be changed randomly (or pseudo-randomly) from one switching cycle to another, such as by randomly selecting the slew rate of each cycle from a set of defined slew rates.

[0018] The low-side driver 126 may also include a slew rate circuit system, which is configured to modulate the slew rate of the low-side drive signal LS_DRIVE at 118 by changing the slew rate of the drive signal from a given slew rate during a switching cycle to another slew rate during the next switching circuit system based on the slew control signal at 134. The modulated slew rate for the low-side drive signal at 118 may be the same or different from the slew rate for the high-side drive signal at 116. Drivers 124 and 126 and drive control circuit 122 may be configured to modulate the corresponding slew rate at a rate depending on the switching frequency of the power converter circuit 100 and the operating frequency of the device implementing the power converter, thereby providing an expected improvement in EMI. For example, at an operating frequency higher than 500MHz (e.g., 700MHz to 1GHz or higher), EMI reduction of 7dB or greater may be achieved by modulating the slew rate as described herein.

[0019] Figure 2 Another example of a power converter circuit 200 is depicted. The power converter circuit 200 provides a circuit that can be used to implement Figure 1 A useful example of a circuit of the power converter 100 is shown. Accordingly, Figure 2 Part of the description also refers to Figure 1 To improve clarity, Figure 2 Various components of the converter circuit 200 (e.g., an error amplifier, a pulse width modulation circuit system, etc.) have been omitted from the drive circuit system 120 of the converter circuit 200. The circuit 200 includes a control loop circuit 140 having a loop input 202 and logic outputs 204 and 206. The loop circuit 140 includes a circuit system that is configured to provide drive logic signals HS_ON and LS_ON at outputs 204 and 206, respectively, based on a feedback signal (shown as a feedback voltage VFB) received at the loop input 202. The HS_ON and LS_ON signals constitute enable signals for enabling the high-side driver and the low-side driver, respectively. The converter circuit 200 also includes a high-side slew control logic 136 and a low-side slew control logic 138. The high-side slew control logic 136, the low-side slew control logic 138, and the control loop circuit 140 can form a drive control circuit system (e.g., Figure 1 1 . The high-side slew control logic 136 has an input coupled to the logic output 204 and one or more outputs coupled to corresponding inputs of the high-side driver 124. The low-side slew control logic 138 has an input coupled to the logic output 206 and one or more outputs coupled to corresponding inputs of the high-side driver 124. In some examples, a single integrated slew control logic can be used regardless of whether one or both of the high-side driver and the low-side driver are configured to modulate the slew rate of the corresponding drive signal.

[0020] like Figure 2 As shown, the high-side slew control logic 136 includes a plurality of high-side slew control outputs 208, 210, and 212. The high-side driver 124 includes an inverter circuit 214 having a plurality (e.g., two or more) of drive paths 216, 218, and 220, each of which has an input coupled to a corresponding slew control output. Figure 2 In the example of FIG. 2 , the inverter circuit 214 includes three drive paths 216, 218, and 220. In other examples, the inverter circuit 214 may include any number of drive circuits in two or more such drive paths.

[0021] exist Figure 2 In the example of , each drive path includes an arrangement of inverters coupled in series between the corresponding slew control outputs 208, 210, and 212 and the input 222 of the charge pump input 222. For example, each drive path 216, 218, and 220 has a path input and a path output, wherein each path input is coupled to the corresponding high-side slew control output 208, 210, and 212. Each path output is coupled to the filter input 222, which can be coupled to the high-side drive output 230 through the charge pump 224 and the push-pull amplifier circuit 226. Therefore, each drive path 216, 218, and 220 is configured (e.g., with inverters of different sizes) to have different drive strengths for the corresponding drive paths. For example, path 216 includes an inverter that is larger than each of the other inverter paths 218 and 220, and inverter path 218 has a larger inverter than path 220. In some examples, the inverters in each path may also increase in size and thus strength in the order of such inverters from the input to the output of each path 216 (e.g., each inverter of the corresponding inverter path is larger than the previous inverter). By forming each of its transistors to have a relatively large area, a larger inverter can be achieved, which provides a higher current drive capability than configuring the inverter with transistors having a relatively small area. Due to the use of transistors with a larger area, the current drive capability is stronger, thereby improving the drive strength. The different drive strengths enable each path 216, 218, and 220 to provide a corresponding drive signal with a different slew rate. Therefore, the high-side slew logic 136 is configured to provide a logic signal to activate a corresponding one of the drive paths, and the high-side driver is configured to provide a high-side drive signal with a slew rate (e.g., rise time and / or fall time) depending on the drive strength of the activated drive path.

[0022] In one example, the high-side slew logic 136 is configured to activate one of the drive paths 216, 218, and 220 in one switching cycle and then activate the other drive path in a subsequent switching cycle, which switching cycles can be continuous cycles or distributed over different time periods within the sequence. The switching cycle can be set according to a clock signal (not shown) used by the drive control circuit system to provide the HS_ON and LS_ON signals. The high-side slew logic 136 can activate the drive paths according to a sequence (e.g., 216->218->220 or 220->218->216 or another sequence), activating one drive path in each switching cycle, and the sequence can be repeated or changed within a number of switching cycles. For example, the high-side slew control logic 136 includes a counter and a multiplexer, wherein the counter has a counter output coupled to a control input of the multiplexer, and the multiplexer output is coupled to the corresponding path input. The multiplexer can be configured to provide a HS_ON signal to the corresponding multiplexer output at 204 and drive the corresponding drive path based on the counter value. In other examples, other types of circuitry may be used to implement the high-side slew control logic 136 to control which of the drive paths 216 , 218 , or 220 is operable to provide a high-side drive signal with a corresponding slew rate for a corresponding switching cycle.

[0023] The charge pump 224 is configured to provide sufficient voltage to turn on the push-pull amplifier 226 to turn on the high-side transistor QHS. For example, the push-pull amplifier 226 includes transistors Q1 and Q2 coupled between the input power supply terminal 106 and the switch terminal 114. For example, Q1 has a control input (e.g., gate) coupled to the input power supply terminal 106, a first current terminal (e.g., source) coupled to the output of the charge pump 224, and a second current terminal coupled to the driver output 230. The driver output 230 is coupled to the control input (e.g., gate) of the high-side transistor QHS. Q2 has a control input (e.g., gate) coupled to the output of the inverter circuit 214. For example, the inverter circuit 214 can be configured to provide a slew rate adjusted control signal at the control input of Q2 from the selected inverter path (e.g., in the drive path for activating Q2) to turn on Q2 out of phase with Q1. Transistor Q2 also has a first current input (e.g., drain) coupled to the drain of transistor Q1 and a second current input (e.g., source) coupled to switch terminal 114. High-side transistor QHS has a first current terminal (e.g., source) coupled to input power supply terminal 106 and a second current terminal (e.g., drain) coupled to switch terminal 114. High-side driver 124 is configured to provide a drive signal HS_DRIVE at a drive output 230, and high-side transistor QHS is activated to couple switch terminal 114 to input voltage VIN to provide a voltage to the converter output (e.g., VIN) through the switch terminal. Figure 1 The output 142) is powered.

[0024] The low-side driver 126 has an output 234 coupled to a control input (e.g., gate) of the low-side transistor QLS. The low-side transistor QLS has a first current terminal (e.g., drain) coupled to the switch terminal 114 and a second current terminal (e.g., source) coupled to the ground terminal 108. The circuit 200 also includes a low-side slew control logic 138 having an input coupled to the output 206 and one or more slew control outputs 238 coupled to one or more corresponding inputs of the low-side driver 126. Furthermore, while an example of a high-side driver 124 for controlling conduction of the high-side transistor QHS has been provided, for improved clarity, this has been removed from FIG. Figure 2 The details of the low-side driver are omitted in the figure. The low-side driver 126 may include a circuit system similar to that described about the high-side driver 124, which is configured to provide a drive signal LS_DRIVE to control the low-side switch transistor QLS. For example, the low-side driver 126 may include several drive paths, wherein as described herein, each drive path has different corresponding drive strengths. The slew control logic 138 is configured to control which drive paths are operable to provide a drive signal LS_DRIVE to the low-side transistor QLS in the corresponding switching cycle. Therefore, the low-side driver 126 is configured to provide a drive signal LS_DRIVE at the output 234 based on the LS_ON logic signal. The converter circuit 200 is further configured to provide a regulated switch voltage at the switch terminal 114 based on the logic signal HS_ON and LS_ON and provide a final output voltage at the output (not shown). As described herein, due to the modulated gate drive signals HS_DRIVE and LS_DRIVE, each of the switch voltage at 114 and the converter output voltage shows reduced EMI.

[0025] Figure 3 Describing can be used to achieve Figure 1 100 is another example of a power converter circuit 300. Therefore, where appropriate, Figure 3 The description also refers to Figure 1. Circuit 300 includes a drive circuit system 301, which includes a high-side driver 124 and a low-side driver 126, which have corresponding drive outputs 116 and 118 coupled to the control input of a bridge circuit. The bridge circuit includes a high-side transistor QHS and a low-side transistor QLS. The high-side driver 124 is configured to provide a high-side drive signal at 116 to drive QHS, and the low-side driver 126 is configured to provide a low-side drive signal at 118 to drive QLS. As described herein, one or both of the drivers 124 and 126 of circuit 300 are configured to modulate the slew rate of one or more drive signals to reduce EMI during circuit operation. For improved clarity, Figure 3 Various components of the converter circuit 300 (eg, drive logic, error amplifier, pulse width modulation circuitry, etc.) have been omitted from the drive circuitry 301 of FIG.

[0026] exist Figure 3In the example of , the high-side driver 124 includes a loop circuit 302 for controlling a high-side drive signal HS_DRIVE in a control path, and the high-side drive signal HS_DRIVE is used to control the activation (e.g., turn on and off) of the high-side transistor QHS. The loop circuit 302 includes a diode-connected transistor Q3 coupled between a current source 304 and a ground terminal 108. The current source 304 is coupled to an input terminal 306 and is configured to supply a first input current at a first input of the loop circuit 302. The resistor R0 is coupled between the control input of the transistor Q3 and the control input of another transistor Q4. The coupling capacitor C_COUP is coupled between the second current input terminal 308 and the control input of the transistor Q4. The buffer capacitor C_BUF is coupled between the control input of the transistor Q4 and the ground terminal 108. The transistor Q4 has a first current terminal (e.g., source) coupled to the ground terminal 108, and a second current terminal (e.g., drain) coupled to the first current terminal (e.g., source) of another transistor Q5. In one example, Q4 and Q5 are NMOS transistors. Transistor Q5 includes a control input (e.g., gate) coupled to the output of a control circuit (e.g., control loop circuit 140) and a second current input (e.g., drain) coupled to startup terminal 316 through resistor R1 and startup capacitor C_BOOT. High-side driver 124 also includes an output transistor Q1. Transistor Q1 has a control input (e.g., gate) coupled to a second current input (e.g., drain) of transistor Q5. Transistor Q1 also has a first current input (e.g., drain) coupled to a driver output 116 and a second current input (e.g., source) coupled to a node terminal between resistor R1 and capacitor C_BOOT. Therefore, transistor Q1 is configured to provide a high-side drive signal (HS_DRIVE) at the driver output 116 to turn on QHS.

[0027] The high-side driver 124 also includes a capacitor network 312 coupled in parallel with C_BUF between the control input of transistor Q4 and the ground terminal 108. The capacitor network 312 is configured to provide a variable capacitance across capacitor C_BUF between the control input of transistor Q4 and the ground terminal 108 based on a slew control signal provided by the slew control logic 318. Figure 3In the example of, capacitor network 312 includes capacitors C1, C2, C3 and C4, each capacitor is coupled in series with corresponding switches SW1, SW2, SW3 and SW4 between the control input and ground terminal 108 of Q4. In one example, capacitors C1, C2, C3 and C4 in network 312 are binary weighted capacitors (e.g., with relative capacitances of 1x, 2x, 4x and 8x). Although C_BUF is shown as being independent of network 312, C_BUF can also be implemented as part of the network. In addition, there can be any number of capacitors in network 312, which can be switched into or out of the circuit. Transistor Q1 is configured to provide a high-side drive signal HS_DRIVE based on the operation of the loop circuit, and as described herein, the high-side drive information HS_DRIVE has a modulated slew rate.

[0028] As another example, the slew control logic 318 has an output 320 coupled to the control inputs of switches SW1, SW2, SW3, and SW4. The slew control logic 318 may be implemented by circuitry configured to control which one or more of the switches SW1, SW2, SW3, and / or SW4 are activated (e.g., turned on) to couple one or more corresponding capacitors C1, C2, C3, C4 into the circuit to provide a corresponding capacitance between the control input of transistor Q4 and the ground terminal 108. The capacitance between the control input of transistor Q4 and the ground terminal 108 is configured to control the activation rate of transistor Q4, which further controls Q1 and the rise and fall times (e.g., slew rate) of the high-side drive signal HS_DRIVE.

[0029] As described herein, the slew control logic 318 is configured to actively change the slew rate (e.g., rise time and / or fall time) of the high-side drive signal HS_DRIVE over a number of switching cycles (e.g., from one cycle to another). For example, the slew control logic 318 can provide a high-side slew control signal to change the time constant of the loop circuit 302, which causes the slew rate of the drive signal HS_DRIVE to change through a sequence of different slew rates (e.g., a different slew rate for each corresponding switching cycle). In other examples, the slew control logic rate 318 can be configured to randomly change the slew rate from one switching cycle to another. By actively changing the slew rate (e.g., rise time and / or fall time) of the high-side drive signal HS_DRIVE, the EMI of the circuit 300 can be reduced during operation. Figure 3In the example of , for simplicity, the pull-down path at the control input of the high-side transistor QHS (e.g., transistor Q2 coupled between the driver output 116 and the switch terminal 114) has been omitted. Such a pull-down path transistor Q2 can be configured to turn off QHS based on a control signal that is out of phase with the signal at the control input of Q1, and a modulated slew rate for controlling the pull-down can also be implemented as described herein.

[0030] The circuit 300 also includes a low-side driver 126 having a drive output 118 coupled to a control input (e.g., a gate) of a low-side transistor QLS. The low-side transistor QLS is coupled between the switch output SW and the ground terminal 108. The low-side driver 126 is configured to provide a low-side drive signal LS_DRIVE at 118 to drive QLS. In some examples, the low-side driver 126 may also include slew control logic and slew rate adjustment circuitry (e.g., a variable capacitor network) that is configured to modulate the slew rate of the low-side drive signal LS_DRIVE provided at 118. The slew control logic and circuitry of the low-side driver 126 may be implemented in the same or different ways, as described herein with respect to Figure 2 As described above for the high-side driver 124. In other examples, the low-side driver may be implemented without being configured at 118 to modulate the slew rate of the low-side drive signal.

[0031] Figure 4 Another example of a power converter circuit 400 is depicted. The power converter circuit 400 may be used to implement Figure 1 The converter circuit 100 is another example of a power converter. Accordingly, Figure 4 The description also refers to Figure 1 For improved clarity, in addition to using an alternative example of drive circuit 402 (instead of Figure 2 and Figure 3 In addition to the drive circuit), the converter circuit 400 can also be connected to Figure 2 The converter circuit is the same as Figure 1 , Figure 2 and Figure 3Similarly, the driver circuit 402 includes a high-side driver 124 and a low-side driver 126. The high-side driver 124 and the low-side driver 126 have respective drive outputs 116 and 118 coupled to the control input of a bridge (e.g., a half-bridge or full-bridge) circuit. The bridge circuit includes a high-side transistor QHS and a low-side transistor QLS. The high-side driver 124 is configured to provide a high-side drive signal at 116 to drive QHS, and the low-side driver 126 is configured to provide a low-side drive signal at 118 to drive QLS. As described herein, one or both of the drivers 124 and 126 of the circuit 400 are configured to modulate the slew rate of one or more drive signals to reduce EMI during circuit operation.

[0032] exist Figure 4 In the example of , the high-side driver 124 includes an inverter circuit 404, a filter 424, and a push-pull amplifier including transistors Q1 and Q2. A first current terminal (e.g., source) of transistor Q1 is coupled to a first (e.g., top) terminal of a boot capacitor C_BOOT, and a second terminal (e.g., drain) of transistor Q1 is coupled to a control terminal of a high-side transistor QHS. A first terminal (e.g., source) of transistor Q2 is coupled to a first terminal of a high-side transistor QHS, which is coupled to a switch terminal SW. A second terminal (e.g., drain) of transistor Q2 is coupled to a second terminal of transistor Q1, which is also coupled to a gate of transistor QHS. The control terminal of transistor Q2 is coupled to the inverter circuit 404.

[0033] Inverter circuit 404 has inputs 406 and 408 and output 410. Input 406 is coupled to the output of a control loop circuit (e.g., circuit 140) to receive a high-side ON (HS_ON) signal, and input 408 is coupled to another output of the control loop circuit to receive an inverted version of the HS_ON signal (illustrated as HS_ONz). Inverter circuit 404 includes transistor Q8, transistor Q9, transistor Q10, current mirror 412, variable resistor R_VAR, transistor Q11, resistor R2, and capacitor C1. For example, transistors Q8 and Q9 are PFETs, while transistors Q10 and Q11 are NFETs. Other types of transistors may be used in other examples. Output 410 is coupled to a first control input (e.g., source) of Q1 through a boot capacitor C_BOOT.

[0034] A first current terminal (e.g., source) of transistor Q8 is coupled to input power supply terminal 414 (e.g., at voltage VIN). A second current terminal (e.g., drain) of transistor Q8 is coupled to a first current terminal (e.g., source) of transistor Q9. A control terminal (e.g., gate) of transistor Q8 is coupled to an output of an inverter (not shown) configured to provide an inverted version of a high-side enable HS_ON signal (illustrated as HS_ONz). A second current terminal (e.g., drain) of transistor Q9 is coupled to a first current terminal (e.g., drain) of transistor Q10, which is also coupled to the bottom plate of capacitor C_BOOT. A control terminal (e.g., gate) of transistor Q9 is coupled to current mirror 412. A second current terminal (e.g., source) of transistor Q10 is coupled to ground terminal 108. A control terminal (e.g., gate) of transistor Q10 is coupled to a control terminal of transistor Q8.

[0035] The current mirror 412 includes a transistor Q12 and a transistor Q13. In one example, the transistors Q12 and Q13 are PFETs. In other examples, the transistors Q12 and Q13 may be implemented as other types of transistors. A first current terminal (e.g., source) of the transistor Q12 is coupled to an input voltage terminal 414. The input voltage terminal 414 is coupled to a control terminal of Q1 through a resistor R3. A second current terminal (e.g., drain) of the transistor Q13 is coupled to a control terminal of the transistor Q9. A control terminal (e.g., gate) of the transistor Q12 is coupled to a control terminal (e.g., gate) of the transistor Q13. A first current terminal (e.g., source) of the transistor Q12 is coupled to an input power supply terminal 414. A second current terminal (e.g., drain) of the transistor Q12 is coupled to a control terminal of the transistor Q12. A capacitor C1 is coupled between the control terminal of the transistor Q12 and the input power supply terminal 414. A resistor R_VAR (e.g., a variable impedance network) is coupled between a second current terminal (e.g., bias terminal) of the transistor Q13 and a ground terminal 108. The resistor R_VAR also includes a control input coupled to the output of the high-side slew control logic 420. As described herein, the high-side slew control logic 420 is configured to provide a slew control signal to define the resistance of the resistor R_VAR, which is configured to control (e.g., adjust) the slew rate of the high-side drive signal HS_DRIVE from one switching cycle to another switching cycle. For example, the high-side slew control logic 420 is configured to adjust the slew rate for each switching cycle with a sequence of defined slew rates, or to randomly change the slew rate from one cycle to another. Therefore, the impedance of the resistor R_VAR can be modulated in response to the slew control signal to define a corresponding slew rate modulated drive signal at the driver output.

[0036] Transistor Q8 is configured to switch current from an input power supply terminal 414 (e.g., at a voltage VIN) to transistor Q9. Transistor Q11 is configured to control current flowing through current mirror 412. A first current terminal (e.g., drain) of transistor Q11 is coupled to a second current terminal of transistor Q12 through resistor R2. A second current terminal (e.g., drain) of transistor Q11 is coupled to ground terminal 108. A control terminal (e.g., gate) of transistor Q11 is coupled to input 406 to receive an enable signal (shown as logic signal HS_ON). When high-side transistor QHS is turned on, transistor Q11 and transistor Q8 are turned on, which causes current to flow through transistors Q12 and Q13 of current mirror 412. The current flowing through transistor Q13 charges the control terminal of transistor Q9 at a rate determined by the resistance of resistor R_VAR and the capacitance at the control terminal of transistor Q9. When the input voltage at 414 decreases, in response to the high-side transistor QHS turning on, the voltage at the control terminal of transistor Q13 decreases (e.g., by discharging capacitor C1), and the voltage at the control terminal of transistor Q9 increases to control the slew rate of the gate drive signal HS_DRIVE for turning on the high-side transistor QHS.

[0037] exist Figure 4 In the example of , filter 424 is coupled between input voltage terminal 414 and the control terminal of transistor Q1. Filter 424 includes resistor R3 and capacitor C2. Resistor R3 is coupled between input voltage terminal 414 and the control terminal of transistor Q1. Capacitor C2 is coupled between the control terminal of transistor Q1 and ground terminal 108. Therefore, filter 424 is configured as a low-pass filter to low-pass filter the power supply voltage VIN at 414 and provide a more stable input voltage at the control terminal of transistor Q1 and the first current terminal of transistor Q13.

[0038] As described herein, the impedance (e.g., resistance) of resistor R_VAR can be adjusted (e.g., modulated) from one switching cycle to another switching cycle to change the conduction rate of transistor Q9, which determines the conduction time of gate pull-up transistor Q1 to further modulate the slew rate of gate drive signal HS_DRIVE based on slew control signal. The feedback path includes a variable impedance network coupled between bias control terminal and ground terminal, the variable impedance network having an impedance control input coupled to slew control output, and the impedance of the variable impedance network is modulated in response to slew control signal to define the corresponding modulated slew rate of the drive signal at the drive output. The impedance change of resistor R_VAR can depend on the configuration of variable resistor R_VAR, which can be configured according to the frequency and EMI requirements of the converter circuit. Low-side driver 126 can be configured in the same or similar manner as the high-side driver to modulate the slew rate of the low-side drive signal provided to the control input of low-side transistor QLS. Alternatively, the slew rate modulation feature can be omitted from the low-side driver in converter circuit 400.

[0039] Figure 5 and Figure 6 is a graph illustrating EMI of a power converter circuit (eg, any of circuits 100 , 200 , 300 , or 400 ) as a function of frequency. Figure 5 and Figure 6 Each of shows a comparison between fixed and variable slew rate drive signals under different operating conditions.

[0040] Figure 5 A comparative example of curves 502 and 504 is provided, which show EMI in dB over a frequency range of 30 MHz to 1000 MHz. Curve 502 is a reference curve representing no modulation of the slew rate (e.g., with a fixed slew rate), where the rise time is approximately 2.8 ns and the fall time is approximately 10 ns. Curve 504 shows the EMI of a circuit implementing slew rate modulation as described herein over the same frequency range (see, e.g., Figure 1-Figure 4 ). For curve 504, the slew rate of the high-side drive signal (e.g., HS_DRIVE) has a rise time selected sequentially for each switching cycle from eight different rise time values ​​(e.g., 1ns, 1.35ns, 1.81ns, 2.44ns, 3.28ns, 4.42ns, 5.4ns, and 8ns) from 1ns to 8ns. For simplicity and focusing on one edge (e.g., the rising edge), the fall time is fixed at 10ns. In other examples, as described herein, either or both of the rise and fall times can be modulated. Figure 5Examples show that EMI is significantly reduced (eg, improved by up to about 7 dB) when the slew rate is modulated as described herein, particularly for higher frequencies from about 700 MHz to about 1000 MHz.

[0041] Figure 6 Another comparative example of curves 602 and 604 is provided, which show EMI in dB over a frequency range of 30 MHz to 1000 MHz. Curve 602 is a reference curve representing the absence of slew rate modulation of the high-side drive signal (e.g., with a fixed slew rate), where the rise time and fall time of the high-side drive signal are both approximately 2.8 ns. Curve 604 shows EMI over the same frequency range when the circuit implements slew rate modulation as described herein. For curve 604, the circuit modulates the rise time and fall time for each switching cycle in sequence from eight different rise time values ​​from 1 ns to 8 ns (e.g., 1 ns, 1.35 ns, 1.81 ns, 2.44 ns, 3.28 ns, 4.42 ns, 5.4 ns, and 8 ns). Compared to Figure 5 similar, Figure 6 Examples show significant reductions in EMI (eg, up to about 10 dB improvement) when the slew rate is modulated as described herein, particularly for higher frequencies from about 700 MHz to about 1000 MHz.

[0042] In this specification, the numerical designations "first," "second," etc. do not necessarily correspond to the same designations in the claims herein.

[0043] In addition, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in the first example, device A is directly coupled to device B; or (b) in the second example, if the intervening element C does not change the functional relationship between device A and device B, device A is indirectly coupled to device B through intervening element C, so device B is controlled by device A via the control signal generated by device A.

[0044] In addition, in this specification, a device "configured to" perform a task or function can be configured (e.g., programmed and / or hardwired) by the manufacturer at the time of manufacture to perform the function and / or can be configured (or reconfigured) by the user after manufacture to perform the function and / or other additional or alternative functions. The configuration can be performed by firmware and / or software programming of the device, by the construction and / or layout of hardware elements and the interconnection of the device or a combination thereof. In addition, a circuit or device described herein as including certain components can be configured to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors and / or inductors) and / or one or more sources (such as voltage sources and / or current sources) can be changed to include only semiconductor elements within a single physical device (e.g., a semiconductor wafer and / or an integrated circuit (IC) package), and can be configured to be coupled to at least some passive elements and / or sources to form the structure at the time of manufacture or after manufacture, such as by an end user and / or a third party.

[0045] Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are possible.

Claims

1. A circuit comprising: a high-side driver having a high-side slew control input, a high-side drive input, and a high-side drive output; a low-side driver having a low-side slew control input, a low-side drive input, and a low-side drive output; as well as A drive control circuit system having a high-side drive control output, a low-side drive control output and a slew control output, wherein the high-side drive control output is coupled to the high-side drive input, the low-side drive control output is coupled to the low-side drive input, the slew control output is coupled to at least one of the high-side slew control input and the low-side slew control input, the drive control circuit system is configured to provide a slew control signal at the slew control output, and at least one of the high-side driver and the low-side driver is configured to modulate the slew rate of the drive signal at its corresponding drive output based on the slew control signal.

2. The circuit of claim 1 , wherein the at least one of the high-side driver and the low-side driver is configured to modulate the slew rate of the drive signal at its respective drive output over a number of switching cycles.

3. The circuit of claim 2 , wherein the at least one of the high-side driver and the low-side driver is configured to modulate the slew rate of the drive signal randomly through a sequence of different slew rates or within the number of switching cycles.

4. The circuit of claim 1, wherein: The high-side driver is configured to provide a high-side drive signal at the high-side drive output, the high-side drive signal having a corresponding slew rate modulated based on the slew control signal; and The low-side driver is configured to provide a low-side drive signal at the low-side driver output, the low-side drive signal having a corresponding slew rate based on the slew control signal.

5. The circuit of claim 1, wherein: The driver control circuit system includes a plurality of high-side slew control outputs, and The high-side driver includes an inverter circuit having a plurality of drive paths, each drive path having a different respective drive strength, wherein each drive path has a path input and a path output, each path input is coupled to a respective high-side slew control output, and each path output is coupled to the high-side drive output. 6 . The circuit of claim 5 , wherein the drive control circuitry includes slew control logic configured to control which of the plurality of drive paths is operable to provide the drive signal for a respective switching cycle.

7. The circuit of claim 1 , wherein the at least one of the high-side driver and the low-side driver comprises a loop-controlled feedback path coupled between a feedback input and the high-side driver output, wherein the feedback path comprises a variable impedance network coupled between a bias control terminal and a ground terminal, the variable impedance network having an impedance control input coupled to the slew control output, and an impedance of the variable impedance network is modulated in response to the slew control signal to define a corresponding modulated slew rate for a drive signal at a corresponding driver output.

8. The circuit of claim 7, wherein: The drive control circuit system includes a plurality of slew control outputs, and The variable impedance network includes a network of capacitors and switches coupled in parallel between the bias control terminal and the ground terminal, wherein each of the switches has a switch control input coupled to a respective one of the slew control outputs.

9. The circuit of claim 1, further comprising: a high-side transistor having a first current terminal, a second current terminal, and a high-side control terminal, wherein the high-side control terminal is coupled to the high-side driver output and the first current terminal is coupled to an input voltage terminal; A low-side transistor having a third current terminal, a fourth current terminal and a low-side control terminal, wherein the low-side control terminal is coupled to the low-side drive output, the third current terminal is coupled to the second current terminal, and the fourth current terminal is coupled to a ground terminal.

10. The circuit of claim 1 , wherein the drive control circuit system is configured to provide a high-side logic signal and a low-side logic signal at the high-side drive control output and the low-side drive control output, respectively, wherein each of the high-side logic signal and the low-side logic signal has a switching cycle length that is one of fixed or variable, and the slew rate of the drive signal varies from one cycle to another based on the slew control signal.

11. The circuit of claim 10, wherein the high-side driver is configured to modulate the slew rate of the high-side drive signal randomly through a sequence of different slew rates or over a number of switching cycles based on the slew control signal.

12. The circuit of claim 1 implemented as an integrated circuit, wherein the high-side driver, the low-side driver, and the drive control circuitry are located on a common substrate.

13. A circuit comprising: a high-side driver configured to provide a high-side drive signal based on the high-side logic signal, wherein the high-side drive signal has a slew rate modulated based on the high-side slew control signal; a driver control circuit system configured to provide the high-side logic signal; as well as A slew control logic is configured to provide the high-side slew control signal.

14. The circuit of claim 13, further comprising a low-side driver configured to provide a low-side drive signal based on a low-side logic signal provided by the drive control circuitry, wherein: The slew control logic includes a high-side slew control logic and a low-side slew control logic, wherein the high-side slew control logic is configured to provide the high-side slew control signal, and the low-side slew control logic is configured to provide a low-side slew control signal, and The low-side driver is configured to modulate a slew rate of the low-side drive signal in response to the low-side slew control signal. 15 . The circuit of claim 13 , wherein the high-side driver is configured to modulate the slew rate of the high-side drive signal within a number of switching cycles in response to the high-side slew control signal provided for the number of switching cycles. 16 . The circuit of claim 15 , wherein the high-side driver is configured to modulate the slew rate of the high-side drive signal randomly through a sequence of different slew rates or within the number of switching cycles. 17 . The circuit of claim 13 , wherein the high-side driver includes a feedback path having a variable impedance network, and the variable impedance network has an impedance that is modulated in response to the high-side slew control signal.

18. The circuit of claim 13, wherein the high-side logic signal has a switching cycle length that is one of fixed or variable, and the slew rate of the high-side drive signal varies from one cycle to another in response to the high-side slew control signal.

19. The circuit of claim 13, further comprising: a low-side driver configured to provide a low-side drive signal based on a low-side logic signal provided by the drive control circuitry; as well as A bridge circuit comprising: High-side transistor; as well as A low-side transistor, wherein the bridge circuit is configured to provide a switching voltage at a switch terminal thereof in response to the high-side drive signal and the low-side drive signal.

20. The circuit of claim 13 implemented as an integrated circuit wherein the high-side driver, the slew control logic, and the drive control circuitry are located on a common substrate.

21. A system comprising: A bridge circuit comprising: a high-side transistor having a first current terminal, a second current terminal, and a high-side control terminal, wherein the first current terminal is coupled to the input voltage terminal; and a low-side transistor having a third current terminal, a fourth current terminal, and a low-side control terminal, wherein the third current terminal is coupled to the second current terminal and the fourth current terminal is coupled to a ground terminal; a high-side driver having a high-side slew control input, a high-side drive input, and a high-side drive output, wherein the high-side drive output is coupled to the high-side control terminal; a low-side driver having a low-side slew control input, a low-side drive input, and a low-side drive output, wherein the low-side drive output is coupled to the low-side control terminal; and A drive control circuit system having a high-side drive control output, a low-side drive control output, a low-side slew control output and a high-side slew control output, wherein the high-side drive control output is coupled to the high-side drive input, the low-side drive control output is coupled to the low-side drive input, the low-side slew control output is coupled to the low-side slew control input, the high-side slew control output is coupled to the high-side slew control input, and at least one of the high-side driver and the low-side driver is configured to modulate the slew rate of the drive signal at its corresponding drive output based on the slew control signal.

22. The system of claim 21, further comprising: a high-side slew control logic configured to provide a high-side slew control signal; as well as A low-side slew control logic configured to provide a low-side slew control signal, wherein: The drive control circuitry is configured to provide a low-side logic signal at the low-side drive control output and a high-side logic signal at the high-side drive control output; The high-side driver is configured to provide a high-side drive signal based on the high-side logic signal, wherein the high-side drive signal has a slew rate modulated based on the high-side slew control signal; and The low-side driver is configured to provide a low-side drive signal based on the low-side logic signal, wherein the low-side drive signal has a slew rate modulated based on the low-side slew control signal.

23. The circuit of claim 22 , wherein the drive control circuit system is configured to provide a high-side logic signal and a low-side logic signal at the high-side drive control output and the low-side drive control output, respectively, wherein the high-side logic signal and the low-side logic signal have a switching cycle length that is one of fixed or variable, and the slew rate of the drive signal varies from one cycle to another in response to the slew control signal.

24. The circuit of claim 23, wherein the high-side driver is configured to modulate the slew rate of the high-side drive signal randomly through a sequence of different slew rates or over a number of switching cycles.

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