Method, circuit and power supply for adjusting output setup time

Abstract

The invention relates to a method, a circuit and a power supply for adjusting output setup time. The method comprises the following steps: carrying out multi-point sampling on an output signal to obtain a plurality of output signal values; comparing the plurality of output signal values with a signal value of each moment corresponding to a pre-fitted curve to obtain a comparison result; outputting an enable signal according to the comparison result, and determining the on-off state of the clamping circuit based on the enable signal; and adjusting the output establishment time according to the on-off state of the clamping circuit. Based on the scheme, the state of the enable signal is determined through logic judgment, and the on-off of the clamping circuit is controlled through the enable signal, so that the error clamping phenomenon can be prevented.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a method, circuit and power supply for adjusting output settling time. Background Art

[0002] In the field of electronic testing, especially in the testing of semiconductor devices, the VI source (voltage and current source) is one of the core components of the test equipment, which is used to provide accurate and controllable voltage and current to evaluate the performance of the device under test (DUT). This type of test usually requires the VI source to respond quickly and accurately and maintain a stable output so that the DC parameters of the DUT can be accurately measured.

[0003] In current technology, the VI source uses its integral characteristics to ensure the stability and adaptability of the output. Ideally, the output settling time of the VI source should be determined only by the integral characteristics. However, in practical applications, the output settling time is affected by many factors, including the influence of the clamping circuit. For example, in FVCI (constant voltage clamping mode), even when the output is unloaded, the clamping circuit will still limit the output slew rate of the integral stage, thereby affecting the output settling time.

[0004] When using a traditional clamping circuit, regardless of whether the clamping protection function is triggered, the output of the integral stage is affected by the clamping circuit, which is prone to "false clamping". This phenomenon causes the integral stage slew rate to decrease, thereby slowing down the actual output settling time of the VI source, thereby reducing the test efficiency. Summary of the invention

[0005] In view of the above problems in the prior art, the present application provides a method, circuit and power supply for adjusting the output setup time, which can avoid the false clamping phenomenon to a certain extent, thereby reducing the impact of the false clamping on the output setup time, shortening the output setup time and improving the test efficiency.

[0006] To achieve the above-mentioned purpose, the first aspect of the present application provides a method for adjusting the output settling time, comprising: performing multi-point sampling on the output signal to obtain multiple output signal values; comparing the multiple output signal values ​​with the signal values ​​at each moment corresponding to a pre-fitted curve to obtain a comparison result; outputting an enable signal according to the comparison result, and determining the on-off state of the clamping circuit based on the enable signal; and adjusting the output settling time according to the on-off state of the clamping circuit.

[0007] From the above, the present application adds a false clamping judgment process (comparing multiple output signal values ​​with the signal values ​​at each moment corresponding to the pre-fitted straight line), and can disable the clamping function by controlling the enable signal when false clamping occurs, thereby avoiding the subsequent false clamping phenomenon. In addition, the false clamping judgment process of the present application is to compare and analyze multiple sampling points and preset fitting straight lines, and judge whether there is a false clamping phenomenon based on the comparison results, thereby solving the false clamping problem, shortening the output settling time, and improving the test efficiency.

[0008] As an implementation of this aspect, before obtaining a comparison result by comparing the multiple output signal values ​​with the signal values ​​at each moment corresponding to the pre-fitted curve, the method further includes:

[0009] Determine that the clamp circuit sends a clamp circuit alarm signal; wherein the clamp circuit alarm signal is output by the clamp circuit when a preset trigger condition is met, and the clamp alarm signal includes a positive clamp alarm signal and a negative clamp alarm signal.

[0010] As an implementation of the present aspect, the step of obtaining a comparison result by comparing the multiple output signal values ​​with the signal values ​​at each moment corresponding to a pre-fitted curve, and outputting an enable signal according to the comparison result, includes: determining whether the output signal value is a positive value or a negative value; when the output signal value is a positive value: comparing the multiple output signal values ​​with the first values ​​at each moment corresponding to a first straight line, respectively, to obtain a first comparison result, and outputting a first enable signal according to the first comparison result; wherein the first enable signal is used to control the on-off of a positive clamping circuit, and the first straight line is a pre-fitted positive clamping judgment straight line; when the output signal value is a negative value: comparing the multiple output signal values ​​with the second values ​​at each moment corresponding to a second straight line, respectively, to obtain a second comparison result, and outputting a second enable signal according to the second comparison result; wherein the second enable signal is used to control the on-off of a negative clamping circuit, and the second straight line is a pre-fitted negative clamping judgment straight line.

[0011] From the above, the present application uses pre-constructed comparison curves to judge whether the positive clamping circuit has a false clamping phenomenon, and to judge whether the negative clamping circuit has a false clamping phenomenon, so that the false clamping judgment can be made more scientifically and reasonably.

[0012] As an implementation of this aspect, the first straight line includes:

[0013]

[0014] Wherein, t represents time t; W(t)1 is the signal value corresponding to time t in the first straight line; Range is the signal value of the full scale; VCP_SET is the pre-set positive clamping coefficient; K_VC is the derating coefficient; K_VH is the time derating coefficient; TD is a debugging parameter used to determine the detection time interval, which is an integer multiple of the data sampling period.

[0015] As an implementation of this aspect, the second straight line includes:

[0016]

[0017] Wherein, t represents time t; W(t)2 is the signal value corresponding to time t in the second straight line; Range is the signal value of the full scale; VCN_SET is the preset negative clamping coefficient; K_VC is the derating coefficient; K_VH is the time derating coefficient; TD is a debugging parameter used to determine the detection time interval, which is an integer multiple of the data sampling period.

[0018] As described above, the parameters in the first straight line and the second straight line can be adjusted arbitrarily, so as to be applicable to various application scenarios.

[0019] As an implementation method of the present aspect, the multiple output signal values ​​are compared with the first values ​​at each moment corresponding to the first straight line, a first comparison result is obtained, and a first enable signal is output according to the first comparison result, including: if the multiple output signal values ​​are all less than or equal to the first value at each moment corresponding to the first straight line, the first enable signal is controlled to be in an invalid state, and the invalid state of the first enable signal indicates that the positive clamp circuit is disconnected; if among the multiple output signal values, there is a value greater than the first value at the moment corresponding to the first straight line, the first enable signal is controlled to maintain a valid state, and the valid state of the first enable signal indicates that the positive clamp circuit is connected.

[0020] As an implementation of this aspect, the following also includes:

[0021] After controlling the first enable signal to be in an invalid state, if the following conditions are met, controlling the first enable signal to be in a valid state:

[0022] Determining that the positive clamp circuit stops outputting the positive clamp alarm signal; or,

[0023] VC≥Range*VCP_SET*K_VC

[0024] Among them, VC is the actual output signal value of the power supply, Range is the full-scale signal value; VCP_SET is the pre-set positive clamping coefficient; K_VC is the derating coefficient.

[0025] As an implementation method of the present aspect, the multiple output signal values ​​are compared with the second values ​​at each moment corresponding to the second straight line, a second comparison result is obtained, and a second enable signal is output according to the second comparison result, including: if the multiple output signal values ​​are all greater than or equal to the second values ​​at each moment corresponding to the second straight line, the second enable signal is controlled to be in an invalid state, and the invalid state of the second enable signal indicates that the negative clamping circuit is disconnected; if among the multiple output signal values, there is a second value less than the second value at the moment corresponding to the second straight line, the second enable signal is controlled to remain in a valid state, and the valid state of the second enable signal indicates that the negative clamping circuit is connected.

[0026] The method further includes: after controlling the second enable signal to be in an invalid state, controlling the second enable signal to be in a valid state if the following conditions are met:

[0027] Determine that the negative clamp circuit stops outputting the negative clamp alarm signal; or,

[0028] VC≤Range*VCN_SET*K_VC

[0029] Among them, VC is the actual output signal value of the power supply, Range is the full-scale signal value; VCN_SET is the preset negative clamping coefficient; K_VC is the derating coefficient.

[0030] From the above, the false clamping judgment of the positive clamping and the negative clamping can be realized and the on-off of the clamping circuit can be controlled, thereby avoiding the occurrence of subsequent false clamping phenomena.

[0031] As an implementation method of this aspect, it also includes: at the initial power-on, controlling the first enable signal and / or the second enable signal to be in a valid state, and the valid state indicates that the clamping function of the positive clamping circuit and / or the negative clamping circuit is in an on state.

[0032] The second aspect of the present application provides a circuit for adjusting output setup time, which is used to adjust its output setup time based on the method described in any one of the first aspects, including: a control chip, which is used to receive multiple output signals, compare the multiple output signal values ​​with the signal values ​​at each moment corresponding to a pre-fitted straight line to obtain a comparison result, and output an enable signal according to the comparison result; wherein the multiple output signals are obtained by multi-point sampling of the output signals; the enable signal includes a first enable signal and a second enable signal; a positive clamp circuit, which is used to receive the first enable signal and control the on-off state of the positive clamp circuit based on the first enable signal; a negative clamp circuit, which is used to receive the second enable signal and control the on-off state of the negative clamp circuit based on the second enable signal; the control chip is also used to adjust the output setup time according to the on-off state of the positive clamp circuit or the negative clamp circuit.

[0033] As described above, by realizing the mis-clamping judgment in the control chip in the form of digital signals, material cost and PCB area are saved, and debugging is convenient. In addition, the beneficial effects of this aspect can also refer to the description of the beneficial effects of each part of the first aspect above.

[0034] As an implementation of this aspect, the positive clamp circuit includes a first control device for controlling the on and off of the positive clamp circuit based on the first enable signal; the negative clamp circuit includes a second control device for controlling the on and off of the negative clamp circuit based on the second enable signal.

[0035] A third aspect of the present application provides a power supply, comprising the circuit described in the second aspect above.

[0036] The beneficial effects of this aspect can also be found in the description of the beneficial effects of each part of the first aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The various technical features of the present application and the relationship between them are further explained below with reference to the accompanying drawings. The accompanying drawings are exemplary, and some technical features are not shown in actual proportion. In addition, some drawings may omit technical features that are commonly used in the technical field to which the present application belongs and are not essential for understanding and implementing the present application, or additional technical features that are not essential for understanding and implementing the present application may be shown. In other words, the combination of the various technical features shown in the accompanying drawings is not used to limit the present application. In addition, throughout the present application, the same figure numbers refer to the same content. The specific description of the drawings is as follows:

[0038] Figure 1 A schematic diagram of a structure of a power supply loop provided in an embodiment of the present application;

[0039] Figure 2 A flowchart of a method for adjusting output setup time provided in an embodiment of the present application;

[0040] Figure 3 A schematic diagram of the structure of a circuit for adjusting output settling time provided in an embodiment of the present application;

[0041] Figure 4 A schematic diagram of mis-clamping judgment provided in an embodiment of the present application;

[0042] Figure 5 A flowchart of a circuit for adjusting output settling time provided in an embodiment of the present application;

[0043] Figure 6 A flow chart of mis-clamping judgment performed within a control chip provided in an embodiment of the present application;

[0044] Figure 7 The following are simulation effect diagrams before and after optimization provided in the embodiments of the present application. DETAILED DESCRIPTION

[0045] The technical solution provided by the present application is further described below with reference to the accompanying drawings and examples. It should be understood that the business scenarios provided in the examples of the present application are mainly to illustrate possible implementation methods of the technical solution of the present application and should not be interpreted as the sole limitation of the technical solution of the present application. It is known to those skilled in the art that with the evolution of the system structure and the emergence of new business scenarios, the technical solution provided by the present application is also applicable to similar technical problems.

[0046] It should be understood that the embodiments of the present application provide a solution for adjusting the output settling time. Since the principles of solving the problems in these technical solutions are the same or similar, some repetitions may not be repeated in the following specific embodiments, but it should be considered that these specific embodiments have been referenced to each other and can be combined with each other.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present application. In case of any inconsistency, the meaning described in this specification or the meaning derived from the contents recorded in this specification shall prevail. In addition, the terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0048] In order to accurately describe the technical content of this application and to accurately understand the present invention, the following explanations or definitions are given for the terms used in this specification before describing the specific implementation methods:

[0049] 1) Positive clamping: Positive clamping refers to the process of limiting the highest value of the signal to a preset maximum value. That is, when the input signal exceeds the preset positive threshold, the circuit will "clamp" it at this positive threshold to prevent the signal value (voltage or current) from further increasing.

[0050] 2) Negative clamping: Negative clamping refers to the process of limiting the lowest value of the signal to a preset minimum value. That is, when the input signal is lower than the preset negative threshold, the circuit will "clamp" it at this negative threshold to prevent the signal value (voltage or current) from further decreasing.

[0051] Before introducing the solution of the present application, the scenarios in which the solution for adjusting the output settling time provided in the embodiments of the present application can be applied are first introduced.

[0052] The solution for adjusting the output settling time provided by the present application can be applied to application scenarios with high requirements for voltage and current control, especially scenarios that require fast response and high-precision testing, and can achieve the purpose of shortening the output settling time and improving test efficiency by eliminating the "false clamping" phenomenon. For example: This solution can be applied to multiple fields such as semiconductor testing, electronic equipment testing, integrated circuit design and verification, etc. The solution for adjusting the output settling time provided by the present application can eliminate the false clamping phenomenon, thereby helping to shorten the output settling time in the above-mentioned test tasks and improve test efficiency.

[0053] It should be understood that the above application scenarios are exemplary descriptions and are not intended to limit the scope of this application.

[0054] Next, the solution of the present application is described in detail.

[0055] like Figure 1 The power supply loop 10 provided in an embodiment of the present application is shown (for example, it can be a VI source, and the VI source is used as an example for description below, but it is not intended to limit the present application), including an analog-to-digital converter (ADC), an FPGA chip, a main digital-to-analog converter (DAC), a NULL stage, an integration stage, a power amplifier (PA), a clamp DAC, a clamp circuit and a switch.

[0056] Among them, the ADC is used to collect the output signal of the VI source, which includes a current output signal (Iback) or a voltage output signal (Vback), and performs analog-to-digital conversion on the collected output signal of the VI source to output a digital signal. The FPGA chip is connected to the ADC to receive the digital signal sent by the ADC, and performs relevant control based on the received digital signal (such as analyzing and judging the mis-clamping phenomenon, such as controlling the signal size, etc.). The main DAC is connected to the FPGA chip to perform digital-to-analog conversion on the result obtained by the FPGA chip control processing to output an analog signal. The NULL stage is connected to the main DAC to receive the analog signal output by the main DAC, and process the received signal and the feedback signal (feedback) (such as difference) to obtain an error signal. The integration stage is connected to the NULL stage to receive the error signal sent by the NULL stage, and perform integration operation to obtain an integration signal. The PA is connected to the integration stage to receive the integration signal sent by the integration stage, and perform power amplification processing on the received integration signal to obtain the required signal value. In the VI source loop, the clamping DAC is connected to the FPGA to perform digital-to-analog conversion on the signal output by the FPGA to obtain an analog signal output to the clamping circuit. The clamp circuit is connected to the clamp DAC and is used to receive the data sent by the clamp DAC and output it to the integration stage after clamp control. In the VI source, the switch is used to control whether the clamp circuit is connected.

[0057] exist Figure 1 In the VI source loop 10 shown, if the clamping circuit adopts the clamping circuit in the prior art, it is easy to cause mis-clamping, thereby affecting the output settling time of the VI source. Therefore, the embodiment of the present application provides a method as follows Figure 2 The method for adjusting the output settling time shown includes steps S510-S540, and each step is described in detail below.

[0058] S510: Perform multi-point sampling on the output signal to obtain multiple output signal values.

[0059] As an implementation, the output signal of the VI source can be directly sampled at multiple points by a control chip (e.g., an FPGA chip) to obtain multiple output signal values. As another implementation, the output signal of the VI source can be sampled at multiple points by an ADC to obtain multiple output signal values, and then the multiple output signal values ​​are sent to the control chip for corresponding processing.

[0060] In this embodiment, by sampling the output signal at multiple points and performing subsequent processing based on the obtained multiple output signal values, the occurrence of false clamping can be avoided, thereby shortening the output settling time.

[0061] S520: Obtain a comparison result according to the plurality of output signal values ​​and the signal values ​​at each moment corresponding to the pre-fitted straight line.

[0062] In this embodiment, before the control chip compares the multiple output signal values ​​with the signal values ​​at each moment corresponding to the pre-fitted curve to obtain a comparison result, the method further includes:

[0063] Determine that the clamp circuit sends a clamp alarm signal; wherein the clamp alarm signal is output by the clamp circuit when a preset trigger condition is met, and the clamp alarm signal includes a positive clamp alarm signal and a negative clamp alarm signal.

[0064] Specifically, after receiving the clamping alarm signal output by the clamping circuit, the control chip performs a judgment and analysis on whether the positive / negative clamping circuit is mis-clamped, wherein the clamping alarm signal includes a positive clamping alarm signal and a negative clamping alarm signal. The specific triggering conditions are shown in the following embodiments and are not introduced in detail here.

[0065] It should be understood that in this embodiment, a plurality of output signal values ​​are compared with a pre-fitted curve, and the type of the pre-fitted curve may be a straight line, a plane curve, etc., without specific limitation.

[0066] S530: Output an enable signal according to the comparison result, and determine the on / off state of the clamp circuit based on the enable signal.

[0067] It should be understood that in this embodiment, the on-off state of the clamp circuit refers to whether the clamp circuit is connected to the integral stage, which can be implemented by a two-choice switch, a relay, etc. The specific implementation method is not specifically limited here.

[0068] Next, combine Figure 3 The circuit shown is used to illustrate the execution process of step S520 and step S530.

[0069] like Figure 3 A circuit for adjusting output settling time is shown. The circuit 20 for adjusting output settling time includes a control chip 210, a positive clamp circuit 220 and a negative clamp circuit 230. The figure also shows an example structure of an integration circuit 240 connected to the clamp circuit. Next, the above steps are described in combination with various parts of the circuit.

[0070] The control chip 210 is used to receive the multiple output signals obtained in step S510, and then compare the multiple output signal values ​​with the signal values ​​at each moment corresponding to the pre-fitted straight line to obtain a comparison result, and output an enable signal according to the comparison result.

[0071] As an implementation manner, the control chip 210 may be a FPGA chip.

[0072] In this embodiment, since the clamp circuit is divided into a positive clamp circuit and a negative clamp circuit, the enable signal includes a first enable signal and a second enable signal, the first enable signal is used to control the on / off state of the positive clamp circuit, and the second enable signal is used to control the on / off state of the negative clamp circuit. Similarly, the pre-fitted straight line also includes a pre-fitted first straight line and a pre-fitted second straight line. When the output signal value is a positive value, the positive clamp needs to be considered at this time, so it is necessary to compare the multiple output signal values ​​with the first values ​​corresponding to the pre-fitted first straight line at each moment to obtain a first comparison result, thereby outputting the first enable signal for controlling the on / off of the positive clamp circuit according to the first comparison result; and when the output signal value is a negative value, the negative clamp needs to be considered at this time, so it is necessary to compare the multiple output signal values ​​with the second values ​​corresponding to the pre-fitted second straight line at each moment to obtain a second comparison result, thereby outputting the second enable signal for controlling the on / off of the negative clamp circuit according to the second comparison result.

[0073] Specifically, the pre-fitted first straight line (positive clamp fitting straight line) can be determined as follows:

[0074]

[0075] Specifically, the pre-fitted second straight line (negative clamp fitting straight line) can be determined as follows:

[0076]

[0077] In the above formula:

[0078] t represents time t;

[0079] W(t)1 represents the signal value corresponding to time t in the first straight line;

[0080] W(t)2 represents the signal value corresponding to time t in the second straight line;

[0081] Range represents the full-scale signal value, which includes the full-scale voltage value V-Range or the full-scale current value I-Range;

[0082] VCP_SET is a preset positive clamp coefficient, which determines the ratio of the maximum voltage or current value allowed by the system to the full range (V-Range or I-Range) under normal working conditions. For example, if the voltage full range Vrange is 10V, and VCP_SET is set to 0.8, the forward clamp value set by the system is 8V; similarly, if the current full range I-Range is 10A, and VCP_SET is set to 0.8, the forward clamp value set by the system is 8A.

[0083] VCN_SET is the preset negative clamping coefficient, which can be understood by referring to the understanding of positive clamping;

[0084] K_VC is the derating factor, which is used to adjust the slope of the fitting line. In practical applications, it can be further reduced or increased to ensure the applicability of the fitting line.

[0085] K_VH is the time derating factor, which is used to dynamically adjust the slope of the fitting line based on time t. In some cases, K_VH is introduced to achieve a more sophisticated control strategy, such as allowing a higher voltage or current at the beginning of system startup, and then gradually reducing the allowed voltage or current value as the running time increases, ultimately improving the applicability of the fitting line.

[0086] TD is a debugging parameter used to determine the detection time interval. Specifically, TD is used to determine the time interval between points of the adjustment fitting straight line. It is an integer multiple of the data sampling period. This ensures that each adjustment occurs at the same phase, thereby improving the accuracy and consistency of detection judgment.

[0087] In this embodiment, the parameter values ​​(i.e., Range, VCP_SET, VCN_SET, K_VC, K_VH, TD) used in pre-fitting the first straight line and the second straight line can be input through a PC, and the control chip performs straight line fitting after receiving these parameter values, thereby obtaining a corresponding fitted straight line. Then, the control chip performs multi-point acquisition of the output signal of the VI source, and compares the multiple output signal values ​​acquired with the values ​​at each moment on the corresponding fitted straight line, thereby analyzing and judging whether there is a mis-clamping phenomenon based on the comparison result, and thereby selecting to turn on or off the clamping function by controlling the value of the enable signal.

[0088] In this embodiment, when the output signal value of the VI source is a positive value, multiple output signal values ​​are compared with the first value of each moment corresponding to the pre-fitted first straight line. If there is a first value higher than the first value at the moment corresponding to the first straight line among the multiple output signal values, it means that the output signal needs to be positively clamped, otherwise, it means that the output signal does not need to be positively clamped. When the output signal value of the VI source is a negative value, multiple output signal values ​​are compared with the second value of each moment corresponding to the pre-fitted second straight line. If there is a second value lower than the second value at the moment corresponding to the second straight line among the multiple output signal values, it means that the output signal needs to be negatively clamped, otherwise, it means that the output signal does not need to be negatively clamped.

[0089] Specifically, the implementation process of comparing the multiple output signal values ​​with the first values ​​at each moment corresponding to the pre-fitted first straight line to obtain the first comparison result, and outputting the first enable signal according to the first comparison result (i.e., the determination of the positive clamp) includes:

[0090] The output signal values ​​at n moments are collected, and the output signal values ​​at the n moments are respectively compared with the first values ​​at the corresponding moments in the first straight line, so that n comparison results can be obtained. In the n comparison results, if all the output signals are less than or equal to the first values ​​at the corresponding moments in the first straight line, it means that there is no need to perform positive signal clamping, that is, it is determined that mis-clamping has occurred, so at this time, the first enable signal is controlled to output an invalid state, so that the positive clamping circuit is disconnected. In the n comparison results, if there is one or more times (that is, there are occurrences) when the output signal is greater than the first value at the moment corresponding to the first straight line, it means that the positive clamping threshold is exceeded, and the positive clamping function needs to be turned on at this time, that is, it is determined that mis-clamping has not occurred, so at this time, the first enable signal output is controlled to remain in a valid state, so that the positive clamping circuit is connected.

[0091] It should be understood that when the power is initially turned on, the first enable signal is in a valid state, that is, the clamping function of the positive clamping circuit is in an on state, and the control chip determines whether there is a false clamping phenomenon after a positive clamping alarm signal is generated; only when it is determined that a false clamping phenomenon has occurred, the clamping function of the positive clamping circuit will be controlled to be turned off through the state of the first enable signal.

[0092] It should be understood that the first enable signal can be represented by a high or low level to indicate whether it is valid or invalid, for example, 1 indicates a valid state and 0 indicates an invalid state; or 0 indicates a valid state and 1 indicates an invalid state.

[0093] In this embodiment, after it is determined that mis-clamping has occurred and the positive clamping circuit is disconnected, the first enable signal can be controlled to be in a valid state after the following conditions are met, thereby restoring the positive clamping function:

[0094] Determining that the positive clamp circuit stops outputting the positive clamp alarm signal; or,

[0095] VC≥Range*VCP_SET*K_VC

[0096] Among them, VC is the actual output signal of the power supply, Range is the signal value of the full scale; VCP_SET is the pre-set positive clamping coefficient; K_VC is the derating factor, which is used to adjust the actual clamping percentage used.

[0097] It should be understood that in this embodiment, when it is determined that the positive clamping circuit stops outputting the positive clamping alarm signal, the positive clamping end alarm can be confirmed, that is, when the positive clamping end alarm occurs, the first enable signal can be controlled to be in a valid state to restore the positive clamping function.

[0098] It should be understood that in this embodiment, after the positive clamp function is turned off, when it is determined that the actual output signal VC of the power supply is greater than or equal to the set voltage value Range*VCP_SET*K_VC, the positive clamp function needs to be restored.

[0099] By setting the recovery condition of the positive clamp function, the clamp protection function can be better played on the basis of improving the test efficiency.

[0100] For example, Figure 4 As shown, whether mis-clamping occurs is determined by comparing the relationship between the actually sampled voltage value VC and the voltage values ​​of each point on the pre-fitted first straight line W(t)1.

[0101] During the comparison process of t1, the actual sampling voltage VC from the first sampling point to the fourth sampling point is smaller than the corresponding point on the first straight line W(t)1, while at the fifth sampling point, the actual sampling voltage VC is greater than the corresponding point on the first straight line W(t)1, indicating that the positive clamping function needs to be turned on (default state), that is, no false clamping occurs. At this time, the judgment of t1 should be ended and the judgment of t2 should be turned on. In t2, since the result of 9 comparisons (9 sampling points) is that the actual sampling voltage VC is all smaller than the voltage value on the first straight line, it means that false clamping has occurred, and the positive clamping function needs to be disabled through the first enable signal. After disabling the positive clamping function, the size relationship between VC and Range*VCP_SET*K_VC is judged to determine whether to re-enable the positive clamping function.

[0102] It should be understood that the 5 comparisons at t1 and the 9 comparisons at t2 in the above examples are exemplary descriptions, and the number of sampling times can be changed as required in other embodiments.

[0103] Specifically, the implementation process of comparing the multiple output signal values ​​with the second values ​​at each corresponding moment on the pre-fitted second straight line to obtain the second comparison result, and outputting the second enable signal according to the second comparison result (i.e., the judgment of negative clamping) includes:

[0104] The output signal values ​​at n moments are collected, and the output signal values ​​at the n moments are respectively compared with the second values ​​at the corresponding moments in the second straight line, so that n comparison results can be obtained. In the n comparison results, if all the output signals are greater than or equal to the second values ​​at the corresponding moments in the second straight line, it means that there is no need to perform negative clamping of the signal, that is, it is determined that mis-clamping has occurred, so at this time, the second enable signal is controlled to output an invalid state, so that the negative clamping circuit is disconnected. In the n comparison results, if there is one or more times (that is, there are occurrences) when the output signal is less than the second value at the corresponding moment of the second implementation, it means that there will be a situation where it is lower than the negative clamping threshold, and then the negative clamping function needs to be turned on at this time, that is, it is determined that mis-clamping has not occurred, so at this time, the second enable signal is controlled to output a valid state, so that the negative clamping circuit is connected.

[0105] It should be understood that when the power is initially turned on, the second enable signal is in a valid state, that is, the clamping function of the negative clamping circuit is in an on state, and the control chip determines whether there is a false clamping phenomenon after a negative clamping alarm signal is generated; only when it is determined that a false clamping phenomenon has occurred, the state of the second enable signal will be used to control the clamping function of the negative clamping circuit to be turned off.

[0106] It should be understood that the second enable signal also indicates validity or invalidity through high or low levels, for example, 1 indicates a valid state and 0 indicates an invalid state; or 0 indicates a valid state and 1 indicates an invalid state.

[0107] Similarly, in this embodiment, after it is determined that mis-clamping has occurred and the negative clamping circuit is disconnected, the second enable signal can be controlled to be in a valid state after the following conditions are met, thereby restoring the negative clamping function:

[0108] Determine that the negative clamp circuit stops outputting the negative clamp alarm signal; or,

[0109] VC≤Range*VCN_SET*K_VC

[0110] Among them, VC is the actual output signal of the power supply, Range is the signal value of the full scale; VCN_SET is the preset negative clamping coefficient; K_VC is the derating factor, which is used to adjust the actual clamping percentage.

[0111] It should be understood that in this embodiment, when it is determined that the negative clamp circuit stops outputting the positive clamp alarm signal, the negative clamp end alarm can be confirmed, that is, when the negative clamp end alarm is triggered, the second enable signal can be controlled to be in a valid state to restore the negative clamp function.

[0112] It should be understood that in this embodiment, after the negative clamp function is turned off, when it is determined that the actual output signal VC of the power supply is less than or equal to the set voltage value Range*VCN_SET*K_VC, the negative clamp function needs to be restored.

[0113] By setting the recovery condition of the negative clamp function, it is possible to better play the role of clamp protection on the basis of improving the test efficiency.

[0114] Next, a positive clamping circuit 220 provided in an embodiment of the present application is introduced. Figure 3 As shown, the positive clamp circuit 220 includes a first comparator U1A, a first diode D1 and a first control device S1. The first control device S1 may be a switch device, a relay, etc. It should be understood that in other embodiments, the positive clamp circuit may have other structures.

[0115] Specifically, the output end of the first comparator U1A is connected to the positive electrode of the first diode D1, the negative electrode of the first diode D1 is connected to one end of the first control device S1, and the other end of the first control device S1 is connected to the lower circuit (the integral stage branch in this embodiment) as the output end of the positive clamp circuit 220. The positive phase input end of the first comparator U1A is used to receive the output signal of the VI source (i.e., the signal to be clamped), and the negative phase input end of the first comparator U1A is used to receive the positive clamp signal threshold (the signal threshold is determined by the control chip based on the pre-fitted first straight line and sent to the first comparator U1A). The first control device S1 is also used to receive the first enable signal, so as to control the on and off of the positive clamp circuit based on the signal value of the first enable signal.

[0116] Next, combine Figure 3 The working principle of the positive clamp circuit 220 is introduced.

[0117] At the initial power-on, the positive clamping function is turned on, and the magnitude relationship between the signal to be clamped and the positive clamping signal threshold is compared, and the conduction or cutoff of the first diode D1 is controlled based on the magnitude relationship, thereby affecting the NULL level output signal. Specifically, when the signal to be clamped is greater than the positive clamping signal threshold, the first diode D1 is turned on, indicating that the positive clamping circuit 220 is working; then, based on the relationship between the voltage difference between the input signal and the output signal of the first diode D1 and the preset threshold, it is determined that the positive clamping circuit 220 outputs a positive clamping alarm signal to the control chip 210 at this time to indicate that the positive clamping circuit is in a working state. After determining that the positive clamping circuit 220 has issued a positive clamping alarm signal, the control chip 210 performs a method for adjusting the output establishment time provided by the present invention to determine whether there is a false clamping phenomenon. According to the judgment and analysis, when it is determined that there is a false clamping phenomenon, the control chip 210 outputs the first enable signal of the invalid state to the first control device S1 to control the positive clamping circuit 220 to be disconnected (that is, not connected to the lower circuit); when it is determined that there is no false clamping phenomenon, the control chip 210 outputs the first enable signal of the valid state to the first control device S1 to control the positive clamping circuit 220 to be turned on (that is, connected to the lower circuit); when the positive clamping circuit 220 is turned on, the output signal of the NULL level is limited by the output value of the positive clamping circuit 220.

[0118] Next, the negative clamp circuit 230 in the embodiment of the present application is introduced. Figure 3 As shown, the negative clamp circuit 230 includes a second comparator U1B, a second diode D2 and a second control device S2. The second control device S2 may be a switch device, a relay, etc. It should be understood that in other embodiments, the negative clamp circuit may have other structures.

[0119] Specifically, the output end of the second comparator U1B is connected to the cathode of the second diode D2, the anode of the second diode D2 is connected to one end of the second control device S2, and the other end of the second control device S2 is connected to the lower circuit (the integration stage branch in this embodiment) as the output end of the negative clamp circuit 230. The negative phase input end of the second comparator U1B is used to receive the output signal of the VI source (i.e., the signal to be clamped), and the positive phase input end of the second comparator U1B is used to receive the negative clamp signal threshold (the signal threshold is determined by the control chip based on the pre-fitted second straight line and sent to the second comparator U1B). The second control device U1B is also used to receive the second enable signal, so as to control the on and off of the negative clamp circuit based on the signal value of the second enable signal.

[0120] Next, combine Figure 3 The working principle of the negative clamp circuit 230 is introduced.

[0121] At the initial power-on, the negative clamp function is turned on, the magnitude relationship between the signal to be clamped and the negative clamp signal threshold is compared, and the conduction or cutoff of the second diode D2 is controlled based on the magnitude relationship, thereby affecting the NULL level output signal. Specifically, when the signal to be clamped is less than the negative clamping signal threshold, the second diode D2 is turned on, indicating that the negative clamping circuit 230 is working, and then according to the relationship between the voltage difference between the input signal and the output signal of the second diode D1 and the preset threshold, it is determined that the negative clamping circuit 230 outputs a negative clamping alarm signal to the control chip 210 to indicate that the negative clamping circuit is in a working state; after determining that the negative clamping circuit 230 has issued a negative clamping alarm signal, the control chip 210 performs a judgment and analysis on whether there is a false clamping phenomenon based on the method for adjusting the output establishment time provided by the present invention. When it is determined that there is a false clamping phenomenon, the control chip 210 outputs a second enable signal of an invalid state to the second control device S2 to control the negative clamping circuit 230 to be disconnected; when it is determined that there is no false clamping phenomenon, the control chip 210 outputs a second enable signal of a valid state to the second control device S2 to control the negative clamping circuit 230 to be turned on; when the negative clamping circuit 230 is turned on, the output signal of the NULL level is limited by the output value of the negative clamping circuit 230.

[0122] Next, the integration circuit 240 in the embodiment of the present application is introduced. Figure 3 As shown, the integration circuit 240 includes an operational amplifier U1C and a capacitor C, the negative phase input terminal of the operational amplifier U1C is connected to the output terminal of the positive clamp circuit 220, the negative phase input terminal of the operational amplifier U1C is also connected to the output terminal of the negative clamp circuit 230, the positive phase input terminal of the operational amplifier U1C is connected to the ground terminal, and the capacitor C is connected between the negative phase input terminal and the output terminal of the operational amplifier U1C. The integration circuit 240 is used to perform integration operations on the received signal. It should be understood that in other embodiments, the integration circuit can be of other structures.

[0123] From the above, the circuit provided by the above-mentioned embodiment of the present application adds a false clamping judgment process in the control chip, so that after the false clamping phenomenon occurs, the clamping function in the corresponding clamping circuit can be disabled by the corresponding enable signal, thereby avoiding the occurrence of subsequent false clamping phenomena, thereby shortening the output establishment time of the VI source and improving the test efficiency.

[0124] S540: Adjust the output settling time according to the on-off state of the clamping circuit.

[0125] Through step S520 and step S530, the occurrence of false clamping is avoided, so that the output settling time is adjusted based on the on-off state of the clamping circuit, thereby improving the test efficiency. In order to more clearly illustrate the working principle of the circuit for adjusting the output settling time provided by the present application, another embodiment of the present application takes positive clamping as an example to illustrate the working process of the circuit.

[0126] Combination Figure 1 and Figure 5 , the workflow of positive clamp judgment includes:

[0127] S410: ADC collects the output signal of the VI source.

[0128] In this embodiment, for example, the output voltage value of the VI source is collected by ADC, and the collected voltage value is converted into analog to digital, so that the digital signal of the voltage value is sent to the lower circuit. It should be understood that in other embodiments, the collection object may also be the output current value of the VI source.

[0129] S420: The control chip (the control chip in this embodiment uses FPGA) receives the digital signal of the voltage value sent by the ADC.

[0130] S430: The control chip compares the collected voltage value with the voltage value corresponding to the pre-fitted first straight line at the same time to obtain a comparison result.

[0131] In this step, the comparison times are multiple times, that is, the multiple voltage values ​​collected are compared with the voltage values ​​at corresponding moments on the first straight line respectively, so as to obtain multiple comparison results.

[0132] S440a: In the multiple comparison results, as long as a voltage value higher than the first moment appears, the positive clamping circuit is controlled to be connected to the integration circuit, thereby starting the positive clamping function.

[0133] S440b: If, in the multiple comparison results, all are lower than the voltage value at the first moment, the positive clamp circuit is controlled to be disconnected, that is, the integration circuit is not connected, and the positive clamp function is disabled.

[0134] This application introduces the judgment process of mis-clamping again through another embodiment, such as Figure 6 The figure shows the mis-clamping judgment flow chart executed inside the control chip.

[0135] In order to ensure the safety of the VI source loop, the clamp function is enabled by default. When the output signal of the VI source is positive, the positive clamp function is enabled by default, and when the output signal of the VI source is negative, the negative clamp function is enabled by default. It should be understood that due to the uniqueness of the VI source output signal, only one of the positive clamp function and the negative clamp function can be enabled, and they cannot be enabled at the same time.

[0136] As an implementation method, the clamp alarm can be set to ensure that the corresponding clamp function is successfully turned on. That is, after the system is powered on, if no clamp alarm signal is issued (i.e., the clamp function is not turned on) or both the positive clamp and the negative clamp send alarm signals (positive and negative clamps are turned on at the same time), the clamp function should be rechecked.

[0137] In some embodiments, before obtaining a comparison result by comparing the plurality of output signal values ​​with the signal values ​​at each moment corresponding to the pre-fitted straight line, the method further includes:

[0138] Determine that the clamp circuit sends out a clamp alarm signal; wherein the clamp alarm signal is sent out by the clamp circuit when a preset trigger condition is met, and the clamp alarm signal includes a positive clamp alarm signal and a negative clamp alarm signal.

[0139] Specific, combined Figure 3 To describe the triggering condition of the clamp alarm signal. For the positive clamp circuit 220, the input signal and the output signal of the first diode D1 are obtained and the first difference between the two is determined. When the first difference is greater than the threshold value (preset threshold) of the first diode D1, the first diode D1 is turned on at this time, and the positive clamp alarm is triggered. It should be understood that the threshold value of the first diode D1 varies depending on the selected diode, for example, it is approximately 0.6V-0.7V for a silicon diode and approximately 0.2V-0.3V for a germanium diode. Similarly, for the negative clamp circuit 230, the input signal and the output signal of the second diode D2 are obtained and the second difference between the two is determined. When the second difference is greater than the conduction threshold value of the second diode D2, the second diode D2 is turned on at this time, and the negative clamp alarm is triggered. Similarly, for the second diode D2, different diodes are selected, and the corresponding conduction threshold values ​​are different, which are not specifically limited in this embodiment.

[0140] It should be understood that the trigger condition in this embodiment is to compare the difference between the input signal and the output signal of the diode with the threshold value (preset threshold value). In other embodiments, the comparison can also be based on the voltage difference value of a specific device in a specific clamping circuit, which is not specifically limited here.

[0141] When only the positive clamp alarm signal is issued, the positive clamp judgment process is entered, and the magnitude relationship between the collected multiple output signal values ​​(voltage values ​​or current values) and the first values ​​corresponding to each moment on the first straight line is compared to determine whether mis-clamping occurs (see the judgment process of positive clamping in the above embodiment). If mis-clamping occurs, the positive clamp function needs to be disabled (the state of the first enable signal is invalid). After disabling the positive clamp function, if VC≥Range*VCP_SET*K_VC is met or the positive clamp end alarm occurs (that is, the positive clamp process is completed), the positive clamp function is restored. The restoration of the positive clamp function can also refer to the description of the restoration of the positive clamp function under step S520 and step S530 in the above embodiment.

[0142] When only the negative clamp alarm signal is issued, that is, the judgment process of negative clamp is entered, by comparing the magnitude relationship between the multiple output signal values ​​collected and the second values ​​corresponding to each moment on the second straight line, it is determined whether mis-clamping occurs (see the judgment process of negative clamping in the above embodiment). If mis-clamping occurs, the negative clamping function needs to be disabled (the state of the second enable signal is invalid). After disabling the negative clamping function, if VC≤Range*VCN_SET*K_VC is satisfied or the negative clamping ends the alarm (that is, the execution of this negative clamping process is completed), the negative clamping function is restored. The restoration of the negative clamping function can also refer to the description of the restoration of the negative clamping function under step S520 and step S530 in the above embodiment.

[0143] The solution provided in the embodiment of the present application can optimize the VI source output establishment time, such as Figure 7 The simulation diagrams before and after optimization are shown, where line a represents the rising edge / falling edge setup time waveform after optimization, and line b represents the rising edge / falling edge setup time waveform before optimization. Figure 7 It can be clearly seen that the output setup time of the VI source of this solution has been significantly optimized, and the setup time of both the rising edge and the falling edge has been greatly reduced.

[0144] Another embodiment of the present application further provides a power supply, which includes the circuit 20 for adjusting the output settling time provided in the above embodiment, and adjusts the output settling time based on the method of steps S510-S540 in the above embodiment. It should be understood that the specific implementation scheme and effects of this embodiment can be referred to the description of the above embodiment, and will not be described in detail in this embodiment.

[0145] Note that the above are only preferred embodiments of the present application and the technical principles used. Those skilled in the art will understand that the present application is not limited to the specific embodiments herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may also include more other equivalent embodiments without departing from the concept of the present application, all of which belong to the protection scope of the present application.

Claims

1. A method for adjusting output settling time, characterized in that: include: Performing multi-point sampling on the output signal to obtain multiple output signal values; Comparing the plurality of output signal values ​​with the signal values ​​at each moment corresponding to the pre-fitted curve to obtain a comparison result; outputting an enable signal according to the comparison result, and determining an on / off state of the clamp circuit based on the enable signal; The output settling time is adjusted according to the on-off state of the clamping circuit.

2. The method according to claim 1, characterized in that: Before obtaining a comparison result by comparing the multiple output signal values ​​with the signal values ​​at each moment corresponding to the pre-fitted curve, the method further includes: Determine that the clamp circuit sends a clamp alarm signal; wherein the clamp alarm signal is output by the clamp circuit when a preset trigger condition is met, and the clamp alarm signal includes a positive clamp alarm signal and a negative clamp alarm signal.

3. The method according to claim 1, characterized in that The step of comparing the plurality of output signal values ​​with the signal values ​​at each moment corresponding to the pre-fitted curve to obtain a comparison result, and outputting an enable signal according to the comparison result, comprises: Determine whether the output signal value is positive or negative; When the output signal value is a positive value: compare the multiple output signal values ​​with the first value at each moment corresponding to the first straight line respectively, obtain a first comparison result, and output a first enable signal according to the first comparison result; wherein the first enable signal is used to control the on and off of the positive clamping circuit, and the first straight line is a pre-fitted positive clamping judgment straight line; When the output signal value is a negative value: compare the multiple output signal values ​​with the second values ​​at each moment corresponding to the second straight line respectively to obtain a second comparison result, and output a second enable signal according to the second comparison result; wherein the second enable signal is used to control the on and off of the negative clamping circuit, and the second straight line is a pre-fitted negative clamping judgment straight line.

4. The method according to claim 3, characterized in that The first straight line comprises: Wherein, t represents time t; W(t)1 is the signal value corresponding to time t in the first straight line; Range is the signal value of the full scale; VCP_SET is the pre-set positive clamping coefficient; K_VC is the derating coefficient; K_VH is the time derating coefficient; TD is a debugging parameter used to determine the detection time interval, which is an integer multiple of the data sampling period.

5. The method according to claim 3, characterized in that: The second straight line includes: Wherein, t represents time t; W(t)2 is the signal value corresponding to time t in the second straight line; Range is the signal value of the full scale; VCN_SET is the preset negative clamping coefficient; K_VC is the derating coefficient; K_VH is the time derating coefficient; TD is a debugging parameter used to determine the detection time interval, which is an integer multiple of the data sampling period.

6. The method according to claim 3, characterized in that The step of comparing the multiple output signal values ​​with the first value at each moment corresponding to the first straight line to obtain a first comparison result, and outputting a first enable signal according to the first comparison result includes: If the values ​​of the multiple output signals are all less than or equal to the first value at each moment corresponding to the first straight line, the first enable signal is controlled to be in an invalid state, and the invalid state of the first enable signal indicates that the positive clamp circuit is disconnected; If there is a first value greater than the first straight line corresponding to the moment among the multiple output signal values, the first enable signal is controlled to maintain a valid state, and the valid state of the first enable signal indicates that the positive clamp circuit is connected.

7. The method according to claim 6, characterized in that Also includes: After controlling the first enable signal to be in an invalid state, if the following conditions are met, controlling the first enable signal to be in a valid state: Determining that the positive clamp circuit stops outputting the positive clamp alarm signal; or, VC≥Range*VCP_SET*K_VC Among them, VC is the actual output signal value of the power supply, Range is the full-scale signal value; VCP_SET is the pre-set positive clamping coefficient; K_VC is the derating coefficient.

8. The method according to claim 3, characterized in that The step of comparing the plurality of output signal values ​​with the second values ​​at each moment corresponding to the second straight line to obtain a second comparison result, and outputting a second enable signal according to the second comparison result comprises: If the values ​​of the plurality of output signals are all greater than or equal to the second value at each moment corresponding to the second straight line, the second enable signal is controlled to be in an invalid state, and the invalid state of the second enable signal indicates that the negative clamp circuit is disconnected; If there is a second value among the multiple output signal values ​​that is smaller than the second straight line at the corresponding moment, the second enable signal is controlled to maintain a valid state, and the valid state of the second enable signal indicates that the negative clamp circuit is connected.

9. The method according to claim 8, characterized in that Also includes: After controlling the second enable signal to be in an invalid state, if the following conditions are met, controlling the second enable signal to be in a valid state: Determine that the negative clamp circuit stops outputting the negative clamp alarm signal; or, VC≤Range*VCN_SET*K_VC Among them, VC is the actual output signal value of the power supply, Range is the full-scale signal value; VCN_SET is the preset negative clamping coefficient; K_VC is the derating coefficient.

10. The method according to claim 3, characterized in that Also includes: At initial power-on, the first enable signal and / or the second enable signal is controlled to be in a valid state, and the valid state indicates that the clamping function of the positive clamping circuit and / or the negative clamping circuit is in an on state.

11. A circuit for adjusting output settling time, characterized in that: Used to adjust the output settling time based on the method according to any one of claims 1 to 9, comprising: A control chip, used for receiving a plurality of output signals, comparing the plurality of output signal values ​​with the signal values ​​at each moment corresponding to the pre-fitted straight line to obtain a comparison result, and outputting an enable signal according to the comparison result; wherein the plurality of output signals are obtained by performing multi-point sampling on the output signals; and the enable signal includes a first enable signal and a second enable signal; a positive clamp circuit, configured to receive the first enable signal and control an on / off state of the positive clamp circuit based on the first enable signal; a negative clamp circuit, configured to receive the second enable signal and control an on / off state of the negative clamp circuit based on the second enable signal; The control chip is also used to adjust the output establishment time according to the on-off state of the positive clamping circuit or the negative clamping circuit.

12. The circuit according to claim 11, characterized in that The positive clamp circuit comprises a first control device for controlling the on and off of the positive clamp circuit based on the first enable signal; The negative clamp circuit includes a second control device for controlling the on and off of the negative clamp circuit based on the second enable signal.

13. A power supply, characterized in that: The invention comprises the circuit described in any one of claims 11 to 12.

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