Voltage undershoot or overshoot limited direct current (DC)-DC converter operating mode transitions

Abstract

Embodiments of a circuit for a direct current (DC)-DC converter and a DC-DC converter are disclosed. In an embodiment, a circuit for a DC-DC converter includes: a resistive voltage divider connected to an electrical terminal of the DC-DC converter; an amplifier connected to the resistive voltage divider; a clock synchronization unit connected to a control circuit of the DC-DC converter and configured to generate a control signal for the control circuit for switching the DC-DC converter between different operating modes; a first comparator connected to the amplifier and the control circuit of the DC-DC converter; a second comparator connected to the resistance voltage divider and the control circuit of the DC-DC converter; and a voltage generator connected to the first comparator and configured to generate a comparator input voltage for the first comparator in response to an output voltage from the amplifier.

Description

Technical Field

[0001] A direct current (DC)-DC converter is involved. Background Art

[0002] A direct current (DC)-DC converter can be used to convert an input power having an input DC voltage into an output signal at a desired output DC voltage. A DC-DC converter can operate in various operating modes and switch or transition between different operating modes. For example, a DC-DC converter can perform a mode transition between a low-power operating mode with a low quiescent current and a normal (high-power) operating mode. However, during the transition from one operating mode to another, voltage glitches may occur, which may trigger overvoltage or undervoltage, thereby possibly destroying the function of the DC-DC converter or damaging the load of the DC-DC converter. In addition, since the supply or output voltage of the load (e.g., a microcontroller) of the DC-DC converter is generally low, the voltage glitches tolerance may be limited. Therefore, a DC-DC regulator technology is needed to limit the voltage undershoot or overshoot during the transition between different operating modes in the DC-DC regulator. Summary of the invention

[0003] The present invention discloses an operation mode transition circuit for a DC-DC converter and an embodiment of a DC-DC converter. In an embodiment, an operation mode transition circuit for a DC-DC converter includes: a resistor divider connected to an electrical terminal of the DC-DC converter; an amplifier connected to the resistor divider; a clock synchronization unit connected to a control circuit of the DC-DC converter and configured to generate a control signal for the control circuit for switching the DC-DC converter between different operation modes; a first comparator connected to the amplifier and the control circuit of the DC-DC converter; a second comparator connected to the resistor divider and the control circuit of the DC-DC converter; and a voltage generator connected to the first comparator and configured to generate a comparator input voltage for the first comparator in response to an output voltage from the amplifier. Other embodiments are also described.

[0004] In an embodiment, the different operation modes include a pulse frequency modulation (PFM) operation mode and a pulse width modulation (PWM) operation mode.

[0005] In an embodiment, the circuit further comprises a resistor-capacitor (RC) circuit connected to the amplifier.

[0006] In an embodiment, the RC circuit comprises a resistor and a capacitor.

[0007] In an embodiment, the voltage generator comprises a switch connected to the RC circuit, a second amplifier connected to the switch, and a switchable capacitor circuit connected to the second amplifier.

[0008] In an embodiment, a control signal from the control circuit is applied to the amplifier and the second amplifier.

[0009] In an embodiment, the amplifier comprises a first input terminal connected to a first reference voltage and a second input terminal configured to receive an output voltage of the resistor divider.

[0010] In an embodiment, the second comparator is connected to a second reference voltage.

[0011] In an embodiment, the amplifier comprises an output connected to an input of the first comparator.

[0012] In an embodiment, the first comparator and the second comparator are configured to enable the control circuit of the DC-DC converter to control a high-side (HS) switch and a low-side (LS) switch of the DC-DC converter to switch the DC-DC converter between the different operation modes.

[0013] In an embodiment, at least one of the HS switch and the LS switch comprises a bipolar junction transistor (BJT) or a metal oxide semiconductor field effect transistor (MOSFET).

[0014] In an embodiment, an output inductor and an output capacitor are connected between two electrical terminals of the DC-DC converter.

[0015] In an embodiment, the circuit further comprises the control circuit.

[0016] In an embodiment, a DC-DC converter includes an operation mode transition circuit, a high-side (HS) driver, an HS switch connected to the HS driver, a low-side (LS) driver, an LS switch connected to the LS driver, and a control circuit, the control circuit being connected to the operation mode transition circuit and configured to control the HS driver, the HS switch, the LS driver, and the LS switch, for switching the DC-DC converter between different operation modes. The operation mode transition circuit includes: a resistor divider connected to an electrical terminal of the DC-DC converter; an amplifier connected to the resistor divider; a clock synchronization unit connected to the control circuit of the DC-DC converter and configured to generate a control signal for the control circuit for switching the DC-DC converter between the different operation modes; a first comparator connected to the amplifier and the control circuit of the DC-DC converter; a second comparator connected to the resistor divider and the control circuit of the DC-DC converter; and a voltage generator connected to the first comparator and configured to generate a comparator input voltage for the first comparator in response to an output voltage from the amplifier.

[0017] In an embodiment, the different operating modes include a low power operating mode and a high power operating mode.

[0018] In an embodiment, the low power operating mode comprises a PFM operating mode, and wherein the high power operating mode comprises a PWM operating mode.

[0019] In an embodiment, the operation mode transition circuit further comprises an RC circuit connected to the amplifier.

[0020] In an embodiment, the voltage generator comprises a switch connected to the RC circuit, a second amplifier connected to the switch, and a switchable capacitor circuit connected to the second amplifier.

[0021] In an embodiment, the control circuit is configured to generate bias signals for the amplifier and the second amplifier.

[0022] In an embodiment, an operation mode transition circuit for a DC-DC converter includes: a resistor divider connected to an electrical terminal of the DC-DC converter; an amplifier connected to the resistor divider; a clock synchronization unit connected to a control circuit of the DC-DC converter and configured to generate a control signal for the control circuit for switching the DC-DC converter between a pulse frequency modulation (PFM) operation mode and a pulse width modulation (PWM) operation mode; a first comparator connected to the amplifier and the control circuit of the DC-DC converter; a second comparator connected to the resistor divider and the control circuit of the DC-DC converter; a resistor-capacitor (RC) circuit connected to the amplifier, wherein the RC circuit includes a resistor and a capacitor; and a voltage generator connected to the first comparator and the RC circuit and configured to generate a comparator input voltage for the first comparator in response to an output voltage from the amplifier. The voltage generator includes a switch connected to the RC circuit, a second amplifier connected to the switch, and a switchable capacitor circuit connected to the second amplifier, and the control signal from the control circuit is applied to the amplifier and the second amplifier.

[0023] Other aspects of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A DC-DC converter according to an embodiment of the present invention is depicted.

[0025] Figure 2 Depiction Figure 1 An example of load current and pulse signal of a DC-DC converter in pulse frequency modulation (PFM) mode of operation is depicted.

[0026] Figure 3 Depiction Figure 1 An example of load current and pulse signal of a DC-DC converter in pulse width modulation (PWM) mode of operation is depicted.

[0027] Figure 4 Describe and Figure 1 Signal diagram corresponding to a transition from a PFM mode of operation to a PWM mode of operation in a DC-DC converter is depicted.

[0028] Figure 5 Describe and Figure 1 Another signal diagram corresponding to a transition from a PFM mode of operation to a PWM mode of operation in a DC-DC converter is depicted.

[0029] Throughout the description, similar reference numerals may be used to identify similar elements. DETAILED DESCRIPTION

[0030] It will be readily appreciated that the components of the embodiments as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following more detailed description of the various embodiments as represented in the accompanying drawings is not intended to limit the scope of the present disclosure, but is merely representative of the various embodiments. Although various aspects of the embodiments are presented in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0031] Without departing from the spirit or essential characteristics of the present invention, the present invention can be implemented in other specific forms. The described embodiments should be considered as illustrative and non-restrictive in all aspects. Therefore, the scope of the present invention is indicated by the appended claims rather than by the specific embodiments. All changes falling within the equivalent meaning and scope of the claims should be included within their scope.

[0032] References throughout this specification to features, advantages, or similar language do not imply that all features and advantages that can be achieved by the present invention should be or are in any single embodiment of the present invention. Rather, language referring to features and advantages should be understood to mean that a particular feature, advantage, or characteristic described in conjunction with an embodiment is included in at least one embodiment of the present invention. Therefore, discussion of features and advantages and similar language throughout this specification may, but does not necessarily, refer to the same embodiment.

[0033] In addition, the described features, advantages and characteristics of the present invention may be combined in one or more embodiments in any suitable manner. Those skilled in the art will recognize that, in view of the description herein, the present invention may be practiced without one or more specific features or advantages of a particular embodiment. In other cases, additional features and advantages may be identified in certain embodiments that may not be present in all embodiments of the present invention.

[0034] References throughout this specification to "one embodiment," "an embodiment," or similar language mean that a particular feature, structure, or characteristic described in connection with the specified embodiment is included in at least one embodiment of the present invention. Thus, the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0035] Figure 1 1 is a schematic block diagram of a DC-DC converter 100 according to an embodiment of the present invention. The DC-DC converter will have an input or supply DC voltage V received from an input or supply electrical terminal or pin 102. SUP The input power is converted into the desired output DC voltage V out The output signal is Figure 1 In the depicted embodiment, a load 112 may be connected to a DC-DC converter via an inductor-capacitor (LC) network 110 including an external inductor Lout and an external capacitor Cout via electrical terminals or pins 104, 106, 108. The DC-DC converter may be used in a variety of applications, such as automotive applications, communications applications, industrial applications, medical applications, computer applications, and / or consumer or appliance applications. In some embodiments, the DC-DC converter is included in a computing device such as a smartphone, a tablet computer, a laptop computer, etc. In some embodiments, the DC-DC converter is implemented in a substrate such as a semiconductor wafer. In an embodiment, the DC-DC converter is constructed as a separate semiconductor IC chip. In Figure 1 In the depicted embodiment, the DC-DC converter is a step-down DC-DC converter, wherein the input or supply voltage V SUP Higher than the output voltage V OUT However, in some embodiments, the DC-DC converter is a step-up DC-DC converter, where the input or supply voltage V SUP Lower than the output voltage V OUT In some embodiments, the DC-DC converter 100 is included in an integrated circuit (IC) chip (e.g., a system on a chip (SoC)), and the LC network 110 and the load 112 are included in a printed circuit board (PCB). For example, the DC-DC converter 100 and the LC network 110 are included in a DC-DC converter system 180. The enable signal can be switched to, for example, "0" to turn off the DC-DC converter 100, or switched to, for example, "1" to turn on the DC-DC converter 100.

[0036] exist Figure 1 In the depicted embodiment, the DC-DC converter 100 includes an input or supply electrical terminal or pin 102, electrical terminals or pins 104, 106, 108, a control circuit 116, a high-side (HS) driver 118, a low-side (LS) driver 120, a HS switch 122, a LS switch 124, a zero-crossing detection (ZCD) comparator 188, and an operating mode transition circuit 114 configured to switch or transition the DC-DC converter 100 between different operating modes. Although the DC-DC converter 100 is in Figure 1 1. The control circuit 116 is shown as including certain circuit elements, but in other embodiments, the DC-DC converter may include fewer or more circuit elements to implement fewer or more functions. In some embodiments, the control circuit 116 is a component of the operation mode transition circuit 114.

[0037] exist Figure 1In the depicted embodiment, the DC-DC converter 100 can operate in various operating modes and switch or transition between different operating modes. The DC-DC converter can perform mode transitions between a low power operating mode with low quiescent current and a normal (high power) operating mode. For example, in an automotive application, the operating modes of the power management IC can include a main operating mode that requires accuracy and efficiency under high load, a low power operating mode where efficiency under low load is more important to ensure that the battery can last for a long period of time without charging, and an off mode where all blocks are turned off and only the wake-up module is turned on.

[0038] exist Figure 1 In the depicted embodiment, the DC-DC converter 100 can operate in a pulse frequency modulation (PFM) operating mode, which is a low power operating mode with low quiescent current, or in a pulse width modulation (PWM) operating mode, which is a normal (high power) operating mode.

[0039] During the transition between different operating modes (e.g., PFM operating mode and PWM operating mode), the voltage glitch in the output voltage Vout may trigger an overvoltage or undervoltage, which may destroy the function of the DC-DC converter 100 or damage the load 112 of the DC-DC converter. In addition, since the supply or output voltage Vout of the load (e.g., microcontroller) is usually low, the voltage glitch tolerance of the load is usually limited. The operating mode transition circuit 114 can limit the voltage undershoot or overshoot during the transition between different operating modes in the DC-DC regulator. Two loops can be used to transition from a low-power operating mode with a low quiescent current to a normal (high power) operating mode. The first loop is used for a low-power operating mode with a low quiescent current, and the second loop is used for a normal (high power) operating mode that requires accuracy, current capability and power efficiency (e.g., with a constant switching frequency) under high load. In some embodiments, the operation mode transition circuit 114 performs a smooth transition from one operation mode to another operation mode by pre-positioning the operation point of the corresponding operation loop to the correct position and performing the operation mode transition at the correct moment so as to limit undershoot and overshoot of the output voltage Vout.

[0040] exist Figure 1In the depicted DC-DC converter 100, the control circuit 116 is configured to generate or set control signals for the HS driver 118, the LS driver 120, the HS switch 122, and the LS switch 124, for example, to switch the DC-DC converter between different operating modes (e.g., PFM operating mode and PWM operating mode). For example, the control circuit 116 is configured to generate or set an enable or disable signal HS_ON for the HS driver 118 and the HS switch 122, and to generate or set an enable or disable signal LS_ON for the LS driver 120 and the LS switch 124. In some embodiments, the enable or disable signal HS_ON is also applied to the operating mode transition circuit 114 to control one or more circuit components of the operating mode transition circuit 114 (e.g., the rising or falling edge of the enable or disable signal HS_ON starts one or more circuit components of the operating mode transition circuit 114). In some embodiments, the control circuit 116 is configured to generate or set a bias signal to bias one or more circuit components of the operating mode transition circuit 114 (e.g., amplifier 134 and amplifier 154). The control circuit 116 may be implemented by at least one processor (eg, a microcontroller, a digital signal processor (DSP), a central processing unit (CPU), or an embedded processor).

[0041] exist Figure 1 In the depicted DC-DC converter 100, the HS switch 122 is connected to receive an input or supply DC voltage V SUP The HS switch 122 may be implemented as a transistor, such as a bipolar junction transistor (BJT) or a metal oxide semiconductor field effect transistor (MOSFET). The HS driver 118 is configured to generate a drive signal for the HS switch 122, for example, based on an enable or disable signal HS_ON from the control circuit 116. The HS driver 118 may be implemented in one or more digital and / or analog circuit elements.

[0042] exist Figure 1 In the depicted DC-DC converter 100, the LS switch 124 is connected to an electrical terminal or pin 106, which may be connected to ground (zero volts). The LS switch 124 may be implemented as a transistor, such as a BJT or a MOSFET. The LS driver 120 is configured to generate a drive signal for the LS switch 124, for example, based on an enable or disable signal LS_ON from the control circuit 116. The LS driver 120 may be implemented in one or more digital and / or analog circuit elements.

[0043] exist Figure 1In the depicted DC-DC converter 100, the operation mode transition circuit 114 includes a clock synchronization unit 126, a resistor divider 128 including two resistors 130, 132, an amplifier 134, a first comparator 136, a second comparator 138, a resistor-capacitor (RC) compensation circuit 144, and a voltage generator 150. The operation mode transition circuit 114 is configured to switch or transition the DC-DC converter 100 between different operation modes. For example, the operation mode transition circuit 114 can perform a mode transition between a low-power operation mode with a low quiescent current and a normal (high power) operation mode. In the low-power operation mode, the quiescent current is kept as low as possible. Although the operation mode transition circuit 114 is Figure 1 100 is shown as including certain circuit elements, but in other embodiments, the operation mode transition circuit 114 may include fewer or more circuit elements to implement fewer or more functions. In an embodiment, the DC-DC converter 100 or the components of the DC-DC converter 100 are packaged as separate integrated circuit (IC) chips. For example, the DC-DC converter 100 or the components of the DC-DC converter 100 may be implemented in at least one substrate (e.g., at least one semiconductor wafer). In an embodiment, the operation mode transition circuit 114 is packaged as a separate IC chip. In an embodiment, the control circuit 116, the HS driver 118, the LS driver 120, the HS switch 122, the LS switch 124, and the operation mode transition circuit 114 are packaged in a separate IC chip.

[0044] exist Figure 1 In the depicted embodiment, the clock synchronization unit 126 is configured to generate clock and control signals for the control circuit 116 based on, for example, control or clock signals mode_pwm, mode_pfm, Hf_clk, sw_clk, HS_on, LS_on. In some embodiments, when the signal mode_pwm is positive (logic 1), the DC-DC converter 100 is in a PWM operation mode and a pulse width modulation mode is enabled. In some embodiments, when the signal mode_pfm is positive (logic 1), the DC-DC converter 100 is in a PFM operation mode and a pulse frequency modulation mode is enabled. In some embodiments, in peak mode, the clock synchronization unit 126 uses the signal HS_ON, and in valley mode, the clock synchronization unit 126 uses the signal LS_ON. Figure 1In the depicted embodiment, the clock synchronization unit 126 generates a clock signal pwm_clk and a control signal pfm_transition that are applied to the control circuit 116. In some embodiments, an effective transition from the PFM mode of operation to the PWM mode of operation is made on a falling edge on the signal pfm_transition, and an effective transition from the PWM mode of operation to the PFM mode of operation is made on a rising edge on the signal pfm_transition. In some embodiments, when the signal pfm_pre_exit is set to 0, the low quiescent current is enabled, and when the signal pfm_pre_exit is set to 1, the low quiescent current is not enabled. Hson_pfm is a signal that controls the high side when the PFM mode of operation is enabled. Pwm_clk is a clock signal used in the PWM mode of operation with a fixed switching frequency.

[0045] exist Figure 1 In the depicted embodiment, the resistor divider 128 is connected to the electrical terminal or pin 108, the amplifier 134, and the comparators 136, 138. The resistor divider 128 acts as a feedback resistor bridge. In some embodiments, there is no feedback bridge (i.e., the resistor divider 128), and the output voltage Vout can be applied to the amplifier 134 and the comparators 136, 138.

[0046] exist Figure 1 In the depicted embodiment, amplifier 134 is connected to resistor divider 128 and comparators 136, 138. Amplifier 134 may be a transconductance (Gm) amplifier. Specifically, a reference voltage Vref is applied to the positive terminal of amplifier 134, and a feedback signal from resistor divider 128 is applied to the negative terminal of amplifier 134 and comparators 136, 138. The output of amplifier 134 is connected to RC compensation circuit 144, and the output of amplifier 134 is applied to RC compensation circuit 144. Amplifier 134 may be controlled (e.g., enabled or disabled or set to a particular value) by a bias signal generated by control circuit 116 (e.g., a rising or falling edge of the bias signal enables or disables amplifier 134). Figure 1 In the depicted embodiment, amplifier 134 generates an output Vea that regulates the current delivered to load 112. In some embodiments, amplifier 134 is used only in PWM current mode control where the switching edges are determined by the clock.

[0047] exist Figure 1In the depicted embodiment, comparator 136 is connected to amplifier 134, control circuit 116, and switchable capacitor circuit 156 of DC-DC converter 100. In some embodiments, a pulse / voltage signal Vsns from switchable capacitor circuit 156 is applied to the positive terminal of comparator 136, and a feedback signal from amplifier 134 is applied to the negative terminal of comparator 136. In some embodiments, in PWM current mode, voltage Vsns is the sum of current sense voltage and slope compensation. In some embodiments, in PWM voltage mode, voltage Vsns is a PWM ramp. Comparator 136 can be, for example, a pulse width modulation (PWM) comparator. In Figure 1 In the depicted embodiment, the comparator 136 is configured to cause the control circuit 116 to control the HS switch 122 and the LS switch 124 of the DC-DC converter to regulate the output voltage Vout.

[0048] exist Figure 1 In the depicted embodiment, comparator 138 is connected to amplifier 134, resistor divider 128, and control circuit 116 of DC-DC converter 100. In some embodiments, there is no feedback bridge (i.e., resistor divider 128), and comparator 138 is connected to electrical terminal or pin 108. In some embodiments, reference voltage Vref is applied to the positive terminal of comparator 138, and a feedback signal from resistor divider 128 or electrical terminal or pin 108 is applied to the negative terminal of comparator 138. Comparator 138 can be, for example, a pulse frequency modulation (PFM) comparator. Figure 1 In the depicted embodiment, the comparator 138 is configured to cause the control circuit 116 to control the HS switch 122 and the LS switch 124 of the DC-DC converter to regulate the output voltage Vout.

[0049] exist Figure 1 In the depicted embodiment, the RC compensation circuit 144 includes a resistor 146 and a capacitor 148. The RC compensation circuit 144 may be connected to a fixed voltage, such as ground (zero volts). Figure 1 In the depicted embodiment, the output Vea of ​​amplifier 134 is applied to resistor 146. Resistor 146 and capacitor 148 are connected to voltage generator 150.

[0050] exist Figure 1In the depicted embodiment, the voltage generator 150 includes a switch 152, an amplifier 154, and a switchable capacitor circuit 156. The voltage generator 150 is configured to generate a voltage signal Vsns for the comparator 136. In some embodiments, the voltage signal Vsns is a scaled voltage representation of the current through the HS switch 122 or the LS switch 124 plus slope compensation, which is used for peak or valley current mode control. The voltage generator 150 utilizes a track and hold circuit that captures the peak or valley of the voltage signal Vsns waveform for peak or valley current mode control, respectively. Figure 1 In the depicted embodiment, switch 152 is connected between resistor 146 and capacitor 148 of RC compensation circuit 144, and the output of amplifier 154 is connected to the negative input of amplifier 154 and switch 152, and the positive input of amplifier 154 is connected to switchable capacitor circuit 156. Amplifier 154 can act as a voltage follower to clamp amplifier 134 and RC compensation circuit 144 to the appropriate level specified by the load current. Switchable capacitor circuit 156 includes four switches 160, 162, 166, 168 connected to a fixed voltage (e.g., ground (zero volts)) and two capacitors 164, 170. Voltage signal Vsns is output from switchable capacitor circuit 156 to, for example, comparator 136. In some embodiments, amplifier 154 and switchable capacitor circuit 156 detect the sum of current sensing and slope compensation information (which is voltage signal Vsns) and force amplifier 134 and RC compensation circuit 144 to reach the value of voltage signal Vsns. Although the voltage generator 150 is Figure 1 1 is shown as including certain circuit elements, but in other embodiments, voltage generator 150 may include fewer or more circuit elements to implement fewer or more functions.

[0051] exist Figure 1 In the depicted embodiment, the DC-DC converter 100 can operate in a pulse width modulation (PWM) operating mode or a pulse frequency modulation (PFM) operating mode. The operating mode transition circuit 114 can limit voltage undershoot or overshoot in the DC-DC regulator during the transition between the PFM operating mode and the PWM operating mode. Figure 1In the depicted embodiment, when the DC-DC converter 100 operates in the PFM operating mode, the control circuit 116, the HS driver 118, the LS driver 120, the HS switch 122, the LS switch 124, the LC network 110, the load 112, the resistor divider 128, the ZCD comparator 188, and the PFM comparator 138 can form a PFM loop 142. When the DC-DC converter 100 operates in the PWM operating mode, the control circuit 116, the HS driver 118, the LS driver 120, the HS switch 122, the LS switch 124, the LC network 110, the load 112, the resistor divider 128, the amplifier 134, the RC compensation circuit 144, and the PWM comparator 136 can form a PWM loop 140. In some embodiments, the operation mode transition circuit 114 (e.g., the voltage generator 150) performs a smooth transition between the PFM operation mode and the PWM operation mode by pre-positioning the operation point of the corresponding operation loop to the correct position and performing the operation mode transition at the correct moment so as to limit the undershoot and overshoot of the output voltage Vout.

[0052] An example of the operation of the DC-DC converter 100 is described below. In the PFM operating mode, the comparator 138 is used to detect when the scaled output voltage from the resistor divider 128 is less than the reference voltage Vref. When the scaled output voltage from the resistor divider 128 is lower than the reference voltage Vref, a current pulse is supplied to the load 112. PFM operation does not require a clock. In the PFM operating mode, the high side (HS) switch 122 is turned on (e.g., turned on) for a time determined by Vout / Vin*Tsw (Tsw is the target switching frequency of the DC-DC converter (this formula (Vout / Vin*Tsw) is valid in the absence of loss)). Afterwards, the low side (LS) switch 124 is turned on (e.g., turned on), and when the second comparator 138 detects that the output is higher than the target, the low side remains turned on until the inductor current slopes down to zero, which can be detected by a zero current detection circuit (e.g., ZCD comparator 188). At this point, the LS switch 124 is closed, thereby providing a light load efficiency improved compared to the PWM operating mode. PWM current mode operation adjusts the output by changing the inductor current cycle by cycle (in a clock-controlled manner), thereby adjusting the output voltage Vout. The output of amplifier 134 can directly determine the peak or valley value of the inductor current according to peak current mode or valley current mode control or voltage mode control. When switching between the PFM mode of operation and the PWM mode of operation, the amplifier 134 needs to be properly pre-positioned, and the PWM clock needs to be aligned with the PFM switching frequency to minimize the output voltage transition between the two independent control loops. Before the final transition from the PFM mode to the PWM mode, the PWM loop can be activated to allow the circuit to be biased, the circuit including the amplifier 134 and the current sensing and slope compensation circuit (i.e., the amplifier 154 and the switchable capacitor circuit 156) without affecting the PFM mode control. When these circuits are enabled, the amplifier 134 can be programmed by the voltage generator 150 to the Vsns voltage level specified by the load current. Before the transition, the zero current detection (ZCD) circuit (e.g., ZCD comparator 188) can be disabled, thereby allowing the DC-DC converter to switch at a frequency close to the PWM switching frequency. When transitioning from the PFM mode of operation to the PWM mode of operation, the amplifier 134 is set to the appropriate value as specified by the load, and the appropriate clock phase is selected to avoid clock errors during the transition, and in the case of peak mode or voltage mode control, the rising edge of the PWM switching frequency clock is aligned with the PFM switching frequency (the rising edge of the HS_ON signal). Under valley mode control, the rising edge of the PWM switching frequency clock is aligned with the PFM switching frequency on the rising edge of the LS_ON signal, and the rising edge of the LS_ON signal corresponds to the falling edge of the HS_ON signal.

[0053] Figure 2 Depiction Figure 1 An example of a load current iload and a pulse signal V(LX) of the DC-DC converter 100 in the PFM operating mode is depicted. The pulse signal V(LX) of the DC-DC converter 100 is a signal at an electrical terminal or pin 104. Figure 2 In the depicted signal diagram, the load current iload has a waveform 210, and the pulse signal V(LX) has a waveform 220. In the PFM mode of operation, the switching frequency is dependent on the load 112, such that the switching frequency varies to meet the load demand.

[0054] Figure 3 An example of the load current iload and the pulse signal V(LX) of the DC-DC converter 100 in the PWM operation mode is depicted. Figure 3 In the depicted signal diagram, the load current iload has a waveform 310, and the pulse signal V(LX) has a waveform 320. In the PWM operating mode, the switching frequency is constant. The PWM operating mode can be a voltage mode, a current mode, or a constant on-time (COT) mode. In some embodiments, PFM mode control is similar to PWM mode control because the PFM mode control uses a rectangular pulse signal to determine the output voltage Vout of the DC-DC converter 100. However, instead of changing the duty cycle of a pulse signal of a fixed frequency to set the output voltage Vout, the PFM mode control changes the frequency of the pulse signal of the fixed high-side on-duration (ton). Under light load, the switching frequency in the PFM operating mode is low and the switching loss is small. In the PFM operating mode, the efficiency under light load is higher than the efficiency under light load in the PWM operating mode.

[0055] Figure 4 Describe and Figure 1 The depicted signal diagram corresponds to the transition from the PFM mode of operation to the PWM mode of operation in the DC-DC converter 100. Figure 4In the signal timing diagram shown, the pfm_transition signal has a waveform 410, the signal pfm_pre_exit from the clock synchronization unit 126 has a waveform 420, the signal pfm_comp (HS_ON signal in the case of peak mode or voltage mode control (LS_ON signal in the case of valley mode control) sent back to the clock synchronization unit 126) has a waveform 430, the PWM switching frequency clock signal pwm_clk has a waveform 440, and the switching clock signal sw_clk has a waveform 445. At time point t1, the PWM operation switches to the PFM operation. Specifically, at time point t1, the pfm_transition signal 410 changes from 0 to 1, the signal pfm_pre_exit 420 changes from 1 to 0, and the clock signal sw_clk 440 changes to zero, and the mode switches from PWM to PFM. At time point t2, signal pfm_pre_exit 420 changes from 0 to 1 and ZCD comparator 188 is disabled, and PFM_comp 430 will start switching. In some embodiments, when signal pfm_pre_exit is set to 0, low quiescent current is enabled, and when signal pfm_pre_exit is set to 1, low quiescent current is not enabled. At time point t3, PFM operation switches to PWM operation. Specifically, at time point t3, pfm_transition signal 410 changes from 1 to 0, and clock signal pwm_clk 440 changes from zero to shift value. After time point t3, by using HF_clk (high frequency clock), clock signal pwm_clk will be gradually aligned with clock signal sw_clk 445.

[0056] Figure 5 Describe and Figure 1 Another signal diagram corresponding to the transition from the PFM mode of operation to the PWM mode of operation in the DC-DC converter 100 is depicted. Figure 5 As shown in the signal timing diagram, from Figure 1 The pfm_transition signal output by the clock synchronization unit 126 in has a waveform 510, the signal mode_pfm has a waveform 515, the signal pfm_pre_exit from the clock synchronization unit 126 has a waveform 520, the signal HS_ON has a waveform 525, the output voltage Vout of the DC-DC converter has a waveform 530, the inductor current has a waveform 535, the voltage Vea from the amplifier 134 has a waveform 540, the voltage Vsns from the voltage generator 150 has a waveform 545, the clock signal pwm_clk from the clock synchronization unit 126 has a waveform 550, and the switching clock signal sw_clk has a waveform 555. Figure 5In the signal timing diagram shown, valley current mode control is implemented. At time point t1, PFM operation begins to transition to PWM operation, zero current detection (ZCD comparator 188) is disabled, the PWM circuit (amplifier 134 and current sensing and slope compensation circuit (i.e., amplifier 154 and switchable capacitor circuit 156)) is biased, and clamping is enabled. Specifically, at time point t1, signal mode_pfm 515 changes from 1 to 0, signal pfm_pre_exit 520 changes from 0 to 1, and voltage Vea 540 and voltage Vsns545 begin to increase, and Vea is pre-positioned to the correct value. For example, when signal pfm_pre_exit is set to 0, low quiescent current is enabled, and when signal pfm_pre_exit is set to 1, low quiescent current is not enabled. The bias for PWM loop 140 is enabled, and voltage Vea is clamped to voltage Vsns. At time point t2, the PFM operation is changed to the PWM operation. Specifically, at time point t2, the pfm transition signal 510 changes from 1 to 0. During the transition from the PFM operation to the PWM operation, the output voltage Vout 530 of the DC-DC converter has an overshoot of less than 1 millivolt (mV) (about 0.12% overshoot), and at time point t2, the rising edge of pwm_clk is synchronized with the falling edge of the signal HS_ON, and the phase synchronization of pwm_clk550 and the clock signal sw_clk 555 is performed by using HF_CLK.

[0057] In the above description, the specific details of various embodiments are provided. However, some embodiments may be practiced without all of these specific details. In other cases, for the sake of brevity and clarity, certain methods, operating steps, components, structures and / or functions are no longer described in detail except to enable various embodiments of the present invention.

[0058] Although the operation of the method is shown and described in a particular order herein, the order of operation of each method can be changed so that some operations can be performed in reverse order or some operations can be performed at least partially simultaneously with other operations. In another embodiment, instructions or sub-operations of different operations can be implemented in an intermittent and / or alternating manner.

[0059] It should also be noted that at least some of the operations of the methods described herein may be implemented using software instructions stored on a computer-usable storage medium for computer execution. For example, an embodiment of a computer program product includes a computer-usable storage medium for storing a computer-readable program. The computer-usable or computer-readable storage medium may be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or device or apparatus). Examples of non-temporary computer-usable and computer-readable storage media include semiconductor or solid-state memory, magnetic tape, removable computer floppy disk, electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), read-only memory (ROM), rigid disk, and optical disk. Current examples of optical disks include high-density disks with read-only memory (CD-ROM), high-density disks with read / write (CD-R / W), and digital video disks (DVD).

[0060] Alternatively, embodiments of the present invention may be implemented entirely in hardware or in an implementation scheme comprising both hardware and software elements. In an embodiment using software, the software may include but is not limited to firmware, resident software, microcode, etc.

[0061] Although specific embodiments of the invention have been described and illustrated, the invention is not to be limited to the specific forms or arrangements of parts so described and illustrated. The scope of the invention is to be defined by the claims appended hereto and their equivalents.

Claims

1. A circuit for a direct current (DC)-DC converter, characterized in that The circuit comprises: a resistor divider connected to electrical terminals of the DC-DC converter; an amplifier connected to the resistor divider; a clock synchronization unit connected to a control circuit of the DC-DC converter and configured to generate a plurality of control signals for the control circuit for switching the DC-DC converter between different operation modes; a first comparator connected to the amplifier and the control circuit of the DC-DC converter; a second comparator connected to the resistor divider and the control circuit of the DC-DC converter; and A voltage generator is connected to the first comparator and is configured to generate a comparator input voltage for the first comparator in response to an output voltage from the amplifier.

2. The circuit according to claim 1, characterized in that The different operation modes include a pulse frequency modulation (PFM) operation mode and a pulse width modulation (PWM) operation mode.

3. The circuit according to claim 1, characterized in that Also included is a resistor-capacitor (RC) circuit connected to the amplifier.

4. The circuit according to claim 3, characterized in that The RC circuit includes a resistor and a capacitor.

5. The circuit according to claim 3, characterized in that The voltage generator includes a switch connected to the RC circuit, a second amplifier connected to the switch, and a switchable capacitor circuit connected to the second amplifier.

6. The circuit according to claim 5, characterized in that A control signal from the control circuit is applied to the amplifier and the second amplifier.

7. The circuit according to claim 1, characterized in that The amplifier includes a first input terminal connected to a first reference voltage and a second input terminal configured to receive an output voltage of the resistor divider.

8. The circuit according to claim 7, characterized in that The second comparator is connected to a second reference voltage.

9. A direct current (DC)-DC converter, characterized in that: include: An operation mode transition circuit comprising: a resistor divider connected to electrical terminals of the DC-DC converter; an amplifier connected to the resistor divider; a clock synchronization unit connected to a control circuit of the DC-DC converter and configured to generate a plurality of control signals for the control circuit for switching the DC-DC converter between different operation modes; a first comparator connected to the amplifier and the control circuit of the DC-DC converter; a second comparator connected to the resistor divider and the control circuit of the DC-DC converter; and a voltage generator connected to the first comparator and configured to generate a comparator input voltage for the first comparator in response to an output voltage from the amplifier; High-side (HS) driver; a HS switch connected to the HS driver; Low-side (LS) driver; an LS switch connected to the LS driver; and The control circuit is connected to the operation mode transition circuit and is configured to control the HS driver, the HS switch, the LS driver, and the LS switch to switch the DC-DC converter between the different operation modes.

10. An operation mode transition circuit for a direct current (DC)-DC converter, characterized in that: The operation mode transition circuit comprises: a resistor divider connected to electrical terminals of the DC-DC converter; an amplifier connected to the resistor divider; a clock synchronization unit connected to the control circuit of the DC-DC converter and configured to generate a plurality of control signals for the control circuit for switching the DC-DC converter between a pulse frequency modulation (PFM) operation mode and a pulse width modulation (PWM) operation mode; a first comparator connected to the amplifier and the control circuit of the DC-DC converter; a second comparator connected to the resistor divider and the control circuit of the DC-DC converter; a resistor-capacitor (RC) circuit connected to the amplifier, wherein the RC circuit includes a resistor and a capacitor; and a voltage generator connected to the first comparator and the RC circuit and configured to generate a comparator input voltage for the first comparator in response to an output voltage from the amplifier, wherein the voltage generator includes a switch connected to the RC circuit, a second amplifier connected to the switch, and a switchable capacitor circuit connected to the second amplifier, and wherein a control signal from the control circuit is applied to the amplifier and the second amplifier.

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