IRIG-B direct current code synchronization pulse per second leading edge generation method based on single-chip microcomputer

Abstract

The invention discloses an IRIG-B direct current code synchronization pulse per second leading edge generation method based on a single-chip microcomputer, which can realize the same pulse per second 1PPS precision by using a domestic single-chip microcomputer, does not need to be realized by using an independent FPGA (Field Programmable Gate Array), and greatly reduces the cost. The method comprises the following steps: identifying a frame start code element through a timer TIMER1, enabling a timer TIMER2 to start counting after receiving an Nmax-th code element, entering overflow interruption when a count value of the timer TIMER2 reaches a count maximum value, and configuring a timer TIMER3 to be in a monopulse mode and enabling the timer TIMER3 after the timer TIMER2 enters the overflow interruption; and after the timer TIMER3 is triggered, the timer TIMER3 outputs a signal pulse per second 1PPS which is synchronous with the rising edge of the frame start code element of the next frame after the fixed delay delta and the programmable delay Delay are triggered by a single pulse.

Description

Technical Field

[0001] The invention belongs to the technical field of time synchronization, and in particular relates to a method for generating a leading edge of an IRIG-B direct current code synchronous second pulse based on a single chip microcomputer, and is suitable for realizing the generation of an IRIG-B direct current code synchronous second pulse through a single chip microcomputer. Background Art

[0002] At present, the global satellite navigation system has become an important technical foundation in many fields due to its wide signal coverage, high-precision time synchronization and all-weather service capabilities. Among them, the IRIG-B code (inter-range instrumentation group-B) generator uses GPS signals to generate synchronous second pulses 1PPS (1 pulse per second) for time synchronization and is widely used. At present, the synchronous second pulses 1PPS in the IRIG-B codec system are mostly implemented by FPGA (field programmable gate array), and the comprehensive implementation cost is relatively high. Summary of the invention

[0003] The purpose of the present invention is to provide a method for generating an IRIG-B DC code synchronous second pulse leading edge based on a single chip microcomputer in view of the above problems existing in the prior art.

[0004] The above-mentioned purpose of the present invention is achieved by the following technical means:

[0005] A method for generating an IRIG-B DC code synchronous second pulse leading edge based on a single chip microcomputer comprises the following steps:

[0006] Step S1, initializing timer TIMER1, timer TIMER2, and timer TIMER3, then enabling timer TIMER1, judging the width of a code element in the IRIG-B DC code by timer TIMER1, and further judging the type of the code element;

[0007] Step S2, repeat step S1 to determine the type of the received code element in turn, use the identified frame start code element as the frame start code element of the current frame IRIG-B DC code, use the rising edge of the frame start code element of the current frame IRIG-B DC code as the frame start position of the current frame IRIG-B DC code, then initialize the number N of received code elements to 1, then continue to receive the remaining code elements in the current frame IRIG-B DC code, and use timer TIMER1 to determine the type of each remaining code element in the current frame IRIG-B DC code in turn, and increase the number N of received code elements by 1 each time a code element is received;

[0008] Step S3: Set the maximum value N of the received codewords max , when receiving the Nth IRIG-B DC code of the current framemax After a code element, enable timer TIMER2 to start counting. When the count value of timer TIMER2 reaches the maximum count value B of timer TIMER2, it enters the overflow interrupt. After timer TIMER2 enters the overflow interrupt, timer TIMER3 is configured to single pulse mode and enabled.

[0009] Step S4, timer TIMER3 is triggered by the rising edge of the last code element of the current frame IRIG-B DC code. After being triggered, after a single pulse trigger fixed delay Δ and a programmable delay Delay, timer TIMER3 outputs a signal second pulse 1PPS synchronized with the rising edge of the frame start code element of the next frame.

[0010] As mentioned above, step S1 specifically includes the following steps:

[0011] Timer TIMER1 enters an interrupt at the rising edge of each IRIG-B DC code element: when the IRIG-B DC code element is at a high level, timer TIMER1 counts; when the IRIG-B DC code element is at a low level, timer TIMER1 stops counting. The code element width is judged according to the count value of timer TIMER1 to obtain the code element type, and then the counter of timer TIMER1 is reset to judge the next code element.

[0012] As described above, the frame start symbol in step S2 is identified by:

[0013] When two consecutive P codes are identified, the second P code of the two consecutive P codes is used as the frame start code element of the current frame IRIG-B DC code.

[0014] As described above, the maximum value B of the count of the timer TIMER2 in step S3 is calculated based on the following formula:

[0015] B=(99-N)*T / T2

[0016] Where, T is the symbol period of the IRIG-B DC code, T2 is the clock period of timer TIMER2, * is the multiplication sign, and / is the division sign.

[0017] As mentioned above, step S3 specifically includes the following steps:

[0018] Step S3.1: Set the maximum value N of received codewords max , when the number of received symbols N is equal to N max When TIMER2 is enabled, timer TIMER2 starts counting; where 60<N max <99;

[0019] Step S3.2, when the count value of timer TIMER2 is B, an overflow interrupt is generated, and timer TIMER3 is configured to single pulse mode, which is triggered by the rising edge of the 100th code element of the current frame IRIG-B DC code, and the programmable delay Delay of the single pulse mode is set to generate the pulse signal width.

[0020] The programmable delay Delay in step S4 as described above is calculated based on the following formula:

[0021] Delay=(T-Δ) / T3

[0022] Where Delay is the programmable delay in the single pulse mode of timer TIMER3, Δ is the fixed delay of the single pulse hardware trigger of the microcontroller timer, T is the symbol period of the IRIG-B DC code, T3 is the clock period of timer TIMER3, and / is the division sign.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] The present invention achieves the same pulse per second 1PPS accuracy by using a domestic single-chip microcomputer (such as UM3243F), without the need to use a separate FPGA, thereby greatly reducing the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of the structure of a system for implementing the method of the present invention;

[0026] Figure 2 is a flow chart of the method of the present invention;

[0027] Figure 3 It is a schematic diagram of the three types of code elements in the IRIG-B DC code: P code, 0 code, and 1 code;

[0028] Figure 4 It is a timing diagram of the single pulse mode of the timer TIMER3 of the present invention;

[0029] Figure 5 This is a schematic diagram of the implementation of embodiment 2 of the present invention. DETAILED DESCRIPTION

[0030] In order to facilitate those skilled in the art to understand and implement the present invention, the present invention is further described in detail below in conjunction with embodiments. The embodiments described herein are only used to illustrate and explain the present invention and are not intended to limit the present invention.

[0031] Embodiment 1:

[0032] A method for generating an IRIG-B DC code synchronous second pulse leading edge based on a single chip microcomputer comprises the following steps:

[0033] Step S1, initialize timer TIMER1, timer TIMER2, and timer TIMER3, then enable timer TIMER1, determine the symbol width of the IRIG-B DC code through timer TIMER1, and then determine the type of the symbol, specifically including the following process:

[0034] The symbol period T of the IRIG-B DC code is 10ms. The IRIG-B DC code includes three types of symbols, namely P code, 0 code, and 1 code. Figure 3 As shown, the P code is a code element signal with a high-level pulse width of 8ms, the 0 code is a code element signal with a high-level pulse width of 2ms, and the 1 code is a code element signal with a high-level pulse width of 5ms; the timer TIMER1 can determine the code element type by counting the code element width.

[0035] Step S1.1, timer TIMER1 enters interruption at the rising edge of each code element of the IRIG-B DC code: when the code element of the IRIG-B DC code is at a high level, timer TIMER1 counts, and when the code element of the IRIG-B DC code is at a low level, timer TIMER1 stops counting, and the code element width is determined according to the count value of timer TIMER1, thereby obtaining the code element type;

[0036] Step S1.2, reset the counter of timer TIMER1, and repeat step S1.1 to determine the next code element.

[0037] Step S2, repeat step S1 to determine the type of the received code element in turn, use the identified frame start code element as the frame start code element of the current frame IRIG-B DC code, use the rising edge of the frame start code element of the current frame IRIG-B DC code as the frame start position of the current frame IRIG-B DC code, initialize the number N of received code elements to 1, and then continue to receive the remaining code elements in the current frame IRIG-B DC code, and use timer TIMER1 to determine the type of each remaining code element in the current frame IRIG-B DC code in turn, so as to obtain the binary time information represented by each code element, and increase the number N of received code elements by 1 each time a code element is received.

[0038] Each frame of IRIG-B DC code includes 100 code elements, among which the 1st code element and the 100th code element are P codes. Therefore, when two consecutive P codes are identified, the first P code of the two consecutive P codes is the last code element of the previous frame of IRIG-B DC code, and the second P code is the first code element of the current frame of IRIG-B DC code, that is, the frame start code element of the current frame of IRIG-B DC code.

[0039] The frame start symbol is identified by:

[0040] When two consecutive P codes are identified, the second P code of the two consecutive P codes is used as the frame start code element of the current frame IRIG-B DC code, and the rising edge of the frame start code element of the current frame IRIG-B DC code is used as the frame start position of the current frame IRIG-B DC code.

[0041] Step S3: Set the maximum value N of the received codewords max , when receiving the Nth IRIG-B DC code of the current frame max After the code element, enable timer TIMER2 to start counting. When the count value of timer TIMER2 reaches the maximum value B of timer TIMER2 (the 99th code element of the current frame IRIG-B DC code is received at this time), an overflow interrupt is entered. After entering the interrupt function, timer TIMER3 is configured to single pulse mode and enabled, which specifically includes the following steps:

[0042] Step S3.1: Set the maximum value N of received codewords max , when the number of received symbols N is equal to N max When TIMER2 is enabled, timer TIMER2 starts counting; where 60<N max <99.

[0043] Step S3.2, timer TIMER2 generates an overflow interrupt when the count value is B, and timer TIMER3 is configured to single-pulse mode, which is triggered by the rising edge of the 100th code element of the current frame IRIG-B DC code (that is, the last code element of the current frame IRIG-B DC code, P code), and the programmable delay Delay of the single-pulse mode is set to generate the pulse signal width.

[0044] Where B is the maximum value of the timer TIMER2, and B satisfies the following formula:

[0045] B= (99-N) *T / T2 (1)

[0046] Wherein, T is the symbol period of the IRIG-B DC code, N is the number of received symbols, T2 is the clock period of timer TIMER2, T2 is a positive integer, * is the multiplication sign, and / is the division sign.

[0047] The programmable delay is based on the following formula:

[0048] Delay=(T-Δ) / T3 (2)

[0049] Wherein, Delay is the programmable delay in the single-pulse mode of timer TIMER3, Δ is the fixed delay triggered by the single-pulse hardware of the microcontroller timer, Δ is a constant, Δ is related to the microcontroller model, T is the symbol period of the IRIG-B DC code, T3 is the clock period of timer TIMER3, and / is the division sign.

[0050] The principle of the single-pulse mode is as Figure 4 shown. The single-pulse output is a special case of the comparison output mode, allowing timer TIMER3 to output a pulse signal with a programmable width after a programmable delay Δ when a set event (in this implementation, the rising edge of the 100th symbol of the external input signal IRIG-B DC code) occurs. Different from other output modes, when the counter is reset, the counter will automatically stop before the next update event arrives. Only when TIM_CCR1 is different from the initial value of the counter, can the pulse be correctly output. When counting up, it is required that CNT < TIM_CCR1 <= TIM_ARR, and when counting down, it is required that TIM_CNT > TIM_CCR1. Figure 4 The counter is triggered by the TI2 input signal. When the counted value is equal to TIM_CCR1, the OCxREF outputs a low level. When counting to TIM_ARR1, the OCxREF returns to a high level, and the counter rolls back to 0 and stops counting. Among them, update event represents the update operation or update event, CNT represents the counter value; CCR1 represents the capture / compare register 1, TIM_CCR1 represents the preset value of the capture / compare register 1. When the counted value of the counter is equal to TIM_CCR1, the timer enters an interrupt and executes the interrupt program. In this embodiment, CCR1 is used to set the programmable delay Δ. By setting the preset value TIM_CCR1, when the counted value of the counter is equal to TIM_CCR1, that is, after a programmable delay Δ; ARR represents the automatic reload register, which is used to reset the counted value of the counter to the preset initial value. TIM_ARR represents the set counting upper limit in the automatic reload register. When the counted value of the counter is equal to TIM_ARR, the counter will be reset to the preset initial value (such as 0); OCxREF represents the external event clear signal, TI2 is the input capture channel, Tpulse is the pulse width of the single pulse, OC1 refers to the output comparison channel 1, and T Delay is the programmable delay Delay.

[0051] Step S4, timer TIMER3 is triggered by the rising edge of the last P code element of the current frame IRIG-B DC code (also the last code element of the current frame IRIG-B DC code, the 100th code element), and then after a single pulse trigger fixed delay Δ and programmable delay Delay, outputs a signal second pulse 1PPS that is synchronized with the rising edge of the frame start code element of the next frame.

[0052] As an implementable method, the chip model of the MCU (single-chip microcomputer) is UM3243F, and an external clock stabilized 10MHz rubidium atomic clock is used as the system clock;

[0053] Timer TIMER1 is configured as 1MHz working clock, the counting function of timer TIMER1 is used, and it is configured as overflow interrupt;

[0054] Timer TIMER2 is configured as 100MHz working clock, the counting function of timer TIMER2 is used, and it is configured as overflow interrupt;

[0055] Timer TIMER3 is configured as 200MHz working clock and uses the single pulse mode of timer TIMER3.

[0056] Embodiment 2:

[0057] A method for generating an IRIG-B DC code synchronous second pulse leading edge based on a single chip microcomputer comprises the following steps:

[0058] like Figure 1 As shown, the encoding and decoding circuit of the IRIG-B DC code used in this embodiment includes a single-chip microcomputer, a 5V-3.3V power conversion circuit, a serial port transceiver circuit, an 8-way bus transceiver, and an input and output buffer; the chip model of the single-chip microcomputer used in this embodiment is UM3243F, and an external clock stable 10MHz rubidium atomic clock is used as the system clock of the single-chip microcomputer, which can provide an accurate time base for the MCU; the timer TIMER1 of the single-chip microcomputer is a 1MHz working clock, the counting mode of the timer TIMER1 is used, and the interrupt type is an external interrupt; the timer TIMER2 is configured as a 100MHz working clock, the counting mode of the timer TIMER2 is used, and the interrupt type is an overflow interrupt; the timer TIMER3 is configured as a 200MHz working clock, the single pulse mode of the timer TIMER3 is used, and the interrupt type is an external interrupt.

[0059] Since the code element no longer carries the required time information of year, month, day, hour, minute, and second when the number of code elements N>60, in this embodiment, the maximum value N of the received code elements is set. max When the number of received code elements N is equal to 68, timer TIMER2 is enabled to start counting.

[0060] Execute steps S1 and S2 in Example 1: initialize timer TIMER1, timer TIMER2, and timer TIMER3, enable timer TIMER1, determine the type of code element in the external signal IRIG-B DC code through timer TIMER1, determine the frame start position and frame start code element of the current frame IRIG-B DC code by detecting two consecutive P codes, and then continue to receive the remaining code elements in the current frame IRIG-B DC code to determine the type of each code element in turn to obtain the binary time information represented by each code element, and increase the number N of received code elements by 1 each time a code element is received.

[0061] Execute step S3 in Example 1: after receiving the 68th code element of the current frame IRIG-B DC code, enable timer TIMER2 to start counting. When the count value of timer TIMER2 reaches the maximum value B of timer TIMER2 (the 99th code element of the current frame IRIG-B DC code is received at this time), an overflow interrupt is entered. After entering the interrupt function, timer TIMER3 is configured to be in single pulse mode and enabled, triggered by the rising edge of the last code element of the current frame IRIG-B DC code, and the programmable delay Delay of the single pulse mode and the width of the generated pulse signal are set.

[0062] In this embodiment, the maximum value B of the count value of timer TIMER2 is:

[0063] B= (99-68) *10*10 -3 / (10 -2 *10 -6 )=31000000 (3)

[0064] In this embodiment, the fixed delay Δ of the single-pulse hardware trigger of the single-chip timer is 10ns (nanoseconds), so the programmable delay Delay in the single-pulse mode of the timer TIMER3 is set to:

[0065] Delay=(10*10 -3 -10*10 -9 )*(200*10 6 )=1999998 (4)

[0066] Execute step S4 in Example 1: the rising edge of the last P code in the current frame IRIG-B DC code triggers a single pulse of timer TIMER3, and after a fixed delay Δ and a programmable delay Delay, a second pulse 1PPS is output that is synchronized with the rising edge of the frame start code element in the next frame IRIG-B DC code.

[0067] The present invention does not need to use FPGA when achieving the same high precision. Through this method, a domestically produced single-chip microcomputer with a lower price can be used to replace the expensive FPGA, which will greatly reduce the application cost in large-scale applications.

[0068] It should be noted that the embodiments described in the present invention are merely examples of the spirit of the present invention. Those skilled in the art may make various modifications or additions to the described embodiments or replace them in similar ways, but they will not deviate from the spirit of the present invention or exceed the scope defined by the attached claims.

Claims

1. A method for generating the leading edge of IRIG-B DC code synchronous second pulse based on a single chip microcomputer, characterized in that: The following steps are involved: Step S1, initializing timer TIMER1, timer TIMER2, and timer TIMER3, then enabling timer TIMER1, judging the width of a code element in the IRIG-B DC code by timer TIMER1, and further judging the type of the code element; Step S2, repeat step S1 to determine the type of the received code element in turn, use the identified frame start code element as the frame start code element of the current frame IRIG-B DC code, use the rising edge of the frame start code element of the current frame IRIG-B DC code as the frame start position of the current frame IRIG-B DC code, then initialize the number N of received code elements to 1, then continue to receive the remaining code elements in the current frame IRIG-B DC code, and use timer TIMER1 to determine the type of each remaining code element in the current frame IRIG-B DC code in turn, and increase the number N of received code elements by 1 each time a code element is received; Step S3: Set the maximum value N of the received codewords max , when receiving the Nth IRIG-B DC code of the current frame max After a code element, enable timer TIMER2 to start counting. When the count value of timer TIMER2 reaches the maximum count value B of timer TIMER2, it enters the overflow interrupt. After timer TIMER2 enters the overflow interrupt, timer TIMER3 is configured to single pulse mode and enabled. Step S4, timer TIMER3 is triggered by the rising edge of the last code element of the current frame IRIG-B DC code. After being triggered, after a single pulse trigger fixed delay Δ and a programmable delay Delay, timer TIMER3 outputs a signal second pulse 1PPS synchronized with the rising edge of the frame start code element of the next frame.

2. According to the method for generating the leading edge of the IRIG-B DC code synchronous second pulse based on a single chip microcomputer as claimed in claim 1, it is characterized in that: The step S1 specifically includes the following steps: Timer TIMER1 enters an interrupt at the rising edge of each IRIG-B DC code element: when the IRIG-B DC code element is at a high level, timer TIMER1 counts; when the IRIG-B DC code element is at a low level, timer TIMER1 stops counting. The code element width is judged according to the count value of timer TIMER1 to obtain the code element type, and then the counter of timer TIMER1 is reset to judge the next code element.

3. According to the method for generating the leading edge of the IRIG-B DC code synchronous second pulse based on a single chip microcomputer as claimed in claim 1, it is characterized in that: The frame start symbol in step S2 is identified by: When two consecutive P codes are identified, the second P code of the two consecutive P codes is used as the frame start code element of the current frame IRIG-B DC code.

4. According to the method for generating the leading edge of the IRIG-B DC code synchronous second pulse based on a single chip microcomputer as claimed in claim 1, it is characterized in that: The maximum value B of the count of the timer TIMER2 in step S3 is calculated based on the following formula: B=(99-N)*T / T2 Where, T is the symbol period of the IRIG-B DC code, T2 is the clock period of timer TIMER2, * is the multiplication sign, and / is the division sign.

5. According to the method for generating the leading edge of the IRIG-B DC code synchronous second pulse based on a single chip microcomputer as claimed in claim 4, it is characterized in that: The step S3 specifically comprises the following steps: Step S3.1: Set the maximum value N of received codewords max , when the number of received symbols N is equal to N max When TIMER2 is enabled, timer TIMER2 starts counting; where 60<N max <99; Step S3.2, when the count value of timer TIMER2 is B, an overflow interrupt is generated, and timer TIMER3 is configured to single pulse mode, which is triggered by the rising edge of the 100th code element of the current frame IRIG-B DC code, and the programmable delay Delay of the single pulse mode is set to generate the pulse signal width.

6. According to the method for generating the leading edge of the IRIG-B DC code synchronous second pulse based on a single chip microcomputer as claimed in claim 1, it is characterized in that: The programmable delay Delay in step S4 is calculated based on the following formula: Delay=(T-Δ) / T3 Where Delay is the programmable delay in the single pulse mode of timer TIMER3, Δ is the fixed delay of the single pulse hardware trigger of the microcontroller timer, T is the symbol period of the IRIG-B DC code, T3 is the clock period of timer TIMER3, and / is the division sign.

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