Clock generator and clock generation method

Abstract

The present disclosure relates to a clock generator comprising: a ring oscillator (202) configured to generate an output frequency signal (FRO); a frequency detector (204) configured to compare a frequency of the output frequency signal to r times a frequency of a reference frequency signal (fREF) and generate a feedback signal (a, a '); and a control circuit (210) configured to: control a loop delay parameter (tau) of the ring oscillator and a supply voltage (Vdd) of the ring oscillator based on the feedback signal; when the frequency of the output frequency signal is higher than the frequency of the reference frequency signal by r times, reducing the frequency of the output frequency signal by reducing the power supply voltage; and when the frequency of the output frequency signal is lower than r times of the frequency of the reference frequency signal, increasing the frequency of the output frequency signal by reducing the loop delay parameter.

Description

Technical Field

[0001] The present disclosure relates generally to electronic circuits, and more particularly to clock generators and methods of clock generation. Background Art

[0002] There is an increasing demand for low power solutions for electronic circuits, especially for battery powered devices such as IoT (Internet of Things) devices where it is desired to increase the life of the battery between charges.

[0003] Low-power clock generators can be one of the solutions to reduce the power consumption of electronic circuits. For example, a particularly power-consuming part of an integrated circuit is the system clock, which is usually at a relatively high frequency. One mechanism for reducing the power consumption of an integrated circuit is to use a low-power or sleep mode when the circuit is not enabled and turn off the system clock during this period. Then, a low-power local clock generator can be used to drive a wake-up circuit that will wake up the integrated circuit at the appropriate time without using a central processing unit (CPU).

[0004] Such a clock generator should be able to generate a clock signal at a frequency that is relatively stable with PVT (process, voltage, temperature) variations, and the frequency is a variable frequency in some cases. This involves the use of a control loop for adjusting the clock frequency. However, there are technical difficulties in implementing such a control loop that can quickly converge to a frequency and voltage state with relatively low power consumption. Summary of the invention

[0005] It is an object of embodiments of the present disclosure to at least partially address one or more needs in the prior art.

[0006] According to one aspect, a clock generator is provided, comprising: a ring oscillator configured to generate an output frequency signal; a frequency detector configured to compare the frequency of the output frequency signal with r times the frequency of a reference frequency signal and generate a feedback signal based on the comparison; and a control circuit configured to control a loop delay parameter of the ring oscillator and a power supply voltage of the ring oscillator based on the feedback signal, wherein the control circuit is configured to: when the frequency of the output frequency signal is higher than r times the frequency of the reference frequency signal, reduce the frequency of the output frequency signal by reducing the power supply voltage, unless the power supply voltage has reached a minimum level, in which case, increase the loop delay parameter to reduce the frequency of the output frequency signal; and when the frequency of the output frequency signal is lower than r times the frequency of the reference frequency signal, increase the frequency of the output frequency signal by reducing the loop delay parameter, unless the loop delay parameter has reached a minimum level, in which case, increase the power supply voltage to increase the frequency of the output frequency signal.

[0007] According to an embodiment, the control circuit is configured to prevent a modification of the supply voltage once the control circuit has detected that the loop delay parameter has reached its minimum level.

[0008] According to one embodiment, the control circuit is configured to iteratively decrease and / or increase the loop delay parameter, with the decrease or increase amount at each iteration being equal to the step size.

[0009] According to one embodiment, the step size is variable as a function of the frequency difference between the frequency of the output frequency signal and the frequency of the reference frequency signal.

[0010] According to one embodiment, the step size is equal to a first step size until the loop delay parameter reaches the minimum level, and after the loop delay parameter reaches the minimum level, the step size is equal to a second step size, which is smaller than the first step size.

[0011] According to one embodiment, the clock generator further comprises a sigma-delta converter configured to convert the loop delay parameter into a plurality of control signals configured to control the ring oscillator.

[0012] According to one embodiment, the frequency detector is configured to compare the frequency of the output frequency signal with r times the frequency of the reference frequency signal by comparing the output frequency signal with r times the frequency of the reference frequency signal.

[0013] According to one embodiment, the ring oscillator includes a plurality of delay stages, each delay stage including: a multiplexer; a delay element coupled to a first input of the multiplexer, the first input being selected by a first state of a control signal of the multiplexer; a bypass path coupled to a second input of the multiplexer, the second input being selected by a second state of the control signal of the multiplexer; and a logic gate coupling an output of a previous stage to an input of the delay element, the logic gate receiving the control signal of the multiplexer and being configured to provide a constant signal to the delay element when the control signal is in a second state.

[0014] According to one embodiment, r is a real number greater than 1.

[0015] According to another aspect, an integrated circuit is provided, comprising: an electronic circuit controlled by a clock signal; and the above-mentioned clock generator, which is configured to provide the clock signal to the electronic circuit.

[0016] According to one embodiment, the integrated circuit further comprises: a voltage regulator configured to generate the supply voltage; and another electronic circuit powered by the supply voltage.

[0017] According to a further aspect, a clock generation method is provided, comprising: generating an output frequency signal through a ring oscillator; comparing the frequency of the output frequency signal with r times the frequency of a reference frequency signal through a frequency detector to generate a feedback signal based on the comparison; and controlling a loop delay parameter of the ring oscillator and a power supply voltage of the ring oscillator through a control circuit based on the feedback signal in the following manner: when the frequency of the output frequency signal is higher than r times the frequency of the reference frequency signal, reducing the frequency of the output frequency signal by reducing the power supply voltage, unless the power supply voltage has reached a minimum level, in which case the loop delay parameter is increased to reduce the frequency of the output frequency signal; and when the frequency of the output frequency signal is lower than r times the frequency of the reference frequency signal, increasing the frequency of the output frequency signal by reducing the loop delay parameter, unless the loop delay parameter has reached a minimum level, in which case the power supply voltage is increased to increase the frequency of the output frequency signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above features and advantages, as well as others, will be described in detail in the following description of specific embodiments with reference to the accompanying drawings, which are given by way of illustration and not limitation, in which:

[0019] Figure 1 schematically illustrates an integrated circuit of a clock generator included according to an example embodiment of the present disclosure;

[0020] Figure 2 In more detail, schematically illustrating an exemplary embodiment of the present disclosure Figure 1 Clock generator;

[0021] Figure 3 is a diagram showing an exemplary embodiment according to the present disclosure Figure 2 A graph of an example of a valid range of supply voltage and delay parameters of a ring oscillator of a clock generator;

[0022] Figure 4 is a flowchart illustrating operations in a method of clock generation in an example embodiment according to the present disclosure;

[0023] Figure 5 schematically illustrates a ring oscillator according to an example embodiment of the present disclosure;

[0024] Figure 6 is a graph showing the frequency variation with the loop delay parameter τ for a range of voltage settings;

[0025] Figure 7is a flowchart illustrating operations in a method of clock generation according to another example embodiment of the present disclosure;

[0026] Figure 8 is a graph showing the frequency variation with the loop delay parameter τ for a range of voltage settings;

[0027] Fig. 9 is a decision tree illustrating selection of a step size according to an example embodiment of the present disclosure;

[0028] Fig.10 is a flowchart illustrating operations in a method of clock generation according to yet another example embodiment of the present disclosure; and

[0029] Fig.11 An alternative implementation of a ring oscillator according to an example embodiment of the present disclosure is schematically illustrated. DETAILED DESCRIPTION

[0030] In the various drawings, the same features are identified by the same reference numerals. In particular, in various embodiments, common structural and / or functional features may have the same reference numerals and may be provided with the same structure, size and material properties.

[0031] For clarity, only the operations and elements useful for understanding the embodiments described herein are illustrated and described in detail.

[0032] Unless otherwise specified, when two elements are referred to as being connected together, it means they are directly connected without any intermediate elements other than conductors; when two elements are referred to as being coupled together, it means the two elements can be connected or coupled through one or more other elements.

[0033] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers, such as terms "front", "rear", "upper", "lower", "left", "right", etc., or relative position qualifiers, such as terms "above", "below", "higher", "lower", etc., or directional qualifiers, such as "horizontal", "vertical", etc., reference is made to the orientation shown in the accompanying drawings.

[0034] Unless otherwise specified, the expressions "approximately", "about", "substantially" and "about" mean within 10%, preferably within 5%.

[0035] Figure 1An integrated circuit 100 is schematically shown, which includes a circuit (CIRCUIT) 102 powered by a power supply voltage Vdd_c generated by a voltage regulator (V_REG) 104 and controlled by a clock signal M_CLK generated by a clock generator (CLK GENERATOR) 106. In some embodiments, the circuit 100 is configured to implement a wake-up function for waking up the integrated circuit 100 at an appropriate time. Alternatively, the circuit 100 has other functions that can be implemented under the control of the clock signal M_CLK.

[0036] For example, the clock generator 106 receives an input frequency signal f_EXT and a power supply voltage Vdd.

[0037] For example, the input frequency signal f_EXT is an external signal generated by an off-chip circuit, such as a PLL (Phase Locked Loop). For example, the input frequency signal f_EXT has a relatively stable frequency that varies with PVT (Process, Voltage, Temperature).

[0038] For example, the supply voltage Vdd is generated by another voltage regulator (V_REG) 108. In some embodiments, the clock generator 106 is configured to control the supply voltage Vdd provided by the voltage regulator 108, for example, by transmitting a control signal V_CTRL to the voltage regulator 108 on a control line 110. In some embodiments, the voltage regulator 108 is further configured to provide the supply voltage Vdd to another circuit (CIRCUIT 2) 112, which is, for example, located outside the integrated circuit 100.

[0039] Figure 2 In more detail, schematically illustrating an exemplary embodiment of the present disclosure Figure 1 A clock generator 106 is provided.

[0040] For example, the clock generator 106 includes a ring oscillator (RO) 202 configured to generate an output frequency signal F_RO.

[0041] For example, the clock generator 106 also includes a frequency detector (FD) 204, which is configured to receive the output frequency signal F_RO from the ring oscillator 202 and compare the frequency of the signal F_RO with the frequency of the reference frequency signal f_REF. For example, the reference frequency signal f_REF is generated by a frequency divider (÷p) 206 according to the input frequency signal f_EXT. For example, the frequency divider 206 is configured to divide the frequency of the input frequency signal f_EXT by a frequency division coefficient p to generate the reference frequency signal f_REF, for example, where p is equal to 1 or more.

[0042] For example, the frequency detector 204 is configured to generate an output signal a', where the output signal a' is equal to freq_RO / freq_REF - r, where freq_RO is the frequency of the signal F_RO, freq_REF is the frequency of the signal f_REF, and r is the desired ratio between the frequency of the signal F_RO and the frequency of the signal f_REF. In some embodiments, r is a real number equal to or greater than 1. For example, the output signal a' is a digital signal. For example, the output signal a' is processed by a low-pass filter (LPF) 208 to generate a feedback signal a, and the feedback signal a is provided to the control circuit (CTRL) 210. The control circuit (CTRL) 210 is configured to apply a control algorithm based on the feedback signal a to adjust the supply voltage Vdd and / or the loop delay parameter τ of the ring oscillator 202. For example, the control circuit 210 outputs a control signal V_CTRL to the voltage regulator 108, and the voltage regulator 108 in turn generates a corresponding supply voltage Vdd, and the supply voltage Vdd powers the ring oscillator 202. For example, the control circuit 210 also outputs a control signal τ, and the control signal τ indicates the delay to be applied by the ring oscillator 202. In some embodiments, the control signal τ is provided to a sigma-delta converter 212, which is configured to generate another control signal τ_ctrl based on the control signal τ, and the control signal τ_ctrl is used to control the ring oscillator. For example, the control signal τ is an n-bit signal, and the control signal τ_ctrl is an n'-bit signal, where n' < n. In one embodiment, the control signal τ is an 8-bit signal, and the control signal τ_ctrl is a 4-bit signal.

[0043] For example, the output frequency signal F_RO is provided to a frequency divider (÷m) 214, which is configured to divide the frequency of the signal F_RO by a division factor m to generate an output clock signal M_CLK. For example, where m is equal to 1 or more.

[0044] In an alternative embodiment of the clock generator 106, the frequency divider 206 and / or the frequency divider 214 may be omitted.

[0045] Figure 3 is a graph showing an example of the effective range of the supply voltage Vdd and the delay τ of the ring oscillator 202 of the clock generator 106 according to an exemplary embodiment of the present disclosure. Figure 2

[0046] As shown, the supply voltage Vdd has a maximum level Vdd_max and a minimum level Vdd_min, such that: Vdd_min < Vdd < Vdd_max.

[0047] Similarly, the ring oscillator delay τ has a maximum level τ maxand the minimum level τ min , so that: τ min <τ<τ max .

[0048] For example, when the power supply voltage is Vdd_max and the ring oscillator delay is τ min , or the supply voltage is Vdd_min and the ring oscillator delay is τ max Errors will occur when the system is not able to generate the desired frequency.

[0049] Reference again Figure 2 , the control circuit 210 is configured to control the loop delay parameter τ of the ring oscillator 202 and the power supply voltage Vdd of the ring oscillator 202 based on the feedback signal a. In particular, the control circuit 210 is configured to reduce the frequency of the output frequency signal F_RO by reducing the power supply voltage when the frequency of the output frequency signal F_RO is higher than r times the frequency of the reference frequency signal f_REF, unless the power supply voltage has reached the minimum level Vdd_min, in which case the loop delay parameter τ is increased to reduce the frequency of the output frequency signal F_RO. The control circuit 210 is also configured to increase the frequency of the output frequency signal F_RO by reducing the loop delay parameter τ when the frequency of the output frequency signal F_RO is lower than r times the frequency of the reference frequency signal f_REF, unless the loop delay parameter τ reaches the minimum value τ min In this case, the power supply voltage Vdd is increased to increase the frequency of the output frequency signal F_RO.

[0050] Figure 4 is a more detailed illustration of an exemplary embodiment of the present disclosure. Figure 2 Flow chart of the operations implemented by the control circuit 210.

[0051] In operation 402, it is determined whether the feedback signal a is greater than 0. In fact, in some embodiments, a positive value of the signal a indicates that the frequency of the signal F_RO is higher than r times the frequency of the reference signal f_REF, while a negative value of the signal a indicates that the frequency of the signal F_RO is lower than r times the frequency of the reference signal f_REF. In alternative embodiments, the feedback signal a may have other values ​​to indicate the relative frequencies of the signals F_RO and f_REF.

[0052] For example, in the case where the feedback signal a is positive (branch Y), the frequency of F_RO is reduced. For example, this involves operation 404, in which it is determined whether the power supply voltage Vdd is greater than Vdd_min. If yes (branch Y), the power supply voltage Vdd is reduced, for example, in operation 406. If no (branch N), the ring oscillator delay τ is increased, for example, in operation 408.

[0053] For example, in case the feedback signal a is negative (branch N), the frequency of F_RO increases. For example, this involves operation 410, in which it is determined whether the ring oscillator delay τ is greater than a minimum level τ min If yes (branch Y), the ring oscillator delay τ is decreased, for example in operation 412. If no (branch N), the supply voltage Vdd is increased, for example in operation 414.

[0054] After operation 406 , 408 , 412 , or 414 , the method is repeated for a new value of the target signal F_RO, for example based on an updated supply voltage Vdd or an updated ring oscillator delay τ.

[0055] The advantage of lowering the power supply voltage to lower the frequency and lowering the ring oscillator delay τ to increase the frequency is that the algorithm converges to a relatively low power supply voltage Vdd, thereby achieving a state of relatively low power consumption.

[0056] Figure 5 In more detail, schematically illustrating an exemplary embodiment of the present disclosure Figure 2 The ring oscillator 202 is provided.

[0057] exist Figure 5 In the example of FIG. 5 , the ring oscillator includes a series of delay elements 502, 504, 506, and 508. In some embodiments, the delay elements have binary weights, for example, element 502 introduces The delay, for example, element 504 introduces The delay, for example, element 506 introduces The delay, for example, element 508 introduces The delay of is a unit delay, for example, between 1ns and 100ns.

[0058] For example, the delay element 502 is coupled between the output of a logic gate 510 (eg, an AND gate) and one input of a multiplexer 512. For example, the second input of the multiplexer 512 is directly connected to the output of the logic gate 510.

[0059] For example, the delay element 504 is coupled between the output of the multiplexer 512 and one input of the multiplexer 514. For example, the second input of the multiplexer 514 is directly connected to the output of the multiplexer 512.

[0060] For example, the delay element 506 is coupled between the output of the multiplexer 514 and one input of the multiplexer 516. For example, the second input of the multiplexer 516 is directly connected to the output of the multiplexer 514.

[0061] For example, the delay element 508 is coupled between the output of the multiplexer 516 and one input of the multiplexer 518. For example, the second input of the multiplexer 518 is directly connected to the output of the multiplexer 516.

[0062] For example, multiplexers 512, 514, 516, and 518 are controlled by control signals S1, S2, S3, and S4, respectively. For example, these control signals form a Figure 2 The control signal τ_CTRL is generated by the sigma-delta converter 212. In one example, a low or zero logic state of any one of the control signals S1 to S4 causes the output signal of the logic gate 510 or the preceding multiplexers 512, 514, 516 to be selected by the corresponding multiplexers 512, 514, 516, 518, while a high or one logic state of any one of the control signals S1 to S4 causes the output of the corresponding delay element 502, 504, 506 or 508 to be selected by the corresponding multiplexers 512, 514, 516, 518.

[0063] The output of the multiplexer 518 is coupled to the input of the logic gate 510, for example, via another delay element 520, which is configured to introduce a wherein n is, for example, equal to between 1 and 50. For example, another input terminal of the logic gate 510 receives the enable signal EN. For example, when the enable signal EN is at a logic high level, the ring oscillator 202 operates.

[0064] Therefore, in Figure 5 In the example of FIG. 1 , the ring oscillator 202 may be controlled to have and The loop delay between

[0065] Figure 6 is a graph showing the frequency (FREQ) of the parameter τ(TAU) for a series of voltage settings and shows Figure 4 An example of a control algorithm.

[0066] exist Figure 6 In the example of Figure 6 Only up to +112 is shown). Such a range of values ​​is obtained, for example, as follows: using Figure 5 and controls the four control bits S1 to S4 to have a corresponding one of their 16 settings, and by using Figure 2 The sigma-delta converter 212 is used to provide another 4 control bits, resulting in a total of 8 control bits, or 256 values ​​of the parameter τ.

[0067] also, Figure 6The 17 curves in FIG. 1 represent the output frequency for a supply voltage ranging from 0.6V to 1.4V.

[0068] According to a first example of a control algorithm EX1, the supply voltage starts at its highest level of 1.4V and the parameter τ starts at the highest level allowed by the clock generator 106, for example equal to 112. Then by Figure 4 Operations 402, 410 and 412 reduce the parameter τ until the frequency of F_RO rises above the target frequency freq_TARGET (equal to r times the frequency of the reference frequency signal f_REF). Figure 4 Operations 402, 404 and 406 iteratively reduce the supply voltage, each iteration causing the frequency of F_RO to drop below the target frequency freq_TARGET and causing the parameter τ to further decrease until the parameter τ reaches its minimum level τ min , -128. At this point, both the power supply voltage and the parameter τ are increased so as to reach the convergence point CP. For example, the power supply voltage and the parameter τ then enter a permanent hysteresis loop in which they oscillate between their values ​​at the convergence point and the next lowest level.

[0069] according to Figure 6 In the example EX2, the power supply voltage level is the lowest value Vdd_min, which causes the frequency of F_RO to be lower than the target frequency freq_TARGET (equal to r times the frequency of the signal f_REF), so Figure 4 Operations 402, 410 and 412 result in a decrease in the parameter τ until the parameter τ reaches its minimum level τ min , -128. The supply voltage is then increased until the frequency of the signal F_RO exceeds the target frequency freq_TARGET, at which point the parameter τ increases to reach the convergence point CP. For example, the supply voltage and the parameter τ then enter a permanent hysteresis loop in which they oscillate between their values ​​at the convergence point and the next lowest level.

[0070] In order to prevent the supply voltage from changing during the hysteresis loop (which may cause additional power consumption), an improved algorithm is used, for example, which now refers to Figure 7 The improved algorithm is described in more detail.

[0071] Figure 7 is a flowchart illustrating operations in a method of clock generation according to another example embodiment of the present disclosure. The method is, for example, Figure 2 The control circuit 210 is implemented.

[0072] Figure 7 Some operations in Figure 4The operations are the same as in , and these operations have been identified with the same figure marks and will not be described in detail again.

[0073] For example, Figure 7 The algorithm starts from operation 402, such as Figure 4 As shown, if the feedback signal a is less than 0 (branch N), operation 410 is implemented, and if the parameter τ is greater than its minimum level τ min (Branch Y), then operation 412 is performed. However, if the parameter τ is not greater than its minimum level τ min (Branch N), then in operation 710, the power supply voltage is increased, and the variable R is set equal to 1. For example, the variable R is a one-bit information, which is initialized to 0 at the beginning of the algorithm.

[0074] If the feedback signal a is less than 0 (branch Y) in operation 402, operation 702 is performed, in which it is determined whether the variable R is equal to 1. If not (branch N), then Figure 4 Operation 404 is performed as shown, and then operation 406 or operation 408 is performed. However, if R is equal to 1 (branch Y), then in operation 704 it is determined whether the parameter τ is greater than or equal to its maximum level τ max , τ max For example, a threshold value for triggering the modification of the variable R. For example, in one example τ max is equal to 112, while the maximum theoretical level that the parameter τ can reach is higher than τ max , for example 127. If the parameter τ is greater than or equal to its maximum level τ max (Branch Y), then in operation 706, the parameter τ is incremented and the variable R is set to zero. However, if the parameter τ is less than τ max , then in operation 708, the parameter τ is increased without setting the variable R to zero. Thus, once the parameter τ reaches its minimum value τ min When τ is at this value and level τ min +1 while the power supply voltage remains unchanged.

[0075] Figure 4 and Figure 7 The algorithm in is based on increasing or decreasing the parameter τ by a step size of one. In an alternative embodiment, using a variable step size can achieve faster convergence, which will now be referred to Figure 8 , Fig. 9 and Fig.10 Describe in more detail.

[0076] Figure 8is a graph showing the frequency (FREQ) as a function of the parameter τ (TAU) for a range of voltage settings. Two examples EX1 and EX2 are shown, showing the convergence of the parameter τ to the convergence point CP, the example EX1 being based on an initial supply voltage equal to Vdd_max and the example EX2 being based on an initial supply voltage equal to Vdd_min. In both examples, the parameter τ decreases until it reaches a minimum level τ min For example, the step size depends on whether the frequency of the signal F_RO exceeds the target frequency freq_TARGET, whether a hysteresis period has been entered, and / or the degree to which the frequency of the signal F_RO is close to r times the frequency of the reference frequency signal f_REF.

[0077] For example, until the frequency of the signal F_RO has exceeded r times the frequency of the reference frequency signal f_REF, the supply voltage is not changed, for example, with a step size equal to a relatively large step size, such as 16 in one example.

[0078] Once the frequency of the signal F_RO has exceeded r times the frequency freq_REF, and if a hysteresis period has not yet been entered (which occurs in EX1 but not in EX2), the step size depends, for example, on how close the frequency of the signal F_RO is to r times the frequency freq_REF. Figure 8 As shown on the right, if the r times of the frequency of the target signal F_RO is:

[0079] - In the frequency interval I1, for example, equal to freq_REF plus or minus j Hz, the step size is equal to 1 (STP=1);

[0080] - within the frequency interval I2, for example, equal to freq_REF plus or minus k Hz, where k>j, then the step size is equal to 2 (STP=2);

[0081] - In the frequency interval I3, for example, equal to freq_REF plus or minus 1 Hz, where l>k, the step size is equal to 4 (STP=4);

[0082] - within the frequency interval I4, for example equal to freq_REF plus or minus s Hz, where s>1, then the step size is equal to 8 (STP=8); and

[0083] - In the frequency interval I5, for example, equal to freq_REF plus or minus q Hz, where q>p, the step size is equal to 16 (STP=16).

[0084] Once the hysteresis period has been entered, the step size may, for example, be reduced to a relatively low value, for example equal to one.

[0085] Fig. 9is a decision tree illustrating the selection of step length according to an example embodiment of the present disclosure. The method is, for example, Figure 2 The control circuit 210 in is implemented.

[0086] In operation 902, it is determined whether the variable SS is set to 1, for example. If so (branch Y), then in operation 904, the step size is set to 1, for example (STP=1). Alternatively, if the variable SS is not set to 1 in operation 902 (branch N), operation 906 is performed.

[0087] In operation 906, it is determined whether the variable BS is set to 1, for example. If so (branch Y), the step size is set to 16 (STP=16) in operation 904, for example. Alternatively, if the variable BS is not set to 1 in operation 906 (branch N), operation 910 is performed.

[0088] In operation 910, for example, it is determined whether the magnitude of the difference between the frequency of the signal F_RO and the frequency freq_REF is less than a first threshold. For example, as described above, Figure 2 The frequency detector 204 is configured to output a value a', a' representing the difference between the frequency of the signal F_RO and r times the frequency freq_REF. Fig. 9 In the example of , each period of the reference frequency is expected to correspond to r=610 periods of the ring oscillator clock, and the value a' represents the number of ring oscillator periods during one period of the reference frequency minus 610. Thus, the value a'=0 represents, for example, that the frequency of the signal F_RO is at the target value, and the value a'=610 represents, for example, that the frequency of the signal F_RO is 2 times higher than expected. For example, in Fig. 9 In the example of , the first threshold is equal to 76. If |a'|<76 (branch Y), then in operation 912, the step size is set to 1 (STP=1), for example. Alternatively, if in operation 910, |a'|≥76 (branch N), operation 914 is performed.

[0089] In operation 914, for example, it is determined whether a' is between a first threshold and a second threshold greater than the first threshold. Fig. 9 In the example of , the second threshold is equal to 122. If 76<|a'|<122 (branch Y), then in operation 916, the step size is set to 2 (STP=2), for example. Alternatively, if in operation 914, |a'|≥122 (branch N), operation 918 is performed.

[0090] In operation 918, for example, it is determined whether a' is between the second threshold and a third threshold greater than the second threshold. Fig. 9In the example of , the third threshold is equal to 244. If 122<|a'|<244 (branch Y), then in operation 920, the step size is set to 4 (STP=4), for example. Alternatively, if in operation 918, |a'|≥244 (branch N), operation 922 is performed.

[0091] In operation 922, for example, it is determined whether a' is between a third threshold and a fourth threshold greater than the third threshold. Fig. 9 In the example of , the fourth threshold is equal to 427. If 244<|a'|<427 (branch Y), in operation 924, the step size is set to 8 (STP=9), for example. Alternatively, if in operation 922, |a'|≥427 (branch N), operation 926 is performed.

[0092] In operation 926, for example, it is determined whether a' is between a fourth threshold and a fifth threshold greater than the fourth threshold. Fig. 9 In the example of , the fifth threshold is equal to 458. If 427<|a'|<458 (branch Y), then in operation 928, the step size is set to 16 (STP=16), for example. Alternatively, if in operation 926, |a'|≥458 (branch N), operation 930 is performed, in which the step size is set to 32 (STP=32), for example.

[0093] Of course, the above-mentioned first threshold, second threshold, third threshold, fourth threshold and fifth threshold are only examples, and other values ​​are also possible. In addition, there may be different numbers of thresholds, such as only one, two, three or four thresholds, or more than five thresholds.

[0094] Fig.10 is a flowchart illustrating operations in a method of clock generation in another exemplary embodiment of the present disclosure. The method is, for example, Figure 2 This is achieved by the control circuit 210 in FIG.

[0095] Fig.10 Some operations in Figure 7 The operations are the same as those of FIG. 1 , and these operations have been identified with the same reference numerals and will not be described in detail again.

[0096] exist Fig.10 In the algorithm, about Figure 7 The algorithm of , some operations have been replaced as shown below.

[0097] exist Fig.10 middle, Figure 7 Operation 704 is replaced by operation 1004, in which it is determined whether τ+step≥τ is satisfied. max If it is (branch Y), then in the alternative Figure 7In operation 1006 of operation 706 of FIG. 1 , parameter τ increases the current step size (e.g., by Fig. 9 ), the variable R is set to 0, and the variable BS is set to 1. If it is determined in operation 1004 that τ+step<τ max , then in the replacement Figure 7 In operation 1008 of operation 708 of the invention, the parameter τ increases the current step size (e.g., by Fig. 9 ), and the variable BS is set to 0.

[0098] exist Fig.10 middle, Figure 7 Operation 408 in is replaced by operation 1009, in which the parameter τ increases the current step size (e.g., by Fig. 9 ), and the variable BS is set equal to 0.

[0099] exist Fig.10 middle, Figure 7 Operation 410 in is replaced by operation 1010, in which it is determined whether τ-step ≥ τ is satisfied. min If it is (branch Y), then in the alternative Figure 7 In operation 1012 of operation 412 of FIG. 4 , the parameter τ is reduced by the current step size (e.g., by Fig. 9 If, in operation 1010, it is determined that τ-step<τ min , then in the replacement Figure 7 In operation 1013 of operation 710 , the power supply voltage Vdd increases, the variable R is set to 1, and the variable SS is set to 1, for example.

[0100] Fig.11 Schematically shows the Figure 5 Alternative Example Embodiments of Ring Oscillators Figure 2 An alternative embodiment of the ring oscillator 202 is provided. Fig.11 Some components are related to Figure 5 The same elements as in the above are marked with the same reference numerals and will not be described in detail again.

[0101] about Figure 5 An example implementation of Fig.11 The embodiment of the present invention further includes, for example, a logic gate 1102 (e.g., an OR gate), which couples the output terminal of the AND gate 510 to the input terminal of the delay element 502. Specifically, for example, one of the input terminals of the OR gate 1102 is coupled to the output terminal of the AND gate 510, the other input terminal of the OR gate 1102 is coupled to receive the control signal S1 through an inverter 1104, and the output terminal of the OR gate 1102 is coupled to the input terminal of the delay element 502.

[0102] Similarly, regarding Figure 5 An example implementation of Fig.11 The embodiment of the present invention further includes, for example, a logic gate 1106 (e.g., an OR gate) that couples the output of the multiplexer 512 to the input of the delay element 504. For example, one of the inputs of the OR gate 1106 is coupled to the output of the multiplexer 512, the other input of the OR gate 1106 is coupled to receive the control signal S2 through the inverter 1108, and the output of the OR gate 1106 is coupled to the input of the delay element 504.

[0103] Likewise, about Figure 5 An example implementation of Fig.11 The embodiment of the present invention further includes, for example, a logic gate 1110 (e.g., an OR gate) that couples the output of the multiplexer 514 to the input of the delay element 506. For example, one of the inputs of the OR gate 1110 is coupled to the output of the multiplexer 514, the other input of the OR gate 1110 is coupled to receive the control signal S3 through an inverter 1112, and the output of the OR gate 1110 is coupled to the input of the delay element 506.

[0104] Likewise, about Figure 5 An example implementation of Fig.11 The embodiment of the present invention further includes, for example, a logic gate 1114 (e.g., an OR gate) that couples the output of the multiplexer 516 to the input of the delay element 508. For example, one of the inputs of the OR gate 1114 is coupled to the output of the multiplexer 516, the other input of the OR gate 1114 is coupled to receive the control signal S4 through an inverter 1116, and the output of the OR gate 1114 is coupled to the input of the delay element 508.

[0105] For example, the addition of logic gates 1102, 1106, 1110, and 1114 helps reduce the risk of glitches when control signals S1 to S4 transition. Specifically, when any control signal is zero, the corresponding logic gates 1102, 1106, 1110, 1114 are configured to output a constant logic high state, rather than oscillating based on propagation around the ring. This means that when any control signal transitions from zero to a logic high state, there is a stable signal at the "1" input of the corresponding multiplexer 512 to 518.

[0106] An advantage of the embodiments described herein is that a clock generator having a ring oscillator can converge quickly toward a target frequency while selecting a relatively low supply voltage, thereby reducing the power consumption of the ring oscillator. In addition, once the clock generator reaches the target frequency, Figure 7 The embodiments allow for a stable supply voltage while Fig.10 Embodiments of allow faster convergence by using a variable step size of the loop delay parameter τ.

[0107] An advantage of using the power supply voltage Vdd to power other circuits (e.g., circuit 112) in addition to the clock generator 106 is that this voltage will be regulated to a relatively low level, resulting in relatively low power consumption, while still achieving the target performance of the clock generator 106, which means that this voltage can also enable other circuits to achieve their desired performance with relatively low power consumption.

[0108] By describing various embodiments and variations, those skilled in the art will appreciate that certain features of these embodiments may be combined, and that other variations will be readily apparent to those skilled in the art. For example, it will be apparent to those skilled in the art that the described implementation of the ring oscillator is merely an example, and that other architectures are possible. Furthermore, the invention may be combined in different ways. Figure 4 , Figure 7 and Fig.10 Characteristics of the algorithm in . For example, Fig.10 The variable step size of the algorithm in can be Figure 4 In other words, the variable R can also be implemented in the algorithm.

[0109] Furthermore, while embodiments involving sigma-delta controllers have been described, in alternative embodiments such controllers may not be used. An advantage of using a sigma-delta controller is that it allows for finer control of the loop delay of the ring oscillator without adding additional multiplexers to the ring oscillator which would degrade its performance.

[0110] Finally, actual implementation of the embodiments and variations described herein are well within the capabilities of those skilled in the art based on the functional description provided above.

Claims

1. A clock generator, comprising: - a ring oscillator (202) configured to generate an output frequency signal (F_RO); - a frequency detector (204) configured to compare the frequency of the output frequency signal (F_RO) with r times the frequency of a reference frequency signal (f_REF) and to generate a feedback signal (a, a') based on the comparison; and - a control circuit (210) configured to control a loop delay parameter (τ) of the ring oscillator and a supply voltage (Vdd) of the ring oscillator based on the feedback signal (a, a′), wherein the control circuit is configured to: When the frequency of the output frequency signal (F_RO) is higher than r times the frequency of the reference frequency signal (f_REF), the frequency of the output frequency signal (F_RO) is reduced by reducing the power supply voltage (Vdd) without changing the loop delay parameter, unless the power supply voltage has reached a minimum level (Vdd_min), in which case the loop delay parameter (τ) is increased to reduce the frequency of the output frequency signal (F_RO); and when the frequency of the output frequency signal (F_RO) is lower than r times the frequency of the reference frequency signal (f_REF), the frequency of the output frequency signal (F_RO) is increased by reducing the loop delay parameter (τ) without changing the power supply voltage, unless the loop delay parameter (τ) has reached a minimum level (τ min ), in this case, the power supply voltage (Vdd) is increased to increase the frequency of the output frequency signal (F_RO).

2. The clock generator according to claim 1, wherein: The control circuit (210) is configured to, once the control circuit (210) has detected that the loop delay parameter (τ) has reached its minimum level (τ min ), the modification of the power supply voltage (Vdd) is prevented.

3. The clock generator according to claim 1 or 2, wherein the control circuit (210) is configured to iteratively reduce and / or increase the loop delay parameter (τ), and the reduction or increase amount in each iteration is equal to the step size (step).

4. The clock generator according to claim 3, wherein: The step size is variable as a function of the frequency difference between the frequency of the output frequency signal (F_RO) and the frequency of the reference frequency signal (f_REF).

5. The clock generator according to claim 3, wherein: The step size is equal to the first step size until the loop delay parameter (τ) reaches the minimum level (τ min ), and when the loop delay parameter (τ) reaches the minimum level (τ min ) after which the step length is equal to a second step length, and the second step length is smaller than the first step length.

6. The clock generator according to claim 1 or 2, further comprising a sigma-delta converter (212) configured to convert the loop delay parameter (τ) into a plurality of control signals (S1, S2, S3, S4), wherein the plurality of control signals (S1, S2, S3, S4) are configured to control the ring oscillator.

7. The clock generator according to claim 1 or 2, wherein: The frequency detector (204) is configured to compare the frequency of the output frequency signal (F_RO) with r times the frequency of the reference frequency signal (f_REF) by comparing the output frequency signal (F_RO) with r times the frequency of the reference frequency signal (f_REF).

8. The clock generator according to claim 1 or 2, wherein: The ring oscillator includes a plurality of delay stages coupled in series, each delay stage being configured to be enabled or disabled by the loop delay parameter.

9. The clock generator of claim 8, wherein each delay stage comprises: - Multiplexer (512, 514, 516, 518); a delay element (502, 504, 506, 508) coupled to a first input of the multiplexer (512, 514, 516, 518), the first input being selected by a first state of a control signal (S1, S2, S3, S4) of the multiplexer; - a bypass path coupled to a second input of the multiplexer (512, 514, 516, 518), the second input being selected by a second state of a control signal (S1, S2, S3, S4) of the multiplexer; and - a logic gate (1102, 1106, 1110, 1114) coupling the output of the previous stage to the input of the delay element (502, 504, 506, 508), the logic gate receiving the control signal (S1, S2, S3, S4) of the multiplexer and being configured to provide a constant signal to the delay element when the control signal is in a second state.

10. The clock generator according to claim 1 or 2, wherein r is a real number greater than 1.

11. An integrated circuit (100), comprising: - an electronic circuit (102) controlled by a clock signal (M_CLK); and - The clock generator (106) of any one of claims 1 to 9, configured to provide the clock signal (M_CLK) to the electronic circuit (102).

12. The integrated circuit of claim 11 , further comprising: - a voltage regulator (V_REG, 108) configured to generate said supply voltage (Vdd); and - another electronic circuit (112) powered by said supply voltage (Vdd).

13. A method for clock generation, comprising: - generating an output frequency signal (F_RO) by means of a ring oscillator (202); - comparing the frequency of the output frequency signal (F_RO) with r times the frequency of the reference frequency signal (f_REF) by a frequency detector (204) to generate a feedback signal (a, a') based on the comparison; and - Controlling the loop delay parameter (τ) of the ring oscillator and the power supply voltage (Vdd) of the ring oscillator based on the feedback signal (a, a′) by the control circuit (210) in the following manner: When the frequency of the output frequency signal (F_RO) is higher than r times the frequency of the reference frequency signal (f_REF), the frequency of the output frequency signal (F_RO) is reduced by reducing the power supply voltage (Vdd) without changing the loop delay parameter, unless the power supply voltage has reached a minimum level (Vdd_min), in which case the loop delay parameter (τ) is increased to reduce the frequency of the output frequency signal (F_RO); and When the frequency of the output frequency signal (F_RO) is lower than r times the frequency of the reference frequency signal (f_REF), the frequency of the output frequency signal (F_RO) is increased by reducing the loop delay parameter (τ) without changing the power supply voltage unless the loop delay parameter (τ) has reached a minimum level (τ min ), in this case, the power supply voltage (Vdd) is increased to increase the frequency of the output frequency signal (F_RO).

14. The method according to claim 13, wherein: The ring oscillator includes a plurality of delay stages coupled in series, wherein reducing the loop delay parameter results in deactivation of one or more of the delay stages.

Images