Digital-to-analog converter

Abstract

The invention relates to a digital-to-analog converter. A method for controlling a digital-to-analog converter (DAC) is provided. The DAC receives a digital input including a plurality of bits including a first segment including X most significant bits (MSBs) and a second segment including Y least significant bits (LSBs). The DAC modifies the connection of the plurality of current sources, changing the current source coupling between the LSB and MSB transconductance stages. By doing so, the monotonicity of the system can be improved in a compact DAC.

Description

Technical Field

[0001] The invention relates to a method for controlling a digital-to-analog converter and a digital-to-analog converter. Background Art

[0002] A digital-to-analog converter (DAC) receives a digital input, code or word, and produces an analog output signal. A segmented DAC can include multiple sections or DACs, each of which is configured to convert a different portion of the digital input. These sections can then be combined to provide the analog output of the DAC.

[0003] The digital input includes one or more most significant bits (MSBs) and one or more least significant bits (LSBs). Therefore, the segmented DAC may include one or more most significant bit portions for converting the MSBs of the digital input, and one or more least significant bit portions for converting one or more LSBs. The outputs of the MSB and LSB portions are then combined to provide an analog

[0004] The segmented DAC can be based on one of several different DAC technologies, such as ladder DAC or string DAC. Depending on how the MSB and LSB portions of the DAC are segmented, the size of the decoder and the number of switches required may change. In addition, the segmentation of the DAC affects the linearity and monotonicity of the system.

[0005] It is desirable to provide a DAC including a limited number of switches having improved monotonicity. Summary of the invention

[0006] A method for controlling a digital-to-analog converter (DAC) is provided. In the method, the following steps are performed: receiving a digital input; detecting a change in the value of the most significant bit of the digital input; decoupling a first current source from a first transconductance stage; and coupling the first current source to a second transconductance stage.

[0007] According to a first aspect of the present disclosure, a method for controlling a digital-to-analog converter DAC is provided, the method comprising: receiving a digital input including a plurality of bits, the plurality of bits including a first segment including X most significant bits MSBs and a second segment including Y least significant bits LSBs; detecting a change in an MSB value and detecting a change in an LSB value; Y -1; decoupling the first current source from the least significant bit LSB transconductance stage of the DAC; and coupling the first current source to the first most significant bit MSB transconductance stage of the decoder.

[0008] According to a second aspect of the present disclosure, a digital-to-analog converter DAC circuit is provided, comprising: an input for: receiving a digital input including a plurality of bits, the plurality of bits including a first segment including X most significant bits MSB and a second segment including Y least significant bits LSB; an LSB transconductance stage; one or more MSB transconductance stages, including a first transconductance stage; a first current source; a switch circuit, the switch circuit being coupled between the first current source and the LSB transconductance stage and the one or more MSB transconductance stages, wherein when a change in the MSB value and a change in the LSB value are 2 Y –1, the switch circuit is configured to: decouple the first current source from the LSB transconductance stage, and couple the first current source to the first MSB transconductance stage.

[0009] According to a third aspect of the present disclosure, a method for controlling a digital-to-analog converter DAC is provided, the method comprising: receiving a digital input; detecting a change in a value of a most significant bit (MSB) of the digital input; and detecting a change in a value of a least significant bit (LSB) of the digital input. Y −1; decoupling a first current source from a first transconductance stage of the DAC; and coupling the first current source to a second transconductance stage of a decoder. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of the segmented DAC;

[0011] Figure 2a is a schematic diagram of a segmented DAC system;

[0012] Figure 2b is formed Figure 2a A schematic diagram of a resistor string that is part of the first stage of a DAC system;

[0013] Figure 3 is a schematic diagram of a four-bit segmented DAC with multiple current sources;

[0014] Figure 4 is a schematic diagram of a four-bit segmented DAC including a switching circuit;

[0015] Figure 5 is a flow chart of a method for controlling a DAC;

[0016] Figure 6a is a schematic diagram of a four-bit segmented DAC including a switch circuit coupled to a current source in a first position;

[0017] Figure 6b is a schematic diagram of a four-bit segmented DAC including a switch circuit coupled to a current source at a second position;

[0018] Figure 6cis a schematic diagram of a four-bit segmented DAC including a switch circuit coupled to a current source at a third position;

[0019] Figure 7 is a schematic diagram of a negative feedback transistor coupled between a current source and a differential pair. DETAILED DESCRIPTION

[0020] A segmented DAC includes one or more most significant bit sections for converting the MSBs of a digital input, and one or more least significant bit sections for converting one or more LSBs of a digital input. Depending on how the MSB and LSB sections of the DAC are segmented, the size of the decoder and the number of switches required may vary.

[0021] The segmented DAC can include a thermometric LSB level. The thermometric DAC guarantees monotonicity of the analog output. The output of a fully monotonic DAC is in the same direction as the input (for example, when the input increases, the output of the DAC also increases). The output of a non-monotonic DAC may change in the opposite direction of the input (for example, when the input increases, the output of the DAC decreases). It is desirable to provide a monotonic DAC. However, typically, a thermometric DAC requires a large number of switches, which takes up a large area. In addition, the large number of switches increases other errors due to leakage. This limits the practical application of thermometric segmented DACs because large DACs are required to provide highly monotonic outputs.

[0022] It is desirable to provide a DAC including a limited number of switches having improved monotonicity.

[0023] The DAC may include a differential pair of devices with the source of the differential pair coupled to a current source. Changing the control signal that provides the gate voltage of the differential pair causes different currents to be drawn, providing an analog output related to the digital input. To improve device linearity, multiple current sources may be used, with a separate current source for each differential pair. To provide a linear system, closely matched input differential pair devices and current sources are used. However, the more closely matched the current sources are, the larger the area required to provide the current sources.

[0024] To provide a monotonic DAC in a small area, a switching circuit can be used to modify the coupling of the current source. During a transition of the DAC input, the current source can be decoupled from the first transconductance stage that provides the LSB portion of the DAC output and coupled to the second transconductance stage that provides the MSB portion of the DAC output. This ensures that the same current source error is provided to the MSB transconductance stage as is provided to the LSB transconductance stage. Maintaining a consistent error during DAC input transitions ensures monotonic transitions of the output. This enables a compact DAC with a limited number of switches and a monotonic output.

[0025] Figure 14 is a schematic diagram of a DAC 400 including a resistor string or resistor device group 401. The DAC 400 receives a digital input and generates an analog output. A switch device group 402 includes a plurality of switches coupled to the resistor string 401. The switches of the switch device group 402 are controlled by the most significant bit (MSB) of the digital input, and specific two switches of the switch device group 402 are closed according to the value of the MSB. Therefore, the switch device group 402 can be regarded as the MSB portion of the DAC 400.

[0026] The MSB portion 402 outputs two reference voltages (V1 and V2). The values ​​of the voltages V1 and V2 depend on which switches of the MSB portion 402 are closed, and therefore represent the MSB of the digital input word.

[0027] Voltages V1 and V2 are provided to a second switch device group 404 including a plurality of switches 405, 406, 407. The switches of the second switch device group 404 are controlled according to the value of the least significant bit (LSB) of the digital input word. Therefore, the second switch device group 404 can be regarded as the LSB part of the DAC 400.

[0028] A plurality of switches of the LSB portion 404 of the DAC 400 couples the voltages V1 and V2 from the MSB portion 402 of the DAC to a transconductance stage 408. The transconductance stage 408 receives a plurality of output voltages from the LSB portion 404 of the DAC and provides proportional output currents. The output voltages of the LSB portion 404 are coupled to the gates of a plurality of transistors 409a-409d of the transconductance stage 408, which form part of a transistor differential pair device. Thus, depending on the value of the LSB, the gate of the differential pair is coupled to either V1 or V2. The source of each of the plurality of transistors 409a-409d is coupled to a current source 411.

[0029] If the value of all LSBs of the digital input is 0, then switches 405-407 are all coupled to voltage V1. This couples voltage V1 to the gates of multiple transistors 409a-409d. If the value of all LSBs of the digital input is 1, then switches 405-407 are all coupled to voltage V2. This couples voltage V2 to the gates of multiple transistors 409b-409d. Changing the gate voltages of multiple transistors 409 causes a current drawn from current source 411 that is proportional to the number of transistors coupled to each of voltages V1 and V2. This changes the output voltage of the DAC.

[0030] Thus, DAC 400 is used to provide an analog output based on a digital input.

[0031] The source terminals of the transistors of the transconductance stage 408 are coupled to a single current source 411. However, this introduces non-linearity as the LSB code changes.

[0032] Figure 1 The DAC 400 shown includes MSB portions 401 / 402 and LSB portions 404. The transconductance stage of the DAC 400 includes a plurality of differential transistor pairs Q1, Q2, Q3. As previously described, all differential transistor pairs are coupled to the same current source. Each transistor pair may instead be coupled to a respective dedicated current source.

[0033] Multiple current sources are provided so that each differential pair of the transconductance stage 408 is coupled to a separate dedicated current source, thereby greatly improving the linearity of the DAC 400 .

[0034] Figure 1 The LSB decoder of the DAC 400 is thermometric, which ensures that the DAC is monotonic. However, due to the segmented manner of the DAC, Figure 1 The DAC 400 requires a large number of switches. For example, when the DAC is an 8-bit DAC, 256 switches are used in the MSB part and the LSB part. It is necessary to reduce the number of switches in the DAC to reduce the overall size of the DAC while maintaining high monotonicity.

[0035] Figure 1 The DAC 400 includes two stages. The first stage outputs two reference voltages V1 and V2. The second stage receives these reference voltages and provides an analog output.

[0036] Figure 2a 2 is a schematic diagram of a DAC system 200. The DAC system 200 receives a digital input signal 202 at a first stage 204. The first stage 204 generates or provides two reference signals V1 206 and V2 208. A second stage 210 receives the reference signals 206, 208 and generates or provides an analog output signal 212.

[0037] Figure 2b 2 is a schematic diagram of a first stage 204 of a DAC system 200. The first stage 204 includes a resistor string or an impedance string including a plurality of resistors or impedances 214 coupled between a reference voltage Vref (e.g., a power supply voltage Vdd) and ground. Although ground is shown in the figure, it should be understood that any other reference voltage may be used instead. A plurality of switch elements 216 (also referred to as a switch group) are coupled to the resistors 214.

[0038] like Figure 1As shown, the switch element 216 of the first stage 204 of the DAC is configured to switch according to the number of bits of the digital input 202 to output a first voltage V1 and a second voltage V2. The values ​​of the voltages V1 and V2 depend on which switch of 216 is closed. Using multiple bits of the digital input to control the switches coupled to the resistor string causes the voltages V1 and V2 to represent multiple bytes of the digital input word. The second stage 210 of the DAC system 202 can then receive the voltages V1 and V2 and configure the output according to the values ​​of the voltages V1 and V2 and different bit sets of the digital input.

[0039] Although Figure 2b A resistor string is shown, but it will be appreciated that any suitable first stage 202 that generates a reference voltage from a digital input may be used.

[0040] like Figure 1 As shown, there is a need to improve the second stage 210 of the DAC system 200 to operate more efficiently, reduce the number of switches, while maintaining high monotonicity. The following figures and description describe how to provide the second stage 210. The second stage 210 will be referred to as a DAC because it receives multiple bits of a digital input and provides an analog output. A DAC is used to receive a digital input and interpolate between two reference values ​​or voltages (V1 and V2) to provide an analog output. A DAC can also be considered a sub-DAC or sub-stage.

[0041] Figure 3 300 is a schematic diagram of a DAC 300 including two parts, which can be used as the second stage 210 of the DAC 200 or can be used independently as a separate DAC. The DAC includes an LSB portion 302 configured to receive the least significant bit of a digital input and an MSB portion 304 configured to receive the most significant bit of the digital input. The LSB portion is used to convert the LSB of the digital input into a first analog signal, and the MSB portion is used to convert the MSB of the digital input into a second analog signal. These corresponding analog outputs can then be combined to provide an analog output of the DAC. The digital input provided to the DAC 300 can be an entire digital word or a portion of a digital word, where the remainder of the digital word is represented by the values ​​of the reference voltages V1 and V2.

[0042] DAC 300 is a four-bit DAC configured to separate a digital input into two least significant bits and two most significant bits. However, it should be understood that the DAC can be configured to receive inputs having different numbers of bits, such as 8 bits, 16 bits, or 32 bits. Similarly, the boundary between the least significant bit and the most significant bit can be modified so that different proportions of the digital input word are considered as MSBs or LSBs.

[0043] The LSB portion 302 and the MSB portion 304 receive a first reference voltage V1 and a second reference voltage V2 (e.g., from the first stage 202 of the DAC 200, or any other suitable source, such as a resistor string). These reference voltages can be any suitable values. For example, the first reference voltage can be ground or 0v, and the second reference voltage can be a voltage rail or power supply voltage of the system. Alternatively, the reference voltage can be generated in the first stage 204 of the DAC system 200 based on the number of bits of the digital input 202. Any two different reference voltages can be used.

[0044] The LSB portion 302 receives the LSB of the digital input and generates a plurality of output control signals. Similarly, the MSB portion 304 receives the MSB of the digital input and generates a plurality of output control signals. The output control signals may be DC signals and have a voltage equal to the first reference voltage V1 or the second reference voltage V2.

[0045] The output control signal is output by the LSB portion 302 and the MSB portion 304 to the corresponding transconductance stages or elements 306, 308, 310, 312. The LSB portion 302 provides the output control signal to the first or LSB transconductance stage 306. The MSB portion 304 provides the output control signal to one or more transconductance stages. Figure 3 In the system of , this includes a first MSB transconductance stage 308 , a second MSB transconductance stage 310 , and a third MSB transconductance stage 312 .

[0046] Systems operating on a large number of bits may have different numbers of MSB transconductance stages. For example, in the case where the digital input includes X most significant bits, the DAC may include 2 X - 1 MSB transconductance stage.

[0047] The transconductance stage includes one or more differential transistor pairs. The source of the differential pair in each transconductance stage is coupled to a corresponding current source 314-320. Each transconductance stage is coupled to a dedicated current source. The gate of one of the transistors in each differential pair is coupled to a corresponding output control signal provided by the LSB portion 302 or the MSB portion 304. When the output control signal provided to the gate of the differential pair changes from V1 to V2 (or vice versa, depending on whether the transistor is an N-type or P-type transistor), the current drawn from each current source changes, and the output voltage of the DAC generated at the output terminal 334 changes. The gate of the second transistor in each differential pair is coupled to the output node or output terminal 334.

[0048] These "transconductance stages" keep the device in its linear operating region by making the two input voltages V1 and V2 close enough that the corresponding current sources are only partially steered in one direction (a MOS drain) or the other, and the degree of current steering is roughly proportional to the voltage difference (V1-V2). The transconductance of the stage can be regarded as the ratio of this ratio, that is, the degree of current control divided by the voltage difference (V1-V2). This is in contrast to the principle of traditional current-controlled DACs, in which each current source is fully switched to one output or the other.

[0049] LSB portion 302 and LSB transconductance stage 306 are used to convert the Y LSB of the digital input into a first analog signal. MSB portion 304 and one or more MSB transconductance stages 308-312 are used to convert the X MSB of the digital input into a second analog signal. The combination of these analog signals provides the analog output signal of DAC 300.

[0050] The LSB transconductance stage 306 includes four differential transistor pairs, the sources of which are coupled to the first current source 314. The number of differential transistor pairs within the LSB transconductance stage depends on the number of LSBs. Figure 3 In the four-bit example, two bits may be LSBs and two bits may be MSBs. Four differential transistor pairs are provided in the LSB transconductance stage 306. If there are Y LSBs, two differential transistor pairs may be provided in the LSB transconductance stage. Y The sources of the differential pairs of the transconductance stages are coupled to the same first current source 314. Each differential pair of the LSB transconductance stage can be independently controlled by a corresponding output control signal of the LSB portion 302.

[0051] Figure 3 The LSB transconductance stage 306 includes 2 Y Differential pairs (4 differential pairs), but it should be understood that in another example, 2 differential pairs may also be used. Y - 1 differential pair (out of 3 differential pairs).

[0052] 2 Y The use of a differential pair allows the LSB transconductance stage 306 to be 1 / 2 Y The step size provides the output resolution (depending on the number of differential pairs turned on). When all switches are turned on (or connected to the reference voltage V2), the output value of the LSB transconductance stage 306 is 2 Y When all differential pairs are off (or connected to reference voltage V1), the output value of LSB transconductance stage 306 is 0. Therefore, 2 Y The value of may be provided by the LSB transconductance stage 306 or one of the MSB transconductance stages 308-312. The LSB transconductance stage may instead include 2 Y -1 differential pair. The LSB transconductance stage can provide 0, 1…2Y -1 value. Y -1 differential pair (such as Figure 4 As shown, this would be three differential pairs in a four-bit DAC), and a value of zero would likely be represented by no differential pairs conducting (or all differential pairs coupled to V1). Y -1 differential pair can reduce the number of differential pairs required in the system. Therefore, in the case of the DAC 300 discussed further in this application, the LSB transconductance stage 306 only includes 2 Y -1 differential pair.

[0053] Each of the MSB transconductance stages 308-312 includes a differential transistor pair coupled to a respective current source. The first MSB transconductance stage 308 includes a differential pair, whose source is coupled to a second current source 316. The second MSB transconductance stage 310 includes a differential pair, whose source is coupled to a third current source 318. The third MSB transconductance stage 312 includes a differential pair, whose source is coupled to a fourth current source 320.

[0054] Therefore, each transconductance stage is coupled to a dedicated current source.

[0055] The width-to-length ratio (W / L) of each transistor included in the differential pair of the MSB transconductance stages 308, 310, 312 is four times the width-to-length ratio of the differential pair of the LSB transconductance stage 306. Thus, the differential pair of the MSB transconductance stage has a higher transconductance and allows a greater current to flow at the same gate voltage than the differential pair of the LSB transconductance stage 306. Therefore, changing one of the output control signals from the MSB portion 304 from V1 to V2 has a greater effect on the output of the DAC than changing one of the output control signals from the LSB portion 302 from V1 to V2.

[0056] Thus, if the three differential pairs of the LSB transconductance stage 306 are turned on, the output of the DAC 300 represents a value of 3 (where the binary input is 0011). If a single one of the MSB transconductance stages is turned on, the output of the DAC represents a value of 4 (where the binary input is 0100). Any binary input between 0000 and 1111 can be represented by turning the differential pairs of the transconductance stages on and off. In the case of a binary input of 0000, all differential pairs receive an output control signal of V1 from the MSB and LSB portions. In the case of a binary input of 1111, all differential pairs receive an output control signal of V2 from the MSB and LSB portions.

[0057] Although Figure 3The W / L ratio of the transistors of the MSB transconductance stage 308, 310, 312 of the example is four times the W / L ratio of the LSB transconductance stage 306, but this ratio may vary depending on the number of bits considered as LSBs. Therefore, in the case of a binary input with Y LSBs, the W / L ratio of the MSB transconductance stage differential pair is twice the W / L ratio of the LSB transconductance stage 306 differential pair. Y Alternatively, each MSB transconductance stage may include multiple differential pairs connected in parallel, with gates of the parallel differential pairs connected to the same output control signal from the MSB portion 304. For example, the differential pairs of the first MSB transconductance stage 308 may be replaced with four differential pairs coupled in parallel to the same output control signal of the MSB portion 304, each differential pair having the same W / L ratio as the differential pairs of the LSB transconductance stage.

[0058] Figure 3 The MSB portion 304 and the LSB portion 302 of the DAC 300 may be multiple multiplexers configured to receive a control signal depending on the digital input signal of the DAC 300 and provide an output control signal to the transconductance stage according to the value of the digital input. The LSB portion and the MSB portion may be implemented using other circuits, such as control circuits or transistors.

[0059] When the digital input of DAC 300 changes from 2 Y The value of -1 is converted to 2 Y When the value of , the output control signals of all differential pairs of the LSB transconductance stage 306 are changed from V2 to V1, and one output control signal of the MSB part 304 is also changed from V1 to V2.

[0060] In a four-bit example, there are two MSBs and two LSBs, which is the change in the digital input from 0011 to 0100.

[0061] The output of the DAC is provided by the LSB transconductance stage 306 and is therefore dependent on the first current source 314. As the digital input changes, the output of the DAC 300 transitions to being provided solely by the first MSB transconductance stage 308 and the second current source 316. Ideally, the current sources coupled to the DAC transconductance stages would be identical. However, as with any circuit, there may be errors or variations in the currents provided by the current sources. If this error is large enough and the value of the second current source 316 is significantly lower than the first current source 314, a transition of the digital input from 0011 to 0100 may cause the output of the DAC to decrease. Therefore, when the system transitions between the use of the LSB portion 302 and the MSB portion 304, the DAC may not have a completely monotonic output.

[0062] In the four-bit example, if the second current source 316 provides a current 1 / 4 lower than the first current source 314, the output will not increase when the LSB transconductance stage 306 is off and the first MSB transconductance stage 308 is on. This results in a non-monotonic output. In a DAC with more LSBs, a smaller percentage variance between the current sources can result in a non-monotonic change in the output. For example, with four LSBs, a 1 / 16 variance in the current provided by the current sources can provide a non-monotonic change in the output.

[0063] and Figure 1 Compared with DAC, Figure 3 The DAC allows the use of fewer switches because each MSB transconductance stage requires a separate differential pair to represent 2 of the digital input. Y The LSB portion, however, is not thermometric. Due to the segmentation of the DAC, the DAC is no longer inherently monotonic. When all differential pairs of the LSB transconductance stage switch simultaneously with one of the MSB transconductance stages, every 2 Y -1 to 2 Y This lack of monotonicity is especially noticeable when converting.

[0064] It would be desirable to provide a DAC, such as DAC 300, with a reduced number of switches while improving the monotonicity of the output.

[0065] Figure 4 is a schematic diagram of a DAC system 500. The DAC system includes Figure 3 DAC 500 includes a switching circuit 502 coupled between a plurality of current sources 314-320 and transconductance stages 306-312 of DAC 500. As previously described, Figure 4 The LSB transconductance stage 306 includes three differential pairs, but four differential pairs may also be used (eg, Figure 3 shown).

[0066] The switch circuit 502 is configured to switchably connect each of the current sources 314 - 320 to a corresponding transconductance stage of the plurality of transconductance stages 306 - 312 .

[0067] The switch circuit 502 may include any suitable switch circuit, such as a plurality of switches, a plurality of switch elements, or one or more multiplexers. The switch or switch element may include one or more transistors, such as MOSFETs. However, other suitable transistor types may also be used.

[0068] DAC 500 includes a control system 504. The control system 504 is configured to receive a digital input 506 for conversion by DAC 500. The control system generates one or more LSB section control signals 508 and one or more MSB section control signals 510. The LSB 508 and MSB 510 section control signals control the operation of the LSB and MSB sections based on the digital input 506. Therefore, the output control signals 322-332 of the LSB and MSB sections are controlled by the LSB control signal 508 and the MSB control signal 510.

[0069] The control system 504 is also configured to generate a switch circuit control signal 512. The switch circuit control signal 512 controls the configuration of the plurality of switch elements within the switch circuit 502. Thus, the switch control signal 512 may configure the switch circuit 502 to couple or decouple the current sources 314-320 of the DAC 500 to or from the corresponding LSB 306 or MSB 308-312 transconductance stages.

[0070] Figure 4 The control system 504 is shown as a separate component, but the control system may be integrated with one or more of the LSB portion 302 and the MSB portion 304 .

[0071] The control system 504 may include one or more processors and memory. The processor may be configured to read from the memory. Alternatively, the control system may include logic circuits or other control devices.

[0072] Figure 5 is a flow chart of a method for controlling DAC 500. The method may be performed by control system 504 of DAC 500 or any suitable control system of a DAC.

[0073] Step S602 includes receiving a digital input including a plurality of bits. The digital input includes a first segment including X most significant bits, MSBs, and a second segment including Y least significant bits, LSBs. The number of bits considered to be MSBs and LSBs may be determined when the device is manufactured. Any number of MSBs or LSBs may be used. Typically, the digital input may include 4, 8, 16, 32, 64, or 128 bits. Half of the bits of the digital input may be MSBs and half may be LSBs, however, any proportion of the bits of the digital input may be LSBs, such as 25%, 50%, 75%.

[0074] The digital input may change over time. Step S506 includes detecting a change in the value of the digital input compared to a previous value of the digital input. If the digital input changes, causing the value of the MSB to change and the value of the LSB to change by 2 Y As mentioned earlier, when the LSB value changes from 2Y –1 becomes 0 and the value of the MSB increases by 2 Y In the case of LSB, the output of the DAC changes from being provided (at least in part) by the LSB transconductance stage 306 to being provided by one or more of the MSB transconductance stages 308-312.

[0075] Step S606 includes modifying the coupling between the current sources 314-320 and the transconductance stages 306-312. Modifying the coupling includes decoupling the current sources from the corresponding transconductance stages and coupling the decoupled current sources to the alternative transconductance stages. Step S606 includes decoupling the first current source 314 from the LSB transconductance stage 306 and coupling the first current source 314 to the first MSB transconductance stage 308.

[0076] Modifying the coupling of the first current source 314 in this manner ensures that the same current source error provided to the LSB transconductance stage 306 is provided to the first MSB transconductance stage 308 when the digital input varies in such a manner that the output is provided by the MSB transconductance stage 308 rather than the LSB transconductance stage 306. This ensures that the transitions between the transconductance stages maintain a monotonic output because the same current source error is present in the output. If the current source did not change, the current source variance could cause the output to decrease even if the DAC 500 input increases.

[0077] Figure 6a A first configuration of DAC 500 is shown, and for convenience, connections provided by switching circuit 502 are shown. Although these connections are shown as simple direct connections, this is only for ease of understanding. Instead, the connections may be provided by one or more switches or switching elements within the switching circuit.

[0078] A first current source 314 is coupled to the LSB transconductance stage 306. A second current source 316 is coupled to the first MSB transconductance stage 308. A third current source 318 is coupled to the second MSB transconductance stage 310. A fourth current source 320 is coupled to the third MSB transconductance stage 312.

[0079] For a four-bit input including two LSBs and two MSBs, the digital input may be 0011. Thus, the output control signals 322-326 may have a value of V2. The output control signals 328-332 may have a value of V1.

[0080] If the digital input becomes 0100, the output control signals 322-326 and 330-332 have a value of V1. The value of the output control signal 328 is V2.

[0081] Figure 6b A second configuration of DAC 400 is shown.

[0082] To ensure that the same error is present in the output, the first current source 314 is decoupled from the LSB transconductance stage 306 and coupled to the first MSB transconductance stage 308 .

[0083] To ensure that all transconductance stages are coupled to a current source, second current source 316 is decoupled from first MSB transconductance stage 308 and coupled to second MSB transconductance stage 310. Third current source 318 is decoupled from second MSB transconductance stage 310 and coupled to LSB transconductance stage 306.

[0084] The input of DAC 400 can be changed from 0100 to 0111. There is no need to change the coupling of the current source to provide this transition because it does not require switching the MSB transconductance stage. Therefore, the switch circuit 402 can continue to couple the same current source and transconductance stage, such as Figure 6b shown.

[0085] A similar error may exist if the digital input transitions from 0111 to 1000. Output control signals 322-326 and 332 have a value of V1. Output control signals 328 and 330 have a value of V2. Thus, the analog output is provided by two MSB transconductance stages, with the second MSB transconductance stage 310 turned on and the LSB transconductance stage 306 turned off.

[0086] Figure 6c A third configuration of DAC 400 is shown.

[0087] Therefore, the third current source 318 is decoupled from the LSB transconductance stage 306 and coupled to the second MSB transconductance stage 310. The first current source 314 remains coupled to the first MSB transconductance stage 308. The second current source 318 is decoupled from the second MSB transconductance stage 310 and coupled to the third MSB transconductance stage 312. The fourth current source 320 is decoupled from the third MSB transconductance stage 312 and coupled to the LSB transconductance stage 306.

[0088] As the digital input value increases, different current sources will be coupled to the LSB transconductance stage 306. Whenever a transition occurs in the digital input, the value of the LSB decreases by the maximum possible amount (i.e., all 1s to all 0s, or 2 Y -1), the current source coupled to the LSB transconductance stage will be coupled to the MSB transconductance stage, which undergoes a transition in its control signal and turns on.

[0089] Although possible errors have been discussed with respect to a decrease in the LSB value and an increase in the MSB value, errors can also occur if the digital input is decreased by one bit. Y Above, the value of LSB changes from 0 to 2 YFor example, in the case where there are two MSBs and two LSBs in a four-bit digital input and the digital input changes from 1100 to 1011, the MSB transconductance is disconnected and all differential pairs of the LSB transconductance stage are turned on.

[0090] Therefore, the current source is decoupled from the disconnected MSB transconductance stage and coupled to the LSB transconductance stage.

[0091] Switching the current sources in the manner described significantly improves the differential nonlinearity (DNL) of the DAC. A small number of additional switching elements are required to provide this improvement, and limited additional logic circuitry is required. The logic or control circuitry used to operate the MSB and LSB portions can be reconfigured to provide control of the switch circuit 502 because the switch circuit switches at the same time as the output control signals for the MSB and LSB portions switch.

[0092] To reduce the integral nonlinearity (INL) of DAC 400, the transconductance of the transconductance stage can be reduced. However, this increases the noise in the analog output and changes the offset of the DAC. Figure 4 For the segmented DAC shown, the linearity is determined by the LSB fraction.

[0093] To improve the INL of the system, the differential pair of the LSB transconductance stage 306 may be degenerated.

[0094] Figure 7 A first pair of differential transistors 702 is shown. The differential pair 702 may represent one of the differential pairs of the LSB transconductance stage 306. As previously described, the current source 704 is coupled to the LSB transconductance stage, and in particular, to the sources of the transistors of the differential pair 702 of the LSB transconductance stage 306. For simplicity, Figure 7 The switch circuit 502 and the remaining transconductance stages and differential pairs of the DAC 400 are not shown, but it should be understood that Figure 7 The differential pairs and circuits can be included in Figure 4 DAC 400.

[0095] The negative feedback transistor 706 is coupled between the current source 704 and the differential pair 702. The switch circuit 502 is coupled between the current source 704 and the negative feedback transistor 706.

[0096] The gate of the negative feedback transistor 706 is coupled to the output 334 of the DAC. The negative feedback transistor 706 is specified to have a width-to-length ratio that is smaller than the differential pair 702 of the LSB transconductance stage. The W / L ratio of the negative feedback transistor 706 can be significantly smaller than the W / L ratio of the differential pair of the LSB transconductance stage 306. For example, the W / L ratio of the negative feedback transistor 706 can be 1 / 4, 1 / 8, 1 / 16, 1 / 32, 1 / 64, etc. of the W / L ratio of the differential pair of the LSB transconductance stage 306. The negative feedback transistor 706 can be a MOSFET that remains in a linear operating region.

[0097] Negative feedback transistor 706 is shown coupled to one differential pair of LSB transconductance stage 306 , however, negative feedback transistors may be coupled to all differential pairs of LSB transconductance stage 306 .

[0098] Including the negative feedback transistor significantly improves the INL of the DAC 300. Due to the structure of the DAC, negative feedback only needs to be applied to the LSB transconductance stage 306. This is because the LSB transconductance stage 306 has the greatest impact on the DAC linearity.

[0099] Although a single degeneration transistor may be used, alternatively, a respective cascode transistor may be coupled between the switch circuit 502 and each differential pair of the LSB transconductance stage 306. The cascode transistor ensures that current from a current source coupled to the LSB transconductance stage 306 is evenly distributed between each differential pair of the LSB transconductance stage 306.

[0100] Various modifications may be made to the above-described examples, whether by adding, deleting, or substituting features, to provide further examples, any and all of which should be encompassed by the following claims.

[0101] Aspects of the invention:

[0102] The following includes a set of numbered aspects according to the present disclosure:

[0103] 1. A method for controlling a digital-to-analog converter DAC, the method comprising:

[0104] receiving a digital input comprising a plurality of bits, the plurality of bits comprising a first segment comprising X most significant bits (MSBs) and a second segment comprising Y least significant bits (LSBs);

[0105] Detecting changes in MSB value and detecting changes in LSB value 2 Y -1;

[0106] decoupling the first current source from the least significant bit (LSB) transconductance stage of the DAC; and

[0107] The first current source is coupled to a first most significant bit (MSB) transconductance stage of the DAC.

[0108] 2. The method according to aspect 1 further comprises:

[0109] decoupling the second current source from the first MSB transconductance stage of the DAC; and

[0110] The second current source is coupled to a second MSB transconductance stage of the DAC.

[0111] 3. The method according to aspect 1 or aspect 2, further comprising:

[0112] decoupling the third current source from the second MSB transconductance stage of the DAC; and

[0113] The third current source is coupled to the LSB transconductance stage of the DAC.

[0114] 4. The method according to aspect 1 further comprises:

[0115] decoupling the second current source from the first MSB transconductance stage of the DAC; and

[0116] The second current source is coupled to the LSB transconductance stage of the DAC.

[0117] 5. A method according to any preceding aspect, wherein the change in the MSB value and the change in the LSB value are detected. Y -1 includes:

[0118] Detect increase in MSB value 2 Y or more and detects changes in LSB value 2 Y -1 to 0.

[0119] 6. A method according to any one of aspects 1 to 4, wherein the change in the MSB value and the change in the LSB value are detected. Y include:

[0120] Detecting a decrease in MSB value 2 Y or more and detects changes in LSB value 0 to 2 Y -1.

[0121] 7. The method according to any of the preceding aspects, further comprising:

[0122] converting the Y LSBs into a first analog signal using the LSB transconductance stage;

[0123] The X MSBs are converted into a second analog signal using an MSB transconductance stage.

[0124] 8. The method according to aspect 7, further comprising:

[0125] The first analog signal and the second analog signal are combined to provide an analog output signal.

[0126] 9. The method according to aspect 7 or aspect 8, wherein:

[0127] The LSB transconductance stage includes one or more differential pairs, and wherein converting the Y LSBs into the first analog signal using the LSB transconductance stage includes modifying one or more control signals provided to one or more differential pairs of the LSB transconductance stage;

[0128] The MSB transconductance stages each include a differential pair, and wherein converting the X MSBs into a second analog signal using the MSA transconductance stage includes modifying one or more control signals provided to the differential pairs of the MSB transconductance stages.

[0129] 10. A digital-to-analog converter (DAC) circuit, comprising:

[0130] input for: receiving a digital input comprising a plurality of bits, the plurality of bits comprising a first segment comprising X most significant bits, MSBs, and a second segment comprising Y least significant bits, LSBs;

[0131] LSB transconductance stage;

[0132] one or more MSB transconductance stages, including a first transconductance stage;

[0133] a first current source;

[0134] a switch circuit coupled between the first current source and the LSB transconductance stage and the one or more MSB transconductance stages, wherein when the change in the MSB value is 2 Y –1, the switch circuit is configured as:

[0135] The first current source is decoupled from the LSB transconductance stage and the first current source is coupled to the first MSB transconductance stage.

[0136] 11. The DAC circuit according to claim 10, further comprising:

[0137] a second current source;

[0138] wherein the one or more MSB transconductance stages include a second MSB transconductance stage, and

[0139] wherein the switch circuit is coupled between the second current source, the LSB transconductance stage and the one or more MSB transconductance stages, wherein when the change in the MSB value is 2 Y –1, the switch circuit is configured as:

[0140] The second current source is decoupled from the first MSB transconductance stage and the second current source is coupled to the second MSB transconductance stage.

[0141] 12. The DAC circuit according to aspect 10 or aspect 11, further comprising:

[0142] a third current source;

[0143] wherein the switch circuit is coupled between the third current source, the LSB transconductance stage and the one or more MSB transconductance stages, wherein when the change in the MSB value is 2 Y –1, the switch circuit is configured as:

[0144] The third current source is decoupled from the second MSB transconductance stage, and the second current source is coupled to the LSB transconductance stage.

[0145] 13. The DAC circuit according to claim 10, further comprising:

[0146] a second current source;

[0147] wherein the one or more MSB transconductance stages include a second MSB transconductance stage, and

[0148] wherein the switch circuit is coupled between the second current source, the LSB transconductance stage and the one or more MSB transconductance stages, wherein when the change in the MSB value is 2 Y –1, the switch circuit is configured as:

[0149] The second current source is decoupled from the first MSB transconductance stage and coupled to the LSB transconductance stage of the DAC.

[0150] 14. The DAC circuit according to any one of aspects 10-13, wherein the LSB transconductance stage comprises:

[0151] 2 Y LSB differential pairs, each LSB differential pair comprising a first transistor and a second transistor,

[0152] A source of the first transistor and a source of the second transistor of the LSB differential pair are coupled to each other and to the switch circuit.

[0153] 15. The DAC circuit according to any one of aspects 10-13, wherein the LSB transconductance stage comprises:

[0154] 2 Y -1LSB differential pair, each LSB differential pair includes a first transistor and a second transistor,

[0155] A source of the first transistor and a source of the second transistor of the LSB differential pair are coupled to each other and to the switch circuit.

[0156] 16. The DAC circuit of any one of aspects 14 or 15, wherein each of the one or more MSB transconductance stages comprises:

[0157] The width-to-length ratio of the MSB differential pair is twice the width-to-length ratio of the LSB differential pair. Y times bigger.

[0158] 17. The DAC circuit according to any one of aspects 14-16, wherein the LSB transconductance stage further comprises:

[0159] A negative feedback transistor is biased in a linear region, the negative feedback transistor being coupled between the switch circuit and the source of the LSB differential pair, wherein a width-to-length ratio of the negative feedback transistor is smaller than a width-to-length ratio of the LSB differential pair.

[0160] 18. The DAC circuit according to any one of aspects 14-16, wherein the LSB transconductance stage further comprises:

[0161] A plurality of cascode transistors, each cascode transistor is coupled between the switch circuit and a source of a corresponding one of the LSB differential pairs.

[0162] 19. A method for controlling a digital-to-analog converter DAC, the method comprising:

[0163] Receive digital input;

[0164] Detecting a change in the value of the most significant bit MSB of the digital input and detecting a change in the value of the least significant bit LSB of the digital input 2 Y –1;

[0165] decoupling a first current source from a first transconductance stage of the DAC; and

[0166] The first current source is coupled to a second transconductance stage of the decoder.

[0167] 20. The method according to aspect 19, further comprising:

[0168] A second current source is decoupled from a second transconductance stage of the decoder; and the second current source is coupled to a third transconductance stage of the decoder.

Claims

1. A method for controlling a digital-to-analog converter (DAC), the method comprising: receiving a digital input comprising a plurality of bits, the plurality of bits comprising a first segment comprising X most significant bits (MSBs) and a second segment comprising Y least significant bits (LSBs); Detecting changes in MSB value and detecting changes in LSB value 2 Y -1; decoupling the first current source from a least significant bit (LSB) transconductance stage of the DAC; and The first current source is coupled to a first most significant bit (MSB) transconductance stage of the DAC.

2. The method according to claim 1, further comprising: decoupling the second current source from the first MSB transconductance stage of the DAC; and The second current source is coupled to a second MSB transconductance stage of the DAC.

3. The method according to claim 2, further comprising: decoupling the third current source from the second MSB transconductance stage of the DAC; and The third current source is coupled to the LSB transconductance stage of the DAC.

4. The method according to claim 1, further comprising: decoupling the second current source from the first MSB transconductance stage of the DAC; and The second current source is coupled to the LSB transconductance stage of the DAC.

5. The method according to claim 1, wherein the change of the MSB value and the change of the LSB value are detected. Y –1 includes: Detect increase in MSB value 2 Y or more and detects changes in LSB value 2 Y -1 to 0.

6. The method according to claim 1, wherein the change of the MSB value and the change of the LSB value are detected. Y include: Detecting a decrease in MSB value 2 Y or more and detects changes in LSB value 0 to 2 Y -1.

7. The method according to claim 1, further comprising: converting the Y LSBs into a first analog signal using the LSB transconductance stage; The X MSBs are converted into a second analog signal using a number of MSB transconductance stages including the first MSB transconductance stage.

8. The method according to claim 7, further comprising: The first analog signal and the second analog signal are combined to provide an analog output signal.

9. The method according to claim 7, wherein: The LSB transconductance stage includes one or more differential pairs, and wherein converting the Y LSBs into a first analog signal using the LSB transconductance stage includes modifying one or more control signals provided to one or more differential pairs of the LSB transconductance stage; and The MSB transconductance stages each include a differential pair, and wherein converting the X MSBs into a second analog signal using the MSB transconductance stages includes modifying one or more control signals provided to the differential pairs of the MSB transconductance stages.

10. A digital-to-analog converter (DAC) circuit, comprising: an input for: receiving a digital input comprising a plurality of bits, the plurality of bits comprising a first segment comprising X most significant bits (MSBs) and a second segment comprising Y least significant bits (LSBs); LSB transconductance stage; one or more MSB transconductance stages, including a first MSB transconductance stage; a first current source; and a switch circuit coupled between the first current source and the LSB transconductance stage and the one or more MSB transconductance stages, wherein when the change in the MSB value is 2 Y –1, the switch circuit is configured as: The first current source is decoupled from the LSB transconductance stage and the first current source is coupled to the first MSB transconductance stage.

11. The DAC circuit according to claim 10, further comprising: a second current source; wherein the one or more MSB transconductance stages include a second MSB transconductance stage, and wherein the switch circuit is coupled between the second current source, the LSB transconductance stage and the one or more MSB transconductance stages, wherein when the change in the MSB value is 2 Y –1, the switch circuit is configured as: The second current source is decoupled from the first MSB transconductance stage and the second current source is coupled to the second MSB transconductance stage.

12. The DAC circuit according to claim 11, further comprising: a third current source; wherein the switch circuit is coupled between the third current source, the LSB transconductance stage and the one or more MSB transconductance stages, wherein when the change in the MSB value is 2 Y –1, the switch circuit is configured as: The third current source is decoupled from the second MSB transconductance stage, and the second current source is coupled to the LSB transconductance stage.

13. The DAC circuit according to claim 10, further comprising: a second current source; wherein the one or more MSB transconductance stages include a second MSB transconductance stage, and wherein the switch circuit is coupled between the second current source, the LSB transconductance stage and the one or more MSB transconductance stages, wherein when the change in the MSB value is 2 Y –1, the switch circuit is configured as: The second current source is decoupled from the first MSB transconductance stage and coupled to the LSB transconductance stage of the DAC.

14. The DAC circuit of claim 10 , wherein the LSB transconductance stage comprises: 2 Y LSB differential pairs, each LSB differential pair comprising a first transistor and a second transistor, A source of the first transistor and a source of the second transistor of the LSB differential pair are coupled to each other and to the switch circuit.

15. The DAC circuit of claim 10 , wherein the LSB transconductance stage comprises: 2 Y -1LSB differential pair, each LSB differential pair includes a first transistor and a second transistor, A source of the first transistor and a source of the second transistor of the LSB differential pair are coupled to each other and to the switch circuit.

16. The DAC circuit of claim 14 , wherein each of the one or more MSB transconductance stages comprises: The width-to-length ratio of the MSB differential pair is twice the width-to-length ratio of the LSB differential pair. Y times bigger.

17. The DAC circuit of claim 14, wherein the LSB transconductance stage further comprises: A negative feedback transistor is biased in a linear region, the negative feedback transistor being coupled between the switch circuit and sources of the LSB differential pair, wherein a width-to-length ratio of the negative feedback transistor is smaller than a width-to-length ratio of the LSB differential pair.

18. The DAC circuit of claim 14, wherein the LSB transconductance stage further comprises: A plurality of cascode transistors, each cascode transistor is coupled between the switch circuit and a source of a corresponding one of the LSB differential pairs.

19. A method for controlling a digital-to-analog converter (DAC), the method comprising: Receive digital input; Detecting a change in the value of the most significant bit (MSB) of the digital input and detecting a change in the value of the least significant bit (LSB) of the digital input 2 Y -1; decoupling a first current source from a first transconductance stage of the DAC; and The first current source is coupled to a second transconductance stage of the decoder.

20. The method according to claim 19, further comprising: decoupling a second current source from a second transconductance stage of the decoder; The second current source is coupled to a third transconductance stage of the decoder.

Images