Time synchronization device and method, electronic equipment and storage medium

Abstract

The invention belongs to the technical field of time synchronization, and particularly relates to a time synchronization device and method, electronic equipment and a storage medium. The device comprises a first branch, the first branch is composed of an input interface module, a time delay correction module and an output interface module, and the input interface module, the time delay correction module and the output interface module are connected in sequence; and the second branch comprises an average path time delay service module, one end of the average path time delay service module is connected with the input interface module, and the other end of the average path time delay service module is connected with the output interface module. The problems of slow tracking process, synchronous oscillation, even convergence failure and the like of a traditional synchronization scheme can be effectively solved, and the synchronous response speed and stability of the system are improved.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of time synchronization, and in particular relates to a time synchronization device, method, electronic device and storage medium. Background Art

[0002] Whether it is the combination of 5G and vertical industries (industrial Internet, power grid, railway, Internet of Vehicles, etc.), or the future 6G concept of ubiquitous connection between the earth and the sky, at the synchronization level, it is necessary to face connections with different clock domains, different protocols, and different media.

[0003] For example, in 5G+TSN application synchronous networking, 5G network and TSN network belong to different clock domains: 5G time domain and TSN working domain1. TSN network needs to be connected through 5G network, which will face the technical problems of transmission in different clock domains and intercommunication of different protocols.

[0004] For example, the future constellation network architecture will also have a synchronization architecture that includes space segment synchronization, ground segment synchronization, user segment synchronization, and synchronization connections between different segments, involving the integration of different time domains and different synchronization technologies.

[0005] The traditional synchronization method has the following problems:

[0006] 1. During the synchronization tracking and adjustment process, when the timestamp unit is synchronized with the main clock module through the clock bus, there is inevitably a synchronization adjustment lag. There are problems such as long synchronization time, synchronization performance oscillation, and even the phenomenon of synchronization failure to converge;

[0007] 2. When the local clock is in dynamic tracking and adjustment, the timestamp unit is required to be able to track quickly to achieve synchronization within the system, which increases the difficulty of designing the timestamp unit. The tracking error caused by dynamic adjustment will affect the accuracy of time synchronization;

[0008] 3. The local clock is tracked and adjusted based on the time deviation information. The error generated in this link affects the accuracy of time synchronization.

[0009] The current system architecture of a single time domain cannot meet future needs. The system's time architecture needs to be redesigned to meet the needs of future ubiquitous integrated applications. Summary of the invention

[0010] In view of the above problems, the present disclosure provides a time synchronization device, the device comprising a first branch, the first branch consisting of an input interface module, a delay correction module and an output interface module, the input interface module, the delay correction module and the output interface module being connected in sequence;

[0011] A second branch, wherein the second branch includes an average path delay service module, one end of the average path delay service module is connected to the input interface module, and the other end of the average path delay service module is connected to the output interface module; the average path delay service module is also connected to the delay correction module;

[0012] The third branch includes a protocol stack module, one end of the protocol stack module is connected to the input interface module, and the other end of the protocol stack module is connected to the output interface module.

[0013] Preferably, the input interface module is used to obtain a timestamp of a received protocol message;

[0014] The average path delay service module is used to measure the average path delay between the local port and the opposite port, and to measure the adjacent port clock rate ratio between the opposite port and the local port;

[0015] The delay correction module is used to obtain the local residence delay and the cumulative clock frequency ratio of the protocol message, and perform CF domain processing on the average path delay and the local residence delay;

[0016] The protocol stack module is used to send a protocol control signal, control the implementation of the protocol through the protocol control signal, and handle protocol compatibility issues;

[0017] The output interface module is used to obtain the timestamp of sending the protocol message.

[0018] The present disclosure also proposes a time synchronization method, the method comprising:

[0019] Obtain average path delay, adjacent port clock rate ratio, and protocol message timestamp difference;

[0020] The path delay is obtained based on the average path delay and the adjacent port clock rate ratio, and the residence delay is obtained based on the average path delay, the adjacent port clock rate and the protocol message timestamp difference;

[0021] Delay correction is performed based on path delay and residence delay to achieve time synchronization.

[0022] Preferably, obtaining the timestamp difference of the protocol message includes:

[0023] Get the timestamp of receiving protocol message and sending protocol message;

[0024] The timestamp of the received protocol message is subtracted from the timestamp of the sent protocol message to obtain the timestamp difference of the protocol message.

[0025] Preferably, obtaining the path delay based on the average path delay and the adjacent port clock rate ratio includes:

[0026] The cumulative clock frequency ratio is obtained by averaging the path delay and the adjacent port clock rate ratio;

[0027] The path delay is obtained by accumulating the clock frequency ratio and the average path delay.

[0028] Preferably, the residence delay is obtained based on the average path delay, the adjacent port clock rate and the protocol message timestamp difference, including:

[0029] The cumulative clock frequency ratio is obtained by averaging the path delay and the adjacent port clock rate ratio;

[0030] The residence delay is obtained by the protocol message timestamp difference and the accumulated clock frequency ratio.

[0031] Preferably, delay correction is performed according to the path delay and the residence delay, including:

[0032] The path delay and residence delay are added to the corresponding protocol message for CF domain processing.

[0033] The present disclosure also provides an electronic device, comprising:

[0034] Processor and memory;

[0035] The processor calls the computer program stored in the memory to execute any of the time synchronization methods described above.

[0036] The present disclosure also provides a computer-readable storage medium,

[0037] The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor is enabled to execute any one of the time synchronization methods described above.

[0038] The present disclosure has the following beneficial effects:

[0039] (1) The present disclosure can effectively solve the problems of slow tracking process, synchronous oscillation, and even failure to converge of traditional synchronization solutions, and improve the system synchronization response speed and stability;

[0040] (2) The present disclosure can reduce the difficulty of system design, reduce the dependence on the synchronization speed of the interface chip, and adapt to multi-domain synchronization design;

[0041] (3) The present disclosure can reduce synchronization tracking links, lower synchronization algorithm losses, and be beneficial to improving synchronization accuracy.

[0042] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by implementing the present disclosure. The purpose and other advantages of the present disclosure can be realized and obtained by the structures indicated in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 A diagram of a time synchronization device in an embodiment of the present disclosure is shown;

[0045] Figure 2 The overall functional block diagram of the time synchronization device in the embodiment of the present disclosure is shown;

[0046] Figure 3 A schematic diagram of a peer-to-peer delay measurement mechanism in an embodiment of the present disclosure is shown;

[0047] Figure 4 A time synchronization framework diagram is shown in an embodiment of the present disclosure;

[0048] Figure 5 A diagram showing a time synchronization method in an embodiment of the present disclosure is shown;

[0049] Figure 6 A diagram of an electronic device in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0050] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0051] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware units or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0052] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the steps. For example, some steps may be decomposed, while some steps may be combined or partially combined, so the actual execution order may change according to the actual situation.

[0053] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example.

[0054] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or sub-modules is not necessarily limited to those steps or sub-modules explicitly listed, but may include other steps or sub-modules not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0055] like Figure 1 As shown, the present disclosure provides a time synchronization device, the device comprising a first branch, the first branch consisting of an input interface module, a delay correction module and an output interface module, the input interface module, the delay correction module and the output interface module are connected in sequence;

[0056] The second branch includes an average path delay service module, one end of the average path delay service module is connected to the input interface module, and the other end of the average path delay service module is connected to the output interface module; the average path delay service module is also connected to the delay correction module;

[0057] The third branch includes a protocol stack module, one end of the protocol stack module is connected to the input interface module, and the other end of the protocol stack module is connected to the output interface module.

[0058] The overall functional block diagram of this device is as follows Figure 2As shown, the functional overall block diagram mathematically presents the P2P TC clock model function, which specifically includes an input interface module, a delay correction module, an average path delay service module, a PTP protocol stack / gPTP protocol stack module, and an output interface module;

[0059] Among them, the input interface module and the output interface module handle the adaptation issues between the external modules to ensure the normal sending and receiving of protocol messages and the processing of protocol messages;

[0060] Implementation of PTP protocol stack / gPTP protocol stack module control protocol and protocol compatibility issues;

[0061] The average path delay service module measures the propagation delay between the local port and the peer port according to the peer-to-peer delay measurement mechanism, namely the average path delay (Mean Link Delay), and also measures the neighbor rate ratio (Neighbor Rate Ratio) between the peer port and the local port.

[0062] The delay correction module obtains the mean link delay and the neighbor rate ratio from the mean link delay service module, calculates the cumulative rate ratio, obtains the local residence delay of the Sync message, and converts the mean link delay and the local residence delay into values ​​based on the upstream original clock frequency through the cumulative rate ratio. Finally, these two values ​​are added to the CF field of the corresponding message.

[0063] like Figure 5 As shown, the present disclosure also proposes a time synchronization method, the method comprising:

[0064] Obtain average path delay, adjacent port clock rate ratio, and protocol message timestamp difference;

[0065] The path delay is obtained based on the average path delay and the adjacent port clock rate ratio, and the residence delay is obtained based on the average path delay, the adjacent port clock rate and the protocol message timestamp difference;

[0066] Delay correction is performed based on path delay and residence delay to achieve time synchronization.

[0067] Specifically, obtaining the timestamp difference of the protocol message includes:

[0068] Get the timestamp of receiving protocol message and sending protocol message;

[0069] The timestamp of the received protocol message is subtracted from the timestamp of the sent protocol message to obtain the timestamp difference of the protocol message.

[0070] Specifically, the path delay is obtained based on the average path delay and the adjacent port clock rate ratio, including:

[0071] The cumulative clock frequency ratio is obtained by averaging the path delay and the adjacent port clock rate ratio;

[0072] The path delay is obtained by accumulating the clock frequency ratio and the average path delay.

[0073] Specifically, the residence delay is obtained based on the average path delay, the adjacent port clock rate, and the protocol message timestamp difference, including:

[0074] The cumulative clock frequency ratio is obtained by averaging the path delay and the adjacent port clock rate ratio;

[0075] The residence delay is obtained by the protocol message timestamp difference and the accumulated clock frequency ratio.

[0076] Specifically, delay correction is performed based on path delay and residence delay, including:

[0077] The path delay and residence delay are added to the corresponding protocol message for CF domain processing.

[0078] The specific technical contents of this method are as follows:

[0079] 1. The clock of the local device does not need to be synchronized.

[0080] 2. The local device is connected to the upstream device through the input interface and to the downstream device through the output interface.

[0081] 3. The timestamp of the Sync message received by the input interface is Tr. The peer-to-peer delay measurement mechanism is used to measure the mean link delay based on the local device and the neighbor rate ratio between the upstream device clock and the local device clock, and the cumulative rate ratio is calculated. Finally, the link delay based on the GM clock is calculated.

[0082] 4. The output interface sends the Sync message with a timestamp of Ts. The output interface obtains the residence delay of the Sync message in the node by calculating Ts-Tr, and then calculates the residence delay RT based on the GM clock.

[0083] 5. Add Link Delay (path delay based on GM clock) and RT (residence delay based on GM clock) to the Follow_up message corresponding to the Sync message, and add the cumulative Rate Ratio to the TLV of the Follow_up message.

[0084] Among them, Figure 3 As shown, the peer-to-peer delay measurement mechanism and related calculations are as follows:

[0085] Neighbor Rate Ratio (neighboring port clock rate ratio) = ((t3)j-(t3)i) / ((t4)j-(t4)i);

[0086] Among them, (t3)i and (t3)j represent the sending time of two adjacent Pdelay_Resp message records, and j is after i; (t4)i and (t4)j represent the receiving time of two adjacent Pdelay_Resp message records, and j is after i.

[0087] Mean Link Delay = [(t4-t1)-(t3-t2)*neighbor Rate Ratio] / 2.

[0088] Cumulative Rate Ratio (cumulative clock frequency ratio) = cumulative Rate Ratio_R*neighbor Rate Ratio;

[0089] The cumulative Rate Ratio_R is the value carried in the cumulative Rate Ratio related bytes in the TLV of the Follow_up message received by the local port.

[0090] Link Delay (path delay based on GM clock) = Mean Link Delay * cumulative RateRatio.

[0091] RT (residence delay based on GM clock) = (Ts-Tr)*cumulative Rate Ratio.

[0092] like Figure 4 As shown, the specific contents of the synchronization architecture of the present disclosure are as follows:

[0093] 1. The local clock of the node no longer tracks the upstream time source information. After the physical layer frequency synchronization, the free oscillation time is maintained. After the node is synchronized, no adjustment is required under normal circumstances, avoiding frequent tracking adjustments of the timestamp unit and synchronous tracking oscillation.

[0094] 2. The time deviation information calculated by the Precision Time Protocol (PTP) is shaped by the synchronization algorithm and the output result is stored as deviation information in the second and nanosecond domains. The second domain deviation information is provided to the timestamp unit to generate a local timestamp. The nanosecond domain information is provided to the synchronization protocol stack to correct the local timestamp information. Based on this, the upstream time source is synchronized and the time information is sent downstream.

[0095] 3. The synchronization protocol stack adopts a centralized processing method to facilitate accurate and synchronous acquisition of time deviation information.

[0096] 4. The clock bus transmits the second pulse (1PPS) information and time deviation second domain information of the local clock output.

[0097] 5. The data bus transmits synchronization messages and local timestamp information.

[0098] 6. Set up the synchronization output module and provide it to other applications that need synchronization information.

[0099] like Figure 6 As shown, corresponding to the clock synchronization method provided above, the present disclosure also provides an electronic device. Since the embodiment of the device is similar to the above method embodiment, the description is relatively simple. For relevant parts, please refer to the description of the above method embodiment part. The device described below is only schematic. The device may include: a processor (processor) 1, a memory (memory) 2 and a communication bus (i.e., the above device bus) and a search engine, wherein the processor 1 and the memory 2 communicate with each other through the communication bus and communicate with the outside through the communication interface. The processor 1 can call the logic instructions in the memory 2 to execute the clock synchronization method.

[0100] In addition, the logic instructions in the above-mentioned memory 2 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: a storage chip, a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk, and other media that can store program codes.

[0101] On the other hand, an embodiment of the present disclosure further provides a processor-readable storage medium, on which a computer program 3 is stored. When the computer program 3 is executed by the processor 1, the clock synchronization method provided in the above embodiments is implemented.

[0102] The processor-readable storage medium can be any available medium or data storage device that can be accessed by the processor 1, including but not limited to magnetic storage (such as floppy disks, hard disks, magnetic tapes, magneto-optical disks (MO), etc.), optical storage (such as CD, DVD, BD, HVD, etc.), and semiconductor storage (such as ROM, EPROM, EEPROM, non-volatile memory (NANDFLASH), solid-state drive (SSD)), etc.

[0103] Those skilled in the art should understand that although the present disclosure is described in detail with reference to the aforementioned embodiments, it is still possible to modify the technical solutions recorded in the aforementioned embodiments, or to make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A time synchronization device, characterized in that: The device comprises: A first branch, wherein the first branch is composed of an input interface module, a delay correction module and an output interface module, and the input interface module, the delay correction module and the output interface module are connected in sequence; A second branch, wherein the second branch includes an average path delay service module, one end of the average path delay service module is connected to the input interface module, and the other end of the average path delay service module is connected to the output interface module; the average path delay service module is also connected to the delay correction module; The third branch includes a protocol stack module, one end of the protocol stack module is connected to the input interface module, and the other end of the protocol stack module is connected to the output interface module.

2. The time synchronization device according to claim 1, characterized in that: The input interface module is used to obtain the timestamp of the received protocol message; The average path delay service module is used to measure the average path delay between the local port and the opposite port, and to measure the adjacent port clock rate ratio between the opposite port and the local port; The delay correction module is used to obtain the local residence delay and the cumulative clock frequency ratio of the protocol message, and perform CF domain processing on the average path delay and the local residence delay; The protocol stack module is used to send a protocol control signal, control the implementation of the protocol through the protocol control signal, and handle protocol compatibility issues; The output interface module is used to obtain the timestamp of sending the protocol message.

3. A time synchronization method based on the time synchronization device of claim 1-2, characterized in that: The method comprises: Obtain average path delay, adjacent port clock rate ratio, and protocol message timestamp difference; The path delay is obtained based on the average path delay and the adjacent port clock rate ratio, and the residence delay is obtained based on the average path delay, the adjacent port clock rate and the protocol message timestamp difference; Delay correction is performed based on path delay and residence delay to achieve time synchronization.

4. The time synchronization method according to claim 3, characterized in that: Get the timestamp difference of protocol messages, including: Get the timestamp of receiving protocol message and sending protocol message; The timestamp of the received protocol message is subtracted from the timestamp of the sent protocol message to obtain the timestamp difference of the protocol message.

5. The time synchronization method according to claim 3, characterized in that: The obtaining of the path delay based on the average path delay and the adjacent port clock rate ratio includes: The cumulative clock frequency ratio is obtained by averaging the path delay and the adjacent port clock rate ratio; The path delay is obtained by accumulating the clock frequency ratio and the average path delay.

6. The time synchronization method according to claim 3, characterized in that: The resident delay is obtained based on the average path delay, the adjacent port clock rate and the protocol message timestamp difference, including: The cumulative clock frequency ratio is obtained by averaging the path delay and the adjacent port clock rate ratio; The residence delay is obtained by the protocol message timestamp difference and the accumulated clock frequency ratio.

7. The time synchronization method according to claim 3, characterized in that: Delay correction is performed based on path delay and residence delay, including: The path delay and residence delay are added to the corresponding protocol message for CF domain processing.

8. An electronic device, characterized in that: include: Processor and memory; The processor calls the computer program stored in the memory to execute the time synchronization method according to any one of claims 3 to 7.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor is enabled to execute the time synchronization method according to any one of claims 3 to 7.

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