Low-power-consumption cross matrix system based on AXI protocol and processing method

Abstract

The invention relates to a low-power-consumption cross matrix system based on an AXI protocol and a processing method. According to the scheme, the low-power-consumption cross matrix system is composed of a slave interface module, a slave switch module, a host switch module, a host interface module, a gated clock module and a power consumption management module. The slave interface modules are responsible for processing read-write requests and write data sent by the hosts, the read-write requests and the write data are sent to the corresponding host interface modules after being subjected to routing and arbitration processing of the slave switches and the host switches, and finally the data are received and processed by the corresponding slaves; when one or more hosts or slaves connected with the cross matrix are in an idle state, the corresponding interface modules can pause the clock and cut off the power supply without processing read-write requests, and the power consumption management module is responsible for completing the operation and performing power consumption management on the whole system, so that the power consumption of the cross matrix is reduced.

Description

Technical Field

[0001] The present application relates to the field of computer information, and in particular to a low-power cross matrix system and a processing method based on an AXI protocol. Background Art

[0002] With the development of embedded systems, mobile devices, computers, consumer electronics and other fields, the complexity of system on chip design has increased significantly. Modern SoC may contain multiple processor cores, DMA controllers, memory, I / O modules, video processors, etc., all of which may need to access shared peripherals and storage resources at the same time, which poses a challenge to the traditional bus architecture.

[0003] In the traditional bus architecture, multiple hosts share the same bus to access slaves. The drawback of this architecture is that the bus bandwidth is limited. When multiple hosts need to access different slaves at the same time, the bus performance becomes a bottleneck. And as the number of masters and slaves increases, more and more devices need to access resources in parallel. For some high-performance SoC designs, especially multi-core processor architectures, parallel communication and efficient resource utilization become critical. Summary of the invention

[0004] The purpose of the present application is to overcome the deficiencies of the prior art and provide a low-power cross matrix system and processing method based on the AXI protocol to reduce system power consumption.

[0005] The purpose of this application is achieved through the following technical solutions:

[0006] The first aspect of the present application provides a low-power crossbar matrix system based on the AXI protocol, the system comprising:

[0007] at least one host, a host switch module, and a host interface module;

[0008] and at least one slave, a slave interface module and a slave switch module;

[0009] Among them, the host is connected to the slave interface module, the slave is connected to the host interface module, and the host switch module and the slave switch module form a cross matrix based on the host interface module and the slave interface module to perform data interaction to complete the corresponding read and write operations between the host and the slave.

[0010] Exemplarily, the host switch module is connected to the slave switch module and the host interface module respectively;

[0011] The host switch module receives the data of the read and write addresses and write data channels from the slave switch module, performs priority arbitration and sends the data to the host interface module;

[0012] And, receiving the read data and write response channel data from the host interface module, and routing them to the corresponding slave switch module according to their ID identifiers.

[0013] Exemplarily, the slave switch module is connected to the slave interface module and the host switch module;

[0014] The slave switch module receives the read and write addresses and data of the write data channel from the slave interface module, and sends it to the corresponding host switch module according to its access address;

[0015] Also, receiving the read data and write response channel data from the host switch module, and then sending them to the slave interface module after priority arbitration.

[0016] Exemplarily, the host interface module receives the read and write addresses and data of the write data channel from the host switch module, and sends the data to the slave after buffering;

[0017] Also, receiving the read data and write response channel data from the slave, caching them and sending them to the host interface module.

[0018] Exemplarily, the slave interface module receives the read and write addresses and write data channel data from the host and sends them to the slave switch module, and the slave interface module is responsible for receiving the read data and write response channel data from the slave switch module and sending them to the host after processing.

[0019] Exemplarily, the system further includes:

[0020] Power consumption management module;

[0021] The power consumption management module is used for the power consumption control of the system. The power consumption management module observes the working state of the system and uses different power consumption management strategies when the system is in sleep mode and working mode.

[0022] Exemplarily, the power consumption management module is divided into independent power consumption management areas based on different working conditions of each module in different working states of the system.

[0023] Exemplarily, the system further includes:

[0024] Gated clock module;

[0025] The gated clock module is used to generate a gated clock signal. The gated clock module generates clock signals of different modules according to the clock gating enable signal generated by the power consumption management module, thereby reducing the power consumption of the clock network of the corresponding module.

[0026] The power management module is used for the power control of the system. The power management module observes the working state of the system, uses different power management strategies when the system is in sleep mode and working mode, manages the power consumption of the system by managing the state of the power domain, and reduces the power consumption. According to the different working conditions of each module in different working states of the system, it is divided into areas for independent power management.

[0027] The gated clock module is used to generate a gated clock signal. The gated clock module generates clock signals of different modules according to the clock gating enable signal generated by the power management module, thereby reducing the power consumption of the clock network of the corresponding module.

[0028] The second aspect of the present application also provides a processing method of the system, the method comprising:

[0029] S101: Start the system, reset and complete the initialization operation;

[0030] S102: a request signal for entering low power consumption is given, and each slave interface and host interface module executes a power-down sequence and enters a power-off state after receiving the request;

[0031] S103: When each host interface module and slave interface module do not receive a read or write request, they will continue to be in a power-off state; once a read or write request is received, the corresponding host interface module and slave interface module will be awakened;

[0032] S104: The slave interface module first responds to the read and write requests, which involves 4K boundary processing, and feeds back to the slave switch module for routing according to its access address, and finally processed by the host switch module;

[0033] S105: When the host switch module receives a read or write request, it needs to perform polling arbitration on multiple read or write requests to determine their access priorities, and after completion, transmit the read or write requests to the host interface module in order of priority;

[0034] S106: After receiving the read and write requests, the host interface module caches them and sends them to the slave for response. When the slave receives a read request, it needs to prepare the read data and send it to the host interface module; when receiving a write request, it needs to complete the writing of the write data and give a response signal of successful writing, which is received by the host interface module;

[0035] S107: The host interface module caches the read data and write response and sends them to the host switch module. The host switch module routes the read data and write response to the corresponding slave switch module according to their ID identifiers. The slave switch module performs polling arbitration on multiple read data and write responses to determine their priorities and then sends them to the slave interface module in order of priority.

[0036] S108: The slave interface module performs 4K boundary processing, deinterleaving and reordering on the read data and then sends it to the host; performs 4K boundary processing and reordering on the write response and then sends it to the host;

[0037] S109: Determine whether there are any unprocessed read or write requests. If there are any read or write requests, continue to process the above process; otherwise, enter a low power consumption state.

[0038] Exemplarily, in S104, the slave interface module determines whether the 4K boundary is crossed, and completes the 4K boundary processing of the read and write requests and write data; the slave switch module receives the data of the slave interface module and forwards it to the corresponding host switch module according to the first address it accesses, and the host switch module polls and arbitrates the read and write requests and write data received from multiple slave switch modules, and gives them to the host interface module, which is finally processed by the slave.

[0039] The beneficial effects of the present application are as follows: the technical solution of the present invention is composed of a slave interface module, a slave switch module, a host switch module, a host interface module, a gated clock module, and a power management module. The low-power cross matrix system design method based on the AXI protocol refers to that the cross matrix can connect multiple hosts (such as CPU, DMA controller) or multiple slaves (such as memory, I / O module), the slave interface module is responsible for processing the read and write requests and write data issued by the host, and after routing and arbitration processing of the slave switch and the host switch, it is given to the corresponding host interface module, and finally the data is received and processed by the corresponding slave; the slave responds to the read and write request, and the read data and write response given are first cached by the host interface module, and then after arbitration and routing of the host switch and the slave switch, it is given to the corresponding slave interface module, and finally the data is received by the corresponding host. When one or more hosts or slaves connected to the cross matrix are in an idle state, the corresponding interface module does not need to process the read and write request, and can perform the operation of pausing the clock and cutting off the power supply. The power management module is responsible for the completion of the above operations, and performs power consumption management on the entire system to reduce the power consumption of the cross matrix. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of the system architecture of an embodiment of the present application;

[0041] Figure 2 This is a structural diagram of a slave interface module according to an embodiment of the present application;

[0042] Figure 3 A flow chart of a system processing method according to an embodiment of the present application;

[0043] Figure 4A diagram of the system power domain architecture of an embodiment of the present application;

[0044] Figure 5 This is a state transition diagram of a state machine in a power consumption management module according to an embodiment of the present application. DETAILED DESCRIPTION

[0045] The technical solution of the present application is further described in detail below in conjunction with specific embodiments, but the protection scope of the present application is not limited to the following.

[0046] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0047] In the description of the present application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0048] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, if the term "plurality" appears, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0049] In this application, unless otherwise clearly specified and limited, if the terms "installed", "connected", "connected", "fixed" and the like appear, these terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0050] In the present application, unless otherwise clearly specified and limited, if there is a description that a first feature is "above" or "below" a second feature, etc., or similar descriptions appear, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "above" and "above" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. The first feature being "below", "below" and "below" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0051] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only implementation method.

[0052] Different from the existing design method of the inter-core cross matrix, the present invention provides a low-power cross matrix system design method based on the AXI protocol, which can realize high-speed data interaction between multiple hosts and slaves. The specific supported functions include: advance transmission, out-of-order transmission, read data interleaving, and 4K boundary processing. At the same time, in a specific SOC, different hosts initiate requests at different frequencies, and different slaves receive requests at different probabilities. There are hosts that frequently initiate requests and slaves that frequently respond to requests. For hosts and slaves whose data interaction is not too intensive, their corresponding slave interface modules and host interface modules will be in an idle state for a long time, and there is no need to transmit data. Therefore, the entire cross matrix can be divided into a working state and a dormant state. In different states, there are different numbers of modules that do not need to work, so the power management module can be used in these stages to manage the power domain in which it is located and perform power-off operations to reduce power consumption.

[0053] AXI (Advanced eXtensible Interface) is part of the ARM AMBA (Advanced MicrocontrollerBus Architecture) protocol, designed specifically for high-performance, low-latency, and high-bandwidth transmission. However, although AXI provides a better communication mechanism, in a system with multiple hosts and multiple slaves, how to efficiently schedule and route these transmissions remains a problem. The AXI crossbar solves this problem. The crossbar is a module used in SoCs to achieve efficient connections between multiple hosts and multiple slaves. It can establish flexible data paths between multiple AXI hosts and slaves, thereby optimizing system bandwidth and reducing resource conflicts.

[0054] With the development of integrated circuit technology, the performance of chips has become stronger and stronger, the computing speed has become faster and faster, and the unit power consumption has become higher and higher. Therefore, when achieving efficient data interaction through the AXI cross matrix system, it is becoming more and more important to reduce the power consumption of the cross matrix.

[0055] Please refer to Figure 1 , Figure 1 A schematic diagram of a system design of a low-power crossbar matrix system based on the AXI protocol according to an embodiment of the present invention.

[0056] In an embodiment of the present invention, the low-power cross matrix system based on the AXI protocol includes at least one host 10, a host switch module 300, a host interface module 400 and at least one slave 20, a slave switch module 200, a host interface module 400, a power management module 500 and a gated clock module 600. The host 10 includes a host switch module 300 and a host interface module 400, and the slave includes a slave interface module 100 and a slave switch module 200; wherein the host switch module 300 and the slave switch module 200 form a cross matrix based on the host interface module 400 and the slave interface module 100 to perform data interaction, so as to complete the corresponding read and write operations between the host and the slave.

[0057] For example, see Figure 1 As shown, it includes 3 groups of hosts 10, host switch modules 300, host interface modules 400 and 3 groups of slaves 20, slave switch modules 200, host interface modules 400, respectively forming a 3×3 matrix. The specific distribution can be referred to Figure 1 shown.

[0058] Specifically, the above-mentioned slave interface module 100 is a slave_interface module, which supports functions such as advance transmission, read data disorder and write response disorder, read data interleaving and 4K boundary processing. The above-mentioned slave switch module 200 is a slave_switch module, which realizes arbitration and routing of each channel data; the above-mentioned host switch modules 300 are all master_switch modules, which also realize arbitration and routing of each channel data. The above-mentioned host interface modules 400 are all master_interface modules, which realize caching of each channel data and also support the advance transmission function. The above-mentioned power consumption management module 500500 is used to manage the status of each power domain in the cross matrix. The above-mentioned gated clock module 600600 is used to generate a gated clock signal for the module in each power domain.

[0059] Please refer to Figure 2 , Figure 2It is a structural block diagram of the slave_interface module in the present invention. The slave_interface module includes a FIFO module, a 4K boundary processing state machine module, a write data control module, and a reordering and deinterleaving module. Further, the slave_interface module realizes the functions of advance transmission, out-of-order transmission, data interleaving and 4K boundary processing. Among them, the advance transmission capability of the cross matrix is ​​determined by the depth of the FIFO module in the slave_interface, and the supported instantiation FIFO depth is 2 to the Nth power. The 4K boundary processing state machine module in the slave_interface module realizes the 4K boundary processing function of read and write requests. First, the state machine reads the write (read) address channel data in AW_FIFO_1 (AR_FIFO_1), and calculates the end address according to the first address, burst type, burst length, burst size and other signals in the write (read) address channel. If the first address and the last address span an integer multiple of 4096, it means that the 4K boundary is crossed. In the AXI protocol, ensuring that data transmission and cache operations follow 4K boundary alignment can improve system performance, reduce cache consistency issues, and simplify memory management. Therefore, the address size assigned to each slave is usually 4KB. If a write (read) data request crosses the 4K boundary, it is usually necessary to split the write (read) request to ensure that the write (read) request accesses a certain slave module. In the 4K boundary processing state machine, when it is detected that the transmission crosses the 4K boundary, the data enters the address generation GEN module and is split into two transmissions. When the 4K boundary is not crossed, the write (read) address data in AW_FIFO_1 (AR_FIFO_1) is directly output to the data selection MUX module. The two-choice MUX module selects one of the data to be transmitted to AW_FIFO_2 (AR_FIFO_2) based on whether it crosses the 4K boundary mark, and the data is finally transmitted to the subsequent module. The 4K boundary processing of the write data channel is completed by the write data control Ctrl module. The write data is first cached in W_FIFO_1, and then the Ctrl module determines whether the read data needs to be split before transmission based on the control information in aw_fifo_1. The reordering and deinterleaving module completes the reordering and deinterleaving of the read data and the reordering of the write response. The read data (write response) channel signal is compared with the read address identifier ARID (write address identifier ARID) recorded in sequence according to the read data identifier RID (write response identifier BID) of the channel. Once it is equal to the ARID (AWID) in the record, the data enters the Route module and is routed to the R_FIFO (B_FIFO) array. By comparing the ID identifiers, the data enters different R_FIFOs in the matching order, which solves the problem of interleaving read data of different IDs.When data enters the R_FIFO (B_FIFO) array, the MUX data selection module outputs the data in sequence, completing the reordering of the read data (write response).

[0060] Please refer to Figure 3 , Figure 3 The flowchart of the working state of the low-power cross matrix system based on the AXI protocol of the present invention is as follows. In order to better describe the design method, the workflow of the low-power cross matrix system based on the AXI protocol is described below:

[0061] S101: Start the system, reset and complete the initialization operation;

[0062] S102: a request signal for entering low power consumption is given, and each slave interface and host interface module executes a power-down sequence and enters a power-off state after receiving the request;

[0063] S103: When each host interface module and slave interface module do not receive a read or write request, they will continue to be in a power-off state; once a read or write request is received, the corresponding host interface module and slave interface module will be awakened;

[0064] S104: The slave interface module first responds to the read and write requests, which involves 4K boundary processing, and feeds back to the slave switch module for routing according to its access address, and finally processed by the host switch module;

[0065] S105: When the host switch module receives a read or write request, it needs to perform polling arbitration on multiple read or write requests to determine their access priorities, and after completion, transmit the read or write requests to the host interface module in order of priority;

[0066] S106: After receiving the read and write requests, the host interface module caches them and sends them to the slave for response. When the slave receives a read request, it needs to prepare the read data and send it to the host interface module; when receiving a write request, it needs to complete the writing of the write data and give a response signal of successful writing, which is received by the host interface module;

[0067] S107: The host interface module caches the read data and write response and sends them to the host switch module. The host switch module routes the read data and write response to the corresponding slave switch module according to their ID identifiers. The slave switch module performs polling arbitration on multiple read data and write responses to determine their priorities and then sends them to the slave interface module in order of priority.

[0068] S108: The slave interface module performs 4K boundary processing, deinterleaving and reordering on the read data and then sends it to the host; performs 4K boundary processing and reordering on the write response and then sends it to the host;

[0069] S109: Determine whether there are any unprocessed read or write requests. If there are any read or write requests, continue to process the above process; otherwise, enter a low power consumption state.

[0070] Furthermore, according to the above process description of the working state of the low-power cross matrix system based on the AXI protocol, it can be found that during the operation of the cross matrix, if a host 10 connected to the cross matrix does not initiate a read or write request, the slave interface module 100 connected to the host 10 may be in a sleep state; if a slave 20 connected to the cross matrix is ​​not accessed by the host 10, the host interface module 400 connected to the slave 20 may be in a sleep state; these modules do not need to perform any work in the sleep state, so the Power Gating strategy can be used to design them for low power consumption to further reduce power consumption.

[0071] Furthermore, according to the working state of the AXI-based low-power cross matrix, the SLV_IF_1, SLV_IF_2, MST_IF_1 and MST_IF_2 modules are divided into power domains. SLV_IF_1 is the PD_SLV_IF_1 power domain, SLV_IF_2 is the PD_SLV_IF_2 power domain, MST_IF_1 is the PD_MST_IF_1 power domain, and MST_IF_2 is the PD_MST_IF_2 power domain.

[0072] Please refer to Figure 4 , Figure 4 The present invention is a low-power power domain architecture diagram of a low-power cross matrix system based on the AXI protocol. The top-level switch modules composed of SLV_IF_0, MST_IF_0, each slave switch and the host switch are uniformly divided into the top-level power domain; SLV_IF_1, SLV_IF_2, MST_IF_1 and MST_IF_2 modules are respectively divided into a separate power domain, and the power networks of these power domains are independent of the power networks of other power domains and do not affect each other. In addition, the power supply of these power domains is provided by the peripheral VDD main power supply network, and the power network inside the power domain is connected to the VDD main power supply network through the power switch powerswitch. When the power switch is in the on state, the power network inside the power domain can supply power to the standard cells inside the power domain, and when the power switch is in the off state, the external power supply is cut off, and the standard cells inside the power domain are in the power-off state. The isolation cells ISOLATION Cells in the figure are inserted into the output signal of the power domain, which can prevent the propagation of indeterminate states on the output signal when the power is off.

[0073] In order to manage the above four power domains PD_SLV_IF_1, PD_SLV_IF_2, PD_MST_IF_1 and PD_MST_IF_2, a PMU power consumption management module 500 is designed.

[0074] Please refer to Figure 5 , Figure 5 The state transition diagram of the PMU module and the state machine in the module designed for the present invention. There are multiple state machines in the PMU module, and each state machine corresponds to a power domain that can shut down the power supply. The state jump of the state machine can control the states of the four power domains PD_SLV_IF_1, PD_SLV_IF_2, PD_MST_IF_1 and PD_MST_IF_2, and the power-on and power-off operations of the power domains are controlled by the power-on sequence and the power-off sequence.

[0075] Table 1

[0076]

[0077]

[0078] Table 1 is a state description of the state machine in the PMU power management module 500. It can be seen that there are 7 states in total, and the jumps between the 7 states are controlled by the low power interface signals described in the AXI protocol.

[0079] Table 2

[0080]

[0081]

[0082] Table 2 is a specific description of the states in the power-on sequence and power-off sequence of the power domain. It can be seen that there are 8 states in total, and the power-on and power-off sequences correspond to 4 of them respectively. Each state corresponds to a different stage in the cross matrix, and the state of each power domain is controlled by the jump of the state machine.

[0083] The cross matrix system is integrated and the power consumption is calculated. Please refer to Tables 4 to 6 for the resource usage report after integration, and the power consumption in the working state and the standby state.

[0084] Table 4

[0085] resource Usage Ports 23856 Nets 81473 Cells 58599 Combinational cells 31918 Sequential cells 26433 Buf / invcells 6396 Totalarea 182670.85

[0086] Table 5

[0087] Working power consumption (W) Normal design Low power design Lower the value Reduce the ratio Dynamic Power Consumption 30.3e-03 14.8e-03 15.5-03 51.2％ Static power consumption 7.67e-05 6.71e-05 0.97e-05 12.6％ Total power consumption 30.4e-03 14.9e-03 15.5e-03 50.9％

[0088] Table 6

[0089] Standby power consumption (W) Normal design Low power design Lower the value Reduce the ratio Dynamic Power Consumption 30.2e-03 6.13e-03 24.1-03 79.7％ Static power consumption 7.23e-05 3.02e-05 4.22e-05 58.3％ Total power consumption 30.3e-03 6.16e-05 24.1e-03 79.6％

[0090] Under the clock cycle of 4ns and TSMC 40nm process, the AXI cross matrix is ​​synthesized, and power consumption reports using different design methods are generated by the EDA tool Prime Time. It shows the power consumption of the cross matrix in the working state and the standby state respectively. As can be seen from the table, after using this low-power design method, the dynamic power consumption and static power consumption of the cross matrix in each state are reduced to varying degrees. The use of this low-power design method can reduce the total power consumption by about 50.9% in the working state, and by about 79.6% in the standby state. This fully illustrates that the AXI-based low-power cross matrix design method of the present invention can effectively reduce the power consumption of the design.

[0091] The above is only a preferred embodiment of the present application. It should be understood that the present application is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge in the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present application, and shall be within the scope of protection of the claims attached to the present application.

Claims

1. A low-power cross-matrix system based on the AXI protocol, characterized in that: The system includes: at least one host, a host switch module, and a host interface module; and at least one slave, a slave interface module and a slave switch module; Among them, the host is connected to the slave interface module, the slave is connected to the host interface module, and the host switch module and the slave switch module form a cross matrix based on the host interface module and the slave interface module to perform data interaction to complete the corresponding read and write operations between the host and the slave.

2. A low-power cross-matrix system based on the AXI protocol according to claim 1, characterized in that: The host switch module is connected to the slave switch module and the host interface module respectively; The host switch module receives the data of the read and write addresses and write data channels from the slave switch module, performs priority arbitration and sends the data to the host interface module; And, receiving the read data and write response channel data from the host interface module, and routing them to the corresponding slave switch module according to their ID identifiers.

3. A low-power cross-matrix system based on the AXI protocol according to claim 1, characterized in that: The slave switch module is connected to the slave interface module and the host switch module; The slave switch module receives the read and write addresses and data of the write data channel from the slave interface module, and sends it to the corresponding host switch module according to its access address; Also, receiving the read data and write response channel data from the host switch module, and then sending them to the slave interface module after priority arbitration.

4. A low-power cross-matrix system based on the AXI protocol according to claim 1, characterized in that: The host interface module receives the data of the read and write addresses and write data channels from the host switch module, and sends them to the slave after buffering; Also, receiving the read data and write response channel data from the slave, caching them and sending them to the host interface module.

5. The low-power crossbar matrix system based on the AXI protocol according to claim 1, characterized in that: The slave interface module receives the read and write addresses and data of the write data channel sent by the host, and sends them to the slave switch module. The slave interface module is responsible for receiving the read data and write response channel data from the slave switch module, and sends them to the host after processing.

6. A low-power crossbar matrix system based on the AXI protocol according to any one of claims 1 to 5, characterized in that: The system also includes: Power consumption management module; The power consumption management module is used for the power consumption control of the system. The power consumption management module observes the working state of the system and uses different power consumption management strategies when the system is in sleep mode and working mode.

7. A low-power cross-matrix system based on the AXI protocol according to claim 6, characterized in that: The power consumption management module is divided into independent power consumption management areas based on the different working conditions of each module in different working states of the system.

8. A low-power cross-matrix system based on AXI protocol according to claim 6, characterized in that: The system also includes: Gated clock module; The gated clock module is used to generate a gated clock signal. The gated clock module generates clock signals of different modules according to the clock gating enable signal generated by the power consumption management module, thereby reducing the power consumption of the clock network of the corresponding module.

9. A processing method based on the system according to any one of claims 1 to 8, characterized in that: The method includes: S101: Start the system, reset and complete the initialization operation; S102: a request signal for entering low power consumption is given, and each slave interface and host interface module executes a power-down sequence and enters a power-off state after receiving the request; S103: When each host interface module and slave interface module do not receive a read or write request, they will continue to be in a power-off state; once a read or write request is received, the corresponding host interface module and slave interface module will be awakened; S104: The slave interface module first responds to the read and write requests, which involves 4K boundary processing, and feeds back to the slave switch module for routing according to its access address, and finally processed by the host switch module; S105: When the host switch module receives a read or write request, it needs to perform polling arbitration on multiple read or write requests to determine their access priorities, and after completion, transmit the read or write requests to the host interface module in order of priority; S106: After receiving the read and write requests, the host interface module caches them and sends them to the slave for response. When the slave receives a read request, it needs to prepare the read data and send it to the host interface module; when receiving a write request, it needs to complete the writing of the write data and give a response signal of successful writing, which is received by the host interface module; S107: The host interface module caches the read data and write response and sends them to the host switch module. The host switch module routes the read data and write response to the corresponding slave switch module according to their ID identifiers. The slave switch module performs polling arbitration on multiple read data and write responses to determine their priorities and then sends them to the slave interface module in order of priority. S108: The slave interface module performs 4K boundary processing, deinterleaving and reordering on the read data and then sends it to the host; performs 4K boundary processing and reordering on the write response and then sends it to the host; S109: Determine whether there are any unprocessed read or write requests. If there are any read or write requests, continue to process the above process; otherwise, enter a low power consumption state.

10. The processing method according to claim 9, characterized in that: In S104, the slave interface module determines whether the 4K boundary is crossed, and completes the 4K boundary processing of the read and write requests and write data; the slave switch module receives the data from the slave interface module and forwards it to the corresponding host switch module according to the first address it accesses, and the host switch module polls and arbitrates the read and write requests and write data received from multiple slave switch modules, and gives them to the host interface module, which is finally processed by the slave.

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