Printed circuit board

Abstract

The invention provides a printed circuit board. The printed circuit board includes: a glass layer having a first surface and a second surface opposite to the first surface; the through via hole penetrates through the glass layer; a first wiring layer disposed on the first surface of the glass layer and in contact with the first surface of the glass layer; a first insulating layer disposed on the first surface and covering the first wiring layer; a second insulating layer disposed on the second surface of the glass layer and covering a side surface of the glass layer, the side surface of the glass layer connecting the first surface and the second surface of the glass layer; a second wiring layer disposed on the second insulating layer; and a connection via penetrating the second insulating layer to connect the second wiring layer and the through via to each other, the connection via being in contact with the through via. The first insulating layer includes an insulating material different from an insulating material of the second insulating layer.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0112008 filed on August 25, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] Due to the recent development of artificial intelligence (AI) technology, a multi-chip package including a memory chip such as a high bandwidth memory (HBM), a processor chip such as a central processing unit (CPU), a graphics processing unit (GPU), and a logic chip such as an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA) has been used to process exponentially growing data. Therefore, the demand for large-area panels has been increasing. Even when manufacturing large-area panels, glass materials can be used to overcome problems such as warping. Therefore, attempts have been made to use glass materials. Summary of the invention

[0004] One aspect of the present disclosure provides a printed circuit board including a glass layer.

[0005] Another aspect of the present disclosure provides a printed circuit board having improved warpage properties.

[0006] Another aspect of the present disclosure provides a printed circuit board having improved reliability.

[0007] According to one aspect of the present disclosure, there is provided a printed circuit board, the printed circuit board comprising: a glass layer having a first surface and a second surface opposite to the first surface; a through-via penetrating the glass layer; a first wiring layer disposed on the first surface of the glass layer and in contact with the first surface of the glass layer; a first insulating layer disposed on the first surface and covering the first wiring layer; a second insulating layer disposed on the second surface of the glass layer and covering a side surface of the glass layer, the side surface of the glass layer connecting the first surface and the second surface of the glass layer; a second wiring layer disposed on the second insulating layer; and a connecting via penetrating the second insulating layer to connect the second wiring layer and the through-via to each other, the connecting via being in contact with the through-via. The first insulating layer may include an insulating material different from the insulating material of the second insulating layer.

[0008] According to one aspect of the present disclosure, a printed circuit board is provided, the printed circuit board comprising: a glass layer having a first surface and a second surface opposite to the first surface; a through-via penetrating the glass layer; a first wiring layer disposed on the first surface of the glass layer, the first wiring layer having an interface with the through-via, the first wiring layer comprising a first metal layer and a second metal layer disposed on the first metal layer; a first insulating layer disposed on the first surface and covering the first wiring layer; a second insulating layer disposed on the second surface of the glass layer and covering a side surface of the glass layer, the side surface of the glass layer connecting the first surface and the second surface of the glass layer, the second insulating layer contacting a portion of the first insulating layer; a second wiring layer disposed on the second insulating layer; and a connecting via penetrating the second insulating layer to connect the second wiring layer and the through-via to each other. At least a portion of the first metal layer may contact the through-via and extend onto the first surface.

[0009] According to example embodiments of the present disclosure, there may be provided a printed circuit board including a glass layer.

[0010] According to example embodiments of the present disclosure, a printed circuit board having improved warpage properties may be provided.

[0011] According to example embodiments of the present disclosure, a printed circuit board having improved reliability may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a schematic block diagram illustrating an example of an electronic device system;

[0014] Figure 2 is a schematic perspective view showing an example of an electronic device;

[0015] Figure 3 is a schematic cross-sectional view showing an example of a printed circuit board;

[0016] Figure 4 is a schematic cross-sectional view showing another example of a printed circuit board;

[0017] Figure 5 is a schematic cross-sectional view showing still another example of a printed circuit board; and

[0018] Figures 6 to 16 is a schematic cross-sectional view illustrating an example of a method of manufacturing a printed circuit board. DETAILED DESCRIPTION

[0019] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. For clearer description, the shapes and sizes of components in the drawings may be exaggerated or reduced.

[0020] Electronic Devices

[0021] Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0022] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 may be physically and / or electrically connected to the mainboard 1010. Such components may be connected to other electronic components to be described below via various signal lines 1090.

[0023] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM) or flash memory); application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors or microcontrollers; and logic chips, such as analog-to-digital converters or application-specific integrated circuits (ASICs). However, the chip-related components 1020 are not limited thereto and may include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips or electronic components.

[0024] The network-related components 1030 may include components that are compatible with or communicate according to protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), The third generation mobile communication technology (3G) protocol, the fourth generation mobile communication technology (4G) protocol and the fifth generation mobile communication technology (5G) protocol and any other wireless protocol and wired protocol specified after the above-mentioned protocol. However, the network-related component 1030 is not limited to this, and may also include components compatible with various other wireless standards or protocols or wired standards or protocols or components that communicate according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the above-mentioned chip-related component 1020.

[0025] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto and may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 and / or network-related components 1030.

[0026] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. The other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. However, the other electronic components are not limited thereto, and may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk) drive, a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. In addition, depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0027] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device for processing data.

[0028] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0029] Reference Figure 2, the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various electronic components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. A portion of the electronic component 1120 may be the above-mentioned chip-related component, for example, a component package 1121, but the present disclosure is not limited thereto. The component package 1121 may be in the form of a printed circuit board on which an electronic component surface including active components and / or passive components is mounted. The electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0030] Printed Circuit Board

[0031] Figure 3 is a schematic cross-sectional view showing an example of a printed circuit board.

[0032] Reference Figure 3 According to the example, the printed circuit board may include: a glass layer 110 having a first surface 110-1 and a second surface 110-2 opposite to the first surface 110-1; a through via 140 penetrating the glass layer 110; a first wiring layer 121 disposed on the first surface 110-1 of the glass layer 110 and in contact with the first surface 110-1; a first insulating layer 111 disposed on the first surface 110-1 of the glass layer 110 and covering the first wiring layer 121; a second insulating layer 112 disposed on the second surface 110-2 of the glass layer 110, the second insulating layer 112 covering a side surface of the glass layer 110 connecting the first surface 110-1 and the second surface 110-2 of the glass layer 110; a second wiring layer 122 disposed on the second insulating layer 112; and a connecting via 141 penetrating the second insulating layer 112 to connect the second wiring layer 122 and the through via 140 to each other, the connecting via 141 being in contact with the through via 140.

[0033] The printed circuit board including the glass layer 110 according to the example may basically have excellent flatness, and may also have a low coefficient of thermal expansion (CTE), which may be advantageous in terms of warpage control. In particular, the printed circuit board according to the example may include the glass layer 110 as the core, so that warpage control may be advantageous even in the operation of stacking other insulating layers. In addition, the first insulating layer 111 may be formed on the first surface 110-1 of the glass layer 110, and the second insulating layer 112 may be formed on the second surface 110-2 of the glass layer 110, so that flatness may be further improved. Therefore, it may be more advantageous to form a high-density fine circuit with a fine pitch. In addition, the glass having a variable property of Dk (dielectric constant) of 2.5 to 11 may reduce the number of layers of the printed circuit board and may also increase the degree of freedom in design.

[0034] According to the example, the printed circuit board may include: a first insulating layer 111, stacked on the first surface 110-1 of the glass layer 110; and a second insulating layer 112, stacked on the second surface 110-2 of the glass layer 110, the second insulating layer 112 including a material different from that of the first insulating layer 111. Even when the first insulating layer 111 and the second insulating layer 112 including different insulating materials of the printed circuit board are stacked, rigidity can be ensured by the glass layer 110, thereby protecting the printed circuit board from warping. However, the present disclosure is not limited thereto. In addition, even when the insulating layers (e.g., Figure 3 The third insulating layer 113 and the fourth insulating layer 114 in the embodiment include insulating layers of different materials or stacked on the first insulating layer 111 (eg, Figure 3 The number (ie, the number of layers) of the fourth insulating layer 114 in the embodiment is the same as the number of insulating layers stacked on the second insulating layer 112 (eg, Figure 3 When the number of the third insulating layer 113 (ie, the number of layers) in the printed circuit board is different, the printed circuit board can also be protected from warping.

[0035] The glass layer 110 may include glass (amorphous solid). The glass may include, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. However, the present disclosure is not limited thereto, and optional glass materials such as fluorine glass, phosphate glass, chalcogenide glass, etc. may also be used as the material of the glass layer 110. In addition, other additives may be further included to form glass with specific physical properties. Such additives may include magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, antimony, and carbonates and / or oxides of these elements and other elements (e.g., sodium), such as calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda). The glass layer 110 is a layer different from a material (e.g., copper clad laminate (CCL), prepreg (PPG), etc.) including glass fibers (such as glass fabrics exemplified by glass cloth), and the glass layer 110 may be understood as, for example, plate glass.

[0036] The glass layer 110 may have a first surface 110-1 and a second surface 110-2. The second surface 110-2 may be a surface opposite to the first surface 110-1. The first surface 110-1 and the second surface 110-2 may be positioned opposite to each other in a stacking direction of the printed circuit board. Figure 3 1, for convenience, the first surface 110-1 is shown as the lower side of the glass layer 110, and the second surface 110-2 opposite to the first surface 110-1 is shown as the upper side of the glass layer 110. However, for convenience, the positions of the first surface 110-1 and the second surface 110-2 are shown, but are not limited thereto. The positional relationship between the first surface 110-1 and the second surface 110-2 may vary.

[0037] Reference Figure 3 In the printed circuit board according to the example, the first wiring layer 121 may be provided on the first surface 110-1 of the glass layer 110 to contact the first surface 110-1, and the first wiring layer 121 may be connected to the through-via 140 to contact the through-via 140. The second wiring layer 122 may be provided on the second insulating layer 112, and may be connected to the through-via 140 through the connection via 141. The connection via 141 may penetrate the second insulating layer 112, and may be connected to the through-via 140 to contact the through-via 140. That is, the through-via 140 of the glass layer 110 may contact the first wiring layer 121 on the first surface 110-1, and may contact the connection via 141 on the second surface 110-2. That is, the printed circuit board according to the example may be implemented as an asymmetric board including different components that contact the first surface 110-1 and the second surface 110-2 of the glass layer 110, respectively.

[0038] The first insulating layer 111 and the second insulating layer 112 may include an organic insulating material. The organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material prepared by impregnating an inorganic filler, an organic filler and / or a glass fiber (such as a glass fabric exemplified by glass cloth) in these resins. For example, the insulating material may be a non-photosensitive insulating material such as an Ajinomoto built-up film (ABF) or a prepreg (PPG), but the present disclosure is not limited thereto, and other polymer materials may be used. In addition, the insulating material may be a photosensitive insulating material such as a photosensitive dielectric (PID). In addition, the insulating material may include an adhesive sheet such as a bonding sheet (BS).

[0039] The first insulating layer 111 and the second insulating layer 112 may include different insulating materials. Different insulating materials may not only refer to different types of insulating materials in the above insulating material group, but may also refer to the same type of insulating material including different types of components. For example, the first insulating layer 111 and the second insulating layer 112 may include ABF, respectively, but some components included in the first insulating layer 111 and some components included in the second insulating layer 112 may be different from each other.

[0040] That is, the first insulating layer 111 and the second insulating layer 112 may include fillers, respectively, but the respective fillers may be different from each other, so that the first insulating layer 111 and the second insulating layer 112 may include different insulating materials. The filler included in the second insulating layer 112 may have a finer structure than the filler included in the first insulating layer 111. In this case, the filler may be an inorganic filler, but the present disclosure is not necessarily limited thereto. The filler included in the second insulating layer 112 being finer than the filler included in the first insulating layer 111 may mean that the size (such as diameter or volume) of the filler included in the second insulating layer 112 is smaller than the size (such as diameter or volume) of the filler included in the first insulating layer 111.

[0041] The fillers different from each other included in the first insulating layer 111 and the second insulating layer 112 can be identified by analyzing the vertical cross-sectional view of the printed circuit board. The polished surface or cut section of the printed circuit board can be scanned using a scanning microscope or an optical microscope, and the scanned polished surface or cut section can be analyzed to compare the fillers. If necessary, the filler can be more easily identified by dyeing the vertical cross section of the printed circuit board. As described above, the size (e.g., diameter) of the filler can be measured on the scanned polished surface or cut section by scanning the polished surface or cut section of the printed circuit board using a scanning microscope or an optical microscope. The diameter of the filler can be an average value of the diameter. Here, the average value of the diameter can be the average value of the values ​​measured at any five points.

[0042] The printed circuit board according to the example may include a core 200. The core 200 may include a material different from the material of the first insulating layer 111 and the material of the second insulating layer 112. For example, the core 200 may include a material having a stiffness greater than that of the first insulating layer 111 and the second insulating layer 112, and may include an insulating material such as a copper clad laminate (CCL). The core 200 may be used as a jig for supporting the glass layer 110 to perform a process of embedding the glass layer 110, thereby preventing the glass layer 110 from being damaged in the process of manufacturing the printed circuit board. The core 200 may also be provided on the outermost side of the printed circuit board to protect the printed circuit board.

[0043] The glass layer 110 may be disposed in a through hole formed in the core 200 and may be buried by the second insulating layer 112. That is, the second insulating layer 112 may be disposed on the second surface 110-2 of the glass layer 110 and may be disposed to cover the side surface of the glass layer 110. In this case, the second insulating layer 112 may also be disposed on the core 200 and may be disposed to fill the through hole formed in the core 200. In addition, the lower surface of the core 200 may be substantially coplanar with the first surface 110-1 of the glass layer 110. This may be because: the glass layer 110 is fixed in the through hole of the core 200 and then buried by the second insulating layer 112. The arrangement relationship between the core 200, the glass layer 110, the first insulating layer 111 and the second insulating layer 112 will be described in detail below in conjunction with the method for manufacturing a printed circuit board.

[0044] The first wiring layer 121 and the second wiring layer 122 may include metals, respectively. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys. Preferably, the metal may include copper (Cu), but the present disclosure is not limited thereto. The first wiring layer 121 and the second wiring layer 122 may perform various functions according to the design. For example, the first wiring layer 121 and the second wiring layer 122 may include a signal pattern, a power pattern, a ground pattern, etc. The pattern may have various shapes (such as a line shape, a plane shape, and a pad shape). Each of the first wiring layer 121 and the second wiring layer 122 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electroplating layer (e.g., an electroplated copper layer). Alternatively, each of the first wiring layer 121 and the second wiring layer 122 may include a metal foil (e.g., a copper foil) and an electroplating layer (e.g., an electroplated copper layer). Alternatively, each of the first wiring layer 121 and the second wiring layer 122 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electroplating layer (e.g., an electroplated copper layer). Each of the first wiring layer 121 and the second wiring layer 122 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), and may include both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer) as needed.

[0045] Each of the first wiring layer 121 and the second wiring layer 122 may be formed using one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a via-tightening (TT) process, and a subtractive process, but the present disclosure is not limited thereto. Any method capable of forming a circuit on a printed circuit board may be used without limitation. In addition, the first wiring layer 121 and the second wiring layer 122 may be formed using different methods according to purpose and design.

[0046] The first wiring layer 121 may include a first metal layer 131 and a second metal layer 132, and the second wiring layer 122 may also include a first metal layer 131 and a second metal layer 132. Both the first metal layer 131 and the second metal layer 132 may be used to form the first wiring layer 121 and the second wiring layer 122, and the first metal layer 131 and the second metal layer 132 may include the same metal. At least a portion of the first metal layer 131 included in the first wiring layer 121 covers and contacts the lower surface of the through-hole 140, and / or extends onto the first surface 110-1. The first metal layer 131 may be used as a seed layer for forming the second metal layer 132. The first metal layer 131 may include an electroless plating layer (e.g., a chemical copper plating layer), and may include a sputtering layer. Alternatively, the first metal layer 131 may include a metal foil (e.g., a copper foil). The first metal layer 131 of the second wiring layer 122 disposed on the second insulating layer 112 may preferably include an electroless plating layer, but the present disclosure is not limited thereto. The first metal layer 131 of the first wiring layer 121 disposed on the glass layer 110 may preferably include a sputtering layer. When the first metal layer 131 of the first wiring layer 121 includes a sputtering layer, it may be advantageous to ensure adhesion between the glass layer 110 and the first metal layer 131. However, the present disclosure is not necessarily limited thereto, and the first metal layer 131 of the first wiring layer 121 may include an electroless plating layer. In order to ensure adhesion between the glass layer 110 and the first wiring layer 121, other components may also be included. The second metal layer 132 may include an electroplating layer formed using the first metal layer 131 as a seed layer.

[0047] The through via 140 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. Preferably, the metal may include copper (Cu), but the present disclosure is not limited thereto. The through via 140 may penetrate the first surface 110-1 and the second surface 110-2 of the glass layer 110. The lower surface and the upper surface of the through via 140 may be substantially coplanar with the first surface 110-1 and the second surface 110-2 of the glass layer 110, respectively. The through via 140 may be a filled via formed by filling a metal material in a via hole, but the present disclosure is not limited thereto. The through via 140 may be a conformal via formed by arranging a metal material along the wall surface of the via hole, and the specific method of forming the through via 140 may vary. The through via 140 may perform various functions according to the design. For example, the through via 140 may include a ground via, a power via, a signal via, and the like. The through hole 140 may have a substantially circular shape, a substantially elliptical shape, or a substantially polygonal shape in a plane, but the present disclosure is not limited thereto, and, for example, in terms of ensuring close contact by increasing the specific surface area, may have a complex shape in which various shapes are combined into one shape in a plane. The side surface of the through hole 140 may be substantially perpendicular to the upper and lower surfaces of the through hole 140, but the present disclosure is not limited thereto, and as needed, the side surface of the through hole 140 may be tapered in opposite directions in a cross section to have an hourglass shape.

[0048] The connection via 141 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys. Preferably, the metal may include copper (Cu), but the present disclosure is not limited thereto. The connection via 141 may include a filled via formed by filling a via hole with a metal material, but may also include a conformal via formed by arranging a metal material along the wall surface of the via hole. The connection via 141 may perform various functions according to the design. For example, the connection via 141 may include a ground via, a power via, a signal via, etc. The connection via 141 may include a first metal layer 131 and a second metal layer 132 in the same manner as the second wiring layer 122.

[0049] The connection via 141 may penetrate the second insulating layer 112 to connect the second wiring layer 122 and the through-via 140 to each other. The connection via 141 may be directly connected to the upper surface of the through-via 140. That is, the lower surface of the connection via 141 and the upper surface of the through-via 140 may be connected to each other on the second surface 110-2 of the glass layer 110. It may not be easy to ensure the adhesion between the glass layer 110 and the metal material. Therefore, after the second insulating layer 112 is formed on the second surface 110-2 of the glass layer 110, the through-via 140 and the second wiring layer 122 may be connected to each other by forming a via hole penetrating the second insulating layer 112 and forming a connection via 141 filling the via hole. In this case, the connection via 141 may be formed as a via hole filling the second insulating layer 112, and may be formed simultaneously with the second wiring layer 122. That is, the first metal layer 131 (seed layer of the connection via 141) may be disposed on the through via 140, and may cover at least a portion of the through via 140. When the bottom surface of the via hole for the connection via 141 is wider than the upper surface of the through via 140, the connection via 141 may be formed to completely cover the through via 140. When the bottom surface of the via hole is narrower than the upper surface of the through via 140, the connection via 141 may be formed to cover a portion of the through via 140.

[0050] The printed circuit board according to the example may include: one or more third insulating layers 113, which are disposed on the second insulating layer 112, and the one or more third insulating layers 113 cover at least a portion of the second wiring layer 122; one or more third wiring layers 123, which are disposed on the one or more third insulating layers 113 and / or in the one or more third insulating layers 113; and one or more first via layers 142, which penetrate at least a portion of the one or more third insulating layers 113 to connect the one or more third wiring layers 123 and the second wiring layer 122 to each other. In addition, the printed circuit board according to the example may include: one or more fourth insulating layers 114, which are disposed on the first insulating layer 111, and the one or more fourth insulating layers 114 cover at least a portion of the fourth wiring layer 124 to be described below; one or more fourth wiring layers 124, which are respectively disposed on the first insulating layer 111 and on the one or more fourth insulating layers 114 and / or in the one or more fourth insulating layers 114; and one or more second via layers 143, which penetrate at least a portion of the first insulating layer 111 and at least a portion of the one or more fourth insulating layers 114 to connect the one or more fourth wiring layers 124 and the first wiring layer 121 to each other.

[0051] One or more third insulating layers 113 may include organic insulating materials, respectively. The organic insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material prepared by impregnating inorganic fillers, organic fillers and / or glass fibers (such as glass fabrics exemplified by glass cloth) in these resins. For example, the insulating material may be a non-photosensitive insulating material such as Ajinomoto built-up film (ABF) or prepreg (PPG), but the present disclosure is not limited thereto, and other polymer materials may be used. In addition, the insulating material may be a photosensitive insulating material such as PID. In addition, the insulating material may include an adhesive sheet such as BS. One or more third insulating layers 113 may include an insulating material substantially the same as the insulating material of the second insulating layer 112, but the present disclosure is not limited thereto, and for example, an insulating material different from the insulating material of the second insulating layer 112 may be included. When one or more third insulating layers 113 include an insulating material substantially the same as the insulating material of the second insulating layer 112, the specific component ratio of the insulating material of the one or more third insulating layers 113 to the insulating material of the first insulating layer 111 may vary slightly. The glass layer 110 may ensure rigidity, and thus, warping of the printed circuit board may be prevented even when the second insulating layer 112 and the one or more third insulating layers 113 include an insulating material different from that of the first insulating layer 111 .

[0052] One or more third wiring layers 123 may include metals, respectively. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys. Preferably, the metal may include copper (Cu), but the present disclosure is not limited thereto. One or more third wiring layers 123 may perform various functions according to the design. For example, one or more third wiring layers 123 may include signal patterns, power patterns, ground patterns, etc. The pattern may have various shapes (such as line shapes, plane shapes, and pad shapes). One or more third wiring layers 123 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electroplating layer (e.g., an electroplated copper layer). Optionally, one or more third wiring layers 123 may include a metal foil (e.g., a copper foil) and an electroplating layer (e.g., an electroplated copper layer). Optionally, one or more third wiring layers 123 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer) and an electroplating layer (e.g., an electroplated copper layer). Optionally, one or more third wiring layers 123 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer) and an electroplating layer (e.g., an electroplated copper layer). One or more third wiring layers 123 may include a sputtered layer instead of an electroless plating layer (eg, a chemical copper plating layer), and may include both a sputtered layer and an electroless plating layer (eg, a chemical copper plating layer) as necessary.

[0053] One or more first via layers 142 may include metals, respectively. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. Preferably, the metal may include copper (Cu), but the present disclosure is not limited thereto. One or more first via layers 142 may include filled vias formed by filling the via holes with a metal material, but may also include conformal vias formed by arranging a metal material along the wall surface of the via hole. One or more first via layers 142 may perform various functions according to the design. For example, one or more first via layers 142 may include ground vias, power vias, signal vias, etc. One or more first via layers 142 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electroplating layer (e.g., an electroplating copper layer). One or more first via layers 142 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), and may include both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer) as required.

[0054] Each of the one or more third wiring layers 123 and the one or more first via layers 142 may be formed using one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a via-tightening (TT) process, and a subtractive process, but the present disclosure is not limited thereto. Any method capable of forming a circuit on a printed circuit board may be used without limitation.

[0055] One or more fourth insulating layers 114 may include organic insulating materials, respectively. The organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material prepared by impregnating an inorganic filler, an organic filler, and / or a glass fiber (such as a glass fabric of a glass cloth) in these resins. For example, the insulating material may be a non-photosensitive insulating material, such as an Ajinomoto stacked film (ABF) or a prepreg (PPG), but the present disclosure is not limited thereto, and other polymer materials may be used. In addition, the insulating material may be a photosensitive insulating material, such as a PID. In addition, the insulating material may include an adhesive sheet such as BS. One or more fourth insulating layers 114 may include an insulating material substantially the same as the insulating material of the first insulating layer 111, but the present disclosure is not limited thereto, and may include different insulating materials. When one or more fourth insulating layers 114 include an insulating material substantially the same as the insulating material of the first insulating layer 111, one or more fourth insulating layers 114 may include an insulating material different from the insulating material of the second insulating layer 112. The glass layer 110 may ensure rigidity, and thus, warping of the printed circuit board may be prevented even when the first insulating layer 111 and the one or more fourth insulating layers 114 include an insulating material different from that of the second insulating layer 112 .

[0056] One or more fourth wiring layers 124 may include metals, respectively. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys. Preferably, the metal may include copper (Cu), but the present disclosure is not limited thereto. One or more fourth wiring layers 124 may perform various functions according to the design. For example, one or more fourth wiring layers 124 may include signal patterns, power patterns, ground patterns, etc. The pattern may have various shapes (such as line shapes, plane shapes, and pad shapes). One or more fourth wiring layers 124 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electroplating layer (e.g., an electroplated copper layer). Optionally, one or more fourth wiring layers 124 may include a metal foil (e.g., a copper foil) and an electroplating layer (e.g., an electroplated copper layer). Optionally, one or more fourth wiring layers 124 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer) and an electroplating layer (e.g., an electroplated copper layer). Optionally, one or more fourth wiring layers 124 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer) and an electroplating layer (e.g., an electroplated copper layer). One or more fourth wiring layers 124 may include a sputtered layer instead of an electroless plating layer (eg, a chemical copper plating layer), and may include both a sputtered layer and an electroless plating layer (eg, a chemical copper plating layer) as necessary.

[0057] One or more second via layers 143 may include metals, respectively. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. Preferably, the metal may include copper (Cu), but the present disclosure is not limited thereto. One or more second via layers 143 may include a filled via formed by filling a via hole with a metal material, but may also include a conformal via formed by arranging a metal material along the wall surface of the via hole. One or more second via layers 143 may perform various functions according to the design. For example, one or more second via layers 143 may include a ground via, a power via, a signal via, and the like. One or more second via layers 143 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electroplating layer (e.g., an electroplating copper layer). One or more second via layers 143 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), and may include both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer) as required.

[0058] Each of the one or more fourth wiring layers 124 and the one or more second via layers 143 may be formed using one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a via-tightening (TT) process, and a subtractive process, but the present disclosure is not limited thereto. Any method capable of forming a circuit on a printed circuit board may be used without limitation.

[0059] As described above, the one or more third insulating layers 113 may include an insulating material substantially the same as the insulating material of the second insulating layer 112, and the one or more fourth insulating layers 114 may include an insulating material substantially the same as the insulating material of the first insulating layer 111. Substantially the same insulating material may refer not only to completely identical insulating materials, but also to the same type of insulating materials. Therefore, the one or more third insulating layers 113 and the one or more fourth insulating layers 114 may include fillers, respectively, and the size of the fillers of the one or more third insulating layers 113 and the size of the fillers of the one or more fourth insulating layers 114 may be substantially the same as the size of the fillers included in the second insulating layer 112 and the size of the fillers included in the first insulating layer 111, respectively.

[0060] The second insulating layer 112 and one or more third insulating layers 113 may be disposed on the second surface 110-2 of the glass layer 110, the first insulating layer 111 and one or more fourth insulating layers 114 may be disposed on the first surface 110-1 of the glass layer 110, and the insulating layer disposed on the second surface 110-2 (e.g., the second insulating layer 112 and / or the third insulating layer 113) and the insulating layer disposed on the first surface 110-1 (e.g., the first insulating layer 111 and / or the fourth insulating layer 114) may include different insulating materials. The insulating layer disposed on the second surface 110-2 may include a filler that is finer than the filler included in the insulating layer disposed on the first surface 110-1. The method of comparing the diameter of the filler may be performed in the same manner as the method of comparing the diameters of the fillers in the first insulating layer 111 and the second insulating layer 112. An insulating layer including finer fillers may facilitate processing finer wiring, and thus processing fine wiring on the second insulating layer 112 and one or more third insulating layers 113 may be more advantageous than processing fine wiring on the first insulating layer 111 and one or more fourth insulating layers 114 .

[0061] The number (ie, the number of layers) of the one or more third insulating layers 113 and the number (ie, the number of layers) of the one or more fourth insulating layers 114 may be different from each other. Figure 3 As shown in , the number of one or more third insulating layers 113 may be greater than the number of one or more fourth insulating layers 114, but the present disclosure is not necessarily limited to this. That is, the number of one or more third insulating layers 113 and the number of one or more fourth insulating layers 114 may be different from each other, so the printed circuit board according to the example may have an asymmetric structure. Generally, a board with an asymmetric structure may be prone to warping due to different numbers of stacked layers and processes. However, the printed circuit board according to the example may include a glass layer 110 having high rigidity to prevent warping. Figure 3, three third insulating layers 113 are shown, and one fourth insulating layer 114 is shown, but the number of layers is not limited thereto. The number of one or more third wiring layers 123 (parts connected to other components (such as semiconductor chips)) may be greater than the number of one or more fourth wiring layers 124 arranged on the opposite side. Parts connected to other components (such as semiconductor chips) may require a larger number of wiring layers. However, it may be common to implement the wiring layers to be symmetrical to each other to prevent warping. In contrast, a printed circuit board according to an example can use a glass layer 110 to prevent warping, so the number of one or more third wiring layers 123 and the number of one or more third insulating layers 113 may be greater than the number of one or more fourth wiring layers 124 and the number of one or more fourth insulating layers 114.

[0062] As described above, the printed circuit board according to the example may have a different layer configuration with respect to the glass layer 110. That is, the insulating layers stacked on the first surface 110-1 and the second surface 110-2 of the glass layer 110 may include different materials and / or have different numbers of layers. In addition, the first wiring layer 121 may be directly formed on the first surface 110-1 of the glass layer 110, the second insulating layer 112 may be formed on the second surface 110-2 of the glass layer 110, and then the second wiring layer 122 may be provided. The through via 140 may be in contact with the first wiring layer 121 on the first surface 110-1, and may be in contact with the connection via 141 on the second surface 110-2 without being in direct contact with the second wiring layer 122.

[0063] That is, the printed circuit board according to the example may have an asymmetric structure with respect to the glass layer 110. Even when the printed circuit board has an asymmetric structure, warping may be prevented. The first surface 110-1 and the second surface 110-2 of the glass layer 110 are not necessarily limited to Figure 3 , and the positional relationship between the first surface 110-1 and the second surface 110-2 may be reversed relative to each other. Figure 3 Unlike that shown in FIG. 1 , the insulating layer covering the wiring layer formed directly on the glass layer 110 may include a finer filler.

[0064] The printed circuit board according to the example may also include a solder resist layer 150 disposed on the third insulating layer 113 and / or the fourth insulating layer 114. The solder resist layer 150 may be disposed on the outermost side of the printed circuit board to protect the printed circuit board from the outside. The solder resist layer 150 may use a known solder resist. The solder resist layer 150 may include a liquid solder resist or a film type solder resist, but the present disclosure is not limited thereto. Other types of insulating materials may be used, and may include a thermosetting resin and an inorganic filler dispersed in the thermosetting resin, but may not include glass fiber. The insulating resin may be a photosensitive insulating resin, and the filler may be an inorganic filler and / or an organic filler, but the present disclosure is not limited thereto. Other polymer materials may be used as needed. The solder resist layer 150 may have an opening, and at least a portion of the third wiring layer 123 and at least a portion of the fourth wiring layer 124 may be exposed via the opening. The third wiring layer 123 and the fourth wiring layer 124 exposed via the opening may be connected to a mainboard or another printed circuit board. The wiring layer exposed through the opening can be used as a pad, and a surface treatment layer can be formed on the pad as needed. Optionally, a metal bump or column can be formed on the pad as needed, or the pad can protrude in the form of a column.

[0065] The printed circuit board according to the example is not limited to Figure 3 The components shown in the figure may also include general components of a printed circuit board. That is, the printed circuit board may also include components that can be used by those skilled in the art.

[0066] Figure 4 is a schematic cross-sectional view showing another example of a printed circuit board.

[0067] Reference Figure 4 , the printed circuit board according to another example does not include the core 200. Such a configuration may be the result of completing the printed circuit board by cutting the printed circuit board along a specific boundary after forming the components of the printed circuit board in the operation of manufacturing the printed circuit board according to another example. That is, the core 200 may be a temporary component (as a jig or frame to accommodate the glass layer 110), and may be the result of forming each printed circuit board in a tape unit and then manufacturing the printed circuit board by a singulation process. Therefore, the printed circuit board according to another example may have a structure in which the second insulating layer 112 (covering the side surface of the glass layer 110) is exposed to the outside.

[0068] In addition to the description of the presence or absence of the core 200, the description of the printed circuit board according to the example can be applied to the Figure 4 The present invention has already been described with reference to a printed circuit board according to another example, and thus a repeated description will be omitted.

[0069] Figure 5 is a schematic cross-sectional view showing still another example of a printed circuit board.

[0070] Reference Figure 5 In a printed circuit board according to yet another example, the wiring density of one or more third wiring layers 123 may be higher than the wiring density of the first wiring layer 121 and / or the wiring density of one or more fourth wiring layers 124, and the thickness of each of the one or more third insulating layers 113 may be less than the thickness of each of the one or more fourth insulating layers 114 and / or the first insulating layer 111.

[0071] One or more third insulating layers 113 of a printed circuit board according to yet another example may include fillers finer than the inorganic filler of the first insulating layer 111 and / or the inorganic filler of the one or more fourth insulating layers 114. Therefore, the one or more third insulating layers 113 may be more conducive to fine pattern processing than the first insulating layer 111 and / or the one or more fourth insulating layers 114, so that the one or more third wiring layers 123 disposed on the one or more third insulating layers 113 and / or in the one or more third insulating layers 113 may include wiring finer than the wiring of the first wiring layer 121 and / or the wiring of the one or more fourth wiring layers 124.

[0072] Higher wiring density is a relative concept, which may mean, for example, that the average spacing of the wiring included in one or more third wiring layers 123 may be shorter than the average spacing of the wiring included in the first wiring layer 121. The spacing may be measured by photographing a cut section of the printed circuit board using a scanning microscope or an optical microscope, and the average spacing may be the average value of the spacing between the wirings measured at any five points. In addition, the interlayer distance between the plurality of third wiring layers 123 (for example, it may be the average interlayer distance) may be smaller than the interlayer distance between the first wiring layer 121 and the fourth wiring layer 124. When a plurality of fourth wiring layers 124 are included, the interlayer distance between the plurality of third wiring layers 123 may be smaller than the interlayer distance between the plurality of fourth wiring layers 124. The interlayer distance may also be measured by photographing a cut section of the printed circuit board using a scanning microscope or an optical microscope, and the interlayer distance may be the average interlayer distance, which may be the average value of the distance between adjacent wiring layers measured at any five points. That is, the wiring included in the one or more third wiring layers 123 may be a high-density fine wiring having a line width / spacing (L / S) smaller than the line width / spacing (L / S) of the wiring included in the first wiring layer 121 and / or the wiring included in the one or more fourth wiring layers 124. As a non-limiting example, the line width / spacing of the wiring included in the one or more third wiring layers 123 may be about 2 / 2 μm (i.e., the line width is 2 μm and the spacing is 2 μm), but the present disclosure is not limited thereto. Since the one or more third wiring layers 123 have a high wiring density, the one or more third wiring layers 123 may be very effective when electronic components such as semiconductor chips are connected to each other. That is, the one or more third wiring layers 123 may be used as a redistribution layer of a semiconductor chip.

[0073] The first wiring layer 121 and the one or more fourth wiring layers 124 may have substantially the same wiring density. Such a configuration does not mean that the first wiring layer 121 and the one or more fourth wiring layers 124 need to be designed to have the same wiring density, and the first wiring layer 121 and the one or more fourth wiring layers 124 have a wiring density lower than the wiring density of the one or more third wiring layers 123, so that the design of the first wiring layer 121 and the one or more fourth wiring layers 124 can be freely changed.

[0074] Generally, a printed circuit board including fine wiring may often suffer from warpage caused by asymmetry of the board. However, a printed circuit board according to another example may include a glass layer 110 having excellent rigidity. Therefore, even when fine wiring is implemented only on one side of the board, the occurrence of warpage caused by asymmetry can be prevented.

[0075] exist Figure 5, the wiring of the one or more third wiring layers 123 is shown to be finer than the wiring of the second wiring layer 122, but the present disclosure is not limited thereto, and the second wiring layer 122 and the one or more third wiring layers 123 have substantially the same wiring density. Figure 5 , the second wiring layer 122 may also include wirings finer than the wirings of the first wiring layer 121 and / or the wirings of the one or more fourth wiring layers 124. In this case, the wiring layer with finer wirings may be directly disposed on the glass layer 110. That is, such a configuration means that finer wirings (such as a redistribution layer) may be directly disposed on the glass layer 110.

[0076] However, the present disclosure is not limited to Figure 5 , and a printed circuit board according to still another example may not include the core 200 in the same manner as the printed circuit board according to another example, but may be manufactured in tape units to perform a singulation process.

[0077] In addition to the description of the wiring density and the interlayer distance, the description of the printed circuit board according to the example and the printed circuit board according to another example can be applied to the Figure 5 The description of the printed circuit board according to still another example is now described, and thus a repeated description will be omitted.

[0078] Method for manufacturing printed circuit board

[0079] Figures 6 to 16 is a schematic cross-sectional view illustrating an example of a method of manufacturing a printed circuit board.

[0080] Reference Figure 6 , the glass layer 110 may be disposed in the through hole of the core 200, and the glass layer 110 may be fixed using the adhesive member 300. In this case, a surface of the glass layer 110 bonded to the adhesive member 300 may be illustrated as a first surface 110-1, and a surface opposite to the first surface 110-1 may be illustrated as a second surface 110-2.

[0081] The core 200 may have the same features as those described in conjunction with the printed circuit board according to the example, but the present disclosure is not limited thereto, and the core 200 may be a temporary assembly as a frame or a fixture as described above in conjunction with the printed circuit board according to another example. Any adhesive member that can be used by those skilled in the art can be used as the adhesive member 300 without limitation. For example, a known adhesive tape or the like can be used. The glass layer 110 can be attached to the through hole of the core 200 by the adhesive member 300, so that the first surface 110-1 of the glass layer 110 and the lower surface of the core 200 can be substantially coplanar with each other.

[0082] The through via 140 may be formed in the glass layer 110. The operation of forming the through via 140 in the glass layer 110 may be used without limitation as long as the operation is a method available to those skilled in the art. After forming the through hole in the glass layer 110, the through via 140 may be formed by forming a seed layer and forming a plating layer. Various methods such as laser processing, mechanical processing, and chemical processing may be used to form the through hole, and the seed layer may be formed using electroless plating (e.g., chemical copper plating) or sputtering. The plating layer may be electroplated (e.g., electroplated copper). Thereafter, as needed, the first surface 110-1 and the second surface 110-2 of the glass layer 110 may be subjected to a planarization process to have a flat surface.

[0083] Reference Figure 7 , a second insulating layer 112 may be provided to bury the glass layer 110. The second insulating layer 112 may be provided on the second surface 110-2 of the glass layer 110, and may be formed by stacking semi-cured insulating layers and then curing the semi-cured insulating layers. The second insulating layer 112 may cover the side surface of the glass layer 110 to fill the through hole of the core 200.

[0084] Reference Figure 8 , the adhesive member 300 may be removed. Even when the adhesive member 300 is removed, the glass layer 110 may be fixed by the second insulating layer 112.

[0085] Reference Fig. 9 and Fig.10 , the connection via 141 and the second wiring layer 122 may be formed, and the first wiring layer 121 may be formed.

[0086] After forming the via hole penetrating the second insulating layer 112, the connection via 141 and the second wiring layer 122 may be formed by forming the first metal layer 131 and the second metal layer 132. The operation of forming the first wiring layer 121 may also be performed by forming the first metal layer 131 and the second metal layer 132. In this case, the first metal layer 131 of the connection via 141 may contact the upper surface of the through via 140 and may cover the upper surface of the through via 140.

[0087] The first wiring layer 121 may be directly formed on the first surface 110-1 of the glass layer 110, and thus the first metal layer 131 of the first wiring layer 121 may be disposed to cover the lower surface of the through via 140. That is, the first wiring layer 121 may be formed after the first surface 110-1 of the glass layer 110 is planarized, the first wiring layer 121 may be distinguished from the through via 140 (e.g., the first wiring layer 121 and the through via 140 have an interface therebetween), and the first metal layer 131 (a seed layer of the first wiring layer 121) may be disposed to cover the through via 140. That is, after the adhesive member 300 is removed, the first wiring layer 121 may be formed on the surface of the glass layer 110 from which the adhesive member 300 is removed.

[0088] Reference Fig. 9 and Fig.10 , it is shown that the first wiring layer 121 is formed after the second wiring layer 122 is formed, but the present disclosure is not limited thereto, and the first wiring layer 121 and the second wiring layer 122 may be simultaneously formed in a single process, or the second wiring layer 122 may be formed after the first wiring layer 121 is formed. That is, the order of forming the second wiring layer 122 and the first wiring layer 121 may be unlimited.

[0089] In the printed circuit board according to the example, the first wiring layer 121 may be formed after the glass layer 110 having the through via 140 is buried by the second insulating layer 112, so that the first metal layer 131 of the first wiring layer 121 may be formed to be distinguished from the through via 140. That is, the first metal layer 131 of the first wiring layer 121 may be disposed to contact the through via 140 and may be disposed on the first surface of the glass layer 110. Based on the same principle, the first metal layer 131 of the connection via 141 may also be distinguished from the through via 140 and may have a similar arrangement.

[0090] Reference Figures 11 to 15 , a first insulating layer 111, one or more third insulating layers 113, and one or more fourth insulating layers 114 may be formed, and one or more third wiring layers 123 and one or more fourth wiring layers 124 may be formed. First, the third insulating layer 113 and the third wiring layer 123 may be formed on the second insulating layer 112. Thereafter, the first insulating layer 111 may be formed on the first surface 110-1 of the glass layer 110, and the fourth wiring layer 124 may be formed on the first insulating layer 111. Thereafter, the third insulating layer 113 and the third wiring layer 123 may be repeatedly stacked. Optionally, the fourth insulating layer 114 and the fourth wiring layer 124 may also be repeatedly stacked. The method of forming the insulating layer and the method of forming the via layer and the wiring layer may be performed using a known method in the method of manufacturing a printed circuit board.

[0091] In the accompanying drawings, it is shown that the third insulating layer 113 is first formed, and then the first insulating layer 111 is formed, but the present disclosure is not limited thereto, and the order of stacking insulating layers can be changed. In addition, in the accompanying drawings, it is shown that the operation of repeatedly forming an insulating layer and a wiring layer on one side and then forming an insulating layer and a wiring layer on the opposite side is performed, but the present disclosure is not limited thereto. The process can be performed in a manner that an insulating layer is formed on each side of one side and the opposite side, and then a wiring layer is formed on each insulating layer. That is, the operation of stacking layers can be performed simultaneously in two directions. In addition, in the accompanying drawings, it is shown that a layer is stacked on each side of one side and the opposite side, but the present disclosure is not limited thereto. After the layer stacking is completed on one side, the layer is stacked on the opposite side. The printed circuit board (including the glass layer 110) according to the example can be protected from warping, and therefore can be not limited by the stacking order or stacking type.

[0092] Reference Fig.16 , a solder resist layer 150 may be formed on the third insulating layer 113 and / or the fourth insulating layer 114. In order to form the solder resist layer 150, a known method such as lamination and coating may be used.

[0093] A printed circuit board according to another example can be manufactured by removing the core 200 of the printed circuit board, not limited to those in the drawings, and a printed circuit board according to another example can be manufactured by changing the wiring density and the stacking order during the stacking process. In addition, the present disclosure is not limited to those shown in the drawings, and may also include a method of forming an assembly that can be used by those skilled in the art.

[0094] As used herein, the term "covering" may include full coverage as well as at least partial coverage, and may include direct coverage as well as indirect coverage. In addition, the term "filling" may include not only full filling, but also substantially filling, for example, may include the presence of some gaps, holes, etc.

[0095] As used herein, “substantially” may be a concept including measurement errors and process errors or positional deviations occurring in the manufacturing process, etc. For example, “substantially perpendicular” may include not only “completely perpendicular” but also “approximately perpendicular”. Furthermore, “substantially coplanar” may include not only “completely coplanar” but also “approximately coplanar”.

[0096] As used herein, the same insulating material may refer not only to the exact same insulating material, but also to the same type of insulating material. Therefore, the components of the insulating material may be substantially the same, but their specific component ratios may vary slightly.

[0097] As used herein, a cross-sectional view may be a view showing the cross-sectional shape of an object when the object is cut vertically, or may be a view showing the cross-sectional shape of the object when the object is viewed from a side perspective. In addition, a plan view may be a view showing the plane shape of the object when the object is cut horizontally, or may be a view showing the plane shape of the object when the object is viewed from a top or bottom perspective.

[0098] As used herein, for convenience, upper side, upper part, upper surface, etc. are used to indicate the direction toward the surface on which electronic components can be mounted based on the cross section of the drawings, and lower side, lower part, lower surface, etc. are used to indicate the opposite direction. However, the above directions are defined for the convenience of description. Therefore, it should be understood that the scope of the claims is not particularly limited by the above directions, and the concepts of "upper" and "lower" can be changed at any time.

[0099] As used herein, the term "connection" may refer not only to "direct connection" but also to "indirect connection" by means of an adhesive layer or the like. The term "electrical connection" may include both a case where components are "physically connected" and a case where components are "not physically connected". In addition, the terms "first", "second", etc. may be used to distinguish one component from another, and may not limit the order and / or importance associated with the components, etc. In some cases, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of example embodiments.

[0100] As used herein, the term "example" is provided to emphasize a particular feature, structure, or characteristic, and does not necessarily refer to the same example. In addition, the particular features or characteristics may be combined in any suitable manner in one or more examples. For example, unless described contrary to or inconsistent with the context in other examples, what is described in a particular example may also be used in other examples even if not described in other examples.

[0101] The terms used herein are intended to describe only specific example embodiments, and the present disclosure is not limited thereto.As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0102] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: a glass layer having a first surface and a second surface opposite to the first surface; A through hole penetrates the glass layer; a first wiring layer disposed on the first surface of the glass layer and in contact with the first surface of the glass layer; a first insulating layer disposed on the first surface and covering the first wiring layer; a second insulating layer, disposed on the second surface of the glass layer and covering a side surface of the glass layer, the side surface of the glass layer connecting the first surface and the second surface of the glass layer; A second wiring layer, disposed on the second insulating layer; as well as a connecting via that penetrates the second insulating layer to connect the second wiring layer and the through via to each other, the connecting via being in contact with the through via, The first insulating layer includes an insulating material different from an insulating material of the second insulating layer.

2. The printed circuit board according to claim 1, wherein: The first insulating layer and the second insulating layer respectively include fillers, and The second insulating layer includes a filler finer than a filler included in the first insulating layer.

3. The printed circuit board according to claim 1, further comprising: One or more third insulating layers, disposed on the second insulating layer, the one or more third insulating layers covering at least a portion of the second wiring layer; as well as One or more third wiring layers are disposed on the one or more third insulating layers and / or within the one or more third insulating layers.

4. The printed circuit board according to claim 3, further comprising: One or more fourth insulating layers, disposed on the first insulating layer; as well as one or more fourth wiring layers, respectively disposed on the first insulating layer and on the one or more fourth insulating layers and / or in the one or more fourth insulating layers, and The one or more fourth insulating layers cover at least a portion of the one or more fourth wiring layers.

5. The printed circuit board according to claim 4, wherein: The number of layers of the one or more third wiring layers is different from the number of layers of the one or more fourth wiring layers.

6. The printed circuit board according to claim 5, wherein: The number of layers of the one or more third wiring layers is greater than the number of layers of the one or more fourth wiring layers.

7. The printed circuit board according to claim 4, wherein: The number of layers of the one or more third insulating layers is different from the number of layers of the one or more fourth insulating layers.

8. The printed circuit board according to claim 7, wherein: The number of the one or more third insulating layers is greater than the number of the one or more fourth insulating layers.

9. The printed circuit board according to claim 3, wherein: An average pitch of wirings of a same third wiring layer among the one or more third wiring layers is shorter than an average pitch of wirings of the first wiring layer.

10. The printed circuit board according to claim 9, further comprising: One or more fourth insulating layers, disposed on the first insulating layer, the one or more fourth insulating layers covering at least a portion of the first wiring layer; as well as One or more fourth wiring layers are disposed on the one or more fourth insulating layers and / or within the one or more fourth insulating layers.

11. The printed circuit board according to claim 1, further comprising: One or more third insulating layers, disposed on the second insulating layer, the one or more third insulating layers covering at least a portion of the second wiring layer; One or more third wiring layers, disposed on the one or more third insulating layers and / or within the one or more third insulating layers; One or more fourth insulating layers, disposed on the first insulating layer; as well as One or more fourth wiring layers are respectively arranged on the first insulating layer and on the one or more fourth insulating layers and / or in the one or more fourth insulating layers, wherein the one or more fourth insulating layers cover at least a portion of the one or more fourth wiring layers, and wherein the one or more third insulating layers comprise the same material as the insulating material of the second insulating layer, The one or more fourth insulating layers include the same insulating material as the first insulating layer.

12. The printed circuit board according to claim 1, further comprising: core, having a through hole, Wherein, the glass layer is arranged in the through hole.

13. The printed circuit board according to claim 1, wherein: The first wiring layer includes a first metal layer and a second metal layer disposed on the first metal layer, and At least a portion of the first metal layer covers a lower surface of the through via.

14. A printed circuit board, comprising: a glass layer having a first surface and a second surface opposite to the first surface; A through hole penetrates the glass layer; A first wiring layer is disposed on the first surface of the glass layer, the first wiring layer has an interface with the through via, and the first wiring layer includes a first metal layer and a second metal layer disposed on the first metal layer; a first insulating layer disposed on the first surface and covering the first wiring layer; a second insulating layer, disposed on the second surface of the glass layer and covering a side surface of the glass layer, the side surface of the glass layer connecting the first surface and the second surface of the glass layer, the second insulating layer contacting a portion of the first insulating layer; A second wiring layer, disposed on the second insulating layer; as well as a connecting via that penetrates the second insulating layer to connect the second wiring layer and the through via to each other, Wherein, at least a portion of the first metal layer contacts the through via and extends onto the first surface.

15. The printed circuit board according to claim 14, wherein The connecting via comprises a third metal layer and a fourth metal layer disposed on the third metal layer, and The third metal layer covers at least a portion of the through via.

16. The printed circuit board according to claim 14, wherein: The first insulating layer includes an insulating material different from an insulating material of the second insulating layer.

17. The printed circuit board according to claim 14, wherein: The first metal layer and the second metal layer include the same metal.

18. The printed circuit board according to claim 14, wherein: The first metal layer includes an electroless plated layer, and the second metal layer includes an electroplated layer formed using the first metal layer as a seed layer.

19. The printed circuit board according to claim 14, wherein: The first metal layer includes a metal foil.

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