Semiconductor device, manufacturing method thereof and memory system

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and a memory system. The manufacturing method comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a semiconductor layer, an etching stop layer and a laminated structure which are stacked in sequence; forming a mask layer on the semiconductor structure; etching by using the mask layer to form a channel hole which penetrates through the laminated structure and extends into the etching stop layer; the mask layer is removed; wherein in the same etching process, the etching rate of the mask layer is greater than the etching rate of the etching stop layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and a memory system. Background Art

[0002] With the continuous improvement of semiconductor manufacturing technology, the current memory manufacturing technology has gradually transitioned from a simple planar structure to a more complex three-dimensional structure. The number of stacked layers in the stacked structure in the memory is increasing, and the manufacturing process of the memory is becoming more and more complicated.

[0003] Therefore, how to optimize the manufacturing process of semiconductor devices becomes an urgent problem to be solved. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, and a memory system.

[0005] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0007] A semiconductor structure is provided, wherein the semiconductor structure comprises a semiconductor layer, an etch stop layer and a stacked structure which are stacked in sequence;

[0008] forming a mask layer on the semiconductor structure;

[0009] Using the mask layer to etch and form a channel hole penetrating the stacked structure and extending into the etch stop layer;

[0010] The mask layer is removed; wherein, in the same etching process, the etching rate of the mask layer is greater than the etching rate of the etching stop layer.

[0011] In some embodiments, after removing the mask layer, the manufacturing method further includes:

[0012] The channel hole is filled to form a first channel structure; the first channel structure includes a first storage structure, a first channel layer and a first filling layer in sequence along the radial direction inward.

[0013] In some embodiments, after filling the channel hole to form the first channel structure, the manufacturing method further includes:

[0014] removing the semiconductor layer and the etch stop layer to expose a portion of the first channel structure;

[0015] The first storage structure of the exposed portion of the first channel structure is removed to expose a portion of the first channel layer of the first channel structure.

[0016] In some embodiments, after removing the exposed portion of the first storage structure of the first channel structure to expose a portion of the first channel layer of the first channel structure, the manufacturing method further includes:

[0017] A first conductive layer is formed to cover the exposed first channel layer.

[0018] In some embodiments, the semiconductor structure further includes: a second conductive layer located between the semiconductor layer and the etch stop layer;

[0019] After removing the mask layer, the manufacturing method further includes:

[0020] The channel hole is filled to form a second channel structure; the second channel structure includes a second storage structure, a second channel layer and a second filling layer in sequence along the radial direction inward.

[0021] In some embodiments, filling the channel hole to form a second channel structure includes:

[0022] forming a second storage structure and a sacrificial layer in the channel hole;

[0023] removing a portion of the sacrificial layer and a portion of the second storage structure located in the etch stop layer to expose the etch stop layer;

[0024] removing the remaining sacrificial layer to expose the second storage structure;

[0025] forming a second channel layer covering the second storage structure and contacting the second conductive layer;

[0026] The channel hole is filled to form a second filling layer; wherein the second storage structure, the second channel layer and the second filling layer together form a second channel structure.

[0027] In some embodiments, after filling the channel hole to form the second channel structure, the manufacturing method further includes:

[0028] The semiconductor layer is removed to expose the second conductive layer.

[0029] In some embodiments, the second channel layer has two ends disposed opposite to each other along a stacking direction; after removing the semiconductor layer to expose the second conductive layer, the manufacturing method further includes:

[0030] Performing a doping process on an end of the second channel layer close to the second conductive layer to form a doped second channel layer;

[0031] The doped second channel layer is annealed.

[0032] In some embodiments, the material of the mask layer includes a carbon material;

[0033] The material of the etch stop layer includes doped carbon material.

[0034] In some embodiments, the process of removing the mask layer is an ashing process.

[0035] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, the semiconductor device comprising: a conductive layer, an etch stop layer and a stacked structure stacked in sequence;

[0036] A channel structure penetrating the stacked structure and the etch stop layer; wherein the channel structure comprises a channel layer, and the channel layer is in contact with the conductive layer.

[0037] In some embodiments, a contact interface between the channel layer and the conductive layer is planar.

[0038] In some embodiments, the channel structure includes a storage structure, a channel layer and a filling layer in sequence radially inward;

[0039] In a portion of the channel structure located within the etch stop layer, the storage structure surrounds the channel layer.

[0040] In some embodiments, the channel layer has two ends disposed opposite to each other along a stacking direction; the channel layer includes a doped channel layer, and the doped channel layer is located at one end close to the conductive layer.

[0041] In some embodiments, the conductive layer is used to electrically connect to the lead pad.

[0042] In some embodiments, the material of the etch stop layer includes a doped carbon material;

[0043] The material of the conductive layer includes doped polysilicon or metal silicide.

[0044] In some embodiments, the thickness of the etch stop layer along the stacking direction is less than 100 nm.

[0045] In a third aspect, an embodiment of the present disclosure provides a memory system, the memory system comprising:

[0046] The semiconductor device as described in the above technical solution; and

[0047] A controller is coupled to the semiconductor device and configured to control the semiconductor device.

[0048] The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and a memory system. The manufacturing method comprises: providing a semiconductor structure, the semiconductor structure comprising a semiconductor layer, an etch stop layer and a stacked structure stacked in sequence; forming a mask layer on the semiconductor structure; using the mask layer to etch to form a channel hole that penetrates the stacked structure and extends into the etch stop layer; removing the mask layer; wherein, in the same etching process, the etching rate of the mask layer is greater than the etching rate of the etch stop layer. In the embodiments of the present disclosure, in the same etching process, the etching rate of the mask layer is greater than the etching rate of the etch stop layer, which can improve the etching damage to the etch stop layer in the process of etching and removing the mask layer, thereby reducing the risk of collapse of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1A and Figure 1B A schematic diagram of a cross-sectional structure of a semiconductor device during a manufacturing process provided as an example;

[0050] Figure 2 A schematic diagram of a process for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0051] 3A to 3H A schematic diagram of a cross-sectional structure of a semiconductor device during a manufacturing process provided by an embodiment of the present disclosure;

[0052] 4A to 4H A schematic cross-sectional structure diagram of another semiconductor device during the manufacturing process provided by an embodiment of the present disclosure;

[0053] Figure 5 A schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment of the present disclosure;

[0054] Figure 6 A block diagram of a memory system provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0056] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0057] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0058] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0059] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0060] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0061] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0062] As the number of stacked layers of the stacked structure increases, when the stacked structure is etched to form channel holes, the etching depths of the multiple channel holes are inconsistent due to the limitations of the etching process, that is, the bottoms of the multiple channel holes are not at the same height, which results in different extension depths of the channel structure after the channel holes are filled to form the channel structure, which in turn leads to inconsistent electrical properties of the channel structure.

[0063] refer to Figure 1A and Figure 1B , Figure 1A and Figure 1B A schematic diagram of the cross-sectional structure of a semiconductor device during the manufacturing process is provided as an example.

[0064] refer to Figure 1A As shown, the semiconductor device includes: a first substrate 100, a first dielectric layer 102, a bottom polysilicon layer (Bottom Poly) 104, a second dielectric layer 106, a top polysilicon layer (Top Poly) 108 and a stacked structure 110 which are stacked in sequence. In order to more clearly illustrate the stacked structure of each layer, Figure 1A The dotted circle shows a partial enlarged view of each layer structure, including a first dielectric layer 102, a bottom polysilicon layer 104, a second dielectric layer 106, a top polysilicon layer 108 and a stacked structure 110 stacked in sequence on the first substrate 100. The stacked structure 110 includes a gate conductive layer 112 and an interlayer insulating layer 114 alternately stacked; at least a plurality of channel structures (Channel Hole, CH) 116 (such as Figure 1A The dotted circle frame) and multiple dummy channel structures (Dummy Channel Hole, DCH) 120 (as shown in Figure 1AA plurality of gate line isolation structures (Gate Line) 122 at least passing through the stacked structure 110. Figure 1A The dotted box illustrates a partial enlarged view of the channel structure 116 , which includes a storage structure 124 , a channel layer 118 and a filling layer 128 in sequence along the radial direction inward, and the storage structure 124 includes a barrier layer 136 , a storage layer 138 and a tunneling layer 140 in sequence along the radial direction inward.

[0065] Figure 1A It is shown that the plurality of channel structures 116, the plurality of dummy channel structures 120 and the plurality of gate line isolation structures 122 may extend into the bottom polysilicon layer 104 along the stacking direction, and may further extend into the first substrate 100. That is, in the process of etching to form the plurality of channel holes, the plurality of dummy channel holes and the plurality of gate line isolation grooves, the etching depths of the plurality of channel holes, the plurality of dummy channel holes and the plurality of gate line isolation grooves are not consistent.

[0066] Still refer to Figure 1A As shown, the semiconductor device further includes: a second substrate 130 and a peripheral circuit 132 (or a complementary metal oxide semiconductor (CMOS)) located on the second substrate 130; wherein the first substrate 100 and the second substrate 130 can be connected by bonding. The first substrate 100 can be, for example, an array substrate (Array Substrate), and the second substrate 130 can be, for example, a peripheral circuit substrate (CMOSSubstrate).

[0067] Combination Figure 1A and Figure 1B As shown, the first substrate 100, the first dielectric layer 102 and at least part of the bottom polysilicon layer 104 can be removed to expose one end of the channel structure 116; wherein the channel structure 116 has two opposite ends arranged along the stacking direction; the storage structure 124 at one end of the exposed channel structure 116, that is, the barrier layer 136, the storage layer 138 and the tunneling layer 140 are removed to expose the channel layer 118 of the channel structure 116; a source polysilicon layer (Pepper Poly) 134 covering the channel layer 118 of the exposed channel structure 116 is formed; wherein the source polysilicon layer 134 is in contact with the remaining bottom polysilicon layer 104, and the channel layers 118 exposed by the multiple channel structures 116 are connected to the source polysilicon layer 134. In order to more clearly illustrate that the source polysilicon layer 134 is in contact with the remaining bottom polysilicon layer 104, and the channel layer 118 is in contact with the source polysilicon layer 134, Figure 1B The dotted line box indicates a local enlarged view.

[0068] Combination Figure 1A and Figure 1B As shown, the first substrate 100, the first dielectric layer 102, the bottom polysilicon layer 104 and the second dielectric layer 106 can also be removed to expose the top polysilicon layer 108 and one end of the channel structure 116; wherein the channel structure 116 has two ends arranged oppositely along the stacking direction; the storage structure 124 at one end of the exposed channel structure 116, that is, the barrier layer 136, the storage layer 138 and the tunneling layer 140 are removed to expose the channel layer 118 of the channel structure 116; a source polysilicon layer 134 covering the channel layer 118 of the exposed channel structure 116 is formed; wherein the source polysilicon layer 134 is in contact with the top polysilicon layer 108, and the exposed channel layers 118 of multiple channel structures 116 are commonly connected to the source polysilicon layer 134. To more clearly illustrate that the source polysilicon layer 134 is in contact with the top polysilicon layer 108 and the channel layer 118 is in contact with the source polysilicon layer 134, Figure 1B The dotted box in the middle shows a local enlarged view.

[0069] It should be noted that, as the number of stacked layers of the stacked structure increases, the depths of the multiple channel holes, the multiple dummy channel holes and the multiple gate line spacers are inconsistent during the process of etching to form multiple channel holes, multiple dummy channel holes and multiple gate line spacers. At this time, the portion of the channel structure exposed by removing the first substrate, the first dielectric layer and at least part of the bottom polysilicon can also be called a "shoot head". The etching depths of the multiple channel holes are inconsistent, and correspondingly, multiple "shoot heads" with inconsistent heights can be formed. In this way, a relatively complex multi-step process is required in the subsequent processing to remove the "shoot heads" to expose the channel layer in the channel structure, so that the channel layer and the source plate (Source Plate) (for example, the source polysilicon layer) are electrically connected. The multi-step process may include but is not limited to a multi-step wet etching process (Wet Etch), a chemical mechanical polishing process (Chemical Mechanical Polishing, CMP), a polysilicon deposition process and an ion implantation process (Implant, IMP), etc.

[0070] In addition, after the first substrate and the second substrate are bonded, in the subsequent process of forming the source plate of the channel layer covering the exposed channel structure, the source plate can only be formed using a low temperature process. However, the low temperature process for forming the source plate results in a high hydrogen content in the source plate, and the source plate formed by the low temperature process is amorphous silicon. At this time, amorphous silicon has no conductivity, and it is necessary to activate the amorphous silicon by laser annealing. During the laser annealing process, remelting will occur, and the hydrogen elements in the source plate will gather to form holes (H void issue).

[0071] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, and a memory system.

[0072] refer to Figure 2 , Figure 2 The flowchart of the method for manufacturing a semiconductor device provided by the embodiment of the present disclosure is as follows. Figure 2 As shown, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the manufacturing method comprising:

[0073] Step S201: providing a semiconductor structure, wherein the semiconductor structure includes a semiconductor layer, an etch stop layer and a stacked structure stacked in sequence;

[0074] Step S202: forming a mask layer on the semiconductor structure;

[0075] Step S203: using the mask layer to etch to form a channel hole penetrating the stacked structure and extending into the etch stop layer;

[0076] Step S204: removing the mask layer; wherein, in the same etching process, the etching rate of the mask layer is greater than the etching rate of the etching stop layer.

[0077] In the disclosed embodiment, the semiconductor structure includes a semiconductor layer, an etch stop layer, a laminated structure, and a mask layer that are stacked in sequence; the mask layer is etched to form a channel hole that penetrates the laminated structure and extends into the etch stop layer. In this way, the difference in etching depths of different channel holes can be reduced, so that the bottoms of multiple channel holes all stay in the etch stop layer, that is, the etching depths of multiple channel holes are consistent. Compared to forming multiple "bamboo shoots" with inconsistent heights, in the disclosed embodiment, a "bamboo shoot" with uniform height and smaller height can be formed subsequently, thereby simplifying the manufacturing process of semiconductor devices.

[0078] In the disclosed embodiment, in the same etching process, the etching rate of the mask layer is greater than the etching rate of the etch stop layer. This can improve the etching damage to the etch stop layer during the process of etching and removing the mask layer, thereby reducing the risk of semiconductor structure collapse.

[0079] Before introducing the semiconductor device and the manufacturing method thereof provided by the embodiment of the present disclosure, various directions that may be involved in the embodiment of the present disclosure are first defined. The direction perpendicular to the semiconductor layer is defined as the Z direction, and the X direction and the Y direction are defined in the plane perpendicular to the Z direction, and the X direction and the Y direction may intersect. In a specific embodiment, the X direction and the Y direction may be perpendicular to each other, so that the X direction, the Y direction and the Z direction are perpendicular to each other.

[0080] refer to 3A to 3H , 3A to 3H The cross-sectional structure diagram of the semiconductor device provided in the embodiment of the present disclosure during the manufacturing process. 3A to 3H The manufacturing process of the semiconductor device provided by the embodiment of the present disclosure is described in detail.

[0081] like Figure 3A As shown, in the embodiment of the present disclosure, in step S201 , a first semiconductor structure 300 is provided. The first semiconductor structure 300 includes a semiconductor layer 302 , an etch stop layer 306 , and a stacked structure 308 which are stacked in sequence.

[0082] Here, the first semiconductor structure 300 may further include an etch barrier layer 304 located between the semiconductor layer 302 and an etch stop layer 306 (Etch Stop Layer, ESL).

[0083] In some embodiments, the material of the etch stop layer 304 may include, but is not limited to, oxide, such as silicon oxide.

[0084] In some embodiments, the semiconductor layer 302 may include a substrate, specifically including at least one elemental semiconductor material (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (for example, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0085] In the embodiment of the present disclosure, the material of the etch stop layer 306 may include a doped carbon material, such as a boron-doped carbon material. The etch stop layer 306 may be used as a stop layer for etching to form the first channel holes, so that the etching depths of the plurality of first channel holes are uniform, that is, the bottoms of the plurality of first channel holes all stay in the etch stop layer 306.

[0086] Here, the two surfaces of the etch stop layer 306 opposite to each other along the Z direction are in contact with the etch barrier layer 304 and the stacked structure 308 respectively. The etch stop layer 306 can be grooved during the process of forming gate line grooves in the subsequent process to reduce stress and improve the adhesion of the etch stop layer.

[0087] In some embodiments, the stacked structure 308 may include first material layers 310 and second material layers 312 that are alternately stacked; wherein the first material layer 310 may be, for example, a gate sacrificial layer, and the second material layer 312 may be, for example, an interlayer insulating layer. The disclosed embodiment has no particular limitation on the number and thickness of the first material layers 310 and the second material layers 312 included in the stacked structure 308, and can be flexibly selected according to actual conditions.

[0088] In a specific embodiment, the material of the first material layer 310 may include but is not limited to nitride, and the material of the second material layer 312 may include but is not limited to oxide.

[0089] In some embodiments, the process of forming the etch barrier layer 304, the etch stop layer 306, the first material layer 310 and the second material layer 312 may include but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or any combination thereof.

[0090] Still Figure 3A As shown, in the embodiment of the present disclosure, in step S202 , a mask layer 314 is formed on the first semiconductor structure 300 .

[0091] In the embodiment of the present disclosure, the material of the mask layer 314 includes carbon material.

[0092] In the embodiment of the present disclosure, the process of forming the mask layer 314 may include but is not limited to PVD, CVD, ALD or any combination thereof.

[0093] like Figure 3B As shown, in the embodiment of the present disclosure, in step S203 , the mask layer 314 is used to etch to form a first channel hole 316 penetrating the stacked structure 308 and extending into the etch stop layer 306 .

[0094] Illustratively, the opening of the mask layer 314 is used to etch along the Z direction to form first channel holes 316 penetrating the stacked structure 308 and extending into the etch stop layer 306 ; wherein the bottoms of the plurality of first channel holes 316 all stay in the etch stop layer 306 .

[0095] In some embodiments, the process of forming the first channel hole 316 includes, but is not limited to, dry etching, wet etching, or a combination thereof.

[0096] like Figure 3B and Figure 3C As shown, in the embodiment of the present disclosure, in step S204 , the mask layer 314 is removed; wherein, in the same etching process, the etching rate of the mask layer 314 is greater than the etching rate of the etch stop layer 306 .

[0097] Exemplarily, after etching to form the first channel hole 316, the mask layer 314 can be removed. Compared with the case where the material of the mask layer and the material of the etch stop layer are the same, in the process of etching and removing the mask layer, the etch stop layer will also be etched and removed, resulting in the collapse of the stacked structure. In the embodiment of the present disclosure, the material of the mask layer 314 is different from the material of the etch stop layer 306; in the same etching process, the etching rate of the mask layer 314 is greater than the etching rate of the etch stop layer 306. In other words, in the process of etching and removing the mask layer 314, the etching damage to the etch stop layer 306 can be improved.

[0098] In the embodiment of the present disclosure, the material of the mask layer 314 may include a carbon material, and the material of the etch stop layer 306 may include a doped carbon material. In the embodiment of the present disclosure, there is no special limitation on the doping element and doping concentration of the etch stop layer 306, and the etching rate of the mask layer 314 and the etch stop layer 306 can be regulated by adjusting the doping element and the doping concentration. For example, a boron-doped carbon film may be formed as the etch stop layer 306.

[0099] In a specific embodiment, the thickness of the etch stop layer 306 may be less than 100 nm.

[0100] As described above, the etching rates of the mask layer 314 and the etch stop layer 306 can be controlled by adjusting the doping elements and doping concentrations. In this way, even if the thickness of the etch stop layer 306 is less than 100 nm, the etching damage to the etch stop layer 306 can be reduced during the removal of the mask layer 314.

[0101] It should be noted that, during the process of etching and removing the mask layer 314 , etching damage may be caused to a portion of the etch stop layer 306 , that is, during the process of etching and removing the mask layer 314 , the etching depth of the first channel hole 316 may increase. Figure 3C The etching depth of the first channel hole 316 shown in the diagram along the Z direction is greater than Figure 3B The etching depth of the first channel hole 316 along the Z direction is shown.

[0102] In the embodiment of the present disclosure, the process of removing the mask layer 314 may be an ashing process.

[0103] In the embodiment of the present disclosure, after step S204, the manufacturing method further includes:

[0104] The first channel hole 316 is filled to form a first channel structure 318 ; the first channel structure 318 includes a first storage structure 320 , a first channel layer 322 and a first filling layer 324 in sequence radially inward.

[0105] Combination Figure 3C and Figure 3D As shown, a first storage structure 320, a first channel layer 322 and a first filling layer 324 are sequentially formed in the first channel hole 316 to form a first channel structure 318. The first storage structure 320 includes a barrier layer, a storage layer and a tunneling layer in sequence radially inward. The first channel structure 318 has two opposite ends along the Z direction, one end of the first channel structure 318 is substantially flush with the surface of the stacked structure 308, and the other end of the first channel structure 318 is located in the etch stop layer 306.

[0106] In some embodiments, the material of the barrier layer may include but is not limited to silicon oxide, silicon oxynitride, or any combination thereof; the material of the storage layer may include but is not limited to silicon nitride, silicon oxynitride, or any combination thereof; the material of the tunneling layer may include but is not limited to silicon oxide, silicon oxynitride, or any combination thereof. The material of the first channel layer 322 may include but is not limited to polysilicon; the material of the first filling layer 324 may include but is not limited to oxide. In a specific embodiment, the first storage structure 320 may include a silicon oxide / silicon nitride / silicon oxide (ONO) composite structure.

[0107] In some embodiments, the orthographic projection shape of the first channel structure 318 on the XY plane may be, for example, a circle, an ellipse, a polygon, etc. The embodiment of the disclosure has no special limitation on the orthographic projection shape of the first channel structure 318 on the XY plane, and those skilled in the art may flexibly select it according to actual conditions.

[0108] In some embodiments, a first channel structure and a dummy channel structure can be formed simultaneously, and the first channel structure and the dummy channel structure have the same structure. The difference between the first channel structure and the dummy channel structure is that the first channel structure can be used to store data, while the dummy channel structure does not have the function of storing data and is only used to ensure the stability and reliability of the semiconductor structure.

[0109] In some embodiments, the process of forming the first memory structure 320 , the first channel layer 322 , and the first filling layer 324 may include, but is not limited to, PVD, CVD, ALD, or any combination thereof.

[0110] In a specific embodiment, the process of forming the first filling layer 324 may include ALD.

[0111] In the embodiment of the present disclosure, after the first channel hole 316 is filled to form the first channel structure 318, the manufacturing method further includes:

[0112] removing the semiconductor layer 302 and the etch stop layer 306 to expose a portion of the first channel structure 318;

[0113] The first storage structure 320 of the exposed portion of the first channel structure 318 is removed to expose the first channel layer 322 of the portion of the first channel structure 318 .

[0114] Combination Figure 3D and Figure 3E As shown, a gate line spacer ( Figure 3E The gate replacement process is performed through the gate line grooves to replace the first material layer 310 (i.e., the gate sacrificial layer) with the third material layer 326 (i.e., the gate conductive layer); the gate line grooves can be filled; and the first semiconductor structure 300 is turned over to facilitate the subsequent back-side process. After the gate replacement process is performed, the second material layer 312 and the third material layer 326, which are alternately stacked, form a stacked structure 308.

[0115] It should be noted that the semiconductor layer 302 has two surfaces disposed opposite to each other along the Z direction, namely, a front surface and a back surface. Figure 3A As shown, the surface in contact with the etch stop layer 304 is the front side of the semiconductor layer 302 , and the surface away from the etch stop layer 304 is the back side of the semiconductor layer 302 .

[0116] In some embodiments, the gate line trenches may be filled with an isolation material to form a gate line isolation structure. In other embodiments, the gate line trenches may also be filled with a conductive material to form an array common source.

[0117] In some embodiments, the third material layer 326 may be, for example, a gate conductive layer, and the material of the third material layer 326 may include a conductive material. In a specific embodiment, the third material layer 326 may be a composite material layer including a high dielectric constant layer, a titanium nitride layer, and a tungsten layer.

[0118] Combination Figure 3E and Figure 3F As shown, the semiconductor layer 302, the etch barrier layer 304, and the etch stop layer 306 are removed from the back side in sequence to expose a portion of the first channel structure 318, more specifically, to expose a portion of the first channel structure 318 located in the etch stop layer 306. The first channel structure 318 has two opposite ends along the Z direction, and removing the semiconductor layer 302, the etch barrier layer 304, and the etch stop layer 306 will expose one end of the first channel structure 318 located in the etch stop layer 306.

[0119] In some embodiments, the process of removing the semiconductor layer 302, the etch barrier layer 304 and the etch stop layer 306 may include, but is not limited to, dry etching, wet etching or a combination thereof. In a specific embodiment, the process of removing the etch stop layer 306 may include an ashing process.

[0120] Combination Figure 3F and Figure 3G As shown, the first channel structure 318 includes a first storage structure 320 (i.e., a barrier layer, a storage layer and a tunneling layer), a first channel layer 322 and a first filling layer 324 in sequence radially inward; at least a portion of the exposed first channel structure 318 is removed to expose at least a portion of the first channel layer 322. Figure 3G The entire first storage structure 320 with the exposed first channel structure 318 removed is shown.

[0121] In some embodiments, the process of removing the exposed at least a portion of the first storage structure 320 may include, but is not limited to, dry etching.

[0122] In the embodiment of the present disclosure, after removing the first storage structure 320 of the exposed portion of the first channel structure 318 to expose the first channel layer 322 of the portion of the first channel structure 318, the manufacturing method further includes:

[0123] A first conductive layer 328 is formed to cover the exposed first channel layer 322 .

[0124] like Figure 3H As shown, a first conductive layer 328 is formed on the stacked structure 308, and the first conductive layer 328 covers the exposed first channel layer 322 of the first channel structure 318. The first channel layer 322 of the first channel structure 318 is electrically connected to the first conductive layer 328, and the first conductive layer 328 can be used as a common source layer (Common Source Plate).

[0125] In some embodiments, the material of the first conductive layer 328 may include a conductive material, such as polysilicon.

[0126] In some embodiments, the process of forming the first conductive layer 328 may include, but is not limited to, PVD, CVD, ALD, or any combination thereof.

[0127] In the disclosed embodiment, an etch stop layer is formed between the semiconductor layer and the stacked structure, so that the etch stop layer can be used as an etch stop layer for forming the first channel hole, thereby preventing the first channel hole from extending into the semiconductor layer. In the disclosed embodiment, etching forms a plurality of first channel holes that penetrate the stacked structure and extend into the etch stop layer, so that the bottoms of the plurality of first channel holes all stay in the etch stop layer; after the first channel holes are filled, the bottoms of the plurality of first channel structures all stay in the etch stop layer; after performing a back process to remove the semiconductor layer and the etch stop layer (for example, using an ashing process), a "bamboo shoot head" with uniform height and small height can be formed, thereby simplifying the manufacturing process of the semiconductor device. In addition, the manufacturing method of the semiconductor device provided in the disclosed embodiment has good compatibility with the current process.

[0128] refer to 4A to 4H , 4A to 4H A schematic diagram of a cross-sectional structure of another semiconductor device during the manufacturing process provided by the embodiment of the present disclosure. 4A to 4H The manufacturing process of the semiconductor device provided by the embodiment of the present disclosure is described in detail.

[0129] In the embodiment of the present disclosure, in step S201 , a second semiconductor structure 400 is provided. The second semiconductor structure 400 includes a semiconductor layer 402 , a second conductive layer 406 , an etch stop layer 408 , and a stacked structure 410 which are sequentially stacked.

[0130] like Figure 4A As shown, a second conductive layer 406, an etch stop layer 408 and a stacked structure 410 are sequentially formed on the semiconductor layer 402 to form a second semiconductor structure 400. The second conductive layer 406 can be used as a common source layer.

[0131] Here, the second semiconductor structure 400 may further include an etch stop layer 404 between the semiconductor layer 402 and the second conductive layer 406 .

[0132] In the embodiment of the present disclosure, the material of the etch stop layer 408 includes a doped carbon material, such as a boron-doped carbon material. The etch stop layer 408 can be used as a stop layer for etching to form the second channel holes, so that the etching depth of the plurality of second channel holes is uniform, that is, the bottoms of the plurality of second channel holes all stay in the etch stop layer 408.

[0133] Here, the two surfaces of the etch stop layer 408 that are relatively arranged along the Z direction are in contact with the stacked structure 410 and the second conductive layer 406 respectively. The etch stop layer 408 can be grooved during the process of forming gate line grooves in the subsequent process to reduce stress and thus improve the adhesion of the etch stop layer 408.

[0134] In some embodiments, the stacked structure 410 may include a first material layer 412 and a second material layer 414 that are alternately stacked; wherein the first material layer 412 may be, for example, a gate sacrificial layer, and the second material layer 414 may be, for example, an interlayer insulating layer. The disclosed embodiment does not specifically limit the number and thickness of the first material layer 412 and the second material layer 414 included in the stacked structure 410, and can be flexibly selected according to actual conditions. In a specific embodiment, the material of the first material layer 412 may include, but is not limited to, nitride, and the material of the second material layer 414 may include, but is not limited to, oxide.

[0135] In the embodiment of the present disclosure, the material of the second conductive layer 406 may include a conductive material, such as doped polysilicon or metal silicide.

[0136] In some embodiments, the process of forming the second conductive layer 406 may include, but is not limited to, PVD, CVD, ALD, or any combination thereof.

[0137] Figure 4A The materials and formation process of the semiconductor layer 402, the etch barrier layer 404, the etch stop layer 408 and the stacked structure 410 in the second semiconductor structure 400 as shown in FIG4H can be referred to. Figure 3A As for the first semiconductor structure shown in FIG3H , its details will not be repeated here.

[0138] Still Figure 4A As shown, in the embodiment of the present disclosure, in step S202 , a mask layer 416 is formed on the second semiconductor structure 400 .

[0139] In the embodiment of the present disclosure, the material of the mask layer 416 includes carbon material.

[0140] In the embodiment of the present disclosure, the process of forming the mask layer 416 may include but is not limited to PVD, CVD, ALD or any combination thereof.

[0141] like Figure 4B As shown, in the embodiment of the present disclosure, in step S203 , the mask layer 416 is used to etch to form a second channel hole 418 penetrating the stacked structure 410 and extending into the etch stop layer 408 .

[0142] Illustratively, the opening of the mask layer 416 is used to etch along the Z direction to form second channel holes 418 penetrating the stacked structure 410 and extending into the etch stop layer 408 ; wherein the bottoms of the plurality of second channel holes 418 all stay in the etch stop layer 408 .

[0143] In some embodiments, the process of forming the second channel hole 418 includes, but is not limited to, dry etching, wet etching, or a combination thereof.

[0144] like Figure 4B and Figure 4C As shown, in the embodiment of the present disclosure, in step S204 , the mask layer 416 is removed; wherein, in the same etching process, the etching rate of the mask layer 416 is greater than the etching rate of the etch stop layer 408 .

[0145] Exemplarily, after etching to form the second channel hole 418, the mask layer 416 can be removed. Compared with the case where the material of the mask layer and the material of the etch stop layer are the same, in the process of etching and removing the mask layer, the etch stop layer will also be etched and removed, resulting in the collapse of the stacked structure. In the embodiment of the present disclosure, the material of the mask layer 416 is different from the material of the etch stop layer 408; in the same etching process, the etching rate of the mask layer 416 is greater than the etching rate of the etch stop layer 408. In other words, in the process of etching and removing the mask layer 416, the etching damage to the etch stop layer 408 can be improved.

[0146] In the embodiment of the present disclosure, the material of the mask layer 416 may include a carbon material, and the material of the etch stop layer 408 may include a doped carbon material. In the embodiment of the present disclosure, there is no special limitation on the doping element and doping concentration of the etch stop layer 408, and the etching rates of the mask layer 416 and the etch stop layer 408 can be regulated by adjusting the doping element and the doping concentration. For example, a boron-doped carbon film may be formed as the etch stop layer 408.

[0147] In a specific embodiment, the thickness of the etch stop layer 408 may be less than 100 nm.

[0148] It should be noted that, during the process of etching and removing the mask layer 416 , etching damage may be caused to a portion of the etch stop layer 408 , that is, during the process of etching and removing the mask layer 416 , the etching depth of the second channel hole 418 may increase. Figure 4C The etching depth of the second channel hole 418 shown in the diagram along the Z direction is greater than Figure 4B The etching depth of the second channel hole 418 along the Z direction is shown.

[0149] In the embodiment of the present disclosure, the process of removing the mask layer 416 may be an ashing process.

[0150] In the embodiment of the present disclosure, after step S204, the manufacturing method further includes:

[0151] The second channel hole 418 is filled to form a second channel structure 420 ; the second channel structure 420 includes a second storage structure 422 , a second channel layer 426 , and a second filling layer 428 in sequence radially inward.

[0152] In the embodiment of the present disclosure, the second channel hole 418 is filled to form a second channel structure 420, including:

[0153] forming a second storage structure 422 and a sacrificial layer 424 in the second channel hole 418;

[0154] Removing a portion of the sacrificial layer 424 and a portion of the second storage structure 422 in the etch stop layer 408 to expose the etch stop layer 408;

[0155] removing the remaining sacrificial layer 424 to expose the second storage structure 422;

[0156] forming a second channel layer 426 covering the second storage structure 422 and contacting the second conductive layer 406;

[0157] The second channel hole 418 is filled to form a second filling layer 428 ; wherein the second storage structure 422 , the second channel layer 426 and the second filling layer 428 together form a second channel structure 420 .

[0158] like Figure 4D As shown, a second storage structure 422 is formed covering the bottom and sidewalls of the second channel hole 418, wherein the second storage structure 422 includes a barrier layer, a storage layer and a tunneling layer in sequence radially inward; a sacrificial layer 424 is formed covering the bottom and sidewalls of the second channel hole 418, and the sacrificial layer 424 is in contact with the second storage structure 422. The second storage structure 422 has two oppositely disposed ends along the Z direction, one end of the second storage structure 422 is substantially flush with the surface of the stacked structure 410, and the other end of the second storage structure 422 is located in the etch stop layer 408.

[0159] In some embodiments, the material of the barrier layer may include but is not limited to silicon oxide, silicon oxynitride, or any combination thereof; the material of the storage layer may include but is not limited to silicon nitride, silicon oxynitride, or any combination thereof; the material of the tunneling layer may include but is not limited to silicon oxide, silicon oxynitride, or any combination thereof. In a specific embodiment, the second storage structure 422 may include a silicon oxide / silicon nitride / silicon oxide (ONO) composite structure.

[0160] In some embodiments, the material of the sacrificial layer 424 may include but is not limited to polysilicon. The purpose of forming the sacrificial layer 424 is to protect the second storage structure 422 during the subsequent deep hole etching process to avoid etching damage to the second storage structure 422, thereby avoiding affecting the reliability and yield of the semiconductor device.

[0161] Combination Figure 4D and Figure 4EAs shown, deep hole etching is performed to remove part of the sacrificial layer 424 and part of the second storage structure 422 in the etch stop layer 408, so as to open the bottom of the sacrificial layer 424 and the second storage structure 422 in the second channel hole 418, thereby exposing the etch stop layer 408; the remaining sacrificial layer 424 is removed to expose the second storage structure 422; a second channel layer 426 covering the second storage structure 422 and contacting the second conductive layer 406 is formed; the second channel hole 418 is filled to form a second filling layer 428; wherein the second storage structure 422, the second channel layer 426 and the second filling layer 428 together form a second channel structure 420. The second channel structure 420 has two oppositely disposed ends along the Z direction, one end of the second channel structure 420 is flush with the surface of the stacked structure 410, and the other end of the second channel structure 420 is located in the etch stop layer 408.

[0162] In some embodiments, the material of the second channel layer 426 may include, but is not limited to, polysilicon; the material of the second filling layer 428 may include, but is not limited to, oxide.

[0163] In some embodiments, the orthographic projection shape of the second channel structure 420 on the XY plane may be, for example, circular, elliptical, polygonal, etc. The embodiment of the present disclosure has no special limitation on the orthographic projection shape of the second channel structure 420 on the XY plane, and those skilled in the art may flexibly select it according to actual conditions.

[0164] In some embodiments, a second channel structure and a dummy channel structure can be formed simultaneously, and the second channel structure and the dummy channel structure have the same structure. The difference between the second channel structure 420 and the dummy channel structure is that the second channel structure can be used to store data, while the dummy channel structure does not have the function of storing data and is only used to ensure the stability and reliability of the semiconductor structure.

[0165] In some embodiments, the process of forming the second memory structure 422 , the sacrificial layer 424 , the second channel layer 426 and the second filling layer 428 may include, but is not limited to, PVD, CVD, ALD, or any combination thereof.

[0166] In a specific embodiment, the process of forming the second filling layer 428 may include ALD.

[0167] In some embodiments, the contact interface between the second channel layer 426 and the second conductive layer 406 is planar.

[0168] Illustratively, deep hole etching is performed to remove a portion of the sacrificial layer 424 and a portion of the second storage structure 422 located in the etch stop layer 408, so as to open the bottom of the sacrificial layer 424 and the second storage structure 422 in the second channel hole 418, thereby exposing the etch stop layer 408; etching can be continued to remove the etch stop layer 408 exposed at the bottom of the second channel hole 418 to expose the second conductive layer 406; and a second channel layer 426 is formed that covers the side walls of the second storage structure 422 and contacts the second conductive layer 406.

[0169] In the embodiment of the present disclosure, after the second channel hole 418 is filled to form the second channel structure 420, the manufacturing method further includes:

[0170] The semiconductor layer 402 is removed to expose the second conductive layer 406 .

[0171] Combination Figure 4E and Figure 4F As shown, a gate line spacer ( Figure 4F The gate replacement process is performed through the gate line grooves to replace the first material layer 412 with the third material layer 430, that is, the gate sacrificial layer is replaced with the gate conductive layer; the gate line grooves can be filled; the second semiconductor structure 400 is turned over to facilitate the subsequent back-side process. After the gate replacement process is performed, the second material layer 414 and the third material layer 430 alternately stacked together form a stacked structure 410.

[0172] It should be noted that the semiconductor layer 402 has two surfaces disposed opposite to each other along the Z direction, namely, a front surface and a back surface. Figure 4A As shown, the surface in contact with the etch stop layer 404 is the front side of the semiconductor layer 402 , and the surface away from the etch stop layer 404 is the back side of the semiconductor layer 402 .

[0173] In some embodiments, the gate line trenches may be filled with an isolation material to form a gate line isolation structure. In other embodiments, the gate line trenches may also be filled with a conductive material to form an array common source.

[0174] In some embodiments, the third material layer 430 may be, for example, a gate conductive layer, and the material of the third material layer 430 may include a conductive material. In a specific embodiment, the third material layer 430 may be a composite material layer including a high dielectric constant layer, a titanium nitride layer, and a tungsten layer.

[0175] like Figure 4F and Figure 4G As shown, the semiconductor layer 402 and the etching stop layer 404 are removed in sequence to expose the surface of the second conductive layer 406. The second conductive layer 406 can be used as a common source layer.

[0176] In the embodiment of the present disclosure, the process of removing the semiconductor layer 402 and the etch stop layer 404 may include but is not limited to dry etching, wet etching or a combination thereof.

[0177] In the disclosed embodiment, a second conductive layer (i.e., a common source layer) is formed between the semiconductor layer and the etch stop layer, and a second channel hole is formed by etching. After forming the second storage structure and the sacrificial layer, deep hole etching is performed to open the second channel hole, so as to form a contact between the second channel layer and the second conductive layer. In this way, there is no need to form a common source layer after processing the "bamboo shoot head", and the process of forming the common source layer can be simplified.

[0178] In the embodiment of the present disclosure, the second channel layer 426 has two ends arranged opposite to each other along the stacking direction; after removing the semiconductor layer 402 to expose the second conductive layer 406, the manufacturing method further includes:

[0179] Performing a doping process on an end of the second channel layer 426 close to the second conductive layer 406 to form a doped second channel layer 432;

[0180] The doped second channel layer 432 is annealed.

[0181] like Figure 4H As shown, the second channel layer 426 has two ends arranged opposite to each other along the Z direction, one end of the second channel layer 426 is basically flush with the stacked structure, and the other end of the second channel layer 426 is in contact with the second conductive layer 406; an ion implantation process is performed on the end of the second channel layer 426 in contact with the second conductive layer 406 to form a doped second channel layer 432 at the end of the second channel layer 426 in contact with the second conductive layer 406, and the remaining second channel layer 426 forms an undoped second channel layer 434; the doped second channel layer 432 is annealed.

[0182] Exemplarily, ion implantation can be performed at one end of the second channel layer, and the doped ions are implanted into the second channel layer in the form of an ion beam. The high-energy ions lose energy due to collisions with atoms in the second channel layer, and finally stay at a certain depth in the second channel layer. It should be noted that in the embodiment of the present disclosure, the channel layer is doped using an ion implantation process, and the doping depth is the ion implantation depth. Different doping depths, doping concentrations, or doping impurity distributions can be set according to actual needs of semiconductor devices. Among them, the doping depth can be controlled by adjusting the acceleration energy of the ion beam, and the doping concentration, that is, the impurity dose, can be controlled by monitoring the ion current during implantation. Therefore, the use of an ion implantation process for doping can more accurately control the doping concentration, doping depth, and doping impurity distribution, and is repeatable.

[0183] In some embodiments, the doping depth, that is, the height of the doped second channel layer 432 along the Z direction, can be controlled by controlling the energy of the ion implantation.

[0184] In some embodiments, the doped second channel layer 432 may be located in the etch stop layer 408, and the undoped second channel layer 434 may be located in the stacked structure 410. In other embodiments, a portion of the doped second channel layer 432 may be located in the etch stop layer 408 and a portion of the doped second channel layer 432 may be located in the stacked structure 410, that is, the doped second channel layer 432 extends from the etch stop layer 408 to the stacked structure 410, and the undoped second channel layer 434 is located in the stacked structure 410. The embodiment of the present disclosure has no particular limitation on the height of the doped second channel layer 432 along the Z direction.

[0185] refer to Figure 5 , Figure 5 A schematic diagram of the cross-sectional structure of a semiconductor device provided in an embodiment of the present disclosure.

[0186] like Figure 5 As shown, an embodiment of the present disclosure provides a semiconductor device, the semiconductor device comprising:

[0187] The conductive layers 506 (ie, 4A to 4H The second conductive layer 406), the etch stop layer 508 (ie, 4A to 4H The etch stop layer 408 in the embodiment of the present invention) and the stacked structure 510 (ie, 4A to 4H The laminated structure 410 in FIG.

[0188] The channel structure 520 (ie, FIG. 4E to FIG. 4H wherein the channel structure 520 includes a channel layer 526 (ie, FIG. 4E to FIG. 4H The second channel layer 426 in the conductive layer 506 is in contact with the channel layer 526.

[0189] In the disclosed embodiment, the semiconductor device includes a second conductive layer, an etch stop layer, and a stacked structure stacked in sequence; a second channel structure that penetrates the stacked structure and the etch stop layer, and the second channel layer in the second channel structure contacts the second conductive layer. In this way, there is no need to perform a back process to remove the etch stop layer to expose one end of the second channel structure, and there is no need to remove a portion of the second storage structure of the second channel structure to expose a portion of the second channel layer of the second channel structure, which can simplify the process of forming a common source layer.

[0190] In the embodiment of the present disclosure, the contact interface between the channel layer 526 (ie, the second channel layer 426) and the conductive layer 506 (ie, the second conductive layer 406) is a plane. In other words, the contact interface between the second channel layer 426 and the second conductive layer 406 is a plane.

[0191] Combination 4A to 4H and Figure 5 As shown, after the second storage structure and the sacrificial layer are formed in the second channel hole, deep hole etching is performed to remove part of the sacrificial layer and part of the second storage structure to open the bottom of the second channel hole; a second channel layer is formed, and the second channel layer can cover the side wall of the second storage structure and contact the second conductive layer.

[0192] In the embodiment of the present disclosure, the channel structure 520 includes storage structures 522 (ie, FIG. 4E to FIG. 4H The second storage structure 422 in the embodiment of the present invention), the channel layer 526 and the filling layer 528 (ie, FIG. 4E to FIG. 4H A second filling layer 428 in;

[0193] In the portion of the channel structure 520 located within the etch stop layer 508 , the storage structure 522 surrounds the channel layer 526 .

[0194] Combination 4A to 4H and Figure 5 As shown, the second channel structure includes a second storage structure, a second channel layer and a second filling layer in sequence along the radial direction inward; in the part of the second channel structure located in the etch stop layer, the second storage structure surrounds the second channel layer. The second storage structure includes a barrier layer, a storage layer and a tunneling layer in sequence along the radial direction inward.

[0195] In the embodiment of the present disclosure, the channel layer 526 has two ends disposed opposite to each other along the stacking direction; the channel layer 526 includes a doped channel layer 532 (ie, Figure 4H The doped second channel layer 432 is located at one end close to the conductive layer 506.

[0196] Combination 4A to 4H and Figure 5 As shown, the channel layer 526 (ie, the second channel layer 526) includes a doped channel layer 532 (ie, the doped second channel layer 432) and an undoped channel layer 534 (ie, Figure 4H The undoped second channel layer 434 in the embodiment of the present disclosure is formed by an ion implantation process to reduce the contact resistance (Rc).

[0197] In the embodiment of the present disclosure, the conductive layer 506 (ie, the second conductive layer 406) is used to be electrically connected to the lead pad. Figure 5 The lead pads are not shown.

[0198] Here, the conductive layer 506 serves as a common source layer, and the conductive layer 506 is electrically connected to the lead-out pad for leading out electrical signals.

[0199] In the embodiment of the present disclosure, the material of the etch stop layer 508 includes a doped carbon material;

[0200] The material of the conductive layer 506 (ie, the second conductive layer 406 ) includes doped polysilicon or metal silicide.

[0201] In the embodiment of the present disclosure, the thickness of the etch stop layer 508 along the stacking direction is less than 100 nm.

[0202] refer to Figure 6 , Figure 6 A block diagram of a memory system provided in an embodiment of the present disclosure. An embodiment of the present disclosure provides a memory system 600, the memory system 600 comprising:

[0203] As the semiconductor device 602 in the above technical solution;

[0204] A controller 604 is coupled to the semiconductor device 602 and configured to control the semiconductor device 602 .

[0205] In the embodiment of the present disclosure, the semiconductor device 602 may be a memory; or may be a part of a memory, that is, the semiconductor device 602 includes a memory cell array, and the memory cell array may form a memory together with peripheral circuits.

[0206] The memory system 600 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the memory system 600 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0207] In some embodiments, the controller 604 is configured to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0208] In other embodiments, the controller 604 is configured to operate in a high duty cycle environment (Solid State Drive, SSD) or an embedded Multi-Media Card (eMMC), where the SSD or eMMC is used for data storage in mobile devices such as smart phones, tablets, and laptops, as well as enterprise storage arrays.

[0209] The controller 604 may be configured to control the operation of the semiconductor device 602, such as read, erase, and program operations. The controller 604 may also be configured to manage various functions regarding data stored or to be stored in the semiconductor device 602, including but not limited to bad block management, garbage collection, logical address to physical address conversion, wear leveling, etc. In some embodiments, the controller 604 is also configured to process error correction codes (ECC) regarding data read from or written to the semiconductor device 602.

[0210] The controller 604 may also perform any other suitable functions, such as formatting the semiconductor device 602. The controller 604 may communicate with an external device (e.g., a host) according to a specific communication protocol. For example, the controller 604 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Drive Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0211] The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and a memory system. The manufacturing method comprises: providing a semiconductor structure, the semiconductor structure comprising a semiconductor layer, an etch stop layer and a stacked structure stacked in sequence; forming a mask layer on the semiconductor structure; using the mask layer to etch to form a channel hole that penetrates the stacked structure and extends into the etch stop layer; removing the mask layer; wherein, in the same etching process, the etching rate of the mask layer is greater than the etching rate of the etch stop layer. In the embodiments of the present disclosure, in the same etching process, the etching rate of the mask layer is greater than the etching rate of the etch stop layer, which can improve the etching damage to the etch stop layer in the process of etching and removing the mask layer, thereby reducing the risk of collapse of the semiconductor structure.

[0212] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0213] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: A semiconductor structure is provided, wherein the semiconductor structure comprises a semiconductor layer, an etch stop layer and a stacked structure which are stacked in sequence; forming a mask layer on the semiconductor structure; Using the mask layer to etch and form a channel hole penetrating the stacked structure and extending into the etch stop layer; The mask layer is removed; wherein, in the same etching process, the etching rate of the mask layer is greater than the etching rate of the etching stop layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: After removing the mask layer, the manufacturing method further includes: The channel hole is filled to form a first channel structure; the first channel structure includes a first storage structure, a first channel layer and a first filling layer in sequence along the radial direction inward.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: After filling the channel hole to form the first channel structure, the manufacturing method further includes: removing the semiconductor layer and the etch stop layer to expose a portion of the first channel structure; The first storage structure of the exposed portion of the first channel structure is removed to expose the first channel layer of the portion of the first channel structure.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: After removing the exposed first storage structure of the first channel structure to expose the first channel layer of the first channel structure, the manufacturing method further includes: A first conductive layer is formed to cover the exposed first channel layer.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The semiconductor structure further includes: a second conductive layer located between the semiconductor layer and the etch stop layer; After removing the mask layer, the manufacturing method further includes: The channel hole is filled to form a second channel structure; the second channel structure includes a second storage structure, a second channel layer and a second filling layer in sequence along the radial direction inward.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The step of filling the channel hole to form a second channel structure includes: forming a second storage structure and a sacrificial layer in the channel hole; removing a portion of the sacrificial layer and a portion of the second storage structure located in the etch stop layer to expose the etch stop layer; removing the remaining sacrificial layer to expose the second storage structure; forming a second channel layer covering the second storage structure and contacting the second conductive layer; The channel hole is filled to form a second filling layer; wherein the second storage structure, the second channel layer and the second filling layer together form a second channel structure.

7. The method for manufacturing a semiconductor device according to claim 5, wherein: After filling the channel hole to form a second channel structure, the manufacturing method further includes: The semiconductor layer is removed to expose the second conductive layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The second channel layer has two ends arranged opposite to each other along the stacking direction; After removing the semiconductor layer to expose the second conductive layer, the manufacturing method further includes: Performing a doping process on an end of the second channel layer close to the second conductive layer to form a doped second channel layer; The doped second channel layer is annealed.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the mask layer includes a carbon material; The material of the etch stop layer includes doped carbon material.

10. The method for manufacturing a semiconductor device according to claim 1, wherein: The process of removing the mask layer is an ashing process.

11. A semiconductor device, characterized in that: The semiconductor device comprises: A conductive layer, an etch stop layer and a laminated structure are sequentially stacked; A channel structure penetrating the stacked structure and the etch stop layer; wherein the channel structure comprises a channel layer, and the channel layer is in contact with the conductive layer.

12. The semiconductor device according to claim 11, characterized in that The contact interface between the channel layer and the conductive layer is a plane.

13. The semiconductor device according to claim 11, characterized in that The channel structure includes a storage structure, a channel layer and a filling layer in sequence radially inwardly; In a portion of the channel structure located within the etch stop layer, the storage structure surrounds the channel layer.

14. The semiconductor device according to claim 11, characterized in that The channel layer has two ends that are arranged opposite to each other along a stacking direction; the channel layer includes a doped channel layer, and the doped channel layer is located at one end close to the conductive layer.

15. The semiconductor device according to claim 11, wherein: The conductive layer is used for electrically connecting to the lead-out pad.

16. The semiconductor device according to claim 11, characterized in that The material of the etch stop layer includes a doped carbon material; The material of the conductive layer includes doped polysilicon or metal silicide.

17. The semiconductor device according to claim 11, characterized in that The thickness of the etch stop layer along the stacking direction is less than 100 nm.

18. A memory system, characterized in that: The memory system comprises: The semiconductor device according to any one of claims 11 to 17; A controller is coupled to the semiconductor device and configured to control the semiconductor device.

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