Power semiconductor device and preparation method thereof

Abstract

The embodiment of the invention provides a power semiconductor device and a preparation method thereof, and belongs to the technical field of semiconductors. The preparation method comprises the following steps: providing a substrate; sequentially forming a first buffer layer and a second buffer layer on the substrate by adopting a physical vapor deposition technology; and forming a device layer on the second buffer layer by adopting a metal organic compound chemical vapor deposition technology. According to the embodiment of the invention, the performance and reliability of the power semiconductor device can be improved, and the production cost is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a power semiconductor device and a method for preparing the same. Background Art

[0002] A power semiconductor device, also known as a power electronic device, is a semiconductor device used for power processing and has the ability to handle high voltage and high current.

[0003] In the related art, a method for preparing a power semiconductor device includes: providing a substrate, and then sequentially forming a first buffer layer, a second buffer layer and a device layer on the substrate using a metal-organic chemical vapor deposition (MOCVD) technique.

[0004] However, when the first buffer layer and the second buffer layer are formed on the substrate using MOCVD technology, the selectivity for the substrate is strong. The poor quality of the substrate can easily cause the first buffer layer and the second buffer layer to warp and have uneven thickness, resulting in poor quality of the first buffer layer and the second buffer layer. Then, forming a device layer on the poor quality second buffer layer will affect the quality of the device layer, thereby affecting the performance and reliability of the power semiconductor device. In addition, the production rate of the first buffer layer and the second buffer layer formed using MOCVD technology is low, which will affect the production capacity and production cost of the power semiconductor device. Summary of the invention

[0005] The embodiment of the present disclosure provides a power semiconductor device and a method for manufacturing the same, which can improve the performance and reliability of the power semiconductor device and reduce production costs. The technical solution is as follows:

[0006] On the one hand, a method for preparing a power semiconductor device is provided, comprising: providing a substrate; forming a first buffer layer and a second buffer layer in sequence on the substrate using physical vapor deposition (PVD) technology; and forming a device layer on the second buffer layer using metal organic compound chemical vapor deposition technology.

[0007] Optionally, the first buffer layer is formed in the following manner: a first sub-buffer layer is formed on the substrate using physical vapor deposition technology, and the first sub-buffer layer is annealed; a second sub-buffer layer is formed on the annealed first sub-buffer layer using physical vapor deposition technology to obtain the first buffer layer.

[0008] Optionally, when the first sub-buffer layer is annealed, the annealing duration is 20 min to 80 min.

[0009] Optionally, a thickness of the second sub-buffer layer is greater than a thickness of the first sub-buffer layer.

[0010] Optionally, the first sub-buffer layer has a thickness of 1 nm to 10 nm, and the second sub-buffer layer has a thickness of 100 nm to 500 nm.

[0011] Optionally, the first sub-buffer layer and the second sub-buffer layer are both formed by radio frequency sputtering, and the power of the radio frequency sputtering is 2000W to 5000W.

[0012] Optionally, the second buffer layer is formed by both direct current sputtering and radio frequency sputtering, the voltage of the direct current sputtering is 150V to 300V, and the power of the radio frequency sputtering is 50W to 500W.

[0013] Optionally, the method further includes: before forming the first buffer layer, placing the substrate in a physical vapor deposition device, introducing Ar and H2, and performing a first plasma treatment on the substrate; and introducing N2, and performing a second plasma treatment on the substrate.

[0014] Optionally, the duration of the first plasma treatment is 200 s to 400 s, and the duration of the second plasma treatment is 100 s to 300 s.

[0015] On the other hand, a power semiconductor device is provided, comprising a substrate, a first buffer layer, a second buffer layer and a device layer stacked in sequence, wherein the first buffer layer and the second buffer layer are formed by physical vapor deposition technology; and the device layer is formed by metal organic compound chemical vapor deposition technology.

[0016] The technical solution provided by the embodiments of the present disclosure brings the following beneficial effects:

[0017] In the disclosed embodiment, the PVD technology is first used to sequentially form the first buffer layer and the second buffer layer on the substrate. Since the selectivity of the PVD technology to the substrate is weaker than that of the MOCVD technology, the PVD technology is used to form the first buffer layer and the second buffer layer on the substrate, which can be applied to large-sized or various quality substrates, and reduce the probability of the film quality of the first buffer layer and the second buffer layer being affected by the poor quality of the substrate, and reduce the probability of the first buffer layer and the second buffer layer being warped, so that the thickness of the first buffer layer and the second buffer layer is more uniform, thereby effectively improving the quality of the first buffer layer and the second buffer layer. Then, the MOCVD technology is used to form the device layer on the high-quality second buffer layer, which can make the crystal quality of the device layer better, thereby effectively improving the performance and reliability of the power semiconductor device. In addition, compared with the MOCVD technology, the production rate of the first buffer layer and the second buffer layer formed by the PVD technology is higher, which is also conducive to improving the production capacity of power semiconductor devices and reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 is a flow chart of a method for preparing a power semiconductor device provided by an embodiment of the present disclosure;

[0020] Figure 2 is a flow chart of another method for preparing a power semiconductor device provided by an embodiment of the present disclosure;

[0021] Figure 3 is a schematic structural diagram of a power semiconductor device provided by an embodiment of the present disclosure;

[0022] Figure 4 is a schematic diagram of a curve of drain leakage current of a power semiconductor device provided by an embodiment of the present disclosure;

[0023] Figure 5 is a schematic diagram of a curve of gate leakage current of a power semiconductor device provided by an embodiment of the present disclosure;

[0024] Figure 6 It is a schematic diagram comparing the dynamic resistivity of a power semiconductor device provided in an embodiment of the present disclosure.

[0025] Reference numerals:

[0026] 10: substrate; 20: first buffer layer; 201: first sub-buffer layer; 202: second sub-buffer layer; 30: second buffer layer; 40: device layer; 401: channel layer; 402: barrier layer; 50: drain; 51: source; 52: gate. DETAILED DESCRIPTION

[0027] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0028] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" and similar words mean that the elements or objects appearing before "include" include the elements or objects listed after "include" and their equivalents, and do not exclude other elements or objects. Words such as "connect" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0029] In order to facilitate understanding of the embodiments of the present disclosure, the following first introduces the preparation method of the power semiconductor device in the related art. Since the surface roughness Ra of the substrate is large, that is, the surface flatness of the substrate is poor, if the PVD technology is used to directly form the first buffer layer and the second buffer layer on the substrate, it is easy to adsorb water and oxygen at the interface between the substrate and the first buffer layer, affecting the quality of the first buffer layer and the second buffer layer. Therefore, in order to ensure the quality of the first buffer layer and the second buffer layer, the MOCVD technology is used in the related art to sequentially form the first buffer layer, the second buffer layer and the device layer on the substrate to prepare a power semiconductor device.

[0030] Figure 1 1 is a flow chart of a method for preparing a power semiconductor device provided by an embodiment of the present disclosure. Figure 1 As shown, the preparation method comprises:

[0031] In step S1001 , a substrate is provided.

[0032] In step S1002, a first buffer layer and a second buffer layer are sequentially formed on a substrate using PVD technology.

[0033] In step S1003 , a device layer is formed on the second buffer layer by using MOCVD technology.

[0034] In the disclosed embodiment, the PVD technology is first used to sequentially form the first buffer layer and the second buffer layer on the substrate. Since the selectivity of the PVD technology to the substrate is weaker than that of the MOCVD technology, the PVD technology is used to form the first buffer layer and the second buffer layer on the substrate, which can be applied to large-sized or various quality substrates, and reduce the probability of the film quality of the first buffer layer and the second buffer layer being affected by the poor quality of the substrate, and reduce the probability of the first buffer layer and the second buffer layer being warped, so that the thickness of the first buffer layer and the second buffer layer is more uniform, thereby effectively improving the quality of the first buffer layer and the second buffer layer. Then, the MOCVD technology is used to form the device layer on the high-quality second buffer layer, which can make the crystal quality of the device layer better, thereby effectively improving the performance and reliability of the power semiconductor device. In addition, compared with the MOCVD technology, the production rate of the first buffer layer and the second buffer layer formed by the PVD technology is higher, which is also conducive to improving the production capacity of power semiconductor devices and reducing production costs.

[0035] Figure 2 FIG. 1 is a flow chart of another method for preparing a power semiconductor device provided by an embodiment of the present disclosure. Figure 2 As shown, the preparation method comprises:

[0036] In step S2001, a plasma treatment is performed on a substrate.

[0037] Optionally, the substrate may be a single crystal substrate or a composite engineered substrate.

[0038] Exemplarily, when the substrate is a single crystal substrate, the single crystal substrate may be a Si substrate, a SiC substrate, a GaN substrate or a sapphire substrate. In the embodiment of the present disclosure, the substrate is a Si substrate.

[0039] Alternatively, the substrate may be a circular substrate or a rectangular substrate.

[0040] Exemplarily, when the substrate is a circular substrate, the diameter of the circular substrate is 2 inches to 8 inches.

[0041] Optionally, step S2001 may include the following steps:

[0042] In the first step, the substrate is placed in a PVD device, Ar and H2 are introduced, and the substrate is subjected to the first plasma treatment.

[0043] The first plasma treatment of the substrate using a mixed gas of Ar and H2 can produce a certain etching effect on the oxide on the surface of the substrate, causing the oxide on the surface of the substrate to undergo a reduction reaction and be removed, thereby etching and cleaning the surface of the substrate. Ar and H2 will not cause significant damage to the surface of the substrate, which is beneficial to improving the surface flatness of the substrate.

[0044] For example, during the first plasma treatment, the etching rate is 0.005 nm / s to 0.02 nm / s. When the etching rate is within this relatively low range, the probability of plasma treatment damaging the surface of the substrate can be effectively reduced, thereby ensuring good quality of the substrate.

[0045] For example, during the first plasma treatment, the gas proportion of H2 is 20% to 50%. The gas proportion refers to the ratio of the volume of H2 to the sum of the volumes of H2 and Ar. This can effectively remove oxides on the surface of the substrate while reducing damage to the substrate.

[0046] Optionally, the duration of the first plasma treatment is 200s to 400s. If the duration of the first plasma treatment is too short, the flatness of the surface of the substrate may be affected; if the duration of the first plasma treatment is too long, the surface of the substrate may be damaged and the production efficiency may be affected. When the duration of the first plasma treatment is within this range, the surface of the substrate can be less damaged, the flatness is higher, and the production efficiency is improved.

[0047] For example, the duration of the first plasma treatment may be 200 s, 300 s, or 400 s.

[0048] In the second step, N2 is introduced to perform a second plasma treatment on the substrate.

[0049] The second plasma treatment of the substrate with N2 can further clean the surface of the substrate, and N2 will not cause significant damage to the surface of the substrate, which is conducive to obtaining a substrate with an atomically flat surface.

[0050] Optionally, the duration of the second plasma treatment is 100 s to 300 s. In this way, the flatness of the surface of the substrate can be maximized, and the influence of water and oxygen on the quality of the first buffer layer and the second buffer layer can be effectively reduced when the first buffer layer and the second buffer layer are sequentially formed on the substrate using PVD technology.

[0051] For example, the duration of the second plasma treatment may be 100 s, 200 s, or 300 s.

[0052] Through the first step to the second step, the substrate can be plasma treated.

[0053] Optionally, the surface roughness Ra of the substrate is 0.2nm to 0.5nm. If the surface roughness Ra of the substrate is too large, the quality of the first buffer layer and the second buffer layer will be affected when the first buffer layer and the second buffer layer are formed on the substrate using the PVD technology. When the surface roughness Ra of the substrate is within this relatively low range, that is, when the first buffer layer and the second buffer layer are formed on the surface of a substrate with a higher flatness using the PVD technology, the influence of water and oxygen on the quality of the first buffer layer and the second buffer layer can be reduced, so that the thickness of the first buffer layer and the second buffer layer is more uniform.

[0054] For example, the surface roughness Ra of the substrate may be 0.2 nm, 0.3 nm, 0.4 nm, etc.

[0055] In other embodiments, other gases may be used to perform plasma treatment on the substrate, or other treatment methods may be used to ensure that the surface roughness Ra of the substrate is small and the flatness is high, and the present disclosure does not limit this.

[0056] In step S2002, a first sub-buffer layer is formed on the substrate by using PVD technology, and the first sub-buffer layer is annealed.

[0057] For example, the first sub-buffer layer can be formed on the substrate by sputtering. Sputtering is the most widely used method in PVD process. The principle of sputtering coating is that under high vacuum conditions, rare gas (such as Ar) is ionized into ions (such as argon ions) under the action of an external electric field, and bombards the target material under a high voltage environment, bombarding atoms or molecules of the target material, which arrive at the film-forming surface through a collision-free flight process to form a thin film.

[0058] Figure 3 Schematic diagram of a power semiconductor device provided by an embodiment of the present disclosure. Figure 3 As shown, the first sub-buffer layer 201 is located on the surface of the substrate 10 .

[0059] For example, the first sub-buffer layer 201 can be formed on the substrate 10 by sputtering, and the substrate 10 and the first sub-buffer layer 201 are transferred to an annealing furnace without being exposed to the atmosphere, and the first sub-buffer layer 201 is annealed in an NH3 atmosphere. The annealing process can recrystallize the first sub-buffer layer 201, improve the stress of the first sub-buffer layer 201, and improve the crystal quality of the first sub-buffer layer 201.

[0060] For example, the PVD equipment and the annealing furnace may be connected via a glove box filled with an inert gas, and the transfer is performed through the glove box, so that the substrate 10 and the first sub-buffer layer 201 are not exposed to atmospheric conditions.

[0061] Optionally, the annealing temperature is 1000°C to 1400°C.

[0062] Optionally, the duration of annealing is 20 minutes to 80 minutes. If the duration of annealing is too short, the crystal quality of the first sub-buffer layer 201 may not be improved; if the duration of annealing is too long, the crystal quality of the first sub-buffer layer 201 is difficult to continue to improve, and the production rate will be affected. When the duration of annealing is within this range, the crystal quality of the first sub-buffer layer 201 can be effectively improved without affecting the production rate.

[0063] For example, the duration of annealing may be 20 min, 50 min, or 80 min, etc.

[0064] Optionally, the first sub-buffer layer 201 is formed by radio frequency sputtering. Radio frequency sputtering is a type of sputtering, and radio frequency sputtering can ensure that the quality of the first sub-buffer layer 201 on the substrate 10 is better, the thickness of the first sub-buffer layer 201 is more uniform, and the film forming rate of radio frequency sputtering is higher, which is conducive to improving production efficiency.

[0065] Optionally, the power of the RF sputtering is 2000 W to 5000 W. If the power of the RF sputtering is too small, the quality of the first sub-buffer layer 201 will be affected; if the power of the RF sputtering is too large, the substrate 10 may be damaged. When the power of the RF sputtering is within this range, the quality of the first sub-buffer layer 201 can be ensured to be good without affecting the quality of the substrate 10.

[0066] For example, the power of RF sputtering may be 2000W, 3500W, or 5000W, etc.

[0067] Exemplarily, a standard deviation (STD) of the thickness of the first sub-buffer layer 201 is less than 1%.

[0068] Optionally, the thickness of the first sub-buffer layer 201 is 1 nm to 10 nm. If the thickness of the first sub-buffer layer 201 is too small, it is difficult for the first sub-buffer layer 201 to form a good lattice foundation, and the film layer formed subsequently may have a large lattice mismatch, affecting the quality of the film layer; if the thickness of the first sub-buffer layer 201 is too large, it may prolong the time to form the first sub-buffer layer 201, affecting the production efficiency. When the thickness of the first sub-buffer layer 201 is within this range, it can ensure that the first sub-buffer layer 201 forms a good lattice foundation without affecting the production efficiency, which is conducive to improving the quality and production rate of the subsequent film layer.

[0069] By way of example, the thickness of the first sub-buffer layer 201 may be 1 nm, 5 nm, 10 nm, or the like.

[0070] Exemplarily, the refractive index of the first sub-buffer layer 201 is 2.075 to 2.09.

[0071] In step S2003, a second sub-buffer layer is formed on the annealed first sub-buffer layer by using PVD technology to obtain a first buffer layer.

[0072] For example, the annealed first sub-buffer layer 201 and the substrate 10 can be transferred back to the PVD device without being exposed to the atmosphere, and the second sub-buffer layer 202 can be formed on the annealed first sub-buffer layer 201 by sputtering to obtain the first buffer layer 20. In this way, the probability of the first sub-buffer layer 201 and the substrate 10 being contaminated by water and oxygen in the atmosphere can be reduced, thereby ensuring a good quality of the film layer.

[0073] Optionally, the second sub-buffer layer 202 is formed by RF sputtering, which can further ensure the quality of the second sub-buffer layer 202 formed on the first sub-buffer layer 201, ensure the quality of the first buffer layer 20 as a whole, and effectively improve the production rate of the first buffer layer 20.

[0074] Optionally, the thickness of the second sub-buffer layer 202 is greater than the thickness of the first sub-buffer layer 201. Since the first sub-buffer layer 201 has a good crystal quality and can form a good lattice transition, the second sub-buffer layer 202 with a larger thickness is formed after having a good lattice foundation, which can ensure a high production rate of the second sub-buffer layer 202, and the overall crystal quality of the first buffer layer 20 is good, thereby effectively alleviating the lattice mismatch between the substrate 10 and subsequent semiconductor materials in the power semiconductor device.

[0075] Optionally, the thickness of the second sub-buffer layer 202 is 100nm to 500nm. If the thickness of the second sub-buffer layer 202 is too small, the overall thickness of the first buffer layer 20 is too small, and the first buffer layer 20 is difficult to improve the lattice mismatch between the substrate 10 and the subsequent semiconductor material; if the thickness of the second sub-buffer layer 202 is too large, the effect of the first buffer layer 20 in improving the lattice mismatch is limited, which may reduce the production rate and cause a waste of production costs. When the thickness of the second sub-buffer layer 202 is within this range, the overall thickness of the first buffer layer 20 can be larger, and the first buffer layer 20 can better improve the lattice mismatch without causing a waste of production costs.

[0076] By way of example, the thickness of the second sub-buffer layer 202 may be 100 nm, 300 nm, or 500 nm.

[0077] Optionally, the first buffer layer 20 may be an AlN first buffer layer.

[0078] Through the above steps S2002 to S2003 , a first buffer layer 20 can be formed on the substrate 10 .

[0079] In step S2004, a second buffer layer is formed on the first buffer layer by using PVD technology.

[0080] Optionally, the second buffer layer 30 is formed by at least one of direct current sputtering and radio frequency sputtering.

[0081] Exemplarily, the second buffer layer 30 is formed by both direct current sputtering and radio frequency sputtering, which can make the second buffer layer 30 more uniform and compact, and the thickness of the second buffer layer 30 more uniform and the surface more flat, and when the device layer 40 is subsequently formed on the second buffer layer 30, the crystal quality of the device layer 40 can be guaranteed to be better.

[0082] Optionally, when forming the second buffer layer 30, the voltage of DC sputtering is 150V to 300V, the pulse duty cycle is 60%, and the power of RF sputtering is 50W to 500W. In this way, the second buffer layer 30 can be ensured to have better quality and more uniform thickness, and will not damage the first buffer layer 20.

[0083] For example, when forming the second buffer layer 30 , the voltage of DC sputtering may be 150V, 250V, or 300V.

[0084] For example, when forming the second buffer layer 30 , the power of the RF sputtering may be 50 W, 300 W, or 500 W.

[0085] Optionally, the second buffer layer 30 is an AlGaN second buffer layer. The AlGaN second buffer layer can effectively alleviate the accumulation of defects and stress introduced when forming the first buffer layer 20, reduce the probability of defects and stress continuing to extend upward to the subsequent device layer 40, and the AlGaN second buffer layer can also reduce the thermal mismatch stress between the substrate and the device layer 40, thereby effectively improving the crystal quality of the device layer 40 and improving the performance and reliability of the power semiconductor device.

[0086] Exemplarily, when forming the AlGaN second buffer layer, the target material for DC sputtering is Al target, and the target material for RF sputtering is Ga target. This can ensure that the production rate of the AlGaN second buffer layer is higher and the thickness is more uniform, which is conducive to improving the quality of the AlGaN second buffer layer.

[0087] Optionally, the second buffer layer 30 has a thickness of 500 nm to 1500 nm.

[0088] Through the above steps S2002 to S2004 , the first buffer layer 20 and the second buffer layer 30 may be sequentially formed on the substrate 10 by using the PVD technology.

[0089] In step S2005 , a device layer is formed on the second buffer layer by using MOCVD technology.

[0090] Optionally, the power semiconductor device may be a Schottky diode or a high electron mobility transistor (HEMT). In the embodiments of the present disclosure, HEMT is used as an example for illustrative description.

[0091] Optionally, step S2005 may include the following steps:

[0092] In the first step, a channel layer is formed on the second buffer layer by using MOCVD technology.

[0093] Exemplarily, the product obtained in step S2004 can be transferred to a MOCVD reaction chamber without being exposed to the atmosphere to form a channel layer 401 on the second buffer layer 30. For example, the product obtained in step S2004 can be transferred via an interconnection device connecting a PVD device and a MOCVD reaction chamber.

[0094] Optionally, the channel layer 401 includes a GaN channel layer.

[0095] Exemplarily, the thickness of the channel layer 401 is 100 nm to 500 nm.

[0096] In the second step, a barrier layer is formed on the channel layer using MOCVD technology to obtain a device layer.

[0097] Optionally, the barrier layer 402 includes an AlGaN barrier layer. Exemplarily, the Al component content in the AlGaN barrier layer is 0.2 to 0.3.

[0098] Illustratively, the barrier layer 402 has a thickness of 20 nm to 30 nm.

[0099] Through the above-mentioned first step to the second step, the device layer 40 can be formed on the second buffer layer 30 by using the MOCVD technology. Since the first buffer layer 20 and the second buffer layer 30 have good quality and uniform thickness, and the surface of the second buffer layer 30 away from the first buffer layer 20 is flat, the device layer 40 is formed on the second buffer layer 30 by using the MOCVD technology, so that the thickness of the device layer 40 is more uniform, the distribution of each element component is more uniform, and the crystal quality is better, thereby effectively improving the performance and reliability of the power semiconductor device.

[0100] Optionally, an etching process may be used to form a plurality of grooves in the barrier layer 402 for subsequent connection with the drain 50 , the source 51 and the gate 52 .

[0101] In step S2006 , a drain electrode, a source electrode, and a gate electrode are formed on the barrier layer.

[0102] Exemplarily, the drain 50 , the source 51 and the gate 52 are all located in the groove and connected to the barrier layer 402 .

[0103] Exemplarily, the orthographic projection of the gate 52 on the barrier layer 402 is located between the orthographic projection of the drain 50 on the barrier layer 402 and the orthographic projection of the source 51 on the barrier layer 402 .

[0104] Exemplarily, the drain electrode 50 , the source electrode 51 , and the gate electrode 52 each include at least one of a TiN layer, a Ni layer, an Au layer, a Pt layer, a W layer, and a Pd layer.

[0105] Optionally, before forming the drain 50, the source 51 and the gate 52, a passivation layer may be formed on the barrier layer 402. When the passivation layer is provided, the passivation layer and the barrier layer 402 have a first groove and a second groove, and the first groove and the second groove both penetrate the passivation layer and extend below the interface between the passivation layer and the barrier layer 402.

[0106] Exemplarily, the passivation layer includes at least one of a SiO 2 layer, a SiN layer, a GaN layer, and an AlN layer.

[0107] Exemplarily, when a passivation layer is provided, the drain 50 , the source 51 and the gate 52 are located on the surface of the passivation layer away from the barrier layer 402 , the drain 50 is connected to the barrier layer 402 through a first groove, and the source 51 is connected to the barrier layer 402 through a second groove.

[0108] Optionally, various performance parameters of the power semiconductor device may be tested after the preparation is completed, for example, resistance, capacitance, current and voltage testing.

[0109] The present disclosure also provides a power semiconductor device, such as Figure 3 As shown, the power semiconductor device comprises a substrate 10, a first buffer layer 20, a second buffer layer 30 and a device layer 40 which are stacked in sequence. The first buffer layer 20 and the second buffer layer 30 are formed by PVD technology, and the device layer 40 is formed by MOCVD technology.

[0110] The beneficial effects of the embodiments of the present disclosure are the same as those of the preparation method embodiments and will not be described in detail here.

[0111] Optionally, the surface roughness Ra of the substrate 10 is 0.2 nm to 0.5 nm.

[0112] Optionally, the first buffer layer 20 includes a first sub-buffer layer 201 and a second sub-buffer layer 202 which are sequentially stacked in a direction away from the substrate 10 .

[0113] Optionally, the device layer 40 includes a channel layer 401 and a barrier layer 402 which are sequentially stacked in a direction away from the second buffer layer 30 .

[0114] Optionally, the power semiconductor device further includes a drain 50 , a source 51 and a gate 52 . The barrier layer 402 has a plurality of grooves for connecting with the drain 50 , the source 51 and the gate 52 .

[0115] Exemplarily, the drain 50 , the source 51 and the gate 52 are all located in the groove and connected to the barrier layer 402 .

[0116] Optionally, the material and thickness of each layer can be found in Figures 1 to 3 The detailed description of the relevant preparation method embodiments is omitted here.

[0117] The following is an exemplary description of the leakage current and dynamic resistivity of the power semiconductor device prepared by the preparation method provided by the embodiment of the present disclosure. Figure 3 The power semiconductor device in the related embodiment adopts Figure 2 The control group refers to the power semiconductor device in the related technology. The difference between the control group and the experimental group is that the preparation methods of the first buffer layer and the second buffer layer are different. The first buffer layer and the second buffer layer of the control group are both formed by MOCVD technology.

[0118] Figure 4 It is a schematic diagram of a curve of drain leakage current of a power semiconductor device provided by an embodiment of the present disclosure. Figure 4 Part (a) shows the drain leakage current of the experimental group. Figure 4 Part (b) in the figure shows the drain leakage current of the control group. A turn-off voltage of -15V was applied to the gates of the experimental group and the control group, and the drain leakage current of the experimental group and the control group was tested in the range of drain voltage from 0V to 200V.

[0119] like Figure 4 As shown in part (a) of the graph, the drain current of the experimental group varies from about 5.25E-09A to 9.25E-09A. Figure 4 As shown in part (b), the drain leakage current of the control group varies from about 1.20E-06A to 2.35E-06A. That is, under the same conditions, the drain leakage current of the experimental group is about 3 orders of magnitude lower than that of the control group.

[0120] Figure 5 It is a schematic diagram of a curve of gate leakage current of a power semiconductor device provided by an embodiment of the present disclosure. Figure 5 Part (a) shows the gate leakage current of the experimental group. Figure 5Part (b) in the figure shows the gate leakage current of the control group. A turn-off voltage of -15V was applied to the gates of the experimental group and the control group, and the gate leakage current of the experimental group and the control group was tested in the range of drain voltage from 0V to 200V.

[0121] like Figure 5 As shown in part (a) of the graph, the gate leakage current of the experimental group varies from about -2.35E-10A to -1.20E-10A. Figure 5 As shown in part (b), the gate leakage current of the control group varies from about -7.25E-06A to -5.40E-06A. That is, under the same conditions, the gate leakage current of the experimental group is about 4 orders of magnitude lower than that of the control group.

[0122] Figure 6 1 is a schematic diagram for comparing the dynamic resistivity of a power semiconductor device provided by an embodiment of the present disclosure. Two control groups, namely control group 1 and control group 2, are used to test the dynamic resistivity of the experimental group and the two control groups respectively. Figure 6 As shown, the dynamic resistivity of the experimental group is 1.16Ω·m, the dynamic resistivity of the control group 1 is 1.28Ω·m, and the dynamic resistivity of the control group 2 is 1.41Ω·m. That is, the dynamic resistivity of the experimental group is lower than that of the two control groups.

[0123] The above tests show that the power semiconductor device prepared by the preparation method provided by the embodiment of the present disclosure has lower drain leakage current, gate leakage current and dynamic resistivity than the control group, thereby improving the performance and reliability of the power semiconductor device.

[0124] The above description does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not used to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure still falls within the scope of the technical solution of the present disclosure.

Claims

1. A method for preparing a power semiconductor device, characterized in that: include: Providing a substrate (10); Using physical vapor deposition technology to sequentially form a first buffer layer (20) and a second buffer layer (30) on the substrate (10); A device layer (40) is formed on the second buffer layer (30) by using a metal organic compound chemical vapor deposition technique.

2. The preparation method according to claim 1, characterized in that: The first buffer layer (20) is formed in the following manner: Forming a first sub-buffer layer (201) on the substrate (10) using a physical vapor deposition technique, and annealing the first sub-buffer layer (201); A second sub-buffer layer (202) is formed on the annealed first sub-buffer layer (201) using a physical vapor deposition technique to obtain the first buffer layer (20).

3. The preparation method according to claim 2, characterized in that: When the first sub-buffer layer (201) is annealed, the annealing duration is 20 minutes to 80 minutes.

4. The preparation method according to claim 2, characterized in that: The thickness of the second sub-buffer layer (202) is greater than the thickness of the first sub-buffer layer (201).

5. The preparation method according to claim 4, characterized in that: The thickness of the first sub-buffer layer (201) is 1 nm to 10 nm, and the thickness of the second sub-buffer layer (202) is 100 nm to 500 nm.

6. The preparation method according to claim 2, characterized in that: The first sub-buffer layer (201) and the second sub-buffer layer (202) are both formed by radio frequency sputtering, and the power of the radio frequency sputtering is 2000W to 5000W.

7. The preparation method according to any one of claims 1 to 6, characterized in that: The second buffer layer (30) is formed by both direct current sputtering and radio frequency sputtering, the voltage of the direct current sputtering is 150V to 300V, and the power of the radio frequency sputtering is 50W to 500W.

8. The preparation method according to any one of claims 1 to 6, characterized in that: The method further comprises: Before forming the first buffer layer (20), placing the substrate (10) in a physical vapor deposition device, introducing Ar and H2, and performing a first plasma treatment on the substrate (10); N2 is introduced to perform a second plasma treatment on the substrate (10).

9. The preparation method according to claim 8, characterized in that: The duration of the first plasma treatment is 200 s to 400 s, and the duration of the second plasma treatment is 100 s to 300 s.

10. A power semiconductor device, characterized in that: It comprises a substrate (10), a first buffer layer (20), a second buffer layer (30) and a device layer (40) which are stacked in sequence. Wherein, the first buffer layer (20) and the second buffer layer (30) are formed by physical vapor deposition technology; The device layer (40) is formed by adopting metal organic compound chemical vapor deposition technology.

Images