Nitride semiconductor device and method for manufacturing nitride semiconductor device

Abstract

The present disclosure relates to a nitride semiconductor device and a method of manufacturing the same. The present disclosure stabilizes the electrical characteristics of the 2DEG. A nitride semiconductor device according to the present disclosure includes an electron transition layer, an electron supply layer, a gate layer formed on the electron supply layer, a gate electrode formed on the gate layer, and a passivation layer having a source opening and a drain opening. The electron migration layer includes a first portion below the gate layer. And a second portion between the gate layer and the source opening and between the gate layer and the drain opening. The electron supply layer includes: a first electron supply layer formed on the first portion and under the gate layer; and a second electron supply layer formed on the second portion and connected to the first electron supply layer.

Description

Technical Field

[0001] The present disclosure relates to a nitride semiconductor device and a method for manufacturing the nitride semiconductor device. Background Art

[0002] Currently, the commercialization of high electron mobility transistors (HEMTs) using group III nitride semiconductors such as gallium nitride (GaN) (hereinafter sometimes referred to as "nitride semiconductors") is being promoted. In HEMTs, a two-dimensional electron gas (2DEG) formed near the semiconductor heterojunction interface is used as a conductive path (channel). Power devices using HEMTs are considered to have lower on-resistance than typical silicon (Si) power devices and are capable of high-speed and high-frequency operation.

[0003] For example, the nitride semiconductor device described in Patent Document 1 includes an electron transition layer composed of a gallium nitride (GaN) layer and an electron supply layer composed of an aluminum gallium nitride (AlGaN) layer. 2DEG is formed in the electron transition layer near the heterojunction interface between the electron transition layer and the electron supply layer.

[0004] In addition, in the nitride semiconductor device of Patent Document 1, a gate layer (e.g., a p-type GaN layer) containing acceptor-type impurities is provided on the electron supply layer, and a gate electrode is arranged on the gate layer. In this configuration, in the region directly below the gate layer, the band energy of the conduction band near the heterojunction interface between the electron transition layer and the electron supply layer is increased by the gate layer, thereby making the channel directly below the gate layer disappear, thereby achieving normally off.

[0005] [Background Technology Literature]

[0006] [Patent Document]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 2017-73506 Summary of the invention

[0008] [summary]

[0009] In the nitride semiconductor device, the gate layer is formed as a remaining portion after a portion of the nitride semiconductor layer formed on the electron supply layer is selectively removed by etching. At this time, in the portion where the gate layer is not formed, the nitride semiconductor layer is etched until the electron supply layer is exposed. At this time, etching damage occurs in the electron supply layer located in this portion. The etching damage generated in the electron supply layer becomes a major cause of changes in the electrical characteristics of the 2DEG generated in the electron transition layer.

[0010] A nitride semiconductor device as one embodiment of the present disclosure includes: an electron transition layer composed of a nitride semiconductor; an electron supply layer formed on the electron transition layer and composed of a nitride semiconductor having a larger band gap than the electron transition layer; a gate layer formed on a portion of the electron supply layer and composed of a nitride semiconductor containing an acceptor-type impurity; a gate electrode formed on the gate layer; a passivation layer covering the electron supply layer, the gate layer, and the gate electrode and having a source opening and a drain opening separated from each other via the gate layer; layer; a source electrode connected to the electron supply layer via the source opening; a drain electrode connected to the electron supply layer via the drain opening; and the electron transition layer includes: a first portion located under the gate layer; and a second portion located between the gate layer and the source opening, and between the gate layer and the drain opening in a top view; the electron supply layer includes: a first electron supply layer formed on the first portion and located under the gate layer; and a second electron supply layer formed on the second portion and connected to the first electron supply layer.

[0011] A method for manufacturing a nitride semiconductor device as one embodiment of the present disclosure includes the following steps: forming an initially formed electron supply layer on an electron transition layer composed of a nitride semiconductor; forming a gate layer composed of a nitride semiconductor containing acceptor-type impurities on the initially formed electron supply layer; removing a portion of the initially formed electron supply layer by etching so that a portion located under the gate layer is retained and the electron transition layer is exposed, thereby forming a first electron transition layer as a retained portion of the initially formed electron supply layer; forming a reformed electron supply layer connected to the first electron supply layer on the electron transition layer exposed by the etching; forming a passivation layer on the reformed electron supply layer; forming a gate electrode on the gate layer; and forming a source electrode and a drain electrode on the reformed electron supply layer; and the initially formed electron supply layer and the reformed electron supply layer are composed of a nitride semiconductor having a larger band gap than the electron transition layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic top view of an exemplary nitride semiconductor device in an embodiment.

[0013] Figure 2 yes Figure 1 2-2 line cross-sectional view.

[0014] Figure 3 It is an enlarged cross-sectional view showing the structure of the periphery of the gate layer as an example.

[0015] Figure 4 It is a schematic cross-sectional view showing an exemplary manufacturing step of the nitride semiconductor device in the embodiment.

[0016] Figure 5 It means next Figure 4 A schematic cross-sectional view of a manufacturing step subsequent to the step shown.

[0017] Figure 6 It means next Figure 5 A schematic cross-sectional view of a manufacturing step subsequent to the step shown.

[0018] Figure 7 It means next Figure 6 A schematic cross-sectional view of a manufacturing step subsequent to the step shown.

[0019] Figure 8 It means next Figure 7 A schematic cross-sectional view of a manufacturing step subsequent to the step shown.

[0020] Fig. 9 It means next Figure 8 A schematic cross-sectional view of a manufacturing step subsequent to the step shown.

[0021] Fig.10 It means next Fig. 9 Schematic cross-sectional view of a manufacturing step following the step shown.

[0022] Fig.11 It means next Fig.10 A schematic cross-sectional view of a manufacturing step subsequent to the step shown.

[0023] Fig.12 It means next Fig.11 Schematic cross-sectional view of a manufacturing step following the step shown.

[0024] Fig.13 It means next Fig.12 A schematic cross-sectional view of a manufacturing step subsequent to the step shown.

[0025] Fig.14 It means next Fig.13 A schematic cross-sectional view of a manufacturing step subsequent to the step shown.

[0026] Fig.15 It means next Fig.14 A schematic cross-sectional view of a manufacturing step subsequent to the step shown.

[0027] Fig.16 It is an enlarged cross-sectional view showing the structure of the periphery of the gate layer according to a modification.

[0028] Fig.17It is an enlarged cross-sectional view showing the structure of the periphery of the gate layer according to a modification.

[0029] Fig.18 It is an enlarged cross-sectional view showing the structure of the periphery of the gate layer according to a modification. DETAILED DESCRIPTION

[0030] [Details]

[0031] Hereinafter, embodiments of the nitride semiconductor device in the present disclosure will be described with reference to the drawings.

[0032] In addition, in order to make the description simple and clear, the components shown in the drawings are not necessarily drawn to a certain scale. In addition, for ease of understanding, hatching is sometimes omitted in the cross-sectional view. The drawings only illustrate the embodiments of the present disclosure and should not be regarded as limiting the present disclosure.

[0033] The following detailed description includes devices, systems, and methods that embody exemplary embodiments of the present disclosure. The detailed description is intended to be illustrative only and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0034] [Schematic Structure of Nitride Semiconductor Device]

[0035] Figure 1 It is a schematic plan view of an exemplary nitride semiconductor device 10 in the embodiment. Figure 2 is a schematic cross-sectional view of the nitride semiconductor device 10. Figure 1 2-2 line cross-sectional view. In addition, Figure 1 and Figure 2 In the nitride semiconductor device 10 shown in , for convenience of description, the +Z direction is defined as the top, the -Z direction is defined as the bottom, the +X direction is defined as the right, and the -X direction is defined as the left. Unless otherwise specified, "top view" means observing the nitride semiconductor device 10 from above along the Z axis. In addition, unless otherwise specified, the thickness refers to the dimension along the Z direction.

[0036] In one example, the nitride semiconductor device 10 may be a HEMT using GaN. Figure 2 After describing the cross-sectional structure of the nitride semiconductor device 10, refer to Figure 1 , the planar structure of the nitride semiconductor device 10 is described.

[0037] like Figure 2As shown, the nitride semiconductor device 10 can be configured as a high electron mobility transistor (HEMT) using a nitride semiconductor. The nitride semiconductor device 10 includes: a substrate 12, a buffer layer 14 formed on the substrate 12, an electron transition layer 16 formed on the buffer layer 14, and an electron supply layer 18 formed on the electron transition layer 16. Further, the nitride semiconductor device 10 includes a gate layer 22 formed on a portion of the electron supply layer 18 via the electron supply layer 18, and a gate electrode 24 formed on the gate layer 22.

[0038] The substrate 12 may be formed of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate materials. The substrate 12 is, for example, a Si substrate. The thickness of the substrate 12 is, for example, not less than 200 μm and not more than 1500 μm. Figure 1 and Figure 2 The Z direction of the mutually orthogonal XYZ axes shown in is the thickness direction of the substrate 12 , and may also be referred to as the thickness direction of the electron supply layer 18 .

[0039] The buffer layer 14 is formed on the substrate upper surface 12A of the substrate 12. The buffer layer 14 can be located between the substrate 12 and the electron transition layer 16. In one example, the buffer layer 14 can be composed of any material that can facilitate epitaxial growth of the electron transition layer 16. The buffer layer 14 can include one or more nitride semiconductor layers.

[0040] The buffer layer 14 can include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 14 can include a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure. In addition, in order to suppress leakage current in the buffer layer 14, impurities can be introduced into a portion of the buffer layer 14 to make the buffer layer 14 semi-insulating. In this case, the impurity is, for example, carbon (C) or iron (Fe), and the concentration of the impurity is, for example, 4×10 16 cm -3 above.

[0041] The electron transit layer 16 is, for example, a GaN layer. The thickness of the electron transit layer 16 is, for example, not less than 0.5 μm and not more than 2 μm. In addition, in order to suppress leakage current in the electron transit layer 16, impurities may be introduced into a portion of the electron transit layer 16 so that the electron transit layer 16 includes a semi-insulating region in addition to the surface region. In this case, the impurity is, for example, C, and the peak concentration of the impurity in the electron transit layer 16 is, for example, 1×10 19 cm -3 above.

[0042] In one example, the electron transition layer 16 includes a first semiconductor layer formed on the buffer layer 14, a second semiconductor layer formed on the first semiconductor layer, and a third semiconductor layer formed on the second semiconductor layer. The first semiconductor layer can be said to be formed above the substrate 12, or it can be said to be formed on the substrate 12. The third semiconductor layer is in contact with the electron supply layer 18. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are GaN layers with different impurity concentrations. The first semiconductor layer and the third semiconductor layer are undoped GaN layers, and the second semiconductor layer is a C-doped GaN layer containing C as an impurity.

[0043] The electron supply layer 18 is composed of a nitride semiconductor having a larger band gap than the electron transit layer 16. The electron supply layer 18 is, for example, an AlGaN layer. In this case, since the greater the Al content, the larger the band gap, the electron supply layer 18 as an AlGaN layer has a larger band gap than the electron transit layer 16 as a GaN layer. In one example, the electron supply layer 18 is composed of Al x Ga 1-x N, and x is 0.1<x<0.4, and more preferably 0.2<x<0.3. The thickness of the electron supply layer 18 is, for example, 5 nm to 20 nm.

[0044] The electron transit layer 16 and the electron supply layer 18 are composed of nitride semiconductors having different lattice constants. Therefore, the nitride semiconductor (e.g., GaN) constituting the electron transit layer 16 and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 18 form a lattice mismatched heterojunction. Due to the spontaneous polarization of the electron transit layer 16 and the electron supply layer 18 and the piezoelectric polarization caused by the stress on the electron supply layer 18 near the heterojunction interface, the energy level of the conduction band of the electron transit layer 16 near the heterojunction interface is lower than the Fermi level. In this way, at a position close to the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 (e.g., within a range of about several nanometers from the interface), a two-dimensional electron gas (2DEG) 20 diffuses in the electron transit layer 16.

[0045] The electron supply layer 18 includes a first electron supply layer 51 and a second electron supply layer 52. Details of the first electron supply layer 51 and the second electron supply layer 52 will be described later.

[0046] The nitride semiconductor device 10 further includes: a gate layer 22 formed on a portion of the electron supply layer 18 (on the electron supply layer 18 sandwiching the first electron supply layer 51 described later), a gate electrode 24 formed on the gate layer 22, and a passivation layer 26. The passivation layer 26 is formed on the electron supply layer 18, the gate layer 22, and the gate electrode 24, and includes a source opening 26A and a drain opening 26B. In addition, the nitride semiconductor device 10 further includes a source electrode 28 connected to the electron supply layer 18 via the source opening 26A, and a drain electrode 30 connected to the electron supply layer 18 via the drain opening 26B.

[0047] The gate layer 22 is located between the source opening 26A and the drain opening 26B of the passivation layer 26 and is away from the source opening 26A and the drain opening 26B respectively. The gate layer 22 is located closer to the source opening 26A than to the drain opening 26B.

[0048] The gate layer 22 is composed of a nitride semiconductor having a smaller band gap than the electron supply layer 18 and containing an acceptor-type impurity. The gate layer 22 can be composed of any material having a smaller band gap than the electron supply layer 18, which is an AlGaN layer. The gate layer 22 is, for example, a GaN layer doped with an acceptor-type impurity (p-type GaN layer). The acceptor-type impurity can contain at least one of zinc (Zn), magnesium (Mg), and C. The maximum concentration of the acceptor-type impurity in the gate layer 22 is, for example, 1×10 18 cm -3 Above 1×10 20 cm -3 the following.

[0049] As described above, since the gate layer 22 contains acceptor-type impurities, the energy levels of the electron transition layer 16 and the electron supply layer 18 can be raised. Therefore, in the region directly below the gate layer 22, the energy level of the conduction band of the electron transition layer 16 near the heterojunction interface between the electron transition layer 16 and the electron supply layer 18 is almost the same as the Fermi level, or is larger than the Fermi level. Therefore, when a zero bias voltage is not applied to the gate electrode 24, the 2DEG 20 is not formed in the electron transition layer 16 in the region directly below the gate layer 22. On the other hand, the 2DEG 20 is formed in the electron transition layer 16 in the region other than the region directly below the gate layer 22.

[0050] In this way, the 2DEG 20 in the region directly below the gate layer 22 is dissipated due to the presence of the gate layer 22 doped with acceptor-type impurities. As a result, the normally-off operation of the transistor is realized. If a suitable on-voltage is applied to the gate electrode 24, a channel generated by the 2DEG 20 is formed in the electron transition layer 16 in the region directly below the gate electrode 24, so that the source and drain are conductive.

[0051] The gate electrode 24 is composed of one or more metal layers. The gate electrode 24 is, for example, a titanium nitride (TiN) layer. Alternatively, the gate electrode 24 may also be composed of the following layers: a first metal layer formed of a material containing Ti; and a second metal layer formed of a material containing TiN, laminated on the first metal layer. The thickness of the gate electrode 24 is, for example, not less than 50 nm and not more than 200 nm.

[0052] The passivation layer 26 is formed on the electron supply layer 18. The passivation layer 26 can also be said to cover the electron supply layer 18. The passivation layer 26 can be composed of a material including any one of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), AlN, and aluminum oxynitride (AlON).

[0053] The thickness of the passivation layer 26 is thicker than the thickness of the electron supply layer 18. The thickness of the passivation layer 26 is, for example, 300 nm or more and 1000 nm or less. In addition, the thickness of the passivation layer 26 can be arbitrarily changed. The passivation layer 26 includes a first passivation layer 61 and a second passivation layer 62. The detailed structure of the first passivation layer 61 and the second passivation layer 62 will be described later.

[0054] The source electrode 28 and the drain electrode 30 are arranged on the upper surface of the electron supply layer 18 with the gate layer 22 interposed therebetween. Hereinafter, the direction (X direction) in which the source electrode 28 and the drain electrode 30 are arranged with the gate layer 22 interposed therebetween in a plan view is sometimes referred to as the first direction. In addition, the first direction can also be said to be the direction in which the source opening 26A and the drain opening 26B in the passivation layer 26 are arranged with the gate layer 22 interposed therebetween.

[0055] The source electrode 28 and the drain electrode 30 can be composed of one or more metal layers. For example, the source electrode 28 and the drain electrode 30 can be composed of a combination of two or more metal layers, and the two or more metal layers are selected from a group including a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. At least a portion of the source electrode 28 is filled in the source opening 26A, and ohmically contacts the 2DEG 20 directly below the electron supply layer 18 through the source opening 26A. Similarly, at least a portion of the drain electrode 30 is filled in the drain opening 26B, and ohmically contacts the 2DEG 20 directly below the electron supply layer 18 through the drain opening 26B.

[0056] The source electrode 28 includes, for example, a source contact portion 28A filled in the source opening portion 26A, and a source field plate portion 28B formed on the passivation layer 26. The source field plate portion 28B is continuous with the source contact portion 28A and is formed integrally with the source contact portion 28A. The source field plate portion 28B includes an end portion 28C located between the drain opening portion 26B and the gate layer 22 in a plan view. The source field plate portion 28B is away from the drain electrode 30. The source field plate portion 28B plays the role of alleviating the electric field concentration near the end of the gate electrode 24 and the end of the gate layer 22 when the drain voltage is applied to the drain electrode 30 in a zero bias state where the gate voltage is not applied to the gate electrode 24.

[0057] [Detailed structure of electron transfer layer, electron supply layer, gate layer, and passivation layer]

[0058] refer to Figure 2 and Figure 3 , the detailed structures of the electron transition layer, the electron supply layer, the gate layer, and the passivation layer 26 are described.

[0059] like Figure 2 As shown, the electron transition layer 16 includes a first portion 41, a second portion 42, and a third portion 43. The first portion 41 is a portion of the electron transition layer 16 located below the gate layer 22. The second portion 42 is a portion of the electron transition layer 16 located between the gate layer 22 and the source opening 26A, and between the gate layer 22 and the drain opening 26B in a plan view. The third portion 43 is a portion located below the source opening 26A and below the drain opening 26B.

[0060] The first portion 41 has a protruding portion 44 that protrudes upward further than the second portion 42. The protruding portion 44 includes an upper surface 44A and a side surface 44B connected to the upper surface 44A. The upper surface 44A of the protruding portion 44 is located at a position higher than the upper surface 42A of the second portion 42, and is formed into a plane parallel to the upper surface 42A. The protruding portion 44 of the present embodiment is formed on the entire first portion 41 in a plan view. Therefore, it can also be said that the first portion 41 protrudes upward further than the second portion 42. In this case, the upper surface 41A of the protruding portion 44 and the upper surface 41A of the first portion 41 have the same meaning.

[0061] Figure 3 yes Figure 2 An enlarged view of the peripheral area (range A) of the gate layer 22 in FIG. Figure 3 , details of the protruding portion 44 will be described.

[0062] The protrusion height H1 of the protrusion 44 is, for example, 1 nm or more, preferably 2 nm or more. In addition, the protrusion height H1 of the protrusion 44 is, for example, 10 nm or less, preferably 5 nm or less. In addition, the protrusion height H1 of the protrusion 44 is the difference between the position of the upper surface 44A of the protrusion 44 (the upper surface 41A of the first part 41) and the position of the upper surface 42A of the second part 42 in the thickness direction.

[0063] The width W1 of the protruding portion 44 is, for example, not less than 630 nm and not more than 750 nm. The width W1 of the protruding portion 44 is the length of the protruding portion 44 in the first direction. The protruding portion 44 may be a rectangular cross-sectional shape with a constant width, or may be a cross-sectional shape with a partially or entirely variable width. In the case where the protruding portion 44 is a cross-sectional shape with a variable width, for example, the average value of the width of the protruding portion 44 is taken as the width W1.

[0064] The width W1 of the protruding portion 44 is, for example, shorter than the width W2 of the gate layer 22 formed on the protruding portion 44. The width W2 of the gate layer 22 is, for example, not less than 640 nm and not more than 760 nm. The difference (W2-W1) between the width W2 of the gate layer 22 and the width W1 of the protruding portion 44 is, for example, not less than 1 nm and not more than 10 nm. In addition, the width W1 of the protruding portion 44 may be the same as the width W2 of the gate layer 22.

[0065] Figure 3 The protrusion 44 shown as an example has a shape in which the width in the first direction gradually increases as it approaches the top, or a shape in which the width in the first direction gradually decreases. The side surface 44B of the protrusion 44 is an inclined surface or a curved surface that intersects the thickness direction. The width of the protrusion 44 in the entire thickness direction is shorter than the width W2 of the gate layer 22. Figure 3 In the example shown, the side surface 44B is a plane in the shape of an inclined surface, the width of the protruding portion 44 in the first direction gradually increases as it approaches upward. The side surface 44B may also be a plane in the shape of an inclined surface, the width of the protruding portion 44 in the first direction gradually decreases as it approaches upward. In addition, the side surface 44B may be a curved surface in the shape of an inverted cone, the width of the protruding portion 44 in the first direction gradually increases as it approaches upward, or may be a curved surface in the shape of a positive cone, the width of the protruding portion 44 in the first direction gradually decreases as it approaches upward. In addition, Figure 3 In order to facilitate understanding of the shape of the side surface 44B of the protruding portion 44 , the shape is exaggeratedly illustrated so as to be greatly recessed in the first direction.

[0066] like Figure 2As shown, the electron supply layer 18 includes a first electron supply layer 51, a second electron supply layer 52, and a third electron supply layer 53. The first electron supply layer 51 is formed on the upper surface 41A of the first portion 41 in the electron transition layer 16 (the upper surface 44A of the protruding portion 44), and is located below the gate layer 22. The second electron supply layer 52 is formed on the second portion 42 in the electron transition layer 16, and is connected to the first electron supply layer 51. The third electron supply layer 53 is formed on the third portion 43 in the electron transition layer 16, and is located below the source opening 26A and below the drain opening 26B, and is connected to the second electron supply layer 52.

[0067] like Figure 3 As shown, the thickness T1 of the first electron supply layer 51 is, for example, not less than 5 nm and not more than 20 nm. The thickness T2 of the second electron supply layer 52 is, for example, not less than 5 nm and not more than 20 nm.

[0068] The material constituting the second electron supply layer 52 is, for example, the same as the material constituting the first electron supply layer 51. In addition, the material constituting the second electron supply layer 52 may be different from the material constituting the first electron supply layer 51. In one example, the first electron supply layer 51 is an AlGaN layer, and the second electron supply layer 52 is an AlGaN layer having a smaller Al composition than the first electron supply layer 51. In this case, the gate threshold voltage can be increased. Therefore, since the gate threshold voltage is increased, it is possible to suppress the gate leakage current. In addition, in another example, the first electron supply layer 51 is an AlGaN layer, and the second electron supply layer 52 is an AlGaN layer having a larger Al composition than the first electron supply layer 51. In this case, the amount of 2DEG20 formed between the gate-source and the gate-drain increases, so it is possible to reduce the on-resistance.

[0069] The thickness T2 of the second electron supply layer 52 is, for example, the same as the thickness T1 of the first electron supply layer 51. In addition, the thickness T2 of the second electron supply layer 52 may be thicker than the thickness T1. In this case, the amount of 2DEG 20 formed between the gate-source and the gate-drain increases, so that the on-resistance can be reduced. In addition, the thickness T2 of the second electron supply layer 52 may be thinner than the thickness T1.

[0070] Figure 3The thickness T2 of the second electron supply layer 52 shown is, for example, the same as or thinner than the protrusion height H1 of the protrusion 44 in the electron transition layer 16. In other words, in the thickness direction, the upper surface 52A of the second electron supply layer 52 is located at the same position as the upper surface 44A of the protrusion 44, or is located below the upper surface 44A of the protrusion 44. In this case, the second electron supply layer 52 includes a connecting portion 52B formed to be locally thick along the side surface 44B of the protrusion 44, and the connecting portion 52B is connected to the first electron supply layer 51.

[0071] Furthermore, the thickness T2 of the second electron supply layer 52 may be greater than the protrusion height H1 of the protrusion 44 in the electron transition layer 16. In other words, in the thickness direction, the upper surface 52A of the second electron supply layer 52 may be located above the upper surface 44A of the protrusion 44. In this case, since the second electron supply layer 52 does not require the connection portion 52B, it is easy to manufacture.

[0072] The material constituting the third electron supply layer 53 is, for example, the same as the material constituting the second electron supply layer 52. The thickness (not shown) of the third electron supply layer 53 is, for example, 5 nm to 20 nm. The thickness of the third electron supply layer 53 is, for example, the same as the thickness T2 of the second electron supply layer 52.

[0073] like Figure 2 As shown, the electron supply layer 18 further includes a covering portion 54 that covers the upper surface 22A and the side surface 22B of the gate layer 22 and is connected to the second electron supply layer 52. Figure 3 As shown, the covering portion 54 includes an upper portion 54A covering the upper surface 22A of the gate layer 22, and a side portion 54B covering the side surface 22B of the gate layer 22. The upper portion 54A of the covering portion 54 is sandwiched between the gate layer 22 and the gate electrode 24. The gate electrode 24 is connected to the gate layer 22 via the upper portion 54A of the covering portion 54. The covering portion 54 is connected to the second electron supply layer 52 at the lower end portion of the side portion 54B. The upper portion 54A of the covering portion 54 located between the gate layer 22 and the gate electrode 24 plays a role in improving the Schottky barrier between the gate layer 22 and the gate electrode 24.

[0074] The material constituting the coating portion 54 is, for example, the same as the material constituting the second electron supply layer 52. The thickness T3 of the coating portion 54 is, for example, not less than 5 nm and not more than 20 nm. The thickness T3 of the coating portion 54 is, for example, the same as the thickness T2 of the second electron supply layer 52. In one example, the thickness T3 of the coating portion 54 is thicker than the thickness T1 of the first electron supply layer 51. In this case, the Schottky barrier between the gate layer 22 and the gate electrode 24 can be further increased. In addition, the thickness T3 of the coating portion 54 may be the same as the thickness T1, or may be thinner than the thickness T1.

[0075] Here, in the electron supply layer 18, the first electron supply layer 51 and the second electron supply layer 52 are layers formed at different time points. Specifically, the first electron supply layer 51 is a layer formed earlier than the gate layer 22 (hereinafter, described as the initially formed electron supply layer), and the second electron supply layer 52 is a layer formed later than the gate layer 22 (hereinafter, described as the re-formed electron supply layer). In this figure, the portion composed of the initially formed electron supply layer is indicated by a darker dotted hatching, and the portion composed of the re-formed electron supply layer is indicated by a lighter dotted hatching.

[0076] like Figure 3 As shown, in an example of the electron supply layer 18, an interface 18A is provided between the first electron supply layer 51 as the initially formed electron supply layer and the second electron supply layer 52 as the reformed electron supply layer. The interface 18A is formed at the end surface of the first electron supply layer 51 in the first direction. In addition to being formed at the end surface, the interface 18A may also be formed at the lower surface of the end of the first electron supply layer 51 in the first direction. In addition, the electron supply layer 18 may also be configured not to have the interface 18A. For example, when the materials constituting the first electron supply layer 51 and the second electron supply layer 52 are the same, there is a case where the interface 18A is not formed.

[0077] The third electron supply layer 53 and the covering portion 54 are composed of reformed electron supply layers. That is, the second electron supply layer 52, the third electron supply layer 53, and the covering portion 54 are continuous reformed electron supply layers formed at the same time.

[0078] like Figure 2 As shown, the passivation layer 26 includes a first passivation layer 61 and a second passivation layer 62. The first passivation layer 61 is formed on the second electron supply layer 52 and the gate layer 22. The first passivation layer 61 can also be said to cover the second electron supply layer 52 and the gate layer 22.

[0079] The first passivation layer 61 includes a gate opening 61A formed in a portion located on the gate layer 22. At least a portion of the gate electrode 24 is filled in the gate opening 61A, and is in contact with the electron supply layer 18 (the upper portion 54A of the covering portion 54) via the gate opening 61A. The first passivation layer 61 is a layer for protecting the second electron supply layer 52 from etching damage during etching performed when forming the gate electrode 24.

[0080] The second passivation layer 62 is formed on the first passivation layer 61 and the gate electrode 24 . It can be said that the second passivation layer 62 covers the first passivation layer 61 and the gate electrode 24 . The source field plate portion 28B of the source electrode 28 is formed on the second passivation layer 62 .

[0081] The material constituting the first passivation layer 61 and the material constituting the second passivation layer 62 may be the same or different. In one example, the first passivation layer 61 is a layer having a relatively high density structure, and the second passivation layer 62 is a layer having a relatively low density structure. Since the first passivation layer 61 and the second passivation layer 62 are provided as the passivation layer 26, the second passivation layer 62 which is not in contact with the electron supply layer 18 adopts a layer having a low density structure, and the manufacturing process can be simplified.

[0082] The thickness of the first passivation layer 61 is, for example, not less than 95 nm and not more than 105 nm. The thickness of the second passivation layer 62 is, for example, not less than 95 nm and not more than 105 nm. The thickness of the second passivation layer 62 is, for example, thicker than the first passivation layer 61. In addition, the thickness of the second passivation layer 62 may be the same as that of the first passivation layer 61, or may be thinner than the first passivation layer 61. In addition, in the passivation layer 26, an interface (not shown) may be provided between the first passivation layer 61 and the second passivation layer 62.

[0083] [Planar Structure of Nitride Semiconductor Device]

[0084] Next, refer to Figure 1 , the planar structure of the nitride semiconductor device 10 is described. Figure 1 In FIG. 2 , the passivation layer 26 and the source electrode 28 are omitted from illustration, and the source opening 26A, the drain opening 26B, and the gate opening 61A of the passivation layer 26 and the end 28C of the source electrode 28 are depicted by dotted lines.

[0085] The nitride semiconductor device 10 includes, for example, an active region that contributes to transistor operation and an inactive region (not shown) that does not contribute to transistor operation. In one example, the active region and the inactive region are alternately arranged in the Y direction.

[0086] In the active region of the semiconductor device 10, the source electrode 28 (refer to Figure 2 ), the gate electrode 24, and the drain electrode 30 are formed on the electron supply layer 18 (reference Figure 2 ), and are arranged adjacent to each other in the first direction (X direction). The combination of the source electrode 28, the gate electrode 24, and the drain electrode 30 adjacent to each other in the first direction constitutes one HEMT unit HC. Figure 1 In the example of FIG. 1 , two HEMT cells HC are arranged in the X direction in the active region. In fact, more HEMT cells HC can be arranged in each active region.

[0087] [Method for manufacturing nitride semiconductor device]

[0088] refer to Figures 4 to 15, an exemplary method for manufacturing the nitride semiconductor device 10 is described. In addition, Figures 4 to 15 In, for and Figure 2 The same components are denoted by the same reference numerals.

[0089] like Figure 4 As shown, the manufacturing method of the nitride semiconductor device 10 includes the steps of sequentially forming a buffer layer 14 and an electron transition layer 16 on a substrate 12. The substrate is, for example, a Si substrate. The buffer layer 14 and the electron transition layer 16 can be epitaxially grown using, for example, an organic metal vapor deposition (MOCVD) method.

[0090] Although detailed illustration is omitted, in one example, the buffer layer 14 is a multilayer buffer layer, and an AlN layer (first buffer layer) is formed on the substrate 12, and then a graded AlGaN layer (second buffer layer) is formed on the AlN layer. The graded AlGaN layer is formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25% in order from the side close to the AlN layer.

[0091] Next, an electron transit layer 16 is formed on the buffer layer 14. The electron transit layer 16 is formed on the substrate 12 via the buffer layer 14. The electron transit layer 16 is, for example, a GaN layer. Although detailed illustration is omitted, in one example, after an undoped GaN layer (first semiconductor layer) is formed on the buffer layer 14, a C-doped GaN layer (second semiconductor layer) is formed on the undoped GaN layer. Furthermore, an undoped GaN layer (third semiconductor layer) is formed on the C-doped GaN layer.

[0092] The method for manufacturing the nitride semiconductor device 10 includes the step of forming the initially formed electron supply layer 70 on the electron transition layer 16 composed of the nitride semiconductor. In addition, the method for manufacturing the nitride semiconductor device 10 includes the steps of forming the gate layer 22 composed of the nitride semiconductor containing the acceptor-type impurity on the initially formed electron supply layer 70; and removing a portion of the initially formed electron supply layer 70 by etching so that the portion located under the gate layer 22 remains and the electron transition layer 16 is exposed, thereby forming the first electron supply layer 51.

[0093] like Figure 4 As shown, an initial electron supply layer 70 is formed on the electron transition layer 16. The initial electron supply layer 70 is a layer for forming the first electron supply layer 51, and is, for example, an AlGaN layer. The initial electron supply layer 70 is composed of a nitride semiconductor having a larger band gap than the electron transition layer 16. The initial electron supply layer 70 can be epitaxially grown using, for example, the MOCVD method.

[0094] Next, the first nitride semiconductor layer 71 is formed on the initially formed electron supply layer 70. The first nitride semiconductor layer 71 is a layer for forming the gate layer 22, and is, for example, a GaN layer containing Mg as an acceptor-type impurity. The first nitride semiconductor layer 71 can be epitaxially grown using the MOCVD method. As an example, the first nitride semiconductor layer 71 is formed on the initially formed electron supply layer 70 by doping GaN with Mg during the growth of GaN.

[0095] Next, if Figure 5 As shown in FIG. 1 , a mask 72 is formed on a portion of the first nitride semiconductor layer 71. Figure 6 As shown in FIG. 1 , the first nitride semiconductor layer 71 and the initially formed electron supply layer 70 are selectively removed by etching in such a manner that a portion of the upper surface of the electron transition layer 16 in the portion where the mask 72 is not formed is exposed in a plan view. Then, the mask 72 is removed. In this way, the gate layer 22 is formed as the remaining portion of the first nitride semiconductor layer 71, and the first electron supply layer 51 is formed as the remaining portion of the initially formed electron supply layer 70.

[0096] Here, when a portion of the electron supply layer 70 initially formed is removed by etching, a portion of the upper surface side of the electron transition layer 16 in the portion where the mask 72 is not formed is also removed. In this way, a protruding portion 44 is formed in the region (first portion 41) under the gate layer 22 in the electron transition layer 16. The protruding height H1 of the protruding portion 44 can be adjusted by changing the etching amount of the electron transition layer 16.

[0097] The etching rate of the material (e.g., AlGaN) constituting the initially formed electron supply layer 70 may be higher than the etching rate of the material (e.g., GaN) constituting the electron transit layer 16. In this case, when a portion of the upper surface side of the electron transit layer 16 is etched, it sinks into the portion located under the gate layer 22 and removes the electron transit layer 16. As a result, Figure 3 As shown, the width W1 of the protruding portion 44 is shorter than the width W2 of the gate layer 22 .

[0098] The manufacturing method of the nitride semiconductor device 10 includes the following steps: a step of forming a reformed electron supply layer 73 connected to the first electron supply layer 51 on the electron transition layer 16 exposed by etching; a step of forming a passivation layer 26 on the reformed electron supply layer 73; and a step of forming a gate electrode 24 on the gate layer 22.

[0099] like Figure 7As shown, a reformed electron supply layer 73 is formed on the electron transition layer 16 and the gate layer 22. The reformed electron supply layer 73 is a layer covering a portion of the electron transition layer 16 and the gate layer 22, and is, for example, an AlGaN layer. The reformed electron supply layer 73 is a continuous layer formed integrally by the second electron supply layer 52, the third electron supply layer 53, and the covering portion 54. The reformed electron supply layer 73 is composed of a nitride semiconductor having a larger band gap than the electron transition layer 16. The reformed electron supply layer 73 can be epitaxially grown using, for example, the MOCVD method.

[0100] In one example, the initially formed electron supply layer 70 is an AlGaN layer, and the re-formed electron supply layer 73 is an AlGaN layer having a smaller Al composition than the initially formed electron supply layer 70. In another example, the initially formed electron supply layer 70 is an AlGaN layer, and the re-formed electron supply layer 73 is an AlGaN layer having a larger Al composition than the initially formed electron supply layer 70.

[0101] Next, if Figure 8 As shown in FIG. 1 , the first passivation layer 61 is formed on the re-formed electron supply layer 73. Fig. 9 As shown, a gate opening 61A is formed in the first passivation layer 61 to expose the re-formed electron supply layer 73 located on the gate layer 22. The first passivation layer 61 is, for example, a SiN layer. The first passivation layer 61 can be formed, for example, using a low-pressure chemical vapor deposition (LPCVD) method. The gate opening 61A is formed by selectively removing a portion of the first passivation layer 61 located on the gate layer 22 by photolithography and etching using a mask.

[0102] Next, if Fig.10 As shown, a first metal layer 74 is formed on the first passivation layer 61 and in the gate opening 61A. The first metal layer 74 is a layer for forming the gate electrode 24, and is, for example, a TiN layer. The first metal layer 74 can be formed by, for example, sputtering.

[0103] Next, if Fig.11 As shown in FIG. 1 , a portion of the first metal layer 74 is selectively removed. In this way, the gate electrode 24 is formed as the remaining portion of the first metal layer 74. The gate electrode 24 is formed to be in contact with the reformed electron supply layer 73 (coated portion 54) exposed from the gate opening 61A of the first passivation layer 61. The gate electrode 24 is formed by selectively removing a portion of the first metal layer 74 by photolithography and etching using a mask.

[0104] Here, the etching for selectively removing a portion of the first metal layer 74 is performed in a state where the first passivation layer 61 is formed on the reformed electron supply layer 73. Therefore, the first passivation layer 61 protects the reformed electron supply layer 73 from the etching. In this way, etching damage is suppressed in the reformed electron supply layer 73 (especially the second electron supply layer 52).

[0105] Next, if Fig.12 As shown, the second passivation layer 62 is formed on the first passivation layer 61 and the gate electrode 24. The second passivation layer 62 is formed to cover a portion of the first passivation layer 61 and the gate electrode 24. The second passivation layer 62 is, for example, a SiN layer. The second passivation layer 62 can be formed using a reduced pressure CVD method, for example. In addition, the above-mentioned step of forming the passivation layer 26 on the re-formed electron supply layer 73 includes the following steps: a step of forming the first passivation layer 61; and a step of forming the second passivation layer 62.

[0106] The method for manufacturing the nitride semiconductor device 10 includes a step of forming the source electrode 28 and the drain electrode 30 on the re-formed electron supply layer 73 .

[0107] like Fig.13 As shown, the source opening 26A and the drain opening 26B are formed in the first passivation layer 61 and the second passivation layer 62 to expose the reformed electron supply layer 73. The source opening 26A and the drain opening 26B are formed by selectively removing a portion of the first passivation layer 61 and the second passivation layer 62 by photolithography and etching using a mask.

[0108] Next, if Fig.14 As shown, a second metal layer 75 is formed on the second passivation layer 62 and in the source opening 26A and the drain opening 26B. The second metal layer 75 is a layer for forming the source electrode 28 and the drain electrode 30, and is, for example, a Ti layer. The second metal layer 75 can be formed by, for example, sputtering.

[0109] Next, if Fig.15 As shown, a portion of the second metal layer 75 is selectively removed. In this way, the source electrode 28 and the drain electrode 30 are formed as the remaining portion of the second metal layer 75. The source electrode 28 is formed to be in contact with the reformed electron supply layer 73 exposed from the source opening 26A of the first passivation layer 61 and the second passivation layer 62. The drain electrode 30 is formed to be in contact with the reformed electron supply layer 73 exposed from the drain opening 26B of the first passivation layer 61 and the second passivation layer 62. The source electrode 28 and the drain electrode 30 are formed by selectively removing a portion of the second metal layer 75 by photolithography and etching using a mask. Through the above steps, the nitride semiconductor device 10 can be obtained.

[0110] [effect]

[0111] Next, the operation of the nitride semiconductor device 10 will be described.

[0112] In a nitride semiconductor device having a conventional structure having a gate layer formed on an electron supply layer, etching performed when forming the gate layer causes etching damage to be generated in the electron supply layer between the gate layer and the source electrode and between the gate layer and the drain electrode. The etching damage generated in the electron supply layer becomes the main reason for the change in the electrical characteristics of the 2DEG generated in the electron transition layer. The electron supply layer that has been etched becomes easy to capture surrounding electrons. It is believed that the reason is that the crystalline structure of the electron supply layer becomes unstable. When etching damage is generated in the electron supply layer, when the current flows with the 2DEG as the conductive path, a part of the electrons moving in the 2DEG are captured by the electron supply layer, resulting in a change in the electrical characteristics of the 2DEG.

[0113] In the nitride semiconductor device 10 of the embodiment, the electron supply layer 18 includes a first electron supply layer 51 located under the gate layer 22, and a second electron supply layer 52 located between the gate layer 22 and the source opening 26A and between the gate layer 22 and the drain opening 26B and connected to the first electron supply layer 51. In this case, by making the first electron supply layer 51 and the second electron supply layer 52 consist of different layers formed at different times, the second electron supply layer 52 can be made into an undamaged layer without etching damage.

[0114] Specifically, after the initially formed electron supply layer 70 is formed on the electron transition layer 16, the gate layer 22 is formed on the initially formed electron supply layer 70. In the etching performed when the gate layer 22 is formed, the initially formed electron supply layer 70 is completely removed except for the portion located under the gate layer 22. Then, on the electron transition layer 16 exposed by removing the initially formed electron supply layer 70, a reformed electron supply layer 73 is formed, and the reformed electron supply layer 73 is used as the second electron supply layer 52. In this case, after the initially formed electron supply layer 70 in which etching damage generated when the gate layer 22 is formed is removed, the second electron supply layer 52 as the newly formed electron supply layer 73 is formed. Therefore, the second electron supply layer 52 becomes an undamaged layer in which etching damage generated when the gate layer 22 is formed is not generated.

[0115] Since the second electron supply layer 52 is an undamaged layer, when current flows through the 2DEG 20 as a conductive path, electrons moving in the 2DEG 20 are suppressed from being captured by the second electron supply layer 52. As a result, the electrical characteristics of the 2DEG 20 in the nitride semiconductor device 10 become stable. In addition, when designing the nitride semiconductor device 10 having the desired electrical characteristics of the 2DEG 20, there is no need to consider the control parameters related to the etching amount. This also contributes to stabilizing the electrical characteristics of the 2DEG 20 in the nitride semiconductor device 10.

[0116] [Effect]

[0117] According to the nitride semiconductor device 10 , the following effects can be obtained.

[0118] (1) The nitride semiconductor device 10 includes: an electron transition layer 16; an electron supply layer 18 formed on the electron transition layer 16; a gate layer 22 formed on a portion of the electron supply layer 18; a gate electrode 24 formed on the gate layer 22; a passivation layer 26 covering the electron supply layer 18, the gate layer 22, and the gate electrode 24 and having a source opening 26A and a drain opening 26B; a source electrode 28 in contact with the electron supply layer 18 via the source opening 26A; and a drain electrode 30 in contact with the electron supply layer 18 via the drain opening 26B. The electron transition layer 16 includes: a first portion 41 located below the gate layer 22; and a second portion 42 located between the gate layer 22 and the source opening 26A, and between the gate layer 22 and the drain opening 26B. The electron supply layer 18 includes a first electron supply layer 51 formed on the first portion 41 and located below the gate layer 22 , and a second electron supply layer 52 formed on the second portion 42 and connected to the first electron supply layer 51 .

[0119] According to the above configuration, an undamaged electron supply layer 18 (second electron supply layer 52) without etching damage can be provided between the gate electrode 24 and the source electrode 28 and between the gate electrode 24 and the drain electrode 30 in a plan view. This stabilizes the electrical characteristics of the 2DEG 20 in the nitride semiconductor device 10.

[0120] (2) The thickness T2 of the second electron supply layer 52 is the same as the thickness T1 of the first electron supply layer 51. In this case, the difference between the amount of 2DEG 20 formed between the gate-source and the gate-drain and the amount of 2DEG 20 formed directly under the gate electrode 24 when the gate electrode 24 is applied with an on-voltage can be reduced.

[0121] (3) The thickness T2 of the second electron supply layer 52 is thicker than the thickness T1 of the first electron supply layer 51. In this case, the amount of 2DEG 20 formed between the gate and the source and between the gate and the drain increases, so that the on-resistance can be reduced.

[0122] (4) The electron supply layer 18 includes the covering portion 54 covering the upper surface 22A of the gate layer 22. An upper portion 54A of the covering portion 54 covering the upper surface 22A of the gate layer 22 is sandwiched between the gate layer 22 and the gate electrode 24. In this case, since the electron supply layer 18 (upper portion 54A of the covering portion 54) is interposed between the gate layer 22 and the gate electrode 24, the Schottky barrier between the gate layer 22 and the gate electrode 24 can be increased. Therefore, the gate leakage current passing through the gate layer 22 can be reduced.

[0123] (5) The covering portion 54 includes a side portion 54B that covers the side surface 22B of the gate layer 22 and is connected to the second electron supply layer 52. In this case, the second electron supply layer 52 as an undamaged layer and the upper portion 54A of the covering portion 54 that plays the role of improving the Schottky barrier can be formed in a single layer by a single formation process.

[0124] (6) The thickness T3 of the coating portion 54 is equal to or thinner than the thickness T1 of the first electron supply layer 51. In this case, it is possible to prevent the Schottky barrier from becoming too high and the on-resistance from becoming too high as the Schottky barrier becomes high.

[0125] (7) The thickness T3 of the covering portion 54 is greater than the thickness T1 of the first electron supply layer 51. In this case, the Schottky barrier can be increased, and thus the gate leakage current through the gate layer 22 can be further reduced.

[0126] (8) The first portion 41 of the electron transition layer 16 has a protruding portion 44 that protrudes upward more than the second portion 42. The first electron supply layer 51 of the electron supply layer 18 is formed on the protruding portion 44. In this case, the initially formed electron supply layer 70 that has been etched and damaged can be removed more completely. Therefore, the effect of (1) can be more significantly obtained.

[0127] <Example of Change>

[0128] The embodiment can be varied in the following manner, for example. As long as no technical contradiction is generated, the embodiment and the following variations can be combined with each other. In addition, in the following variations, for the parts common to the embodiment, the same symbols as the embodiment are attached and their descriptions are omitted.

[0129] ·like Fig.16As shown, the first portion 41 of the electron transition layer 16 may also be a structure without the protruding portion 44. In this case, the upper surface 41A of the first portion 41 and the upper surface 42A of the second portion 42 are located at the same position in the thickness direction, that is, the upper surface 41A and the upper surface 42A are located in the same plane. In addition, the electron transition layer 16 of the above structure can be formed as follows. In the step of removing a portion of the initially formed electron supply layer 70 by etching in the method for manufacturing the nitride semiconductor device 10 (refer to Figure 6 ), the initially formed electron supply layer 70 is etched without removing a portion of the upper surface side of the electron transition layer 16. In this way, the electron transition layer 16 having a shape without the protruding portion 44 can be formed.

[0130] ·like Fig.17 As shown, the thickness T4 of the portion 54A1 located under the gate electrode 24 in the upper portion 54A of the covering portion 54 may be partially thinned. The thickness T4 of the portion 54A1 is, for example, not less than 1 nm and not more than 10 nm. The ratio (T4 / T3) of the thickness T4 of the portion 54A1 and the thickness T3 of the portion other than the portion 54A1 in the covering portion 54 is, for example, not less than 1 and not more than 10. In addition, the ratio (T4 / T2) of the thickness T4 of the portion 54A1 and the thickness T2 of the second electron supply layer 52 is, for example, not less than 1 and not more than 10. By adjusting the thickness T4 of the portion 54A1, the height of the Schottky barrier between the gate layer 22 and the gate electrode 24 can be controlled. For example, by making the thickness T2 of the second electron supply layer thicker than the thickness T1 of the first electron supply layer 51, it is considered possible to increase the amount of 2DEG 20 generated. In this case, by making the thickness T3 of the portion 54A1 thinner than the thickness T2 of the second electron supply layer, it is possible to suppress the Schottky barrier between the gate layer 22 and the gate electrode 24 from becoming too high.

[0131] The covering portion 54 having the above-described structure can be formed as follows. In the step of forming the gate opening portion 61A in the method for manufacturing the nitride semiconductor device 10 (see Figure 8 ), when a portion of the first passivation layer 61 is removed by etching, a portion of the upper surface side of the portion located under the gate opening 61A in the covering portion 54 is also removed. In this way, the thickness T4 of the portion 54A1 located under the gate electrode 24 in the upper portion 54A of the covering portion 54 can be locally thinned.

[0132] In addition, in the step of forming the gate opening portion 61A (refer to Figure 8 ), when a portion of the first passivation layer 61 is removed by etching, the portion of the covering portion 54 located under the gate opening 61A may also be completely removed. Fig.18As shown, the gate electrode 24 is in contact with the gate layer 22 via the gate opening 61A.

[0133] The electron supply layer 18 may be configured without the covering portion 54. In this case, the gate electrode 24 is in contact with the gate layer 22 via the gate opening 61A.

[0134] In the above-described embodiment, the nitride semiconductor device 10 is configured as a nitride semiconductor HEMT, but is not limited to a nitride semiconductor HEMT, and may be configured as a nitride semiconductor diode.

[0135] The term "on" used in the present disclosure includes both "on" and "above" as long as the context does not indicate otherwise. Therefore, the expression "the first layer is formed on the second layer" is intended to indicate that in one embodiment, the first layer can be directly disposed on the second layer in a manner of contacting the second layer, while in another embodiment, the first layer can be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which other layers are formed between the first layer and the second layer.

[0136] The Z direction used in the present disclosure is not necessarily the vertical direction, nor is it necessarily completely consistent with the vertical direction. Therefore, in various structures related to the present disclosure, the "up" and "down" of the Z direction described in this specification are not limited to the "up" and "down" of the vertical direction. For example, the X direction may also be the vertical direction, or the Y direction may also be the vertical direction.

[0137] The terms "first", "second", "third" and the like in this disclosure are used only to distinguish objects, and do not rank the objects.

[0138] <Remarks>

[0139] The following describes the technical ideas that can be grasped by this disclosure. In addition, the constituent elements described in the notes are given reference symbols corresponding to the constituent elements in the embodiments in order to assist understanding but not to limit them. The reference symbols are exemplified to assist understanding, and the constituent elements described in each note should not be limited by the constituent elements represented by the reference symbols.

[0140] [Note 1]

[0141] A nitride semiconductor device (10), comprising:

[0142] An electron transfer layer (16) composed of a nitride semiconductor;

[0143] An electron supply layer (18) formed on the electron transition layer (16) and composed of a nitride semiconductor having a larger band gap than the electron transition layer (16);

[0144] A gate layer (22) formed on a portion of the electron supply layer (18) and made of a nitride semiconductor containing an acceptor-type impurity;

[0145] A gate electrode (24) formed on the gate layer (22);

[0146] a passivation layer (26) covering the electron supply layer (18), the gate layer (22), and the gate electrode (24), and having a source opening (26A) and a drain opening (26B) separated from each other via the gate layer (22);

[0147] a source electrode (28) connected to the electron supply layer (18) via the source opening (26A); and

[0148] a drain electrode (30) connected to the electron supply layer (18) via the drain opening (26B); and

[0149] The electron transfer layer (16) comprises:

[0150] a first portion (41) located below the gate layer (22); and

[0151] A second portion (42) located between the gate layer (22) and the source opening (26A), and between the gate layer (22) and the drain opening (26B) in a plan view;

[0152] The electron supply layer (18) comprises:

[0153] a first electron supply layer (51) formed on the first portion (41) and located below the gate layer (22); and

[0154] A second electron supply layer (52) is formed on the second portion (42) and is connected to the first electron supply layer (51).

[0155] [Note 2]

[0156] According to the nitride semiconductor device (10) described in attachment 1, an interface (18A) is formed between the first electron supply layer (51) and the second electron supply layer (52).

[0157] [Note 3]

[0158] The nitride semiconductor device (10) according to Note 1 or Note 2, wherein the electron supply layer (18) includes a covering portion (54) covering the upper surface (22A) and the side surface (22B) of the gate layer (22) and connected to the second electron supply layer (52),

[0159] A portion (54A) of the covering portion (54) that covers an upper surface (22A) of the gate layer (22) is sandwiched between the gate layer (22) and the gate electrode (24).

[0160] [Note 4]

[0161] The nitride semiconductor device (10) according to any one of Notes 1 to 3, wherein the first portion (41) of the electron transition layer (16) has a protruding portion (44) that protrudes upward more than the second portion (42),

[0162] The first electron supply layer (51) of the electron supply layer (18) is formed on the protruding portion (44).

[0163] [Note 5]

[0164] According to the nitride semiconductor device (10) described in Note 4, in the direction in which the source electrode (28) and the drain electrode (30) are arranged across the gate layer (22),

[0165] The width (W1) of the protruding portion (44) of the first portion (41) is shorter than the width (W2) of the gate layer (22).

[0166] [Note 6]

[0167] The nitride semiconductor device (10) according to Note 4 or Note 5, wherein in the thickness direction, the upper surface (52A) of the second electron supply layer (52) is located at the same position as the upper surface (44A) of the protruding portion (44), or is located below the upper surface (44A) of the protruding portion (44),

[0168] The second electron supply layer (52) includes a connection portion (52B) that covers a side surface (44B) of the protruding portion (44) and is connected to the first electron supply layer (51).

[0169] [Note 7]

[0170] According to the nitride semiconductor device (10) described in Note 4 or Note 5, in the thickness direction, the upper surface (52A) of the second electron supply layer (52) is located above the upper surface (44A) of the protruding portion (44).

[0171] [Note 8]

[0172] A nitride semiconductor device (10) according to any one of Notes 1 to 3, wherein an upper surface (42A) of the second portion (42) of the electron transition layer (16) and an upper surface (41A) of the first portion (41) of the electron transition layer (16) are located on the same plane.

[0173] [Note 9]

[0174] The nitride semiconductor device (10) according to any one of Notes 1 to 8, wherein the thickness (T2) of the second electron supply layer (52) is the same as the thickness (T1) of the first electron supply layer (51).

[0175] [Note 10]

[0176] A nitride semiconductor device (10) according to any one of Notes 1 to 9, wherein the passivation layer (26) comprises: a first passivation layer (61) covering the second electron supply layer (52), and a second passivation layer (62) covering the first passivation layer (61) and the gate electrode (24).

[0177] [Note 11]

[0178] The nitride semiconductor device (10) according to any one of Notes 1 to 10, wherein the electron transition layer (16) is a GaN layer,

[0179] The electron supply layer (18) is an AlGaN layer,

[0180] The gate layer (22) is a GaN layer containing the acceptor-type impurities.

[0181] [Note 12]

[0182] A method for manufacturing a nitride semiconductor device comprises the following steps:

[0183] A step of initially forming an electron supply layer (70) on an electron transit layer (16) composed of a nitride semiconductor;

[0184] A step of forming a gate layer (22) composed of a nitride semiconductor containing acceptor-type impurities on the initially formed electron supply layer (70);

[0185] A step of removing a portion of the initially formed electron supply layer (70) by etching so that a portion located under the gate layer (22) remains and the electron transition layer (16) is exposed, thereby forming a first electron supply layer (51) as a remaining portion of the initially formed electron supply layer (70);

[0186] A step of forming a reformed electron supply layer (73) connected to the first electron supply layer (51) on the electron transition layer (16) exposed by the etching;

[0187] The step of forming a passivation layer (26, 61, 62) on the reformed electron supply layer (73);

[0188] forming a gate electrode (24) on the gate layer (22); and

[0189] forming a source electrode (28) and a drain electrode (30) on the reformed electron supply layer (73); and

[0190] The initially formed electron supply layer (70) and the reformed electron supply layer (73) are composed of a nitride semiconductor having a larger band gap than the electron transition layer (16).

[0191] [Note 13]

[0192] The method for manufacturing a nitride semiconductor device according to note 12, wherein the reformed electron supply layer (73) is formed to include a covering portion (54) covering the upper surface (22A) and the side surface (22B) of the gate layer (22),

[0193] The gate electrode (24) is formed on a portion (54A) of the covering portion (54) that covers an upper surface (22A) of the gate layer (22).

[0194] [Note 14]

[0195] The method for manufacturing a nitride semiconductor device according to note 12 or note 13, wherein when a portion of the initially formed electron supply layer (70) is removed by etching, a portion of the upper surface side of the electron transition layer (16) is also removed.

[0196] [Note 15]

[0197] According to the method for manufacturing a nitride semiconductor device as described in any one of Notes 12 to 14, the step of forming the gate electrode (24) on the gate layer (22) comprises:

[0198] The steps of forming a metal layer (74) on the gate layer (22); and removing a portion of the metal layer (74) by etching to form the gate electrode (24) as the remaining portion of the metal layer (74); and

[0199] The step of forming a passivation layer (26, 61, 62) on the reformed electron supply layer (73) comprises:

[0200] The invention also provides a step of forming a first passivation layer (61) on the reformed electron supply layer (73) before forming the metal layer (74); and a step of forming a second passivation layer (62) on the first passivation layer (61) after forming the gate electrode (24).

[0201] [Explanation of Symbols]

[0202] H1: Highlight height

[0203] HC:HEMT unit

[0204] T1~T4:Thickness

[0205] W1,W2: Width

[0206] 10: Nitride semiconductor device

[0207] 12: Substrate

[0208] 12A: Substrate upper surface

[0209] 14: Buffer layer

[0210] 16: Electron transfer layer

[0211] 18:Electron supply layer

[0212] 18A: Interface

[0213] 20: Two-dimensional electron gas

[0214] 22: Gate layer

[0215] 22A: Upper surface

[0216] 22B: Side surface

[0217] 24: Gate electrode

[0218] 26: Passivation layer

[0219] 26A: Source opening

[0220] 26B: Drain opening

[0221] 28: Source electrode

[0222] 28A: Source contact portion

[0223] 28B: Source field plate

[0224] 28C: End

[0225] 30: Drain electrode

[0226] 41:Part 1

[0227] 41A: Upper surface

[0228] 42: Part 2

[0229] 42A: Upper surface

[0230] 43: Part 3

[0231] 44: Protrusion

[0232] 44A: Upper surface

[0233] 44B: Side surface

[0234] 51:1st electron supply layer

[0235] 52: Second electron supply layer

[0236] 52A: Upper surface

[0237] 52B: Connecting part

[0238] 53: 3rd electron supply layer

[0239] 54: Covered part

[0240] 54A: Upper part

[0241] 54B: Side

[0242] 61: 1st passivation layer

[0243] 61A: Gate opening

[0244] 62: Second passivation layer

[0245] 70: Initial formation of electron supply layer

[0246] 71: First nitride semiconductor layer

[0247] 72: Mask

[0248] 73: Re-forming the electron supply layer

[0249] 74: 1st metal layer

[0250] 75: 2nd metal layer.

Claims

1. A nitride semiconductor device, comprising: An electron transfer layer composed of a nitride semiconductor; An electron supply layer formed on the electron transition layer and composed of a nitride semiconductor having a larger band gap than the electron transition layer; a gate layer formed on a portion of the electron supply layer and composed of a nitride semiconductor containing an acceptor-type impurity; a gate electrode formed on the gate layer; a passivation layer covering the electron supply layer, the gate layer, and the gate electrode and having a source opening and a drain opening separated from each other via the gate layer; a source electrode connected to the electron supply layer via the source opening; and a drain electrode connected to the electron supply layer via the drain opening; and The electron transfer layer comprises: a first portion located below the gate layer; and a second portion located between the gate layer and the source opening, and between the gate layer and the drain opening in a plan view; The electron supply layer comprises: A first electron supply layer formed on the first portion and below the gate layer; and A second electron supply layer is formed on the second portion and connected to the first electron supply layer. 2 . The nitride semiconductor device according to claim 1 , wherein an interface is formed between the first electron supply layer and the second electron supply layer.

3. The nitride semiconductor device according to claim 1 or 2, wherein the electron supply layer includes a covering portion that covers the upper surface and the side surface of the gate layer and is connected to the second electron supply layer, A portion of the covering portion that covers the upper surface of the gate layer is sandwiched between the gate layer and the gate electrode.

4. The nitride semiconductor device according to any one of claims 1 to 3, wherein the first portion of the electron transition layer has a protruding portion that protrudes upward more than the second portion, The first electron supply layer of the electron supply layer is formed on the protruding portion.

5. The nitride semiconductor device according to claim 4, wherein in a direction in which the source electrode and the drain electrode are arranged with the gate layer interposed therebetween, The width of the protruding portion of the first portion is shorter than the width of the gate layer.

6. The nitride semiconductor device according to claim 4 or 5, wherein in the thickness direction, the upper surface of the second electron supply layer is located at the same position as the upper surface of the protruding portion, or is located below the upper surface of the protruding portion, The second electron supply layer includes a connection portion that covers a side surface of the protruding portion and is connected to the first electron supply layer. 7 . The nitride semiconductor device according to claim 4 , wherein an upper surface of the second electron supply layer is located above an upper surface of the protruding portion in a thickness direction. 8 . The nitride semiconductor device according to claim 1 , wherein an upper surface of the second portion of the electron transition layer and an upper surface of the first portion of the electron transition layer are located on the same plane. 9 . The nitride semiconductor device according to claim 1 , wherein a thickness of the second electron supply layer is the same as a thickness of the first electron supply layer. 10 . The nitride semiconductor device according to claim 1 , wherein the passivation layer includes: a first passivation layer covering the second electron supply layer, and a second passivation layer covering the first passivation layer and the gate electrode.

11. The nitride semiconductor device according to any one of claims 1 to 10, wherein the electron transition layer is a GaN layer, The electron supply layer is an AlGaN layer, The gate layer is a GaN layer containing the acceptor-type impurity.

12. A method for manufacturing a nitride semiconductor device, comprising the following steps: a step of initially forming an electron supply layer on the electron transit layer composed of a nitride semiconductor; forming a gate layer composed of a nitride semiconductor containing acceptor-type impurities on the initially formed electron supply layer; A step of removing a portion of the initially formed electron supply layer by etching so that a portion located under the gate layer remains and the electron transition layer is exposed, thereby forming a first electron supply layer as a remaining portion of the initially formed electron supply layer; forming a reformed electron supply layer connected to the first electron supply layer on the electron transition layer exposed by the etching; forming a passivation layer on the reformed electron supply layer; forming a gate electrode on the gate layer; and forming a source electrode and a drain electrode on the reformed electron supply layer; and The initially formed electron supply layer and the reformed electron supply layer are composed of a nitride semiconductor having a larger band gap than that of the electron transition layer.

13. The method for manufacturing a nitride semiconductor device according to claim 12, wherein the reformed electron supply layer is formed to include a covering portion covering an upper surface and a side surface of the gate layer, The gate electrode is formed on a portion of the covering portion that covers the upper surface of the gate layer. 14 . The method for manufacturing a nitride semiconductor device according to claim 12 , wherein when a portion of the initially formed electron supply layer is removed by etching, a portion of the upper surface side of the electron transition layer is also removed.

15. The method for manufacturing a nitride semiconductor device according to any one of claims 12 to 14, wherein the step of forming the gate electrode on the gate layer comprises: forming a metal layer on the gate layer; and removing a portion of the metal layer by etching to form the gate electrode as a remaining portion of the metal layer; The step of forming a passivation layer on the reformed electron supply layer comprises: Before forming the metal layer, forming a first passivation layer on the reformed electron supply layer; and forming a second passivation layer on the first passivation layer after forming the gate electrode.

Images