Novel heterojunction field plate gallium oxide MOSFET device

Abstract

The invention belongs to the technical field of power semiconductors, and relates to a novel heterojunction field plate gallium oxide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device. The heterojunction field plate is composed of P-type oxide above the drift region and gallium oxide regrown on the drain electrode side, the effect of modulating electric field distribution on the surface of the device can be achieved, and the withstand voltage of the device is improved. The effect of the P-type oxide and the gallium oxide in the drift region is similar to that of a P / N column of a super junction, the auxiliary depletion effect is introduced, the doping concentration of the drift region is improved, the on-resistance is reduced, the substrate auxiliary depletion effect brought by a silicon-based transverse device does not exist, and charge balance can be better regulated and controlled. And the P-type oxide adopts a sputtering process, so that the interface problem caused by etching is avoided.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductors and relates to a novel heterojunction field plate gallium oxide MOSFET device. Background Art

[0002] The development of power supplies, motor drives and electric vehicles has put forward higher requirements for energy-saving electronic systems and efficient semiconductor power devices. Among all emerging semiconductor materials, β-Ga2O3 has an ultra-wide band gap of 4.5-4.9 eV and a theoretical breakdown electric field strength (E C ), which has unique advantages over SiC / GaN materials. With the continuous development of Ga2O3 power devices, in order to make full use of the high critical breakdown field strength of Ga2O3 to achieve high breakdown voltage (BV), various electric field management strategies have been adopted, including vertical fin channel structure, field plate structure, super junction (SJ) technology and heterojunction gate, but some structures inevitably introduce process complexity and negative effects. ON，SP The trade-off between the breakdown voltage (BV) and the on-resistance (R ON，SP ) will increase, and the device performance needs to be further improved. Summary of the invention

[0003] The purpose of the present invention is to propose a novel heterojunction field plate gallium oxide MOSFET device in view of the above problems.

[0004] The technical solution of the present invention is:

[0005] A novel heterojunction field plate gallium oxide MOSFET device, comprising a gallium oxide substrate layer 1, a gallium oxide buffer layer 2, and a gallium oxide epitaxial layer 3 stacked in sequence from bottom to top along the vertical direction of the device;

[0006] The invention is characterized in that an N+ source region 5 and an N+ drain region 6 are respectively provided at both ends of the upper surface of the gallium oxide epitaxial layer 3, and the bottoms of the N+ source region 5 and the N+ drain region 6 are embedded in the upper layer of the gallium oxide epitaxial layer 3; a source electrode 11 and a drain electrode 12 are respectively provided on the upper surfaces of the N+ source region 5 and the N+ drain region 6; a dielectric layer 10 is provided on the upper surface of the gallium oxide epitaxial layer 3 between the N+ source region 5 and the N+ drain region 6, and the upper surface of the dielectric layer 10 is in contact with the N+ source region 5 and the N+ drain region 6. The upper surface of the device is flush along the lateral direction; a first P-type oxide 8 and a second P-type oxide 7 are connected to each other on the side of the upper layer of the dielectric layer 10 that contacts the N+ drain region 6, wherein the side of the second P-type oxide 7 contacts the side of the N+ drain region 6, so that the first P-type oxide 8, the second P-type oxide 7 and the N+ drain region 6 form a heterojunction field plate structure; an HFP electrode 13 is provided on the upper surface of the first P-type oxide 8, and the HFP electrode 13 is connected to the source electrode 11;

[0007] A gate electrode 9 is provided in the dielectric layer 10 between the first P-type oxide 8 and the N+ source region 5, the lower end of the gate electrode 9 is embedded in the dielectric layer 10 and is spaced apart from the upper surface of the gallium oxide epitaxial layer 3; the upper end of the gate electrode 9 extends out of the dielectric layer 10, and a space is provided between the two ends of the gate electrode 9 and the N+ source region 5 and the first P-type oxide 8; a thermal oxidation region 4 is provided in the gallium oxide epitaxial layer 3 below the gate electrode 9, the thermal oxidation region 4 penetrates the gallium oxide epitaxial layer 3 in a vertical direction, the lower surface of the thermal oxidation region 4 contacts the upper surface of the gallium oxide buffer layer 2, and the upper surface of the thermal oxidation region 4 contacts the lower surface of the dielectric layer 10.

[0008] Furthermore, the material used for the first P-type oxide 8 and the second P-type oxide 7 is nickel oxide.

[0009] The beneficial effects of the present invention are:

[0010] 1) By introducing a heterojunction field plate, this structure can modulate the surface electric field distribution of the device and improve the device's withstand voltage.

[0011] 2) The role of P-type oxide and drift region gallium oxide is similar to that of the P / N column of the superjunction, which introduces an auxiliary depletion effect, increases the doping concentration of the drift region, and reduces the on-resistance.

[0012] 3) There is no substrate-assisted depletion effect brought by silicon-based lateral devices, which can better regulate the charge balance.

[0013] 4) P-type oxide adopts sputtering process to avoid interface problems caused by etching.

[0014] 5) The local thermal oxidation region under the gate allows the channel to be better depleted, realizing an enhancement mode device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural schematic diagram of Example 1;

[0016] Figure 2 Schematic diagram of the process flow of the new heterojunction field plate gallium oxide MOSFET device. DETAILED DESCRIPTION

[0017] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and embodiments:

[0018] Example 1

[0019] like Figure 1As shown, the novel heterojunction field plate gallium oxide MOSFET device of this example comprises a gallium oxide substrate layer 1, a gallium oxide buffer layer 2, and a gallium oxide epitaxial layer 3 which are sequentially arranged from bottom to top along the vertical direction of the device; a local thermal oxidation region 4 is provided below the gate in the gallium oxide epitaxial layer 3, an N+ source region 5 and an N+ drain region 6 are provided above the epitaxial layer 3 near the source and drain, respectively, a source electrode 11 and a drain electrode 12 are provided on the upper surfaces, and a dielectric layer 10 is provided between the N+ source region 5 and the N+ drain region 6. A heterojunction field plate structure is provided on the side of the dielectric layer 10 close to the drain; the heterojunction field plate structure is composed of a first P-type oxide 8, a second P-type oxide 7 and an N+ drain region 6; the first P-type oxide 8 and the second P-type oxide 7 are located on the side of the dielectric layer 10 close to the drain, and the second P-type oxide 7 is in contact with the drain region 10; the gate electrode 9 is located on the side of the dielectric layer 10 close to the source, and is not in contact with the first P-type oxide 8; the first P-type oxide 8 leads to an HFP electrode 13 which is short-circuited with the source electrode 11.

[0020] This example works like this:

[0021] The present invention proposes a novel heterojunction field plate gallium oxide MOSFET device. When the gate electrode applied voltage is less than the threshold voltage and the drain voltage is greater than 0, the device is in the off state. The first P-type oxide 8 and the second P-type oxide 7 in the heterojunction field plate structure help to assist in depleting the gallium oxide epitaxial layer 3, similar to the P / N column of the superjunction structure, thereby adjusting the electric field distribution and improving the device withstand voltage. At the same time, the diode formed by the P-type oxide and the N+ drain region 6 is reverse biased, which helps to suppress the leakage current in the heterojunction field plate HFP. When the gate voltage is greater than the threshold voltage, the auxiliary depletion effect of the heterojunction field plate structure can increase the doping concentration of the gallium oxide epitaxial layer 3, thereby reducing the on-resistance of the device in the on state.

[0022] like Figure 2 (a)-(h) in the figure is a schematic diagram of the process flow of Example 1 of the present invention, and the process steps are as follows:

[0023] 1) Take out the gallium oxide substrate sample and clean the sample surface.

[0024] 2) An unintentionally doped layer and a gallium oxide drift region with a certain concentration are grown on the gallium oxide substrate by MOCVD to form a gallium oxide buffer layer 2 and a gallium oxide epitaxial layer 3.

[0025] 3) Use MOCVD to grow N+ epitaxy again to form N+ source region 5 and N+ drain region 6.

[0026] 4) Deposit a mask layer as a thermal oxidation barrier layer, and thermally oxidize a local area under the gate in an oxygen atmosphere to form a local thermal oxidation area 4.

[0027] 5) Photolithography of source and drain and evaporation of source and drain metal. The source and drain metal adopts Ti / Au double-layer metal to form source electrode 11 and drain electrode 12.

[0028] 6) A gate dielectric aluminum oxide is grown by ALD coating to form a dielectric layer 10 .

[0029] 7) Magnetron sputtering of P-type oxide, forming a first P-type oxide 8 and a second P-type oxide 7 of different concentrations by adjusting the O2 content during the growth process.

[0030] 8) The gate metal Ni / Au and the heterojunction field plate HFP metal are evaporated by the EBE method, and the gate electrode 9 and the heterojunction field plate HFP electrode 10 are obtained by the lift-off process.

Claims

1. A novel heterojunction field plate gallium oxide MOSFET device, comprising a gallium oxide substrate layer (1), a gallium oxide buffer layer (2), and a gallium oxide epitaxial layer (3) stacked in sequence from bottom to top along the vertical direction of the device; It is characterized in that An N+ source region (5) and an N+ drain region (6) are respectively provided at both ends of the upper surface of the gallium oxide epitaxial layer (3), and the bottoms of the N+ source region (5) and the N+ drain region (6) are embedded in the upper layer of the gallium oxide epitaxial layer (3); a source electrode (11) and a drain electrode (12) are respectively provided on the upper surfaces of the N+ source region (5) and the N+ drain region (6); a dielectric layer (10) is provided on the upper surface of the gallium oxide epitaxial layer (3) between the N+ source region (5) and the N+ drain region (6), and the upper surface of the dielectric layer (10) is in contact with the N+ source region (5) and the N+ drain region (6). ) is flush with the upper surface of the device in the lateral direction; a first P-type oxide (8) and a second P-type oxide (7) are connected to each other on the side of the upper layer of the dielectric layer (10) in contact with the N+ drain region (6), wherein the side surface of the second P-type oxide (7) is in contact with the side surface of the N+ drain region (6), so that the first P-type oxide (8), the second P-type oxide (7) and the N+ drain region (6) form a heterojunction field plate structure; an HFP electrode (13) is provided on the upper surface of the first P-type oxide (8), and the HFP electrode (13) is connected to the source electrode (11); A gate electrode (9) is provided in the dielectric layer (10) between the first P-type oxide (8) and the N+ source region (5), the lower end of the gate electrode (9) is embedded in the dielectric layer (10) and is spaced apart from the upper surface of the gallium oxide epitaxial layer (3); the upper end of the gate electrode (9) extends out of the dielectric layer (10), and the two ends of the gate electrode (9) are spaced apart from the N+ source region (5) and the first P-type oxide (8); a thermal oxidation region (4) is provided in the gallium oxide epitaxial layer (3) below the gate electrode (9), the thermal oxidation region (4) penetrates the gallium oxide epitaxial layer (3) in a vertical direction, the lower surface of the thermal oxidation region (4) is in contact with the upper surface of the gallium oxide buffer layer (2), and the upper surface of the thermal oxidation region (4) is in contact with the lower surface of the dielectric layer (10).

2. A novel heterojunction field plate gallium oxide MOSFET device according to claim 1, characterized in that: The materials used for the first P-type oxide (8) and the second P-type oxide (7) are nickel oxide.

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