Gallium oxide-based power device with dielectric layer electric field shielding ring and preparation method of gallium oxide-based power device

Abstract

The invention discloses a gallium oxide-based power device with a dielectric layer electric field shielding ring and a preparation method thereof, and relates to the field of semiconductor devices. The device comprises a first electrode layer, a gallium oxide substrate, a gallium oxide epitaxial layer and a first dielectric layer which are sequentially stacked from bottom to top, the p-type semiconductor layer is continuously located on the surface of the gallium oxide epitaxial layer and the partial surface of the first dielectric layer, and the part, located on the partial surface of the first dielectric layer, of the p-type semiconductor layer is a first field plate; the p-type semiconductor shielding ring is located on the surface of the first dielectric layer and is spaced from the first field plate; the second dielectric layer is continuously positioned on the surface of the first dielectric layer, the surface of the p-type semiconductor shielding ring and part of the surface of the first field plate; and the second electrode layer is continuously positioned on the surface of the p-type semiconductor layer and the partial surface of the second dielectric layer, and the part, positioned on the partial surface of the second dielectric layer, of the second electrode layer is a second field plate. The device provided by the invention has a higher breakdown electric field and better voltage resistance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a gallium oxide-based power device with a dielectric layer electric field shielding ring and a preparation method thereof. Background Art

[0002] Gallium oxide (Ga2O3) materials can bring significant performance improvements to power devices, such as: the ultra-high critical breakdown field strength of about 8MV / cm can greatly improve the breakdown voltage of power devices, the ultra-wide bandgap of about 4.8eV can improve the reliability of power devices in extreme environments such as high temperature and strong radiation, and the substrate material grown by the melt method can reduce the material cost of power devices. However, since there is no effective p-type doping scheme for gallium oxide materials, the mature terminal technology in silicon (Si)-based and SiC-based power devices cannot be used to improve the device breakdown voltage in gallium oxide-based power devices at this stage. In addition, the ultra-high critical breakdown field strength and large dielectric constant (k) of gallium oxide materials will also cause extremely high electric fields in the dielectric layer of the device, resulting in premature breakdown of the dielectric layer, which limits the optimization of the device breakdown voltage. Therefore, based on the unique material properties of gallium oxide, the development of terminal technology and preparation process suitable for gallium oxide-based power devices is of great significance to improving device performance.

[0003] Therefore, the prior art still needs to be improved and developed. Summary of the invention

[0004] Based on the above-mentioned deficiencies of the prior art, the purpose of the present invention is to provide a gallium oxide-based power device with a dielectric layer electric field shielding ring and a preparation method thereof, aiming to provide a terminal structure suitable for gallium oxide-based power devices so that the gallium oxide-based power devices have a higher breakdown voltage.

[0005] The technical solution of the present invention is as follows:

[0006] In a first aspect of the present invention, a gallium oxide-based power device with a dielectric layer electric field shielding ring is provided, wherein the gallium oxide-based power device with a dielectric layer electric field shielding ring comprises a first electrode layer, a gallium oxide substrate and a gallium oxide epitaxial layer stacked in sequence from bottom to top;

[0007] The gallium oxide-based power device having a dielectric layer electric field shielding ring further comprises:

[0008] A first dielectric layer, located on the surface of the gallium oxide epitaxial layer;

[0009] A p-type semiconductor layer is continuously located on the surface of the gallium oxide epitaxial layer and on a portion of the surface of the first dielectric layer, and a portion of the p-type semiconductor layer located on the portion of the surface of the first dielectric layer is a first field plate;

[0010] A p-type semiconductor shielding ring, located on the surface of the first dielectric layer and spaced apart from the first field plate;

[0011] A second dielectric layer is continuously disposed on a surface of the first dielectric layer, a surface of the p-type semiconductor shielding ring, and a portion of a surface of the first field plate;

[0012] The second electrode layer is continuously located on the surface of the p-type semiconductor layer and on a portion of the surface of the second dielectric layer. The portion of the second electrode layer located on the portion of the surface of the second dielectric layer is the second field plate.

[0013] Optionally, the gallium oxide substrate has a thickness of 50 to 650 μm;

[0014] The gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration of 10 18 ~10 20 cm -3 ;

[0015] The thickness of the gallium oxide epitaxial layer is 2 to 20 μm;

[0016] The gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer with a doping concentration of 10 15 ~10 17 cm -3 .

[0017] Optionally, the thickness of the first dielectric layer is 100 nm to 1 μm; the material of the first dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium dioxide;

[0018] The thickness of the second dielectric layer is 300 nm to 2 μm; the material of the second dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium dioxide.

[0019] Optionally, the material of the first electrode layer includes at least one of Ti, Ni, Ag and Au;

[0020] The material of the second electrode layer includes Ni, Mo, W, Pt, PtO x , Al, Au and Ag.

[0021] Optionally, the thickness of the p-type semiconductor layer is 100-600 nm; the p-type semiconductor layer includes at least one of p-type NiO, p-type Cu2O, p-type gallium oxide and p-type diamond;

[0022] The thickness of the p-type semiconductor shielding ring is 100-600 nm; the p-type semiconductor shielding ring includes at least one of p-type NiO, p-type Cu2O, p-type gallium oxide and p-type diamond.

[0023] Optionally, a distance between the first field plate and the p-type semiconductor shielding ring is 2-10 μm.

[0024] Optionally, when in a first direction on a horizontal plane, the width of the p-type semiconductor layer is the same as the width of the first dielectric layer and the width of the p-type semiconductor shielding ring, then in a direction perpendicular to the first direction on the horizontal plane:

[0025] The width of the first field plate is 3 to 20 μm;

[0026] The width of the p-type semiconductor shielding ring is 3 to 10 μm.

[0027] Optionally, the projection of the second electrode layer on the gallium oxide epitaxial layer covers the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer; or, the projection of the second electrode layer on the gallium oxide epitaxial layer coincides with the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer.

[0028] Optionally, a projection of one end of the second field plate away from the first field plate on the gallium oxide epitaxial layer is located within a projection of the p-type semiconductor shielding ring on the gallium oxide epitaxial layer;

[0029] The gallium oxide-based power device having a dielectric layer electric field shielding ring further comprises:

[0030] A passivation layer is continuously located on the surface of the second dielectric layer and on a portion of the surface of the second electrode layer.

[0031] A second aspect of the present invention provides a method for preparing a gallium oxide-based power device having a dielectric layer electric field shielding ring as described above, comprising the following steps:

[0032] providing a gallium oxide substrate;

[0033] forming a gallium oxide epitaxial layer on the surface of the gallium oxide substrate;

[0034] forming a first dielectric layer on the surface of the gallium oxide epitaxial layer;

[0035] forming a p-type semiconductor layer on the surface of the gallium oxide epitaxial layer and on a portion of the surface of the first dielectric layer, wherein the portion of the p-type semiconductor layer located on the portion of the surface of the first dielectric layer is a first field plate;

[0036] forming a p-type semiconductor shielding ring spaced apart from the first field plate on the surface of the first dielectric layer;

[0037] forming a second dielectric layer on the surface of the first dielectric layer, on the surface of the p-type semiconductor shielding ring, and on a portion of the surface of the first field plate;

[0038] forming a second electrode layer on the surface of the p-type semiconductor layer and on a portion of the surface of the second dielectric layer, wherein a portion of the second electrode layer located on the portion of the surface of the second dielectric layer is a second field plate;

[0039] A first electrode layer is formed on the side of the gallium oxide substrate away from the gallium oxide epitaxial layer to obtain the gallium oxide-based power device with a dielectric layer electric field shielding ring.

[0040] Beneficial effects: The present invention introduces a double-layer field plate structure in a gallium oxide-based power device, and forms a first field plate structure by extending the p-type semiconductor layer to the surface of the first dielectric layer to suppress the electric field concentration phenomenon at the edge of the interface between the p-type semiconductor layer and the gallium oxide epitaxial layer, thereby reducing the electric field peak. By extending the second electrode layer to the surface of the second dielectric layer to form a second field plate structure, the electric field concentration on the surface of the first dielectric layer and the gallium oxide epitaxial layer below the edge of the first field plate structure can be suppressed. Therefore, the double-layer field plate structure can optimize the terminal electric field distribution, reduce the electric field peak, and increase the device breakdown voltage. Furthermore, by introducing a p-type semiconductor shielding ring structure, the electric field peak in the dielectric layer can be effectively reduced, suppressing the occurrence of premature breakdown of the dielectric layer, and further increasing the device breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 Schematic diagram of the structure of a gallium oxide-based power device with a dielectric layer electric field shielding ring in an embodiment of the present invention.

[0042] Figure 2 The present invention is a schematic diagram of the preparation process of a gallium oxide-based power device with a dielectric layer electric field shielding ring in an embodiment of the present invention, wherein (a) is a schematic diagram of forming a gallium oxide epitaxial layer on the surface of a gallium oxide substrate, (b) is a schematic diagram of forming a first dielectric layer precursor layer on the surface of the gallium oxide epitaxial layer, (c) is a schematic diagram of etching the first dielectric layer precursor layer to obtain the first dielectric layer, (d) is a schematic diagram of forming a p-type semiconductor layer on the surface of the gallium oxide epitaxial layer and on a portion of the surface of the first dielectric layer, and forming a p-type semiconductor shielding ring on the surface of the first dielectric layer spaced apart from the first field plate, (e) is a schematic diagram of forming a second dielectric layer on the surface of the first dielectric layer, on the surface of the p-type semiconductor shielding ring, and on a portion of the surface of the first field plate, (f) is a schematic diagram of forming a second electrode layer on the surface of the p-type semiconductor layer and on a portion of the surface of the second dielectric layer, (g) is a schematic diagram of forming a passivation layer on the surface of the second dielectric layer and on a portion of the surface of the second electrode layer, and (h) is a schematic diagram of forming a first electrode layer on the side of the gallium oxide substrate away from the gallium oxide epitaxial layer.

[0043] Figure 3 Schematic diagram of the structure of a gallium oxide-based power device with a conventional single field plate structure terminal.

[0044] Figure 4 Schematic diagram of the structure of a gallium oxide-based power device with a double field plate structure.

[0045] Figure 5 The graphs are surface electric field distribution curves of a gallium oxide-based power device with a conventional single field plate structure terminal, a gallium oxide-based power device with a double field plate structure terminal, and a gallium oxide-based power device with a dielectric layer electric field shielding ring in Example 1.

[0046] Figure 6 The two-dimensional electric field distribution and maximum electric field position simulation results of gallium oxide based power devices with different structures are shown in Figure 1, where (a) is a gallium oxide based power device with a conventional single field plate structure terminal, (b) is a gallium oxide based power device with a double field plate structure, and (c) is a gallium oxide based power device with a dielectric layer electric field shielding ring in Example 1.

[0047] Reference numerals in the accompanying drawings:

[0048] 1. First electrode layer; 2. Gallium oxide substrate; 3. Gallium oxide epitaxial layer; 4. First dielectric layer; 4', first dielectric layer precursor layer; 5. P-type semiconductor layer; 51. First field plate; 52. Second part of the P-type semiconductor layer; 6. P-type semiconductor shielding ring; 7. Second dielectric layer; 8. Second electrode layer; 81. Second field plate; 82. Second part of the second electrode layer; 9. Passivation layer. DETAILED DESCRIPTION

[0049] The present invention provides a gallium oxide-based power device with a dielectric layer electric field shielding ring and a preparation method thereof. To make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail below. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0050] Unless otherwise defined, all technical terms and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0051] The terms used herein such as “vertical”, “horizontal”, “upper”, “lower”, “left”, “right” and similar expressions are for illustrative purposes only and do not represent the only implementations.

[0052] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0053] If there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features.

[0054] An embodiment of the present invention provides a gallium oxide-based power device having a dielectric layer electric field shielding ring, wherein: Figure 1 As shown, the gallium oxide-based power device with a dielectric layer electric field shielding ring comprises a first electrode layer 1, a gallium oxide substrate 2 and a gallium oxide epitaxial layer 3 which are stacked in sequence from bottom to top;

[0055] The gallium oxide-based power device having a dielectric layer electric field shielding ring further comprises:

[0056] A first dielectric layer 4, located on the surface of the gallium oxide epitaxial layer 3;

[0057] A p-type semiconductor layer 5 is continuously disposed on the surface of the gallium oxide epitaxial layer 3 and a portion of the surface of the first dielectric layer 4, and a portion of the p-type semiconductor layer 5 disposed on the portion of the surface of the first dielectric layer 4 is a first field plate 51;

[0058] A p-type semiconductor shielding ring 6, located on a portion of the surface of the first dielectric layer 4 and spaced apart from the first field plate 51;

[0059] A second dielectric layer 7 is continuously disposed on the surface of the first dielectric layer 4 , the surface of the p-type semiconductor shielding ring 6 , and a portion of the surface of the first field plate 51 ;

[0060] The second electrode layer 8 is continuously located on the surface of the p-type semiconductor layer 5 and on a portion of the surface of the second dielectric layer 7 . The portion of the second electrode layer 8 located on the portion of the surface of the second dielectric layer 7 is the second field plate 81 .

[0061] The present invention introduces a double-layer field plate structure in a gallium oxide-based power device, and forms a first field plate structure by extending the p-type semiconductor layer to the surface of the first dielectric layer to suppress the electric field concentration phenomenon at the interface edge between the p-type semiconductor layer and the gallium oxide epitaxial layer, thereby reducing the electric field peak. By extending the second electrode layer to the surface of the second dielectric layer to form a second field plate structure, the electric field concentration on the surface of the first dielectric layer and the gallium oxide epitaxial layer below the edge of the first field plate structure can be suppressed. Therefore, the double-layer field plate structure can optimize the terminal electric field distribution, reduce the electric field peak, and increase the device breakdown voltage. Furthermore, by introducing a p-type semiconductor shielding ring structure to shield the high electric field in the dielectric layer, the electric field peak in the dielectric layer can be effectively reduced, the occurrence of premature breakdown of the dielectric layer can be suppressed, and the device breakdown voltage can be further increased.

[0062] In the embodiment of the present invention, Figure 1 As shown, the p-type semiconductor layer 5 is continuously located on the surface of the gallium oxide epitaxial layer 3 and on a portion of the surface of the first dielectric layer 4. That is, the p-type semiconductor layer 5 includes two parts, namely a first part and a second part, wherein the first part of the p-type semiconductor layer, namely the first field plate 51, is located on a portion of the surface of the first dielectric layer 4 (the portion of the surface mentioned in the present invention refers to not the entire surface), and the second part 52 of the p-type semiconductor layer is located on the surface of the gallium oxide epitaxial layer 3. Specifically, in the left-right direction, the second part 52 of the p-type semiconductor layer is connected to the first dielectric layer 4.

[0063] The second electrode layer 8 is continuously located on the surface of the p-type semiconductor layer 5 and on a portion of the surface of the second dielectric layer 7. That is, the second electrode layer 8 includes two parts, namely, a first part and a second part, the first part of the second electrode layer, namely, the second field plate 81, is located on a portion of the surface of the second dielectric layer 7, and the second part 82 of the second electrode layer is located on the surface of the p-type semiconductor layer 5. Specifically, in the left-right direction, the second part 82 of the second electrode layer is connected to the second dielectric layer 7.

[0064] In some embodiments, the gallium oxide substrate has a thickness of 50 to 650 μm, for example, 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm or 650 μm.

[0065] In some embodiments, the gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration (ie, electron concentration) of 10 18 ~10 20 cm -3 , the doping element is at least one of Si and Sn.

[0066] In some embodiments, the gallium oxide epitaxial layer has a thickness of 2 to 20 μm, for example, 2 μm, 3 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm or 20 μm.

[0067] In some embodiments, the gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer, and the doping concentration (ie, the electron concentration) is 10 15 ~10 17 cm -3 , the doping element is at least one of Si and Sn.

[0068] In some embodiments, the thickness of the first dielectric layer is 100 nm to 1 μm, for example, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm or 1 μm, etc. Figure 1 The thickness in the vertical direction shown in the figure is as follows: Figure 1 Thickness in the up and down direction as shown.

[0069] In some embodiments, a material of the first dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide, and hafnium dioxide, but is not limited thereto.

[0070] In some embodiments, the thickness of the second dielectric layer is 300 nm to 2 μm (i.e., the thickness of each part of the second dielectric layer is within this range), for example, it can be 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm or 2 μm, etc.

[0071] In some embodiments, a material of the second dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide, and hafnium dioxide, but is not limited thereto.

[0072] In some embodiments, the material of the first electrode layer includes at least one of Ti, Ni, Ag and Au, but is not limited thereto. In some specific embodiments, the first electrode layer is composed of a stacked Ti layer and an Au layer, or the first electrode layer is composed of a stacked Ti layer and an Ag layer, or the first electrode layer is composed of a stacked Ti layer, a Ni layer and an Ag layer.

[0073] In some embodiments, the thickness of the first electrode layer is 250 nm to 2 μm. For example, it can be 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm or 2 μm, etc.

[0074] In some embodiments, the material of the second electrode layer includes Ni, Mo, W, Pt, PtO x In some specific embodiments, the second electrode layer is composed of a stacked Ni layer and an Al layer, and further, the Ni layer can be replaced by a Mo layer, a W layer, a Pt layer or a PtO x layer, the Al layer can be replaced by an Au layer or an Ag layer.

[0075] In some embodiments, the thickness of the second electrode layer is 250 nm to 5 μm. For example, it can be 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, 3 μm, 3.2 μm, 3.5 μm, 3.8 μm, 4 μm, 4.2 μm, 4.5 μm, 4.8 μm or 5 μm, etc.

[0076] In some embodiments, the thickness of the p-type semiconductor layer is 100-600 nm (i.e., the thickness of the first part and the second part of the p-type semiconductor layer are both within the range, and the thickness of the first part and the second part of the p-type semiconductor layer can be the same or different), for example, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm or 600 nm. The hole concentration in the p-type semiconductor layer is 10 16 ~10 19 cm -3 .

[0077] In some embodiments, the p-type semiconductor layer includes at least one of p-type NiO, p-type Cu2O, p-type gallium oxide, and p-type diamond, but is not limited thereto.

[0078] In some embodiments, the thickness of the p-type semiconductor shielding ring is 100-600 nm, for example, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm or 600 nm. The hole concentration in the p-type semiconductor shielding ring is 10 16 ~10 19 cm -3 .

[0079] In some embodiments, the p-type semiconductor shielding ring includes at least one of p-type NiO, p-type Cu2O, p-type gallium oxide, and p-type diamond, but is not limited thereto.

[0080] In some embodiments, when in a first direction on a horizontal plane, the width of the p-type semiconductor layer is the same as the width of the first dielectric layer and the width of the p-type semiconductor shielding ring, then in a direction perpendicular to the first direction on the horizontal plane:

[0081] The width of the first field plate is 3-20 μm, for example, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm or 20 μm;

[0082] The width of the p-type semiconductor shielding ring is 3-10 μm, for example, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm.

[0083] Specifically, Figure 1 Taking the structure shown in FIG. 1 as an example, the horizontal plane is the plane where the front-to-back direction (the direction perpendicular to the paper surface) and the left-to-right direction are located. In the front-to-back direction, the width of the p-type semiconductor layer is the same as the width of the first dielectric layer and the width of the p-type semiconductor shielding ring. At this time, in the left-to-right direction perpendicular to the front-to-back direction, the width L1 of the first field plate is 3 to 20 μm.

[0084] The width L2 of the p-type semiconductor shield ring is 3 to 10 μm.

[0085] In some embodiments, the projection of the second electrode layer on the gallium oxide epitaxial layer covers the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer; or, the projection of the second electrode layer on the gallium oxide epitaxial layer coincides with the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer.

[0086] Specifically, Figure 1As shown, the rightmost end of the projection of the second electrode layer on the gallium oxide epitaxial layer covers the rightmost end of the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer. In this way, the second field plate can better suppress the electric field concentration on the surface of the first dielectric layer and the gallium oxide epitaxial layer below the edge of the first field plate.

[0087] Drawing on the working principle of the field confinement ring structure in Si-based or SiC-based power devices, although the guard ring structure of other p-type oxides (such as p-NiO) can be applied to gallium oxide-based power devices, in the blocking state, the guard ring provides holes to assist the expansion of the depletion layer in the terminal region, suppress the electric field peak in the terminal region, and improve the device's withstand voltage. However, unlike Si or SiC, the critical breakdown field strength of gallium oxide materials is higher, so the electron concentration of the device epitaxial layer is higher at the same voltage level. In order to achieve good results, the size of the guard ring needs to be more finely designed, and the spacing between adjacent guard rings also needs to be closer, usually less than 1μm, so the device processing is more difficult. Based on this, in some specific embodiments of the present invention, the projection of the end of the second field plate away from the first field plate on the gallium oxide epitaxial layer is located in the projection of the p-type semiconductor shielding ring on the gallium oxide epitaxial layer. Specifically, if Figure 1 As shown, the projection of the rightmost end of the second field plate 81 on the gallium oxide epitaxial layer 3 is located between the projection of the leftmost end of the p-type semiconductor shielding ring 6 on the gallium oxide epitaxial layer 3 and the projection of the rightmost end of the p-type semiconductor shielding ring 6 on the gallium oxide epitaxial layer 3. That is, the projection of the rightmost end of the second field plate 81 on the p-type semiconductor shielding ring 6 is located between the leftmost end of the p-type semiconductor shielding ring and the rightmost end of the p-type semiconductor shielding ring. In this way, the second field plate structure can promote the depletion of the region between the p-type semiconductor layer and the p-type semiconductor shielding ring, so that the p-type semiconductor layer and the p-type semiconductor shielding ring can still play a good role at a large spacing, reducing the dependence of the device on the processing size and improving the device yield. In other words, the combination of the field plate structure and the shielding ring structure can make the shielding ring in the gallium oxide-based power device provided by the present invention still have an excellent effect under the condition of a wide ring spacing, thereby simplifying the device preparation process. At the same time, the p-type semiconductor shielding ring can effectively shield the electric field peak at the edge of the second field plate, inhibit the occurrence of premature breakdown, and improve the device withstand voltage capability.

[0088] Therefore, in some embodiments, Figure 1 As shown, the distance L3 between the first field plate and the p-type semiconductor shielding ring is 2-10 μm, for example, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm.

[0089] In some embodiments, the gallium oxide-based power device having a dielectric layer electric field shielding ring further includes:

[0090] A passivation layer 9 is continuously located on the surface of the second dielectric layer 7 and on a portion of the surface of the second electrode layer 8 .

[0091] The passivation layer can be set according to actual needs.

[0092] In some embodiments, the material of the passivation layer includes at least one of polyimide (PI), silicon nitride, silicon oxide and SU-8 glue.

[0093] The present invention also provides a method for preparing a gallium oxide-based power device having a dielectric layer electric field shielding ring as described above in the present invention, wherein: Figure 2 As shown, the following steps are included:

[0094] S1, such as Figure 2 As shown in (a), a gallium oxide substrate 2 is provided;

[0095] S2, such as Figure 2 As shown in (a), a gallium oxide epitaxial layer 3 is formed on the surface of the gallium oxide substrate 2;

[0096] S3, such as Figure 2 As shown in (c), a first dielectric layer 4 is formed on the surface of the gallium oxide epitaxial layer 3;

[0097] S4, such as Figure 2 As shown in (d), a p-type semiconductor layer 5 is formed on the surface of the gallium oxide epitaxial layer 3 and on a portion of the surface of the first dielectric layer 4, and the portion of the p-type semiconductor layer 5 located on the portion of the surface of the first dielectric layer 4 is a first field plate 51; a p-type semiconductor shielding ring 6 is formed on the surface of the first dielectric layer 4 and is spaced apart from the first field plate 51;

[0098] S5, such as Figure 2 As shown in (e), a second dielectric layer 7 is formed on the surface of the first dielectric layer 4, the surface of the p-type semiconductor shielding ring 6, and a portion of the surface of the first field plate 51;

[0099] S6, such as Figure 2 As shown in (f), a second electrode layer 8 is formed on the surface of the p-type semiconductor layer 5 and on a portion of the surface of the second dielectric layer 7, and a portion of the second electrode layer 8 located on the portion of the surface of the second dielectric layer 7 is a second field plate 81;

[0100] S7, such as Figure 2 As shown in (g), a passivation layer 9 is formed on the surface of the second dielectric layer 7 and on a portion of the surface of the second electrode layer 8;

[0101] S8, such as Figure 2As shown in (h), a first electrode layer 1 is formed on the side of the gallium oxide substrate 2 away from the gallium oxide epitaxial layer 3 to obtain the gallium oxide-based power device with a dielectric layer electric field shielding ring.

[0102] In the present invention, in steps S1 and S2, a gallium oxide substrate having a gallium oxide epitaxial layer on its surface may be directly provided, and then inorganic and organic cleaning may be performed before the subsequent steps are performed.

[0103] In step S1, the selection of the gallium oxide substrate is specifically described above and will not be repeated here.

[0104] In step S2, the material, thickness, etc. of the gallium oxide epitaxial layer are as described above and will not be described again here.

[0105] In step S3, the material, thickness, etc. of the first dielectric layer are as described above and will not be described again here.

[0106] In some embodiments, the step of forming a first dielectric layer on the surface of the gallium oxide epitaxial layer specifically includes:

[0107] like Figure 2 As shown in (b), a first dielectric layer precursor layer 4' is formed on the surface of the gallium oxide epitaxial layer by a deposition method; wherein the deposition method includes but is not limited to one of a plasma enhanced chemical vapor deposition (PECVD) method, an atomic layer deposition (ALD) method, a low pressure chemical vapor deposition (LPCVD) method, an inductively coupled plasma chemical vapor deposition (ICPCVD) method and a magnetron sputtering method.

[0108] like Figure 2 As shown in (c), photolithography is performed on the surface of the first dielectric layer precursor layer 4', and then the first dielectric layer precursor layer 4' is patterned by dry-wet combined etching or wet etching to obtain the first dielectric layer 4.

[0109] In step S4 , the material and thickness of the p-type semiconductor layer are as described above and will not be described again here.

[0110] In some embodiments, a deposition method (including but not limited to magnetron sputtering deposition, pulsed laser deposition, metal organic chemical vapor deposition, metal thermal oxidation, etc.) may be used to form a p-type semiconductor layer precursor layer (see the case of the first dielectric precursor layer);

[0111] Then, the p-type semiconductor layer precursor layer is patterned by a stripping or etching method to obtain a p-type semiconductor layer and a p-type semiconductor shielding ring.

[0112] For example, when the material of the p-type semiconductor layer and the p-type semiconductor shielding ring is p-type NiO, the p-type NiO precursor layer may be prepared by using a Ni metal thermal oxidation method.

[0113] In step S5, the material and thickness of the second dielectric layer are as described above and will not be described again here.

[0114] The method for forming the second dielectric layer is similar to the method for forming the first dielectric layer.

[0115] In step S6, the material and thickness of the second electrode layer are as described above and will not be described again here.

[0116] Specifically, the deposition is performed by electron beam evaporation or magnetron sputtering, and the second electrode layer is formed by a lift-off process.

[0117] In step S7, the material of the passivation layer is as described above and will not be described again here.

[0118] Specifically, when the material of the passivation layer is PI, a standard PI photolithography process can be used to form the passivation layer.

[0119] In step S8, the material and thickness of the first electrode layer are as described above and will not be described again here.

[0120] The method for forming the first electrode layer is similar to the method for forming the second electrode layer.

[0121] The present invention will be further described below by means of specific examples.

[0122] Example 1

[0123] The embodiment of the present invention provides a gallium oxide-based power device with a dielectric layer electric field shielding ring, wherein the gallium oxide-based power device with a dielectric layer electric field shielding ring comprises a first electrode layer 1, a gallium oxide substrate 2 and a gallium oxide epitaxial layer 3 which are stacked in sequence from bottom to top; wherein the first electrode layer comprises a Ti layer (with a thickness of 100 nm), a Ni layer (with a thickness of 300 nm) and an Ag layer (with a thickness of 1 μm) which are stacked in sequence, and the Ti layer side is bonded to the gallium oxide substrate; the gallium oxide substrate has a thickness of 500 μm, and the gallium oxide substrate is a Sn-doped β-Ga2O3 substrate with an electron concentration of 10 20 cm -3 The thickness of the gallium oxide epitaxial layer is 10 μm. The gallium oxide epitaxial layer is a Si-doped β-Ga2O3 epitaxial layer with an electron concentration of 10 16 cm -3 ;

[0124] The gallium oxide-based power device having a dielectric layer electric field shielding ring further comprises:

[0125] A first dielectric layer 4 is located on the surface of the gallium oxide epitaxial layer 3; the material of the first dielectric layer is silicon nitride (grown by PECVD method), and the thickness of the first dielectric layer is 300 nm;

[0126] The p-type semiconductor layer 5 is continuously located on the surface of the gallium oxide epitaxial layer 3 and on a part of the surface of the first dielectric layer 4. The part of the p-type semiconductor layer 5 located on the part of the surface of the first dielectric layer 4 is the first field plate 51. The thickness of the p-type semiconductor layer is 500nm (that is, the thickness of the second part 52 of the p-type semiconductor layer and the first field plate 51 are both 500nm; the thickness of the part where the second part 52 of the p-type semiconductor layer is connected to the first dielectric layer in the left and right directions is also 500nm). The p-type semiconductor layer is a p-type NiO layer with a hole concentration of 10 18 cm -3 ; The width L1 of the first field plate is 10 μm;

[0127] The p-type semiconductor shielding ring 6 is located on the surface of the first dielectric layer 4 and is spaced apart from the first field plate 51; the thickness of the p-type semiconductor shielding ring is 500nm, and the width L2 is 5μm; the p-type semiconductor shielding ring is a p-type NiO layer; the spacing L3 between the first field plate and the p-type semiconductor shielding ring is 5μm;

[0128] The second dielectric layer 7 is continuously located on the surface of the first dielectric layer 4, the surface of the p-type semiconductor shielding ring 6 and the partial surface of the first field plate 51; in the left-right direction, the first field plate is connected to the portion of the second dielectric layer located on the surface of the first dielectric layer, the thickness of the portion of the second dielectric layer located on the surface of the first dielectric layer is 700nm, the thickness of the portion of the second dielectric layer located on the partial surface of the first field plate and on the p-type semiconductor shielding ring is 350nm, and the material of the second dielectric layer is silicon nitride (grown by PECVD method);

[0129] The second electrode layer 8 is continuously located on the surface of the p-type semiconductor layer 5 and on a part of the surface of the second dielectric layer 7, and the part of the second electrode layer 8 located on the part of the surface of the second dielectric layer 7 is the second field plate 81; the material of the second electrode layer is a stacked Ni layer and an Al layer, the Ni layer is arranged in contact with the surface of the p-type semiconductor layer 5 and the part of the surface of the second dielectric layer 7, and the maximum thickness of the second electrode layer is 3.2 μm (wherein the thickness of the Ni layer is 200 nm, and the thickness of the Al layer is 3 μm); the rightmost end of the projection of the second electrode layer on the gallium oxide epitaxial layer is located in the middle of the projection of the p-type semiconductor shielding ring on the gallium oxide epitaxial layer;

[0130] The passivation layer 9 is located on the surface of the second dielectric layer 7 and part of the surface of the second electrode layer 8; the material of the passivation layer is PI, and the maximum thickness of the passivation layer is 10 μm.

[0131] In Example 1, a gallium oxide power device with a dielectric layer electric field shielding ring (without a passivation layer) is introduced and a gallium oxide-based power device with a conventional single field plate structure terminal (its structural schematic diagram is shown in FIG. Figure 3 As shown, it includes a first electrode layer 1, a gallium oxide substrate 2, a gallium oxide epitaxial layer 3 and a first dielectric layer 4 stacked in sequence from bottom to top, and also includes a p-type semiconductor layer 5 located on the surface of the gallium oxide epitaxial layer 3 and a portion of the surface of the first dielectric layer 4, a second electrode layer 8 located on the surface of the portion of the first dielectric layer 4 and on the surface of the p-type semiconductor layer 5, the portion of the p-type semiconductor layer 5 located on the portion of the surface of the first dielectric layer 4 is a field plate, and the materials of each layer are the same as those in Example 1), a gallium oxide-based power device with a double field plate structure terminal (its structural schematic diagram is shown in Figure 4 As shown, it includes a first electrode layer 1, a gallium oxide substrate 2, a gallium oxide epitaxial layer 3 and a first dielectric layer 4 stacked in sequence from bottom to top, and also includes a p-type semiconductor layer 5 located on the surface of the gallium oxide epitaxial layer 3 and a portion of the surface of the first dielectric layer 4, a second dielectric layer 7 located on the surface of the first dielectric layer 4 and the p-type semiconductor layer 5, and a second electrode layer 8 located on the surface of the p-type semiconductor layer 5 and a portion of the surface of the second dielectric layer 7. The portion of the p-type semiconductor layer 5 located on the portion of the first dielectric layer 4 is a first field plate, and the portion of the second electrode layer 8 located on the portion of the second dielectric layer 7 is a second field plate. The materials of each layer are the same as those in Example 1. The surface electric field distribution diagram at the time of breakdown is shown in FIG. Figure 5 and 6 As shown. Figure 5 As shown, compared with a gallium oxide-based power device with a conventional single field plate structure terminal and a gallium oxide-based power device with a double field plate structure terminal, the terminal structure in Example 1 can achieve a more uniform electric field distribution, and thus a higher breakdown voltage. Figure 6The two-dimensional electric field distribution of the three terminal structures during breakdown is shown. It can be seen that the maximum electric field of the gallium oxide material does not reach its critical breakdown electric field (~8MV) when the single field plate structure terminal and the double field plate structure terminal are broken down, and thus the application advantage of the high critical breakdown electric field of the gallium oxide material cannot be fully utilized. In the structure of the gallium oxide-based power device provided in Example 1 of the present invention, at the time of breakdown, the highest electric field in the gallium oxide reaches its critical breakdown field strength, so the material advantages can be fully utilized. Further, it can be seen that for the single field plate structure terminal, at the time of breakdown, the electric field in the dielectric layer reaches about 12MV / cm (the breakdown electric field of silicon nitride grown by PECVD is about 11.6MV / cm), and the highest electric field in the gallium oxide is only 3MV / cm. For the double field plate structure terminal, at the time of breakdown, the electric field in the dielectric layer (11.75MV / cm) also reaches its critical breakdown electric field, and at this time the electric field in the gallium oxide is also much smaller than its critical breakdown field strength. For the structure of the gallium oxide-based power device provided in Example 1 of the present invention, when the gallium oxide is broken down, it reaches its critical breakdown electric field, and the maximum electric field in the dielectric layer (11.48 MV / cm) is less than its breakdown electric field (11.6 MV / cm). Therefore, this fully demonstrates that the structure provided by the present invention can achieve an effective dielectric layer electric field shielding effect, thereby increasing the breakdown voltage of the device.

[0132] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A gallium oxide-based power device having a dielectric layer electric field shielding ring, characterized in that: The gallium oxide-based power device with a dielectric layer electric field shielding ring comprises a first electrode layer, a gallium oxide substrate and a gallium oxide epitaxial layer stacked in sequence from bottom to top; The gallium oxide-based power device having a dielectric layer electric field shielding ring further comprises: A first dielectric layer, located on the surface of the gallium oxide epitaxial layer; A p-type semiconductor layer is continuously located on the surface of the gallium oxide epitaxial layer and on a portion of the surface of the first dielectric layer, and a portion of the p-type semiconductor layer located on the portion of the surface of the first dielectric layer is a first field plate; A p-type semiconductor shielding ring, located on the surface of the first dielectric layer and spaced apart from the first field plate; A second dielectric layer is continuously disposed on a surface of the first dielectric layer, a surface of the p-type semiconductor shielding ring, and a portion of a surface of the first field plate; The second electrode layer is continuously located on the surface of the p-type semiconductor layer and on a portion of the surface of the second dielectric layer. The portion of the second electrode layer located on the portion of the surface of the second dielectric layer is the second field plate.

2. The gallium oxide-based power device with a dielectric layer electric field shielding ring according to claim 1, characterized in that: The gallium oxide substrate has a thickness of 50 to 650 μm; The gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration of 10 18 ~10 20 cm -3 ; The thickness of the gallium oxide epitaxial layer is 2 to 20 μm; The gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer with a doping concentration of 10 15 ~10 17 cm -3 .

3. The gallium oxide-based power device with a dielectric layer electric field shielding ring according to claim 1, characterized in that: The thickness of the first dielectric layer is 100 nm to 1 μm; the material of the first dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium dioxide; The thickness of the second dielectric layer is 300 nm to 2 μm; the material of the second dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium dioxide.

4. The gallium oxide-based power device with a dielectric layer electric field shielding ring according to claim 1, characterized in that: The material of the first electrode layer includes at least one of Ti, Ni, Ag and Au; The material of the second electrode layer includes Ni, Mo, W, Pt, PtO x , Al, Au and Ag.

5. The gallium oxide-based power device with a dielectric layer electric field shielding ring according to claim 1, characterized in that: The thickness of the p-type semiconductor layer is 100-600 nm; the p-type semiconductor layer includes at least one of p-type NiO, p-type Cu2O, p-type gallium oxide and p-type diamond; The thickness of the p-type semiconductor shielding ring is 100-600 nm; the p-type semiconductor shielding ring includes at least one of p-type NiO, p-type Cu2O, p-type gallium oxide and p-type diamond.

6. The gallium oxide-based power device with a dielectric layer electric field shielding ring according to claim 1, characterized in that: The distance between the first field plate and the p-type semiconductor shielding ring is 2-10 μm.

7. The gallium oxide-based power device with a dielectric layer electric field shielding ring according to claim 1, characterized in that: When in a first direction on a horizontal plane, the width of the p-type semiconductor layer is the same as the width of the first dielectric layer and the width of the p-type semiconductor shielding ring, then in a direction perpendicular to the first direction on the horizontal plane: The width of the first field plate is 3 to 20 μm; The width of the p-type semiconductor shielding ring is 3 to 10 μm.

8. The gallium oxide-based power device with a dielectric layer electric field shielding ring according to claim 1, characterized in that: The projection of the second electrode layer on the gallium oxide epitaxial layer covers the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer; or, the projection of the second electrode layer on the gallium oxide epitaxial layer coincides with the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer.

9. The gallium oxide-based power device with a dielectric layer electric field shielding ring according to claim 8, characterized in that: The projection of one end of the second field plate away from the first field plate on the gallium oxide epitaxial layer is located within the projection of the p-type semiconductor shielding ring on the gallium oxide epitaxial layer; The gallium oxide-based power device having a dielectric layer electric field shielding ring further comprises: A passivation layer is continuously located on the surface of the second dielectric layer and on a portion of the surface of the second electrode layer.

10. A method for preparing a gallium oxide-based power device having a dielectric layer electric field shielding ring according to claim 1, characterized in that: The steps include: providing a gallium oxide substrate; forming a gallium oxide epitaxial layer on the surface of the gallium oxide substrate; forming a first dielectric layer on the surface of the gallium oxide epitaxial layer; forming a p-type semiconductor layer on the surface of the gallium oxide epitaxial layer and on a portion of the surface of the first dielectric layer, wherein the portion of the p-type semiconductor layer located on the portion of the surface of the first dielectric layer is a first field plate; forming a p-type semiconductor shielding ring spaced apart from the first field plate on the surface of the first dielectric layer; forming a second dielectric layer on the surface of the first dielectric layer, on the surface of the p-type semiconductor shielding ring, and on a portion of the surface of the first field plate; forming a second electrode layer on the surface of the p-type semiconductor layer and on a portion of the surface of the second dielectric layer, wherein a portion of the second electrode layer located on the portion of the surface of the second dielectric layer is a second field plate; A first electrode layer is formed on the side of the gallium oxide substrate away from the gallium oxide epitaxial layer to obtain the gallium oxide-based power device with a dielectric layer electric field shielding ring.

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