Formation method of semiconductor structure
By forming a sacrificial layer, trench and vertical auxiliary layer on the substrate of the semiconductor device, and forming a first channel layer in the trench, the performance degradation caused by the short channel effect is solved, and more efficient patterning is achieved Process and performance improvement.
Patent Information
- Application Number
- CN202311016538.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-11
- Publication Date
- 2025-02-25
AI Technical Summary
With the decrease in the feature size of semiconductor devices, short channel effects are more likely to occur, resulting in a decline in device performance, and the prior art is difficult to effectively overcome this problem.
By forming a sacrificial layer on the top of the substrate, trenches are formed in the substrate and sacrificial layer, vertical auxiliary layers are formed on the side walls and bottom of the trench, a first channel layer is formed in the remaining space of the trench, and The first channel layer and the sacrificial layer above the top of the substrate are planarized.
This method improves the performance of the semiconductor structure by forming a vertical auxiliary layer and the first channel layer, increases the process window of the patterned substrate and channel layer, and reduces the process difficulty in the patterning process.
Smart Images
Figure CN119521751A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art
[0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also shortened accordingly. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, so the control ability of the gate structure over the channel becomes worse, and the difficulty of pinching off the channel by the gate voltage becomes increasingly greater, making subthreshold leakage, the so-called short-channel effects (SCE), more likely to occur.
[0003] In order to overcome the short channel effect and promote the development of semiconductor technology in the prior art, different devices use channels of different materials to meet their respective performance requirements. For example, by replacing the channel material with silicon germanium (SiGe) material, since silicon germanium material has a high hole mobility, which is usually 6 to 25 times that of silicon (Si) material, the performance of the device can be greatly improved by using silicon germanium material as the material of the channel region. Summary of the invention
[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to improving the performance of the semiconductor structure.
[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a sacrificial layer on the top of the substrate; forming a groove in the substrate and the sacrificial layer; forming an auxiliary layer on the sidewall and bottom of the groove, the sidewall of the auxiliary layer is perpendicular to the bottom of the auxiliary layer; forming a first channel layer in the remaining space of the groove, the first channel layer covers the sidewall and bottom of the auxiliary layer, and the top of the sacrificial layer; and planarizing the first channel layer and the sacrificial layer above the top of the substrate.
[0006] Optionally, the auxiliary layer and the substrate that are higher than the bottom surface of the trench constitute a second channel layer; the method for forming the semiconductor structure further includes: patterning the first channel layer and the second channel layer to form a fin protruding from the remaining substrate.
[0007] Optionally, after forming the sacrificial layer and before forming the groove, it also includes: forming an etch stop layer on top of the sacrificial layer; the step of forming the groove includes: forming a patterned first mask layer on top of the etch stop layer; patterning the etch stop layer using the first mask layer as a mask, and using the remaining etch stop layer as a second mask layer; removing the first mask layer; using the second mask layer as a mask, sequentially etching the sacrificial layer and the substrate to form a groove in the substrate and the sacrificial layer; and removing the second mask layer.
[0008] Optionally, the material of the etch stop layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride.
[0009] Optionally, the process of forming the groove includes a dry etching process.
[0010] Optionally, the step of forming an auxiliary layer on the sidewall and the bottom of the trench includes: performing a growth process on the bottom and the sidewall of the trench to form the auxiliary layer.
[0011] Optionally, the growth processing process includes an epitaxial process.
[0012] Optionally, the material of the auxiliary layer includes one or both of Si and SiC.
[0013] Optionally, with the direction perpendicular to the sidewall of the groove as the lateral direction, the lateral dimension of the auxiliary layer is 1 nanometer to 10 nanometers.
[0014] Optionally, in the step of providing a substrate, a grinding stop layer is also formed on the top of the substrate; in the step of forming the sacrificial layer, the sacrificial layer covers the grinding stop layer; the step of planarizing the first channel layer above the top of the substrate includes: using the top of the grinding stop layer as a stopping position, and removing the sacrificial layer and the first channel layer above the grinding stop layer.
[0015] Optionally, the process of removing the sacrificial layer and the first channel layer above the grinding stop layer includes a chemical mechanical grinding process.
[0016] Optionally, the material of the grinding stop layer is one or more of silicon oxide, silicon nitride and silicon oxynitride.
[0017] Optionally, after performing the planarization process, the method for forming a semiconductor structure further includes: removing the grinding stop layer.
[0018] Optionally, the process of removing the grinding stop layer includes a wet etching process.
[0019] Optionally, the process of forming the first channel layer in the remaining space of the trench includes an epitaxial growth process.
[0020] Optionally, the material of the first channel layer includes silicon germanium; and the material of the second channel layer includes silicon.
[0021] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0022] An embodiment of the present invention provides a method for forming a semiconductor structure, wherein a sacrificial layer is formed on the top of the substrate, a groove is formed in the substrate and the sacrificial layer, an auxiliary layer is formed on the sidewall and bottom of the groove, the sidewall of the auxiliary layer is perpendicular to the bottom of the auxiliary layer, a first channel layer is formed in the remaining space of the groove, the first channel layer covers the sidewall and bottom of the auxiliary layer and the top of the sacrificial layer, and the first channel layer and the sacrificial layer above the top of the substrate are planarized. In the embodiment of the present invention, by forming the sacrificial layer on the top of the substrate, in the subsequent process of forming the first channel layer, a part of the first channel layer will be formed on the top surface of the sacrificial layer located on the side of the groove, and the first channel layer will not be formed on the top surface of the substrate. Subsequently, by planarizing the sacrificial layer and the first channel layer above the top surface of the substrate, a planarization process can be performed. The first channel layer will not appear on the top of the substrate. Accordingly, in the subsequent process of patterning the substrate and the first channel layer to form a target pattern (for example, a fin), the top surface of the substrate can be completely exposed, thereby increasing the process window for patterning the substrate. At the same time, the side wall of the auxiliary layer is perpendicular to the bottom of the auxiliary layer, that is, the corners of the remaining space of the groove are all right angles, so that the shape of the first channel layer subsequently formed in the remaining space of the groove is square. In the process of patterning the first channel layer to form a target pattern, the entire first channel layer can be used as a patterned object, thereby increasing the process window for patterning the first channel layer. In summary, the process window for patterning the substrate and the first channel layer can be further increased, thereby reducing the process difficulty in the patterning process and further improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figures 1 to 3 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;
[0024] Figures 4 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0025] The performance of the current semiconductor structure needs to be improved. The reasons why the performance needs to be improved are analyzed in combination with a method for forming a semiconductor structure.
[0026] Figures 1 to 3The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.
[0027] refer to Figure 1 , providing a substrate 10, a patterned mask layer 11 is formed on the top of the substrate 10.
[0028] refer to Figure 2 , using the mask layer 11 as a mask, the substrate 10 is patterned to form a groove 12.
[0029] After forming the trench 12, the mask layer 11 is removed.
[0030] refer to Figure 3 , a channel layer 16 is formed in the trench 12 .
[0031] It has been found that in the process of forming the groove 12, due to the performance limitation of the etching equipment, the corner where the side wall and the bottom of the groove 12 are connected is rounded. At the same time, in the process of forming the channel layer 16, part of the channel layer 16 is formed on the top surface of the substrate 10. Accordingly, in the subsequent process of patterning the channel layer 16 and the substrate 10 to form a target pattern (for example, a fin), on the one hand, the substrate 10 covered by the channel layer 16 cannot be used for patterning to form the fin, so that the substrate area that can be patterned becomes smaller, that is, The process window of the patterned substrate 10 is reduced and the difficulty of the patterning process is increased. On the other hand, the channel layer 16 formed at the corner of the groove 12 is rounded, so that the fins formed by subsequent patterning cannot meet the electrical requirements. In order to make the fins formed by the patterned channel layer 16 meet the process requirements, the channel layer 16 at the corner of the groove 12 needs to be discarded, resulting in a smaller area of the channel layer 16 that can be patterned, thereby reducing the process window of the patterned channel layer 16 and increasing the difficulty of the patterning process, thereby affecting the performance of the semiconductor structure.
[0032] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a sacrificial layer on the top of the substrate; forming a groove in the substrate and the sacrificial layer; forming an auxiliary layer on the sidewall and bottom of the groove, the sidewall of the auxiliary layer is perpendicular to the bottom of the auxiliary layer; forming a first channel layer in the remaining space of the groove, the first channel layer covers the sidewall and bottom of the auxiliary layer, and the top of the sacrificial layer; and planarizing the first channel layer and the sacrificial layer that are higher than the top of the substrate.
[0033] In the formation method provided by the embodiment of the present invention, a sacrificial layer is formed on the top of the substrate, a groove is formed in the substrate and the sacrificial layer, an auxiliary layer is formed on the sidewall and bottom of the groove, the sidewall of the auxiliary layer is perpendicular to the bottom of the auxiliary layer, and a first channel layer is formed in the remaining space of the groove, the first channel layer covers the sidewall and bottom of the auxiliary layer and the top of the sacrificial layer, and the first channel layer and the sacrificial layer above the top of the substrate are planarized. In the embodiment of the present invention, by forming the sacrificial layer on the top of the substrate, in the subsequent process of forming the first channel layer, a part of the first channel layer will be formed on the top surface of the sacrificial layer located on the side of the groove, and the first channel layer will not be formed on the top surface of the substrate. Subsequently, by planarizing the sacrificial layer and the first channel layer above the top surface of the substrate, the substrate can be made flat. The first channel layer will not appear on the top. Accordingly, in the subsequent process of patterning the substrate and the first channel layer to form a target pattern (for example, a fin), the top surface of the substrate can be completely exposed, thereby increasing the process window for patterning the substrate. At the same time, the side wall of the auxiliary layer is perpendicular to the bottom of the auxiliary layer, that is, the corners of the remaining space of the groove are all right angles, so that the shape of the first channel layer subsequently formed in the remaining space of the groove is square. In the process of patterning the first channel layer to form a target pattern, the entire first channel layer can be used as a patterned object, thereby increasing the process window for patterning the first channel layer. In summary, the process window for patterning the substrate and the first channel layer can be further increased, thereby reducing the process difficulty in the patterning process and further improving the performance of the semiconductor structure.
[0034] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0035] Figures 4 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0036] refer to Figure 4 , providing a substrate 100.
[0037] The substrate 100 provides a process platform for subsequent process steps.
[0038] In this embodiment, the substrate 100 is a silicon substrate 100. In other embodiments, the material of the substrate 100 may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate 100 may also be other types of substrates 100 such as a silicon substrate 100 on an insulator or a germanium substrate 100 on an insulator. The material of the substrate 100 may be a material suitable for process requirements or easy to integrate.
[0039] In this embodiment, the substrate 100 includes a region for forming a first-type transistor and a region for forming a second-type transistor. Specifically, the first-type transistor is an NMOS transistor, and the second-type transistor is a PMOS transistor. In other embodiments, the first-type transistor is a PMOS transistor, and the second-type transistor is an NMOS transistor.
[0040] It should be noted that the material of the substrate 100 is silicon, and the use of Si channel technology for NMOS transistors is beneficial to improving the performance of NMOS transistors, that is, improving the carrier mobility of NMOS transistors.
[0041] In this embodiment, in the step of providing the substrate 100 , a grinding stop layer 101 is further formed on the top of the substrate 100 .
[0042] After the first channel layer and the sacrificial layer are subsequently formed, during the process of planarizing the first channel layer and the sacrificial layer that are higher than the top of the substrate 100, the top of the grinding stop layer 101 plays a grinding stop role, thereby improving the flatness of the remaining first channel layer and the top surface of the substrate 100, providing a process basis for the subsequent graphic processing of the first channel layer and the substrate 100, and at the same time, reducing the probability of over-grinding during the planarization process, so that the overall height of the remaining first channel layer meets the process requirements, thereby improving the performance of the semiconductor structure.
[0043] In this embodiment, the material of the grinding stop layer 101 is one or more of silicon oxide, silicon nitride and silicon oxynitride.
[0044] Silicon oxide, silicon nitride and silicon oxynitride are all dielectric material layers, and have a higher grinding selectivity ratio with the material selected for the first channel layer to be formed subsequently. Accordingly, in the process of planarizing the first channel layer and the sacrificial layer above the top of the substrate 100, the top of the grinding stop layer 101 can play a grinding stop role, thereby reducing the probability of over-grinding during the planarization process, thereby improving the performance of the semiconductor structure.
[0045] refer to Figure 5 , a sacrificial layer 102 is formed on the top of the substrate 100 .
[0046] It should be noted that, by forming a sacrificial layer 102 on the top of the substrate 100, in the subsequent process of forming the first channel layer, a portion of the first channel layer will be formed on the top surface of the sacrificial layer 102 located on the side of the groove, and the first channel layer will not be formed on the top surface of the substrate 100. Subsequently, by planarizing the sacrificial layer 102 and the first channel layer that are higher than the top surface of the substrate 100, the first channel layer will not appear on the top of the substrate 100. Accordingly, in the subsequent process of patterning the substrate 100 and the first channel layer to form a target pattern (for example, a fin), the top surface of the substrate 100 can be completely exposed, thereby enlarging the process window for patterning the substrate 100.
[0047] In this embodiment, in the step of forming the sacrificial layer 102 , the sacrificial layer 102 covers the grinding stop layer 101 .
[0048] Specifically, the sacrificial layer 102 covers the grinding stop layer 101. In the subsequent process of planarizing the sacrificial layer 102, the grinding stop layer 101 at the bottom of the sacrificial layer 102 can play a grinding stop role, thereby completely removing the sacrificial layer 102 and reducing the probability of the sacrificial layer 102 remaining on the top of the substrate 100.
[0049] In this embodiment, the material of the sacrificial layer 102 includes amorphous silicon.
[0050] Amorphous silicon has a high etching selectivity ratio with the material used for the subsequently formed etch stop layer. In the subsequent process of patterning the sacrificial layer 102 using the etch stop layer as a mask, the accuracy of the patterning transfer is improved, so that the morphology quality of the groove sidewalls subsequently formed in the sacrificial layer 102 is high, thereby providing a process basis for the subsequent growth process on the groove sidewalls to form an auxiliary layer.
[0051] Continue to refer Figure 5 After forming the sacrificial layer 102 and before subsequently forming the trench, the method further includes: forming an etch stop layer 103 on the top of the sacrificial layer 102 .
[0052] Specifically, in the subsequent process of forming the grooves, the etch stop layer 103 is used as an etching mask and can also serve as an etching stop, thereby reducing the probability of over-etching during the process of forming the grooves, so that the depths of the multiple grooves formed in the substrate 100 are consistent, thereby making the height of the first channel layer subsequently formed in the grooves consistent, and further, after the first channel layer is subsequently patterned to form the fins, the height of the fins is consistent, thereby improving the performance of the semiconductor structure.
[0053] In this embodiment, the material of the etch stop layer 103 includes one or more of silicon oxide, silicon nitride and silicon oxynitride.
[0054] Silicon oxide, silicon nitride and silicon oxynitride are all dielectric material layers. Silicon oxide, silicon nitride and silicon oxynitride have a higher etching selectivity ratio with the material selected for the sacrificial layer 102 and the material selected for the substrate 100. Accordingly, in the subsequent process of forming the groove, the etch stop layer 103 can be used as an etching mask and can also serve as an etching stop.
[0055] refer to Figures 6 to 8 , trenches 106 are formed in the substrate 100 and the sacrificial layer 102 .
[0056] The groove 106 provides a spatial location for the subsequent formation of a first channel layer and an auxiliary layer. Meanwhile, during the subsequent growth process at the bottom and sidewall of the groove 106 , the groove 106 provides a process window for the growth process.
[0057] In this embodiment, the step of forming the groove 106 includes: forming a patterned first mask layer 105 on the top of the etch stop layer 103; patterning the etch stop layer 103 using the first mask layer 105 as a mask, and using the remaining etch stop layer 103 as a second mask layer; removing the first mask layer 105; using the second mask layer as a mask, etching the sacrificial layer 102 and the substrate 100 in sequence to form a groove 106 in the substrate 100 and the sacrificial layer 102.
[0058] Specifically, the etch stop layer 103 is patterned using the first mask layer 105 as a mask, so that the etch stop layer 103 serves as an etching mask for the patterned substrate 100 and the sacrificial layer 102, thereby reducing the probability of over-etching during the formation of the groove 106, so that the depths of the multiple grooves 106 formed in the substrate 100 are consistent.
[0059] In this embodiment, the process of forming the trench 106 includes a dry etching process.
[0060] Specifically, the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, and its longitudinal etching rate is much greater than the lateral etching rate. In the process of forming the groove 106 in the substrate 100 and the sacrificial layer 102, the dry etching process has the characteristics of high graphic transfer accuracy, which improves the formation quality of the groove side wall, provides a process basis for the subsequent growth process to form an auxiliary layer, and at the same time, reduces the probability of damage to the substrate 100 on the side wall of the groove 106.
[0061] As an example, the substrate 100 on both sides of the trench 106 is located in a region where the first transistor is formed, and the trench 106 is located in a region where the second-type transistor is formed.
[0062] It should be noted that, after forming the trench 106 , the method for forming the semiconductor structure further includes: removing the second mask layer.
[0063] The process of removing the second mask layer includes a wet etching process.
[0064] refer to Fig. 9 , an auxiliary layer 110 is formed on the sidewall and bottom of the trench 106 , and the sidewall of the auxiliary layer 110 is perpendicular to the bottom of the auxiliary layer 110 .
[0065] It should be noted that the side walls of the auxiliary layer 110 are perpendicular to the bottom of the auxiliary layer 110, that is, the corners of the remaining space of the groove 106 are all right angles, so that the shape of the first channel layer subsequently formed in the remaining space of the groove 106 is square. In the process of patterning the first channel layer to form a target pattern, the entire first channel layer can be used as a patterned object, thereby enlarging the process window for patterning the first channel layer. While increasing the process window of the patterned substrate 100, the process window of the patterned first channel layer can also be further increased, thereby reducing the process difficulty in the patterning process and further improving the performance of the semiconductor structure.
[0066] In this embodiment, the step of forming the auxiliary layer 110 on the sidewall and the bottom of the trench 106 includes: performing a growth process on the bottom and the sidewall of the trench 106 to form the auxiliary layer 110 .
[0067] Specifically, the auxiliary layer 110 is formed by growth treatment at the bottom and sidewalls of the groove 106 , which can modify the morphology of the bottom and sidewalls of the groove 106 and the corners where the bottom and sidewalls are connected, so that the sidewalls of the auxiliary layer 110 are perpendicular to the bottom of the auxiliary layer 110 .
[0068] In this embodiment, the growth process includes an epitaxial process.
[0069] The epitaxial process is a commonly used process in growth processing, and has the characteristics of high film layer formation quality. At the same time, in the process of forming the auxiliary layer 110 by the epitaxial process, the growth rate of the auxiliary layer 110 at the corner where the bottom and side walls of the groove 106 are connected is relatively slow, and the growth rate at the side walls and bottom of the groove 106 is relatively fast, so that the thickness of the auxiliary layer 110 formed at the side walls and bottom of the groove 106 is greater than the thickness of the auxiliary layer 110 at the corners, thereby enabling the corners of the groove 106 to gradually change from rounded corners to right angles, so that the shape of the first channel layer subsequently formed in the remaining space of the groove 106 is square.
[0070] In this embodiment, the material of the auxiliary layer 110 includes one or both of Si and SiC.
[0071] Specifically, the auxiliary layer 110 is made of Si and SiC. In the process of subsequently forming the first channel layer, it is beneficial to directly grow the first channel layer on the surface of the auxiliary layer 110 through an epitaxial growth process, so that the growth rate of the first channel layer at the bottom and sidewalls of the auxiliary layer 110 can remain unchanged, thereby improving the formation quality of the first channel layer, thereby improving the electrical performance of the subsequently formed fins.
[0072] It should be noted that, with the direction perpendicular to the sidewall of the groove 106 as the lateral direction, the lateral dimension of the auxiliary layer 110 should not be too large or too small. If the lateral dimension of the auxiliary layer 110 is too large, it is easy to cause the lateral dimension of the remaining space of the groove 106 to become smaller, so that the lateral dimension of the first channel layer formed in the groove 106 becomes smaller. Accordingly, in the subsequent process of patterning the first channel layer, the process window of patterning the first channel layer is reduced, and the process difficulty of patterning the first channel layer is increased; if the lateral dimension of the auxiliary layer 110 is too small, since the growth rate of the auxiliary layer 110 at the corner where the bottom and the sidewall of the groove 106 are connected is relatively slow, and the growth rate at the sidewall and the bottom of the groove 106 is relatively fast, it means that the auxiliary layer 110 at the corner of the groove 106 is smaller, so that the trend of the corner of the groove 106 gradually changing from rounded to right-angled is not obvious, that is, the corner of the groove 106 is still rounded, which affects the subsequent patterning process. To this end, in this embodiment, with the direction perpendicular to the sidewall of the trench 106 as the lateral direction, the lateral dimension of the auxiliary layer 110 is 1 nanometer to 10 nanometers.
[0073] In this embodiment, the auxiliary layer 110 and the substrate 100 that are higher than the bottom surface of the trench 106 constitute a second channel layer (not shown).
[0074] By forming the second channel layer with the auxiliary layer 110 and the substrate 100 which are higher than the bottom surface of the groove 106, compared with only using the substrate 100 as the direction of the second channel layer, the process window for subsequent patterning of the second channel layer is increased and the difficulty of the patterning process is reduced.
[0075] In this embodiment, the material of the second channel layer includes silicon.
[0076] Specifically, the auxiliary layer 110 and the substrate 100 above the bottom surface of the trench 106 form a second channel layer, and the second channel layer provides a fin for forming an NMOS transistor. Therefore, the auxiliary layer 110 and the substrate 100 are made of the same material, that is, silicon.
[0077] refer to Fig.10A first channel layer 126 is formed in the remaining space of the trench 106 , and the first channel layer 126 covers the sidewall and the bottom of the auxiliary layer 110 and the top of the sacrificial layer 102 .
[0078] In the subsequent process of the semiconductor structure, the first channel layer 126 provides a process basis for patterning to form a target pattern (eg, a fin).
[0079] Specifically, as an example, the first channel layer 126 is used to provide a fin for the PMOS transistor.
[0080] In this embodiment, the process of forming the first channel layer 126 in the remaining space of the trench 106 includes an epitaxial growth process.
[0081] The epitaxial process has the characteristics of fast growth rate and simple process. In the process of forming the first channel layer 126 by the epitaxial process, the first channel layer 126 can completely fill the remaining space of the groove 106, thereby reducing the probability of generating gaps between the interface between the first channel layer 126 and the auxiliary layer 110, thereby improving the performance of the semiconductor structure.
[0082] In this embodiment, the material of the first channel layer 126 includes germanium silicon.
[0083] Specifically, the first channel layer 126 is used to provide a fin for the PMOS transistor. The material of the first channel layer 126 is silicon germanium. Using SiGe channel technology for the PMOS transistor is beneficial to improving the performance of the PMOS transistor, that is, improving the carrier mobility of the PMOS transistor.
[0084] refer to Fig.11 , the first channel layer 126 and the sacrificial layer 102 which are higher than the top of the substrate 100 are planarized.
[0085] Specifically, the first channel layer 126 and the sacrificial layer 102 that are higher than the top of the substrate 100 are planarized, so that the first channel layer 126 does not appear on the top surface of the substrate 100. Accordingly, in the subsequent process of patterning the substrate 100 and the first channel layer 126 to form a target pattern (for example, a fin), the top surface of the substrate 100 can be completely exposed, which enlarges the process window of patterning the substrate 100. At the same time, the flatness of the remaining first channel layer 126 and the top surface of the substrate 100 is also improved, providing a process basis for the subsequent patterning of the first channel layer 126 and the substrate 100.
[0086] In this embodiment, the step of planarizing the first channel layer 126 above the top of the substrate 100 includes: using the top of the grinding stop layer 101 as a stop position, and removing the sacrificial layer 102 and the first channel layer 126 above the grinding stop layer 101 .
[0087] In this embodiment, the process of removing the sacrificial layer 102 and the first channel layer 126 above the grinding stop layer 101 includes a chemical mechanical grinding process.
[0088] The chemical mechanical polishing process is a commonly used process in the planarization process, which can improve the flatness of the top surface of the remaining first channel layer 126 .
[0089] refer to Fig.12 After the planarization process is performed, the method for forming the semiconductor structure further includes: removing the grinding stop layer 101.
[0090] It should be noted that the grinding stop layer 101 is located on the top of the substrate 100 . By removing the grinding stop layer 101 , the top surface of the substrate 100 is exposed, thereby providing a process window for subsequent patterning of the substrate 100 .
[0091] In this embodiment, the process of removing the grinding stop layer 101 includes a wet etching process.
[0092] The material selected for the grinding stop layer 101 has a high etching selectivity ratio with the materials selected for the substrate 100 and the first channel layer 126. The grinding stop layer 101 can be completely removed under the wet etching process. At the same time, the wet etching process is isotropic etching, and the lateral etching rate of the isotropic etching is much greater than the longitudinal etching rate, which is beneficial to completely remove the grinding stop layer 101 on the top surface of the substrate 100.
[0093] It should also be noted that the grinding stop layer 101 is relatively thin. Therefore, after removing the grinding stop layer 101 , the top surfaces of the first channel layer 126 and the second channel layer can be considered flush, which has little impact on the subsequent patterning of the first channel layer 126 and the second channel layer.
[0094] As an example, after removing the grinding stop layer 101 , the method for forming the semiconductor structure further includes: patterning the first channel layer 126 and the second channel layer to form a fin protruding from the remaining substrate 100 (not shown).
[0095] The fin is used as a conductive channel of the first type transistor and the second type transistor.
[0096] In this embodiment, the process of patterning the first channel layer 126 and the second channel layer to form the fin includes a dry etching process.
[0097] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a sacrificial layer on top of the substrate; forming trenches in the substrate and the sacrificial layer; forming an auxiliary layer on the sidewall and bottom of the trench, wherein the sidewall of the auxiliary layer is perpendicular to the bottom of the auxiliary layer; forming a first channel layer in the remaining space of the groove, wherein the first channel layer covers the sidewall and the bottom of the auxiliary layer and the top of the sacrificial layer; The first channel layer and the sacrificial layer above the top of the substrate are planarized.
2. The method for forming a semiconductor structure according to claim 1, wherein: The auxiliary layer and the substrate which are higher than the bottom surface of the groove constitute a second channel layer; The method for forming a semiconductor structure further includes: patterning the first channel layer and the second channel layer to form a fin protruding from the remaining substrate.
3. The method for forming a semiconductor structure according to claim 1, wherein: After forming the sacrificial layer and before forming the groove, the method further includes: forming an etch stop layer on top of the sacrificial layer; The steps of forming the groove include: forming a patterned first mask layer on top of the etch stop layer; patterning the etch stop layer using the first mask layer as a mask, and using the remaining etch stop layer as a second mask layer; removing the first mask layer; using the second mask layer as a mask, etching the sacrificial layer and the substrate in sequence to form a groove in the substrate and the sacrificial layer; and removing the second mask layer.
4. The method for forming a semiconductor structure according to claim 3, wherein: The material of the etch stop layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride.
5. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the trench includes a dry etching process.
6. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming an auxiliary layer on the sidewall and the bottom of the trench includes: performing a growth process on the bottom and the sidewall of the trench to form the auxiliary layer.
7. The method for forming a semiconductor structure according to claim 6, wherein: The growth process includes an epitaxial process.
8. The method for forming a semiconductor structure according to claim 1, wherein: The material of the auxiliary layer includes one or both of Si and SiC.
9. The method for forming a semiconductor structure according to claim 1, wherein: Taking the direction perpendicular to the sidewall of the groove as the lateral direction, the lateral dimension of the auxiliary layer is 1 nanometer to 10 nanometers.
10. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing a substrate, a grinding stop layer is also formed on the top of the substrate; In the step of forming the sacrificial layer, the sacrificial layer covers the grinding stop layer; The step of planarizing the first channel layer higher than the top of the substrate includes: taking the top of the grinding stop layer as a stop position, and removing the sacrificial layer and the first channel layer higher than the grinding stop layer.
11. The method for forming a semiconductor structure according to claim 10, wherein: The process of removing the sacrificial layer and the first channel layer above the polishing stop layer includes a chemical mechanical polishing process.
12. The method for forming a semiconductor structure according to claim 10, wherein: The material of the grinding stop layer is one or more of silicon oxide, silicon nitride and silicon oxynitride.
13. The method for forming a semiconductor structure according to claim 10, wherein: After the planarization process is performed, the method for forming a semiconductor structure further includes: removing the grinding stop layer.
14. The method for forming a semiconductor structure according to claim 13, wherein: The process of removing the grinding stop layer includes a wet etching process.
15. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the first channel layer in the remaining space of the trench includes an epitaxial growth process.
16. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first channel layer includes germanium silicon; A material of the second channel layer includes silicon.