Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a forming method thereof, and the method comprises the steps: providing a plurality of to-be-processed wafers, each to-be-processed wafer comprises a substrate and a device structure formed on the substrate, and gaps are formed between the device structures; sequentially processing the to-be-processed wafer based on the sequence of parameter groups in a preset parameter set, and forming a deposition layer completely covering the gap on the to-be-processed wafer; the parameter set comprises a plurality of parameter groups, one parameter group corresponds to one group of wafers to be processed, and different parameter groups correspond to different states of the deposition equipment; a sacrificial layer is formed on the deposition layer. According to the scheme, the yield of the semiconductor device can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] In the process of forming semiconductor devices, it is necessary to form uneven device structures on the substrate, so that there are gaps of different sizes between the device structures on the substrate surface. At this time, a deposition process is usually used to fill the gaps and further completely cover the device structures, thereby protecting and isolating the device structures.

[0003] However, in the existing process, the yield rate of semiconductor devices needs to be improved. Summary of the invention

[0004] An embodiment of the present invention provides a semiconductor device and a method for forming the same, so as to improve the yield of the semiconductor device.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor device, comprising:

[0006] Providing a plurality of groups of wafers to be processed, wherein the wafers to be processed include a substrate and a device structure formed on the substrate, wherein gaps are formed between the device structures;

[0007] Based on the order of parameter groups in a preset parameter set, the wafers to be processed are processed in sequence to form a deposition layer that completely covers the gap on the wafers to be processed; the parameter set includes a plurality of parameter groups, one parameter group corresponds to a group of wafers to be processed, and different parameter groups correspond to different states of a deposition device;

[0008] A sacrificial layer is formed on the deposited layer.

[0009] Optionally, the parameter groups in the parameter set are executed cyclically, and each time the parameter groups are executed once in a cycle, a device cleaning process is performed once.

[0010] Optionally, in the step of forming a deposition layer completely covering the gap on the wafer to be processed, the deposition layer is formed by a deposition process; wherein the parameter group at least includes a reaction gas flow rate;

[0011] Among the parameter sets, the reaction gas flow rate increases in sequence with the order of the parameter sets.

[0012] Optionally, in the step of forming a deposition layer completely covering the gap on the wafer to be processed, the deposition layer is formed by a deposition process; wherein the parameter group includes at least a bias power;

[0013] Among the parameter sets, the bias power increases in sequence with the order of the parameter sets.

[0014] Optionally, in the step of forming a deposition layer completely covering the gap on the wafer to be processed, the deposition layer is formed by a deposition process; wherein the parameter group at least includes a deposition time;

[0015] Among the parameter sets, the deposition time increases in sequence with the order of the parameter sets.

[0016] Optionally, the number of parameter groups in the parameter set is 4 to 20.

[0017] Optionally, in the deposition process, the reaction gas is SIH4, and in the parameter group, the side flow rate of the reaction gas is 6 to 15 Sccm, the top flow rate of the reaction gas is 6 to 15 Sccm, the bias power is 1200 to 2000 W, and the deposition time is 110 to 200 S.

[0018] Optionally, after the step of forming a deposition layer completely covering the gap on the wafer to be processed and before the step of forming a sacrificial layer on the deposition layer, the method further includes:

[0019] forming a supplementary deposition layer on the deposition layer;

[0020] The step of forming a sacrificial layer on the deposition layer is specifically to form a sacrificial layer on the supplementary deposition layer.

[0021] Optionally, the device structure includes a gate structure protruding from the substrate and source-drain structures located on both sides of the gate structure, wherein the source-drain structure is located in the substrate and an isolation structure for isolating the device structure is included between adjacent device structures.

[0022] An embodiment of the present invention further provides a semiconductor device, wherein the semiconductor device is formed by the above-mentioned method for forming a semiconductor device.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0024] An embodiment of the present invention provides a semiconductor device and a method for forming the same. The method comprises: providing a plurality of groups of wafers to be processed, wherein the wafers to be processed comprise a substrate and a device structure formed on the substrate, wherein gaps are formed between the device structures; processing the wafers to be processed in sequence based on an order of parameter groups within a preset parameter set, and forming a deposition layer on the wafers to be processed that completely covers the gaps; the parameter set comprises a plurality of parameter groups, one parameter group corresponds to a group of wafers to be processed, and different parameter groups correspond to different states of a deposition device; and forming a sacrificial layer on the deposition layer.

[0025] It can be seen that in the method provided in the embodiment of the present invention, by setting multiple parameter groups in the parameter set, and making different parameter groups correspond to different states of the deposition equipment, at the same time, one parameter group corresponds to a group of wafers to be processed. Therefore, after each group of wafers to be processed is processed, a parameter adjustment can be achieved to adapt to the state change of the deposition equipment, thereby ensuring the surface quality of the deposition layer of each wafer to be processed and improving the yield of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0027] Figures 1 to 3 It is a structural schematic diagram corresponding to each step in a method for forming a semiconductor device;

[0028] Figures 4 to 7 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor device according to an embodiment of the present invention;

[0029] Figure 8 It is a schematic diagram of the structure corresponding to another embodiment of the method for forming a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] As described in the background art, the yield of semiconductor devices formed by the prior art needs to be improved.

[0031] Next, the cause of this problem is analyzed in conjunction with an existing method for forming a semiconductor device.

[0032] refer to Figures 1 to 3 , Figures 1 to 3 It is a structural schematic diagram corresponding to each step in a method for forming a semiconductor device.

[0033] refer to Figure 1, a plurality of groups of wafers to be processed are provided, wherein the wafers to be processed include a substrate 1 and a device structure 2 (shown in a dotted box) formed on the substrate, wherein gaps (areas indicated by arrows L) are formed between the device structures.

[0034] refer to Figure 2 , forming a deposition layer 3 completely covering the gap on the wafer to be processed;

[0035] refer to Figure 3 , a sacrificial layer 4 is formed on the deposited layer.

[0036] However, the inventors found that the yield of semiconductor devices in the above process flow is not high. After further observation and analysis, it is believed that in semiconductor devices, the quality of the surface morphology of the deposition layer 3 shows a certain regularity, that is, every certain number of wafers, the surface morphology quality of the deposition layer will decline to a certain extent, thereby affecting the yield of semiconductor devices. After analysis, the inventors believe that this is because, during the deposition process, after processing a preset number of wafers, an equipment cleaning process is performed, so that the equipment is in a relatively ideal state, and the deposition layer formed thereafter exhibits a good surface morphology quality. However, after processing a certain number of wafers, the state of the equipment changes, resulting in a decrease in the surface morphology quality of the deposition layer of the remaining wafers, which affects the yield of semiconductor devices.

[0037] For example, in the production process of a wafer with a line width (i.e., gate width) greater than 40nm, the surface morphology of the deposited layer of the wafer with low yield is characterized by low quality of the outer area of ​​the deposited layer. After a batch of 25 wafers were processed continuously, the pattern of the wafers with low yield was as follows: the wafers with the above problems were actually the second and third wafers out of every three wafers, among which the yield of the second wafer decreased by about 6%, and the yield of the third wafer decreased by about 15%. At the same time, SEM (Scanning Electron Microscope) analysis showed that the outer area of ​​the deposited layer had a bridging problem between the device structures because the deposited layer failed to completely cover the device structure.

[0038] However, in the wafer processing flow, performing an equipment cleaning process consumes too much time, which makes it unrealistic to perform the equipment cleaning process too frequently to ensure wafer quality.

[0039] In view of this, an embodiment of the present invention provides a semiconductor device and a method for forming the same, the method comprising: providing a plurality of groups of wafers to be processed, the wafers to be processed comprising a substrate, and a device structure formed on the substrate, wherein gaps are formed between the device structures; based on an order of parameter groups within a preset parameter set, processing the wafers to be processed in sequence, and forming a deposition layer on the wafers to be processed that completely covers the gaps; the parameter set comprises a plurality of parameter groups, one parameter group corresponds to a group of wafers to be processed, and different parameter groups correspond to different states of a deposition device; and forming a sacrificial layer on the deposition layer.

[0040] It can be seen that in the method provided in the embodiment of the present invention, by setting multiple parameter groups in the parameter set, and making different parameter groups correspond to different states of the deposition equipment, at the same time, one parameter group corresponds to a group of wafers to be processed. Therefore, after each group of wafers to be processed is processed, a parameter adjustment can be achieved to adapt to the state change of the deposition equipment, thereby ensuring the surface quality of the deposition layer of each wafer to be processed and improving the yield of semiconductor devices.

[0041] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Figures 4 to 7 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor device of the present invention.

[0043] refer to Figure 4 , providing a plurality of groups of wafers to be processed, wherein the wafers to be processed include a substrate 100, and a device structure 200 (shown in a dotted box) formed on the substrate, wherein gaps are formed between the device structures (shown by arrows L in the figure).

[0044] The wafer to be processed may be understood as a semi-finished wafer, which is used to provide a process basis for the formation of semiconductor devices, on which corresponding device structures may be formed, and the gaps L between the device structures are to be covered by subsequent processes.

[0045] In this embodiment, the substrate 100 may be silicon. In other embodiments, the material of the substrate 100 may also be other semiconductor materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate 100 may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0046] A device structure 200 may be formed on the substrate 100, and the device structure may be a device structure of an active device, such as a PMOS transistor, a CMOS transistor, an NMOS transistor, a resistor, a capacitor, or an inductor, etc. It is understood that, on a wafer to be processed, there are usually multiple device structures, and in order to ensure electrical isolation and interference between the device structures, the device structures are usually isolated in space, so that gaps are formed between the device structures to achieve spatial isolation of the device structures.

[0047] In a specific example, the device structure is a MOS device structure, wherein the device structure 200 may include a gate structure 201 protruding from a substrate, and a source-drain structure 202 located on both sides of the gate structure 201, wherein the source-drain structure 202 may be located in the substrate, and within the substrate, between adjacent device structures, an isolation structure 300 for isolating the device structure is also included.

[0048] On a wafer, the size of the gap between different device structures varies based on the wafer layout design. When some device structures are close together, the corresponding gap size is smaller, and when some device structures are far apart, the corresponding gap size is larger. It can be understood that the larger the gap, the greater the corresponding filling difficulty, and accordingly, the higher the requirements for the deposition process.

[0049] In the embodiment of the present invention, the yield problem of semiconductor devices is addressed, and multiple groups of wafers to be processed are provided to ensure the yield of multiple groups of wafers to be processed at the same time. A group of wafers to be processed is a group of wafers to be processed that are processed by a deposition device at one time, and the number of wafers to be processed in a group of wafers to be processed can be one or more, for example, 2, 3 or 4.

[0050] refer to Figure 5 Based on the order of parameter groups in the preset parameter set, the wafer to be processed is processed in sequence to form a deposition layer 400 that completely covers the gap on the wafer to be processed.

[0051] The parameter set includes a plurality of parameter groups, one parameter group corresponds to a group of wafers to be processed, and different parameter groups correspond to different states of the deposition equipment.

[0052] By setting multiple parameter groups in the parameter set and making different parameter groups correspond to different states of the deposition equipment, a parameter adjustment can be achieved after each group of wafers to be processed to adapt to the state changes of the deposition equipment and ensure the surface quality of the subsequent group of wafers to be processed.

[0053] The order of the parameter groups in the parameter set is preset, corresponding to different states of the deposition device. Therefore, in the embodiment of the present invention, the wafers to be processed need to be processed in sequence based on the order of the parameter groups in the preset parameter set. In addition, the parameter set can be pre-configured in the deposition device so that the deposition device can directly realize continuous and uninterrupted processing of the wafers to be processed based on the parameter set.

[0054] Among them, based on the regular changes in the state of the deposition equipment and the changes in the equipment cleaning process cycle, the parameter set corresponds to the process of the deposition equipment from the completion of one cleaning process to the next cleaning process. Accordingly, the parameter group in the parameter set is cyclically executed, and the parameter group is executed once per cycle to execute an equipment cleaning process.

[0055] The deposited layer may be silicon oxide. In some optional examples, the deposited layer may also be silicon nitride, silicon oxynitride, etc.

[0056] In an optional example, the formation process of the deposition layer can adopt a deposition process, such as HDP (high-density plasma chemical vapor deposition). The HDP deposition process has good filling capability, better deposited film characteristics and higher yield, so that a deposition layer covering the gap can be formed quickly and efficiently.

[0057] In an optional example, the parameter group corresponding to the deposition process includes at least a reaction gas flow rate, and in the parameter set, the reaction gas flow rate increases with the order of the parameter groups. This is because, corresponding to multiple groups of wafers to be processed, the later the processing flow is, the greater the probability of the corresponding deposition depression. By adjusting the flow rate of the reaction gas to be larger and larger, so that there are more and more reaction gases in the deposition equipment, the corresponding deposition reactions are also more and more, thereby reducing the probability of deposition depressions in the wafers to be processed in the subsequent process. Among them, in a specific example, the reaction gas can be SIH4, and the corresponding reaction gas flow rate can include a top flow rate (SIH4 TOP) and a side flow rate (SIH4 side). The side flow rate of the reaction gas can be 6 to 15 Sccm, and the top flow rate of the reaction gas can be 6 to 15 Sccm. The specific parameters of the corresponding reaction gas flow rate can be selected within the range while ensuring the corresponding change trend.

[0058] In a specific optional example, within the parameter set, the side flow rate of the reaction gas in each parameter group can be 6Sccm, 8Sccm, 10Sccm, 12Sccm and 14Sccm respectively, and the top flow rate of the reaction gas in each parameter group can be 6Sccm, 8Sccm, 10Sccm, 12Sccm and 14Sccm respectively.

[0059] In a further optional example, the parameter group corresponding to the deposition process includes at least a bias power, and in the parameter set, the bias power increases with the order of the parameter groups. This is because, corresponding to multiple groups of wafers to be processed, the further the processing flow is, the greater the probability of the corresponding deposition depression. By adjusting the bias power to be larger and larger, the deposition reaction in the deposition equipment is more and more sufficient, thereby reducing the probability of deposition depressions in the wafers to be processed in the subsequent process. Among them, in a specific example, the bias power can be 1200~2000W, and the specific parameters of the corresponding bias power can be selected within the range while ensuring the corresponding change trend.

[0060] In a specific optional example, within the parameter set, the bias power of each parameter group may be 1200W, 1400W, 1600W, 1800W and 2000W respectively.

[0061] In a further optional example, the parameter group corresponding to the deposition process includes at least deposition time, and in the parameter set, the deposition time increases with the order of the parameter groups. This is because, corresponding to multiple groups of wafers to be processed, the further the processing flow is, the greater the probability of the corresponding deposition depression. By adjusting the deposition time to be longer and longer, the deposition reaction in the deposition equipment is more and more sufficient, thereby reducing the probability of deposition depressions in the wafers to be processed in the subsequent process. Among them, in a specific example, the deposition time can be 110 to 200S, and the specific parameters of the corresponding deposition time can be selected within the range while ensuring the corresponding change trend.

[0062] In a specific optional example, within the parameter set, the deposition time of each parameter group may be 110S, 130S, 150S, 170S and 190S respectively.

[0063] It is understandable that, based on the embodiments of the present invention, the parameters can be adjusted based on the state of the equipment, so as to maximize the processing quality of the wafers to be processed. In the embodiments of the present invention, the number of processing times of the wafers to be processed between adjacent equipment cleaning processes can also be increased accordingly, and accordingly, the number of parameter groups in the parameter set can also be increased accordingly. In a specific example, the number of parameter groups in the parameter set can be 4 to 20, for example, 4, 8, 12 or 16, and the present invention does not make specific limitations here.

[0064] In a specific example, the reaction gas may further include O2 and PH3.

[0065] Among them, the flow rate of O2 can be 40-80 Sccm. In the parameter set, the flow rate of O2 in each parameter group can be, for example, 40 Sccm, 50 Sccm, 60 Sccm, 70 Sccm and 80 Sccm in sequence, and the present invention does not make any specific limitation here.

[0066] The top flow rate of PH3 can be 1.5-3 Sccm, and the side flow rate can be 1.5-3 Sccm. The corresponding parameter settings can be selected by referring to the above method, and the present invention does not make specific limitations here.

[0067] refer to Figure 6 , a sacrificial layer 500 is formed on the deposition layer.

[0068] The sacrificial layer is used to further protect and isolate the device structure, wherein the sacrificial layer has a flat surface. The sacrificial layer can be formed by a deposition process, specifically, the deposition process can be PETEOS (plasma enhanced tetraethyl orthosilicate deposition), and accordingly, the material of the sacrificial layer can be one or more of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0069] Specifically, in order to form a flat surface of the sacrificial layer, the process of forming the sacrificial layer may include:

[0070] A sacrificial material layer is formed on the deposition layer, wherein the thickness of the sacrificial material layer is greater than the thickness of the sacrificial layer; and an excess thickness of the sacrificial material layer is removed by grinding to form the sacrificial layer.

[0071] The sacrificial material layer provides a process basis for forming the sacrificial layer. Accordingly, the material of the sacrificial material layer is the same as the material of the sacrificial layer.

[0072] It is understandable that, since the surface of the wafer to be processed has a device structure, the corresponding surface morphology is uneven, and the deposited layer formed on this basis is usually not completely flat, and the sacrificial material layer formed on this basis is also not completely flat.

[0073] Therefore, in the embodiment of the present invention, the thickness of the sacrificial material layer formed first is greater than the thickness of the sacrificial layer formed subsequently, so that a portion of the thickness of the sacrificial material layer can be removed based on the grinding process to form a sacrificial layer with a flat surface.

[0074] Among them, the excess thickness refers to the difference between the thickness of the preset sacrificial layer and the thickness of the formed sacrificial material layer. Based on the characteristics of the grinding process, a flat surface can be formed. The embodiment of the present invention can use the grinding process to form a sacrificial layer with a flat surface.

[0075] It can be seen that in the method provided in the embodiment of the present invention, by setting multiple parameter groups in the parameter set, and making different parameter groups correspond to different states of the deposition equipment, at the same time, one parameter group corresponds to a group of wafers to be processed. Therefore, after each group of wafers to be processed is processed, a parameter adjustment can be achieved to adapt to the state change of the deposition equipment, thereby ensuring the surface quality of the deposition layer of each wafer to be processed and improving the yield of semiconductor devices.

[0076] It should be noted that the embodiments of the present invention can achieve good filling even for gaps with a size greater than 40 nm.

[0077] It can be understood that in the HDP deposition process, the film growth rate is slow, about 1800 to 4000A / min. Correspondingly, the speed of processing wafers is slow, and the WPH (wafer per hour) is relatively small. In the process of producing a film with a thickness of about 5000A, the WPH is usually less than 3. The embodiment of the present invention can increase the WPH and improve the processing speed of the wafer.

[0078] In a further embodiment of the present invention, a supplementary deposition layer is further formed on the deposition layer to further protect and isolate the device structure and improve the yield of the device structure. Specifically, in an embodiment of the present invention, after the step of forming a deposition layer completely covering the gap on the wafer to be processed, the method further includes:

[0079] refer to Figure 7 , forming a supplementary deposition layer 600 on the deposition layer;

[0080] The supplementary deposition layer may be, for example, silicon oxide, and defects such as depressions that may occur during the deposition layer formation process may be corrected by further forming the supplementary deposition layer. The material of the supplementary deposition layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride, and the like.

[0081] Specifically, the supplementary deposition layer can be formed by a deposition process, and the deposition process can be, for example, HARPTEOS (high aspect ratio tetraethyl orthosilicate deposition). HARPTEOS has excellent filling ability and extensibility, so that both larger and smaller gaps can be better and more fully filled.

[0082] Accordingly, in the example of forming a supplementary deposition layer, the step of forming a sacrificial layer on the deposition layer is specifically referred to as Figure 8 , a sacrificial layer 500 is formed on the supplementary deposition layer 600 .

[0083] In another embodiment of the present invention, a semiconductor device is further provided. The semiconductor device is formed based on the method for forming the semiconductor device provided in the above embodiment, wherein, with reference to Figure 8 , the semiconductor device comprises:

[0084] A substrate 100 and a device structure formed on the substrate, wherein gaps are formed between the device structures (as indicated by arrows L in the figure).

[0085] In this embodiment, the substrate 100 may be silicon. In other embodiments, the material of the substrate 100 may also be other semiconductor materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate 100 may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0086] A device structure may be formed on the substrate 100, and the device structure may be a device structure of an active device, such as a PMOS transistor, a CMOS transistor, an NMOS transistor, a resistor, a capacitor, or an inductor, etc. It can be understood that the number of device structures is usually multiple, and in order to ensure electrical isolation and interference between device structures, the device structures are usually isolated in space, so that gaps are formed between the device structures to achieve spatial isolation of the device structures.

[0087] In a specific example, the device structure is a MOS device structure, wherein the device structure may include a gate structure 201 protruding from a substrate, and a source-drain structure 202 located on both sides of the gate structure 201, wherein the source-drain structure 202 may be located in the substrate, and within the substrate, between adjacent device structures, an isolation structure 300 for isolating the device structure is also included.

[0088] The size of the gap between different device structures varies based on the layout design of the wafer. When some device structures are close together, the corresponding gap size is smaller, and when some device structures are far apart, the corresponding gap size is larger. It can be understood that the larger the gap, the greater the corresponding filling difficulty, and accordingly, the higher the requirements for the deposition process.

[0089] The semiconductor device further includes a deposition layer 400 that completely covers the gap. The deposition layer may be silicon oxide. In some optional examples, the deposition layer may also be silicon nitride, silicon oxynitride, etc.

[0090] The deposition layer 400 may further include a sacrificial layer 500 , and the material of the sacrificial layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride, and the like.

[0091] In some optional examples, the deposition layer may further include a supplementary deposition layer 600. The material of the supplementary deposition layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride, etc. Specifically, the supplementary deposition layer is located between the deposition layer and the sacrificial layer.

[0092] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0093] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor device, characterized in that: include: Providing a plurality of groups of wafers to be processed, wherein the wafers to be processed include a substrate and a device structure formed on the substrate, wherein gaps are formed between the device structures; Based on the order of parameter groups in a preset parameter set, the wafers to be processed are processed in sequence to form a deposition layer that completely covers the gap on the wafers to be processed; the parameter set includes a plurality of parameter groups, one parameter group corresponds to a group of wafers to be processed, and different parameter groups correspond to different states of a deposition device; A sacrificial layer is formed on the deposited layer.

2. The method for forming a semiconductor device according to claim 1, wherein: The parameter groups in the parameter set are executed cyclically, and each time the parameter groups are executed once in a cycle, a device cleaning process is performed.

3. The method for forming a semiconductor device according to claim 2, wherein: In the step of forming a deposition layer completely covering the gap on the wafer to be processed, the deposition layer is formed by a deposition process; wherein the parameter group at least includes a reaction gas flow rate; Among the parameter sets, the reaction gas flow rate increases in sequence with the order of the parameter sets.

4. The method for forming a semiconductor device according to claim 2, wherein: In the step of forming a deposition layer completely covering the gap on the wafer to be processed, the deposition layer is formed by a deposition process; wherein the parameter group includes at least a bias power; Among the parameter sets, the bias power increases in sequence with the order of the parameter sets.

5. The method for forming a semiconductor device according to claim 2, wherein: In the step of forming a deposition layer completely covering the gap on the wafer to be processed, the deposition layer is formed by a deposition process; wherein the parameter group at least includes a deposition time; Among the parameter sets, the deposition time increases in sequence with the order of the parameter sets.

6. The method for forming a semiconductor device according to claim 2, wherein: The number of parameter groups in the parameter set is 4 to 20.

7. The method for forming a semiconductor device according to claim 3, wherein: In the deposition process, the reaction gas is SIH4, in the parameter group, the side flow rate of the reaction gas is 6 to 15 Sccm, the top flow rate of the reaction gas is 6 to 15 Sccm, the bias power is 1200 to 2000 W, and the deposition time is 110 to 200 S.

8. The method for forming a semiconductor device according to claim 1, wherein: After the step of forming a deposition layer completely covering the gap on the wafer to be processed and before the step of forming a sacrificial layer on the deposition layer, the method further includes: forming a supplementary deposition layer on the deposition layer; The step of forming a sacrificial layer on the deposition layer is specifically to form a sacrificial layer on the supplementary deposition layer.

9. The method for forming a semiconductor device according to claim 1, wherein: The device structure includes a gate structure protruding from a substrate and source-drain structures located on both sides of the gate structure, wherein the source-drain structure is located in the substrate and an isolation structure for isolating the device structure is included between adjacent device structures.

10. A semiconductor device, characterized in that: The semiconductor device is formed by the method for forming a semiconductor device according to any one of claims 1 to 9.

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