Integrated circuit device and method of forming same

Abstract

Integrated circuit devices and methods of forming the same are provided. As an example, an integrated circuit device may include: a substrate; a first transistor structure on the substrate; a second transistor structure stacked on the first transistor structure in a vertical direction; an isolation layer between the first transistor structure and the second transistor structure in the vertical direction; and a diode structure on the substrate and adjacent to the first transistor structure in a horizontal direction. The diode structure may be part of a discharge path between the gate electrode of the second transistor structure and the substrate. The discharge path may extend through the isolation layer.

Description

Technical Field

[0001] The present disclosure relates generally to the field of integrated circuit devices, and more particularly, to three-dimensional integrated circuit devices including stacked transistors. Background Art

[0002] Various structures of integrated circuit devices including stacked transistors and methods of forming the same have been proposed for reliable isolation between elements of the stacked transistors (eg, stacked source / drain regions or stacked gate electrodes). Summary of the invention

[0003] According to some embodiments of the present inventive concept, an integrated circuit device may include: a substrate; a first transistor structure on the substrate; a second transistor structure stacked on the first transistor structure in a vertical direction; an isolation layer between the first transistor structure and the second transistor structure in a vertical direction; and a diode structure on the substrate and adjacent to the first transistor structure in a horizontal direction. The diode structure may be part of a discharge path between a gate electrode of the second transistor structure and the substrate. The discharge path may extend through the isolation layer.

[0004] According to some embodiments of the present invention, an integrated circuit device may include a substrate and a stacked structure. The stacked structure may include: a first transistor structure, on the substrate and including a first source / drain region having a first conductivity type; and a second transistor structure, stacked on the first transistor structure in a vertical direction, the second transistor structure including a second source / drain region having a second conductivity type opposite to the first conductivity type. The integrated circuit device may also include: an isolation layer between the first transistor structure and the second transistor structure in a vertical direction; and a discharge path between the gate electrode of the second transistor structure and the substrate. The discharge path may extend through the isolation layer. The discharge path may include a diode structure, and at least a portion of the diode structure may be below the upper surface of the substrate.

[0005] According to some embodiments of the present invention, a method for forming an integrated circuit device may include: forming a stacked structure on a substrate, the stacked structure including a lower channel layer, an upper channel layer, and an isolation layer between the lower channel layer and the upper channel layer; forming a source / drain region in the stacked structure, the source / drain region including a lower source / drain region and an upper source / drain region; forming a diode structure in the stacked structure; forming a gate structure in the stacked structure, the gate structure including a lower gate structure and an upper gate structure; and forming a discharge path between the upper gate structure and the substrate, the discharge path including the diode structure and extending through the isolation layer.

[0006] The present disclosure is not limited to the above-described embodiments and inventive concepts, and other embodiments and inventive concepts are provided in the accompanying drawings and detailed description thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a layout of an integrated circuit device according to some embodiments. Figure 2A and Figure 2B According to some embodiments, Figure 1 A cross-sectional view of the integrated circuit device taken along line AA′ and line BB′ in FIG.

[0008] Figure 3 is a schematic diagram illustrating a discharge path of an integrated circuit device according to some embodiments.

[0009] Figure 4 is a circuit diagram illustrating a discharge path of an integrated circuit device according to some embodiments.

[0010] Figure 5 According to some embodiments, Figure 1 A cross-sectional view of the integrated circuit device taken along line BB' in FIG.

[0011] Figure 6 According to some embodiments, Figure 1 A cross-sectional view of the integrated circuit device taken along line BB' in FIG.

[0012] Figure 7 According to some embodiments, Figure 1 A cross-sectional view of the integrated circuit device taken along line BB' in FIG.

[0013] Figure 8 According to some embodiments, Figure 1 A cross-sectional view of the integrated circuit device taken along line BB' in FIG.

[0014] Fig. 9 is a Flowchart illustrating operations in a method of forming an integrated circuit device, in accordance with some embodiments.

[0015] Fig.10 , Fig.11A , Fig. 12A and Fig.13 It is along Figure 1 The middle cross-sectional view taken along the line A-A', Fig. 11B , Fig. 12B , Fig.14 , Fig.15 and Fig.16 It is along Figure 1 An intermediate cross-sectional view taken along line BB'.

[0016] Like reference numerals may designate corresponding parts throughout the drawings. DETAILED DESCRIPTION

[0017] Figure 1 is a layout of an integrated circuit device according to some embodiments. Figure 2A and Figure 2B According to some embodiments, Figure 1 1 is a cross-sectional view of the integrated circuit device 1 taken along the lines AA' and BB' in FIG. In order to simplify the drawings and their descriptions, not all components are shown in every drawing, and some components may be completely omitted from the drawings.

[0018] Reference Figure 1 , Figure 2A and Figure 2B , the integrated circuit device 1 may include a stacked structure 1S provided on a substrate 112. In some embodiments, a plurality of stacked structures 1S may be provided. Each stacked structure 1S may include an upper transistor structure 200 and a lower transistor structure 100 provided between the substrate 112 and the upper transistor structure 200. The upper transistor structure 200 may be stacked on the lower transistor structure 100, and the lower transistor structure 100 may be on the substrate 112.

[0019] The substrate 112 may include a lower surface 112a and an upper surface 112b opposite to the lower surface 112a. The lower surface 112a and the upper surface 112b may be parallel to each other. As used herein, a "lower" component on the substrate 112 may refer to a first component that is closer to the lower surface 112a of the substrate 112 than a second component on the substrate 112. Similarly, an "upper" component may refer to a second component that may be on the substrate 112 and further away from the lower surface 112a of the substrate 112 than the first component.

[0020] The semiconductor region 114 may be provided on the substrate 112. The semiconductor region 114 may extend in a first direction D1 (also referred to as a first horizontal direction) and may be spaced apart from other semiconductor regions 114 in a second direction D2 (also referred to as a second horizontal direction). As used herein, an element (e.g., "element A") stated as extending in one direction (e.g., "direction X") or similar language may indicate that the element extends longitudinally in the direction. The first direction D1 may be perpendicular to the second direction D2.

[0021] The semiconductor region 114 may be located at an upper portion of the substrate 112, for example, adjacent to the upper surface 112b of the substrate 112 in a third direction D3 (also referred to as a vertical direction). The third direction D3 may be perpendicular to the first direction D1 and the second direction D2. In some embodiments, the third direction D3 may be perpendicular to the lower surface 112a and the upper surface 112b of the substrate 112.

[0022] The substrate 112 may include one or more semiconductor materials (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP), or may include an insulating material (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, silicon boron nitride, and / or a low-k material). In some embodiments, the substrate 112 may be a bulk substrate (e.g., a bulk silicon substrate) or a semiconductor-on-insulator (SOI) substrate. For example, the substrate 112 may be a silicon wafer or may be an insulating layer.

[0023] The semiconductor region 114 may be, for example, a portion of the substrate 112, or may be a layer formed by, for example, an epitaxial growth process using the substrate 112 as a seed layer. For example, the semiconductor region 114 may include a semiconductor material such as Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP.

[0024] A trench isolation layer (not shown) may be provided in the substrate 112. Semiconductor regions 114 adjacent to each other may be separated from each other by a portion of the trench isolation layer. The trench isolation layer may include an insulating material (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, and / or a low-k material). The low-k material may include, for example, fluorine-doped silicon oxide, organic silicate glass, carbon-doped oxide, porous silicon dioxide, porous organic silicate glass, spin-on organic polymer dielectrics, and / or spin-on silicon-based polymer dielectrics. In some embodiments, a bottom insulating layer (not shown) may be formed between the substrate 112 and at least a portion of the lower transistor structure 100.

[0025] The lower transistor structure 100 may include a lower channel region 120, which may be stacked on the substrate 112 in the third direction D3 and may overlap each other in the third direction D3. As used herein, if, as an example, at least one (straight) line can be drawn in a given direction intersecting both the first element and the second element, it can be said that the first element and the second element overlap each other in the given direction. The lower channel region 120 may be stacked on a semiconductor region (e.g., semiconductor region 114). The lower channel region 120 may include opposite side surfaces spaced apart from each other in the first direction D1, and the lower transistor structure 100 may include a pair of lower source / drain regions 140, respectively, on those opposite side surfaces of the lower channel region 120. The pair of lower source / drain regions 140 may contact those opposite side surfaces of the lower channel region 120, respectively.

[0026] The lower transistor structure 100 may further include a lower gate structure 130, which may include a lower gate insulator 131 and a lower gate electrode 132. The lower gate electrode 132 may extend in the second direction D2 and may cross over one or more semiconductor regions 114. A portion of the lower channel region 120 may be surrounded by the lower gate electrode 132, and the lower gate insulator 131 may separate the lower channel region 120 from the lower gate electrode 132. The lower channel region 120 may extend through the lower gate electrode 132 in the first direction D1 and may contact the lower gate insulator 131.

[0027] The upper transistor structure 200 may include an upper channel region 220, which may be stacked on the substrate 112 in the third direction D3 and may overlap each other in the third direction D3. The upper channel region 220 may also overlap with the lower channel region 120 in the third direction D3. The upper channel region 220 may include opposite side surfaces spaced apart from each other in the first direction D1, and the upper transistor structure 200 may include a pair of upper source / drain regions 240 respectively on those opposite side surfaces of the upper channel region 220. The pair of upper source / drain regions 240 may contact those opposite side surfaces of the upper channel region 220, respectively.

[0028] The upper transistor structure 200 may further include an upper gate structure 230, which may include an upper gate insulator 231 and an upper gate electrode 232. The upper gate electrode 232 may extend in the second direction D2 and may cross the semiconductor region 114. A portion of the upper channel region 220 may be surrounded by the upper gate electrode 232, and the upper gate insulator 231 may separate the upper channel region 220 from the upper gate electrode 232. The upper channel region 220 may extend through the upper gate electrode 232 in the first direction D1 and may contact the upper gate insulator 231.

[0029] The lower channel region 120 and the upper channel region 220 may include, for example, a semiconductor material (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP). In some embodiments, the lower channel region 120 may include a material different from that of the upper channel region 220. In some embodiments, each of the lower channel region 120 and the upper channel region 220 may be a nanosheet that may have a thickness in the range of 1 nm to 100 nm in the third direction D3, or may be a nanowire that may have a circular cross-section having a diameter in the range of 1 nm to 100 nm.

[0030] The lower gate insulator 131 and the upper gate insulator 231 may include, for example, a silicon oxide layer and / or a high-k material layer. The high-k material layer may include, for example, Al 2 O 3 , HfO 2 、ZrO 2、HfZrO 4 、TiO 2 Sc 2 O 3 , Y 2 O 3 ,La 2 O 3 、Lu 2 O 3 , Nb 2 O 5 and / or 2 O 5 The lower gate insulator 131 and the upper gate insulator 231 may be gate dielectric layers. The lower gate electrode 132 and the upper gate electrode 232 may include, for example, a metal layer (which includes, for example, W, Al, Cu, Mo, Co, and / or Ru), and may additionally include a work function layer (for example, a TiN layer, a TaN layer, a TiAl layer, a TiC layer, a TiAlC layer, a TiAlN layer, and / or a WN layer).

[0031] In some embodiments, a lower insulating spacer (e.g., a lower gate spacer or a lower inner gate spacer (not shown)) may be provided between and separate the lower gate structure 130 and the lower source / drain region 140. In some embodiments, an upper insulating spacer (e.g., an upper gate spacer or an upper inner gate spacer (not shown)) may be provided between and separate the upper gate structure 230 and the upper source / drain region 240. Each of the lower insulating spacer and the upper insulating spacer may include, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, and / or a low-k material.

[0032] In some embodiments, the lower transistor structure 100 and the upper transistor structure 200 may have different conductivity types, and the stacked structure 1S including the lower transistor structure 100 and the upper transistor structure 200 may be a complementary metal oxide semiconductor (CMOS). In some embodiments, the lower source / drain region 140 of the lower transistor structure 100 may have a first conductivity type (e.g., p-type conductivity), and the upper source / drain region 240 of the upper transistor structure 200 may have a second conductivity type opposite to the first conductivity type (e.g., n-type conductivity).

[0033] Still refer to Figure 1 , Figure 2A and Figure 2B, the integrated circuit device 1 may further include an intermediate isolation layer 300 between the lower transistor structure 100 and the upper transistor structure 200 in the third direction D3. The intermediate isolation layer 300 may provide isolation between the lower transistor structure 100 and the upper transistor structure 200. Although the intermediate isolation layer 300 is shown as a single layer, the present disclosure is not limited thereto. For example, in some embodiments, an inter-gate isolation layer may be provided between the lower gate structure 130 and the upper gate structure 230, and an inter-source / drain isolation layer may be provided between the lower source / drain region 140 of the lower transistor structure 100 and the upper source / drain region 240 of the upper transistor structure 200. The inter-gate isolation layer and the inter-source / drain isolation layer may be provided at substantially equal distances from the upper surface 112 b of the substrate 112.

[0034] In some embodiments, the integrated circuit device 1 may further include an additional insulating layer, such as the insulating layer 320. The additional insulating layer may be on one or more sides of the integrated circuit device 1 or its lower transistor structure 100 or upper transistor structure 200, for example, in the first direction D1, the second direction D2, and / or the third direction D3.

[0035] The gate contact 330 may be arranged to provide electrical connection to the lower gate electrode 132 / upper gate electrode 232. The source / drain contact 340 may be arranged to provide electrical connection to the lower source / drain region 140 / upper source / drain region 240. Although the source / drain contact 340 is Figure 2A 100 is shown as being connected to the upper transistor structure 200, but the present disclosure is not limited thereto, and the source / drain contact 340 may be connected to the lower source / drain region 140 of the lower transistor structure 100. Similarly, although the gate contact 330 is Figure 2A 3 is shown as being connected to the upper transistor structure 200 , but the disclosure is not limited thereto, and the gate contact 330 may be connected to the lower gate electrode 132 of the lower transistor structure 100 .

[0036] Although not in Figure 1 and Figure 2A In the Figure 2B As can be seen in FIG. 1 , one or more metal layers (including a first metal layer 360) may be provided above the source / drain contacts 340 and the gate contacts 330. The one or more metal layers may be back-end-of-line (BEOL) metal layers. Metal lines provided in the one or more metal layers may be electrically coupled to the source / drain contacts 340 and / or the gate contacts 330.

[0037] During the semiconductor manufacturing process, a process utilizing plasma may be used at one or more steps. Plasma-induced charges may be trapped on one or more metal lines, and the plasma-induced charges may flow into a gate dielectric layer (such as the lower gate insulator 131 or the upper gate insulator 231), resulting in potential breakdown of the gate dielectric layer. This accumulation of charges may be particularly problematic for the upper transistor structure 200, because the presence of the intermediate isolation layer 300 may act as an obstacle for the accumulated charges in the upper gate structure 230 to discharge into, for example, the substrate 112.

[0038] Therefore, according to some embodiments of the inventive concept, a discharge path may be provided between the substrate 112 and the upper transistor structure 200. The discharge path may include a diode structure DS. Figure 1 and Figure 2B , the diode structure DS may be positioned adjacent to the stack structure 1S in a horizontal direction (eg, the second direction D2 ).

[0039] The diode structure DS may include a first semiconductor region 106 and a second semiconductor region 108, which are respectively a first diode region 106 and a second diode region 108. The first diode region 106 may be a lower diode region and may have the same conductivity type as the conductivity type (e.g., the first conductivity type) of the lower source / drain region 140. The second diode region 108 may be an upper diode region and may have the same conductivity type as the conductivity type (e.g., the second conductivity type) of the upper source / drain region 240. The first diode region 106 and the second diode region 108 may be in direct contact with each other and form a junction (e.g., a PN junction) therebetween. In some embodiments, the first diode region 106 and the second diode region 108 may be vertically stacked, wherein the second diode region 108 is on the first diode region 106 in a third (vertical) direction D3.

[0040] The first diode region 106 and the second diode region 108 are shown as being wider than the lower source / drain region 140 and the upper source / drain region 240 in the second direction D2, but this is merely an example and the present disclosure is not limited thereto. In some embodiments, the first diode region 106 and / or the second diode region 108 may have the same size as the lower source / drain region 140 and the upper source / drain region 240 in one or more directions. In some embodiments, the first diode region 106 and / or the second diode region 108 may have a different size than one or both of the lower source / drain region 140 and the upper source / drain region 240 in one or more directions. At least one of the first diode region 106 and the second diode region 108 (or a portion thereof) may overlap horizontally with the lower source / drain region 140, for example in the second direction D2.

[0041] As in Figure 2B As seen in FIG. 1 , in some embodiments, the upper surface of the lower source / drain region 140 of the lower transistor structure 100 and the upper surface of the second diode region 108 of the diode structure DS may be at an equal distance from the substrate 112 . Figure 2B As seen in FIG. 1 , in some embodiments, at least the lower surface 106a of the first diode region 106 can be below the upper surface 112b of the substrate 112. In some embodiments, the entire first diode region 106 can be below the upper surface 112b of the substrate 112. In some embodiments, the first diode region 106 can be a region or portion of the substrate 112 that is doped or receives a dopant to provide a selected conductivity type therein. For example, where the first semiconductor region 106 is a p-type layer, a region or portion of the substrate 112 where the diode structure DS is located can be provided with a p-type dopant (e.g., boron (B), arsenic (As), phosphorus (P), and / or others).

[0042] In some embodiments, the second diode region 108 can be formed simultaneously with the lower source / drain region 140 .

[0043] In some embodiments, the intermediate isolation layer 300 may be above the diode structure DS.

[0044] In some embodiments, the third semiconductor region 208 may be formed over the second semiconductor region / second diode region 108 and the first semiconductor region / first diode region 106. The third semiconductor region 208 may be a dummy source / drain region and may be formed simultaneously with the upper source / drain region 240.

[0045] A discharge contact 370 may be formed, which may have at least a lower surface that contacts (e.g., directly contacts) the second diode region 108. The discharge contact 370 may penetrate or extend through the intermediate isolation layer 300. The discharge contact 370 may be in electrical contact with the first metal layer 360 through a discharge path 372. The discharge path 372 may directly contact an upper surface or an upper portion of the discharge contact 370. A gate path 332 may be formed, which may electrically connect the first metal layer 360 to the gate contact 330. In some embodiments, one or more of the discharge path 372 and the gate path 332 are optional, and the bottom or lower surface of the first metal layer 360 may directly contact an upper surface of the discharge contact 370 and / or an upper surface of the gate contact 330.

[0046] Figure 3 is a schematic diagram showing that a discharge path DP can be formed between an upper transistor structure 200 and a substrate 112 of a stacked structure 1S by utilizing at least one metal layer (e.g., a first metal layer 360) and a diode structure DS formed adjacent to the stacked structure 1S, and the at least one metal layer can be a BEOL metal layer). Figure 4 According to some embodiments Figure 3 Circuit diagram of some components of an integrated circuit device.

[0047] The discharge path DP may be an electrical path from the upper gate structure 230 or the upper gate electrode 232 of the upper transistor structure 200 (which may be a test transistor) to the substrate 112, and the discharge path DP may include the gate contact 330, the gate path 332, the metal line formed in the first metal layer 360, the discharge path 372, the discharge contact 370, and the diode structure DS (the second diode region 108 and the first diode region 106). The discharge path DP may extend through the intermediate isolation layer 300.

[0048] Note that although the at least one metal layer is described as the first metal layer 360 , it will be understood that any metal layer on a common side of the substrate 112 with the stacked structure 1S may function as part of the discharge path DP.

[0049] The discharge path DP can provide a path for charges that may be trapped in the upper transistor structure 200 (e.g., plasma-induced charges) to dissipate or discharge, rather than accumulating in a portion of the upper transistor structure 200 that may be a floating region (such as the upper channel region 220). This can improve the performance and / or reliability of the integrated circuit device 1, for example, because the upper gate insulator 231 does not degrade due to the accumulated plasma-induced charges or does not experience breakdown due to the accumulated plasma-induced charges.

[0050] Figure 5 According to some embodiments, Figure 1 The integrated circuit device 2 can be similar to Figure 1 , Figure 2A and Figure 2B The integrated circuit device 1 is mainly different in that the third semiconductor region 208 (dummy source / drain region) may not be formed. Figure 5 It is also shown that in some embodiments, the lower surface of the second diode region 108 can be below the upper surface 112b of the substrate 112. The Figure 1 , Figure 2A and Figure 2B Integrated circuit device 1.

[0051] Figure 6 According to some embodiments, Figure 1 The integrated circuit device 3 can be similar to Figure 1 , Figure 2A and Figure 2BThe integrated circuit device 1 is mainly different in that the second diode region 108 and the first diode region 106 may not be stacked vertically, and the second diode region 108 is adjacent to the first diode region 106 in a horizontal direction (e.g., the second direction D2). In some embodiments, the length of the second diode region 108 in the third direction D3 may be greater than the length of the first diode region 106 in the third direction D3. In some embodiments, the length of the second diode region 108 in the third direction D3 may be greater than the length of the lower source / drain region 140 in the third direction D3.

[0052] Although the second diode region 108 is Figure 6 108. Although shown as a continuous region in FIG. 104, the present disclosure is not limited thereto, and in some embodiments, one or more sub-regions or layers (which together constitute the second diode region 108) may be formed. Unless otherwise stated, any layer or region provided herein may also be so.

[0053] Figure 7 According to some embodiments, Figure 1 4 is a cross-sectional view of the integrated circuit device 4 taken along the line BB' in FIG. The integrated circuit device 4 may be similar to the integrated circuit device 1, with the main difference that the semiconductor layer 52 is provided between the third semiconductor region 208 and the second diode region 108 and contacts both the third semiconductor region 208 and the second diode region 108. The third semiconductor region 208 may be a third diode region 208. The third semiconductor region 208, the semiconductor layer 52, and the second diode region 108 may together form a single diode region, and together with the first diode region 106, may together form a single diode. The third semiconductor region 208, the semiconductor layer 52, and the second diode region 108 may have a common conductivity type (which may be the same conductivity type as the upper source / drain region 240 of the upper transistor structure 200).

[0054] Figure 8 According to some embodiments, Figure 1 . The integrated circuit device 5 may be similar to the integrated circuit device 1, with the main difference that the diode structure DS may be formed by a first diode region 106 and a third semiconductor region 208 that may be in direct contact with each other. The first diode region 106 may have the same conductivity type as the lower source / drain region 140, and the first diode region 106 and the lower source / drain region 140 may be formed simultaneously and by the same process. The third semiconductor region 208 may have the same conductivity type as the upper source / drain region 240, and the third semiconductor region 208 and the upper source / drain region 240 may be formed simultaneously and by the same process. The third semiconductor region 208 and the first diode region 106 may form a single diode together. The second diode region 108 may not be formed.

[0055] Fig. 9 is a Flowchart illustrating operations in a method of forming an integrated circuit device, in accordance with some embodiments. Fig.10 , Fig.11A , Fig. 12A and Fig.13 It is along Figure 1 The middle cross-sectional view taken along the line A-A', Fig. 11B , Fig. 12B , Fig.14 , Fig.15 and Fig.16 It is along Figure 1 An intermediate cross-sectional view taken along line BB'.

[0056] Reference Fig. 9 and Fig.10 , a stacked structure STU( Fig. 9 902). For example, the upper stacked portion UST may be formed by forming an upper channel layer 220, an upper sacrificial layer 1230 alternately stacked with the upper channel layer 220, and an insulator layer 1300 on an upper substrate 1112, and then performing an ion implantation process to form a separation layer 1111. The ion implantation process may implant ions (e.g., hydrogen ions) into a portion of the upper substrate 1112, so that the separation layer 1111 may include those implanted ions. Alternatively, the upper stacked portion UST may be formed by forming a separation layer 1111 on an upper substrate 1112 by, for example, a deposition process, and then forming an upper channel layer 220, an upper sacrificial layer 1230, and an insulator layer 1300 on the separation layer 1111. The separation layer 1111 may include, for example, SiN, SiBCN, SiOCN, SiBN, SiCN, SiO, and / or SiON.

[0057] A lower stack portion LST may be formed, which may include a lower substrate 112 , and lower channel layers 120 and lower sacrificial layers 1130 alternately stacked with the lower channel layers 120 on the lower substrate 112 .

[0058] The lower sacrificial layer 1130 and the upper sacrificial layer 1230 may include a material having an etching selectivity relative to the lower channel layer 120 and the upper channel layer 220. The lower sacrificial layer 1130 and the upper sacrificial layer 1230 may include, for example, a semiconductor material (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP). In some embodiments, the lower sacrificial layer 1130 and the upper sacrificial layer 1230 may include a SiGe layer.

[0059] The upper surface of the insulator layer 1300a may be stacked on the uppermost layer 120 / 1130 of the lower stack portion LST. The upper substrate 1112 and the spacer layer 1111 may then be removed to form a stacked structure STU. For example, the spacer layer 1111 may be removed by performing an annealing process to separate the spacer layer 1111 from the upper channel layer 220. In some embodiments, a dry etching process and / or a chemical mechanical polishing (CMP) process may be performed to remove the upper substrate 1112 and the spacer layer 1111, and the spacer layer 1111 may be used as an etching stop layer when removing the upper substrate 1112.

[0060] In some embodiments, the lower stack portion LST may also include an insulator layer similar to the insulator layer 1300 of the upper stack portion UST, and the upper stack portion UST may be stacked on the insulator layer of the lower stack portion LST. In some embodiments, the lower stack portion LST may include an insulator layer similar to the insulator layer 1300 of the upper stack portion UST, the insulator layer 1300 of the upper stack portion UST may be omitted, and the upper stack portion UST may be stacked on the insulator layer of the lower stack portion LST.

[0061] In some embodiments, the stacked structure STU may be formed by providing a lower substrate 112, then alternately stacking lower channel layers 120 and lower sacrificial layers 1130 on the lower substrate 112, then forming an insulator layer 1300 on the stack of the lower channel layers 120 and the lower sacrificial layers 1130, and alternately stacking upper sacrificial layers 1230 and upper channel layers 220 on the insulator layer 1300, and the insulator layer 1300 may become the intermediate isolation layer 300. Therefore, in some embodiments, the upper substrate 1112 and the separation layer 1111 may not be used for the formation of the stacked structure STU.

[0062] Reference Fig.11A and Fig. 11B , a source / drain trench 140T and a diode trench DT may be formed in the stacked structure STU. For example, a mask layer (not shown) may be formed, and the stacked structure STU may be etched using the mask layer as an etching mask until the substrate 112 is exposed, thereby forming the semiconductor region 114. The mask layer may then be removed, and an insulating layer 320 may be formed on the remaining portion of the stacked structure STU. In some embodiments, the diode trench DT may have a different size from the source / drain trench 140T. For example, the diode trench DT may extend from the upper surface 112b of the substrate 112 farther into the substrate 112 than the source / drain trench 140T.

[0063] Reference Fig. 9 , Fig. 12A and Fig. 12B, the lower source / drain region 140 and the upper source / drain region 240 may be formed in at least some of the source / drain trenches 140T, and the diode structure DS may be formed in the diode trench DT ( Fig. 9 904).

[0064] For example, the lower source / drain region 140 may be formed by an epitaxial growth process using the lower channel region 120 as a seed layer, and the upper source / drain region 240 may be formed by an epitaxial growth process using the upper channel region 220 as a seed layer. In some embodiments, a source / drain insulator may be formed on the lower source / drain region 140 before forming the upper source / drain region 240.

[0065] The diode structure DS may include a first semiconductor region 106 and a second semiconductor region 108, which are respectively a first diode region 106 and a second diode region 108. The first diode region 106 may be a lower diode region and may have the same conductivity type as the conductivity type (e.g., the first conductivity type) of the lower source / drain region 140, and may be formed simultaneously with the lower source / drain region 140. The second semiconductor region 108 may be an upper diode region and may have the same conductivity type as the conductivity type (e.g., the second conductivity type) of the upper source / drain region 240, and may be formed simultaneously with the upper source / drain region 240. The first diode region 106 and the second diode region 108 may be in direct contact with each other and form a junction (e.g., a PN junction) therebetween. In some embodiments, the first diode region 106 and the second diode region 108 may be vertically stacked, wherein the second diode region 108 is on the first diode region 106 in a third (vertical) direction D3.

[0066] When the lower source / drain region 140 and the first diode region 106 are formed as p-type regions, a p-type impurity source gas (such as diborane (B)) may be introduced during the epitaxial growth process thereof (e.g., during the selective epitaxial growth process (SEG)). 2 H 6 ) gas) to form the lower source / drain region 140 and the first diode region 106 to be doped with p-type impurities. When the upper source / drain region 240 and the second diode region 108 are formed as n-type regions, an n-type impurity source gas (such as POCl) may be introduced during the epitaxial growth process thereof. 3 , P 2 O 5etc.) to form the upper source / drain region 240 and the second diode region 108 to be doped with n-type impurities. The present disclosure is not limited to using an impurity source gas to form the lower source / drain region 140 and the upper source / drain region 240 as well as the first diode region 106 and the second diode region 108 during the epitaxial growth process. In some embodiments, the lower source / drain region 140 and the first diode region 106 can be formed as n-type regions (e.g., using an n-type impurity source gas), and the upper source / drain region 240 and the second diode region 108 can be formed as p-type regions (e.g., using a p-type impurity source gas). Fig. 12B , the first diode region 106 and the second diode region 108 are shown to be wider than the lower source / drain region 140 in the second direction D2, but this is only an example and the present disclosure is not limited thereto.

[0067] In some embodiments, the third semiconductor region 208 and the upper source / drain region 240 may be formed at the same time and by the same process. In some embodiments, the third semiconductor region 208 and the first diode region 106 may form a single diode together. In some embodiments, the second diode region 108 may not be formed. In some embodiments, the intermediate isolation layer 300 may be formed (or re-formed) between the lower source / drain region 140 and the upper source / drain region 240, and the intermediate isolation layer 300 may be formed (or re-formed) on the second diode region 108.

[0068] A source / drain contact (not shown) may be formed in the source / drain trench 140T. In some embodiments, an additional insulating layer may be formed to fill the remaining portion of the source / drain trench 140T and the remaining portion of the diode trench DT. The additional insulating layer may have the same material as the insulating layer 320 formed previously, so that they may be collectively referred to as the insulating layer 320.

[0069] Reference Fig. 9 and Fig.13 , a lower gate structure 130 and an upper gate structure 230 may be formed ( Fig. 9 906). Fig.13 , the upper sacrificial pattern 1230 and the lower sacrificial pattern 1130 may be removed to expose the lower channel region 120 and the upper channel region 220, and then a lower gate insulator 131 and an upper gate insulator 231 may be formed on the lower channel region 120 and the upper channel region 220, respectively. The lower gate insulator 131 may define a first opening, and the upper gate insulator 231 may define a second opening. The lower gate electrode 132 may be formed in the first opening, and the upper gate electrode 232 may be formed in the second opening.

[0070] The lower gate structure 130 , the lower channel region 120 , and the lower source / drain region 140 may form a lower transistor structure 100 . The upper gate structure 230 , the upper channel region 220 , and the upper source / drain region 240 may form an upper transistor structure 200 .

[0071] Reference Fig. 9 , Fig.14 , Fig.15 , Fig.16 , Figure 2A , Figure 2B and Figure 3 , a discharge path DP ( Fig. 9 The discharge path DP may include a diode structure DS. The discharge path DP may extend through the intermediate isolation layer 300. Fig.14 , a mask layer M1 may be formed on the upper surface of the insulating layer 320. A gate contact trench 330T and a discharge contact trench 370T may be formed in the insulating layer 320 to expose a portion of the upper gate structure 230 and a portion of the diode structure DS, respectively. Fig.15 , the gate contact 330 may be formed in the gate contact trench 330T, and the discharge contact 370 may be formed in the discharge contact trench 370T. The mask layer M1 may be removed. Fig.16 , the gate path 332 may be formed on the gate contact 330, and the discharge path 372 may be formed on the discharge contact 370. Figure 2A and Figure 2B , one or more metal layers including a first metal layer 360 may be formed on the gate via 332 and the discharge via 372 .

[0072] Return to reference Figure 3 , a discharge path DP may be formed to extend from a gate contact 330, which may be formed to electrically contact an upper gate electrode 232 of an upper transistor structure 200. The discharge path DP may include one or more metal layers (including a first metal layer 360), which may be formed above the gate contact 330. The one or more metal layers may be back-end-of-line (BEOL) metal layers. The discharge path DP may include a discharge contact 370, which may be formed and may penetrate or extend through the intermediate isolation layer 300 in some embodiments. The discharge contact 370 may be in electrical contact with the first metal layer 360 through a discharge path 372 that may be formed. The gate contact 330 may be in electrical contact with the first metal layer 360 through a gate path 332 that may be formed.

[0073] Some examples of embodiments are described herein with reference to the accompanying drawings. Without departing from the scope of the present invention, many different forms and embodiments are possible. Therefore, the present invention should not be construed as being limited to the example embodiments set forth herein. On the contrary, these example embodiments are provided so that this disclosure will be thorough and complete, and the scope of the present invention will be conveyed to those skilled in the art. In the accompanying drawings, for clarity, the sizes and relative sizes of layers and regions may be exaggerated. The same reference numerals always refer to the same elements.

[0074] Example embodiments of the present invention are described herein with reference to cross-sectional views, which are schematic diagrams of idealized embodiments and intermediate structures of example embodiments. Thus, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, example embodiments of the present invention should not be construed as limited to the specific shapes shown herein, but rather include deviations in shapes, for example, caused by manufacturing, unless the context clearly indicates otherwise.

[0075] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted as an idealized or overly formal meaning, unless explicitly defined as such herein.

[0076] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "one", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will also be understood that the terms "include", "includes ...", "includes" and / or "includes ...", when used in this specification, specify the presence of the features, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts and / or their combinations. As used herein, the term "and / or" includes any and all combinations of one or more related listed items.

[0077] It will be understood that although the terms first, second, etc. can be used here to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the scope of the present invention, the first element can be called the second element.

[0078] The subject matter disclosed above is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the scope of the invention. Therefore, to the maximum extent permitted by law, the scope is to be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

[0079] This application claims priority to U.S. Provisional Application No. 63 / 519,293, entitled “Integrated Circuit Device Including a Discharge Path and Method for Forming the Same,” filed in the U.S. Patent and Trademark Office on August 14, 2023, and U.S. Non-Provisional Application No. 18 / 543,111, filed in the U.S. Patent and Trademark Office on December 18, 2023, the entire contents of the above applications are incorporated herein by reference in their entirety.

Claims

1. An integrated circuit device, comprising: substrate; a first transistor structure on the substrate; a second transistor structure stacked on the first transistor structure in a vertical direction; an isolation layer between the first transistor structure and the second transistor structure in the vertical direction; as well as a diode structure on the substrate and horizontally adjacent to the first transistor structure, Wherein the diode structure is part of a discharge path between a gate electrode of the second transistor structure and the substrate, and wherein the discharge path extends through the isolation layer. 2 . The integrated circuit device of claim 1 , further comprising a back end of line (BEOL) metal layer, wherein the discharge path comprises the BEOL metal layer.

3. The integrated circuit device of claim 1 , wherein the first transistor structure comprises a first source / drain region having a first conductivity type, and wherein the second transistor structure comprises a second source / drain region having a second conductivity type opposite to the first conductivity type.

4. The integrated circuit device of claim 3, wherein the diode structure comprises a first diode region having the first conductivity type and a second diode region having the second conductivity type and comprising a first portion horizontally overlapping the first source / drain region. The integrated circuit device of claim 4 , wherein the first diode region is in the substrate. 6 . The integrated circuit device of claim 4 , wherein the second diode region is stacked on the first diode region in the vertical direction. 7 . The integrated circuit device of claim 4 , wherein the first diode region and the second portion of the second diode region are adjacent to each other in a horizontal direction.

8. The integrated circuit device of claim 4, wherein the diode structure includes a third diode region having the second conductivity type.

9. The integrated circuit device of claim 1, further comprising a discharge contact directly contacting the diode structure, wherein the discharge path includes the discharge contact.

10. The integrated circuit device of claim 9, wherein the discharge contact extends through the isolation layer.

11. An integrated circuit device comprising: substrate; The stacking structure includes: a first transistor structure on the substrate and including a first source / drain region having a first conductivity type; and a second transistor structure stacked vertically on the first transistor structure, the second transistor structure comprising a second source / drain region having a second conductivity type opposite to the first conductivity type; an isolation layer between the first transistor structure and the second transistor structure in the vertical direction; and a discharge path between the gate electrode of the second transistor structure and the substrate, wherein the discharge path extends through the isolation layer and includes a diode structure, At least a portion of the diode structure is below the upper surface of the substrate.

12. The integrated circuit device of claim 11, wherein the discharge path comprises a back end of line (BEOL) metal layer.

13. The integrated circuit device of claim 11, wherein the diode structure comprises a first diode region having the first conductivity type and a second diode region having the second conductivity type and comprising a first portion horizontally overlapping the first source / drain region.

14. The integrated circuit device of claim 13, wherein an upper surface of the first diode region is below the upper surface of the substrate. 15 . The integrated circuit device of claim 13 , wherein the second diode region is stacked on the first diode region in the vertical direction. 16 . The integrated circuit device of claim 13 , wherein the first diode region and the second portion of the second diode region are adjacent to each other in a horizontal direction.

17. A method of forming an integrated circuit device, the method comprising: forming a stacked structure on a substrate, the stacked structure comprising a lower channel layer, an upper channel layer, and an isolation layer between the lower channel layer and the upper channel layer; forming a source / drain region in the stacked structure, the source / drain region comprising a lower source / drain region and an upper source / drain region; forming a diode structure in the stacked structure; forming a gate structure in the stacked structure, the gate structure comprising a lower gate structure and an upper gate structure; as well as A discharge path is formed between the upper gate structure and the substrate, the discharge path including the diode structure and extending through the isolation layer.

18. The method of claim 17, further comprising forming a back end of line (BEOL) metal layer, wherein the discharge path comprises the BEOL metal layer. 19 . The method of claim 17 , wherein the lower source / drain region has a first conductivity type and the upper source / drain region has a second conductivity type opposite to the first conductivity type.

20. The method of claim 19, wherein the diode structure comprises a first diode region having the first conductivity type and a second diode region having the second conductivity type and comprising a first portion horizontally overlapping one of the lower source / drain regions.

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