Semiconductor element

Abstract

The invention discloses a semiconductor element which comprises a substrate, a well region, a first field plate, a second field plate, a first diode and a second diode. The substrate has a first conductivity type. The well region has a second conductivity type and is disposed on the substrate. The first field plate is arranged on the substrate, and the second field plate is arranged on the substrate and laterally separated from the first field plate. The first diode comprises an anode and a cathode, the anode of the first diode is adjacent to the well region, and the cathode of the first diode comprises part of the well region. And the second diode comprises an anode and a cathode, the anode of the second diode is electrically connected with the anode of the first diode, and the cathode of the second diode is electrically connected with the second field plate.

Description

Technical Field

[0001] The present invention relates to integrated circuit technology, and more particularly to an integrated circuit structure including a lateral diffusion trench type metal oxide semiconductor element. Background Art

[0002] Metal-oxide semiconductor field effect transistor (MOSFET) is the most commonly used device in integrated circuits, which includes horizontal structures, such as laterally-diffused metal-oxide semiconductor (LDMOS) field effect transistor (FET), and vertical structures, such as planar gate MOSFET and trench gate MOSFET, wherein the gate of the trench gate MOSFET is set in a trench.

[0003] In order to achieve the effect of high voltage resistance, the length of the field plate and the drift region can be increased in the lateral diffused metal oxide semiconductor field effect transistor, or the depth of the trench can be increased in the trench gate metal oxide semiconductor field effect transistor. However, these methods will cause problems such as increased device size, incompatibility with other device processes, and increased process difficulty.

[0004] In addition, for a trench-type field plate structure, when the device is in the off state, the field plate is usually charged by the positive voltage from the drain; and when the device is in the on state, the field plate is usually discharged. That is, the field plate is charged or discharged as the device switches between the off state and the on state, which causes unnecessary power consumption.

[0005] Therefore, the industry is in great need of metal oxide semiconductor devices that can meet various requirements in integrated circuits. Summary of the invention

[0006] In view of this, the present invention proposes an integrated circuit structure including a lateral diffusion trench type metal oxide semiconductor device to solve the defects of the prior art.

[0007] According to one embodiment of the present invention, a semiconductor element is provided, comprising a substrate, a well region, a first field plate, a second field plate, a first diode and a second diode. The substrate has a first conductivity type. The well region has a second conductivity type and is disposed on the substrate. The first field plate is disposed on the substrate, and the second field plate is disposed on the substrate and is laterally separated from the first field plate. The first diode comprises an anode and a cathode, wherein the anode of the first diode is adjacent to the well region, and the cathode of the first diode comprises a portion of the well region. The second diode comprises an anode and a cathode, wherein the anode of the second diode is electrically connected to the anode of the first diode, and the cathode of the second diode is electrically connected to the second field plate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to while reading the present invention. The specific embodiments of the present invention are explained in detail through the specific embodiments in this article and with reference to the corresponding drawings, and the working principles of the specific embodiments of the present invention are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced.

[0009] Figure 1 is a simplified circuit diagram of a semiconductor device according to an embodiment of the present invention.

[0010] Figure 2 is a schematic top view of a local area of ​​a semiconductor element according to an embodiment of the present invention, corresponding to Figure 1 The simplified circuit shown.

[0011] Figure 3 An embodiment of the present invention is along the Figure 2 A schematic cross-sectional view shown by the AA' section line.

[0012] Figure 4 An embodiment of the present invention is along the Figure 2 A schematic cross-sectional view shown along the BB' section line.

[0013] Figure 5 is a simplified circuit diagram of a variation of an embodiment of the present invention including semiconductor components.

[0014] Figure 6 is a schematic top view of a local area of ​​a semiconductor element according to an embodiment of the present invention, corresponding to Figure 5 The simplified circuit shown.

[0015] Figure 7 An embodiment of the present invention is along the Figure 6 A schematic cross-sectional view shown by the AA' section line.

[0016] Figure 8 An embodiment of the present invention is along the Figure 6A schematic cross-sectional view shown by the CC' section line.

[0017] Fig. 9 An embodiment of the present invention is along the Figure 6 A schematic cross-sectional view shown along the D-D' section line.

[0018] Fig.10 It is a schematic cross-sectional view of a local area of ​​a semiconductor element according to a variant embodiment of the present invention.

[0019] Fig.11 It is a schematic cross-sectional view of a local area of ​​a semiconductor element according to a variant embodiment of the present invention.

[0020] Fig.12 It is a schematic cross-sectional view of a local area of ​​a semiconductor element according to a variant embodiment of the present invention.

[0021] The reference numerals are described as follows:

[0022] 100…Semiconductor components

[0023] 101…Base

[0024] 103… Well region

[0025] 104…Epitaxial layer

[0026] 105-1…First groove

[0027] 105-2…Second groove

[0028] 105-3…Third groove

[0029] 106-1…first dielectric layer

[0030] 106-2…Second dielectric layer

[0031] 106-3…third dielectric layer

[0032] 107…Field Plate

[0033] 107-1…First round

[0034] 107-2…Second round

[0035] 107-3…Third board

[0036] 108…Dielectric isolation part

[0037] 108-1…first dielectric isolation portion

[0038] 108-2…Second dielectric isolation portion

[0039] 108-3…Third dielectric isolation section

[0040] 109G…Gate

[0041] 100-1, 100-2…repeating units

[0042] 110-1…first capacitor

[0043] 110-2…Second capacitor

[0044] 110-3…Third capacitor

[0045] 111S…Source region

[0046] 113D…Drain region

[0047] 117…Matrix area

[0048] 117-1…First base area

[0049] 117-2…Second base area

[0050] 117-3…The third matrix area

[0051] 118…Substrate contact area

[0052] 120…Interlayer dielectric layer

[0053] 130-1…First diode

[0054] 130-2…Second diode

[0055] 130-3…The third diode

[0056] 130-4…The fourth diode

[0057] 130-5…Fifth diode

[0058] 130-6…the sixth diode

[0059] 130-7…the seventh diode

[0060] 130-8…The eighth diode

[0061] 132, 132-1, 132-2, 132-4, ... patterned semiconductor layer

[0062] 150...Transistor components

[0063] 152-1…First resistor

[0064] 152-2…Second resistor

[0065] 152-3…The third resistor

[0066] 152-4…the fourth resistor

[0067] CT, CT_1, CT_2a, CT_2b, CT_3, CT_4a, CT_4b, CT_5, CT_6a…Contact plug

[0068] D…Drain input terminal

[0069] D'…Drain terminal

[0070] D1+, D2+, D3-, D4+, D5+, D6+, D7+, D8+...Anode-

[0071] D1-, D2-, D3-, D4-, D5-, D6-, D7-, D8-………cathode-

[0072] M1, M1_1, M1_2, M1_3, M1_4, M1_5…interconnection wires

[0073] N1, N2, N3, N4... nodes

[0074] S…Source terminal DETAILED DESCRIPTION

[0075] The present invention provides several different embodiments that can be used to implement different features of the present invention. For the sake of simplicity of description, the present invention also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration, not for any limitation. For example, the description below for "a first feature is formed on or above a second feature" may refer to "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments of the present invention may use repeated reference symbols and / or text annotations. The use of these repeated reference symbols and annotations is to make the description more concise and clear, rather than to indicate the association between different embodiments and / or configurations.

[0076] In addition, for the spatially related descriptive words mentioned in the present invention, such as "under", "low", "down", "above", "on", "top", "bottom" and similar words, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the swing direction shown in the drawings, these spatially related words are also used to describe the possible swing direction of the semiconductor device during use and operation. As the swing direction of the semiconductor device is different (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its swing direction should also be interpreted in a similar manner.

[0077] Although the present invention uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and / or block from another element, component, region, layer, and / or block, and they themselves do not imply or represent any previous ordinal number of the element, nor do they represent the arrangement order of a certain element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or block discussed below can also be referred to as the second element, component, region, layer, or block.

[0078] The terms "about" or "substantially" mentioned in the present invention generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of a specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

[0079] The terms "coupled", "coupled", and "electrically connected" mentioned in the present invention include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0080] Although the invention of the present invention is described below by specific embodiments, the inventive principle of the present invention can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, certain details will be omitted, and these omitted details belong to the knowledge scope of those with ordinary knowledge in the relevant technical field.

[0081] Figure 1 FIG. 1 is a simplified circuit diagram of an embodiment of the present invention including semiconductor components. Figure 1 As shown, the semiconductor device 100 includes a switch element (e.g., a transistor element 150), two capacitors (e.g., a first capacitor 110-1 and a second capacitor 110-2), two diodes (e.g., a first diode 130-1 and a second diode 130-2), and two resistors (e.g., a first resistor 152-1 and a second resistor 152-2). The second capacitor 110-2, the first diode 130-1, the second diode 130-2, the first resistor 152-1, and the second resistor 152-2 may constitute a repeating unit 100-1, and the number of the repeating units 100-1 is not limited to Figure 1The number shown is 1, but may be 2 or any number greater than two.

[0082] The source terminal S of the transistor element 150 is electrically connected to the first end of the first capacitor 110-1, and both are grounded or electrically connected to an external circuit. The first end of the first resistor 152-1, the drain terminal D' of the transistor element 150, the second end of the first capacitor 110-1 and the cathode D1- of the first diode 130-1 are electrically connected to the same node N1. The first end of the second capacitor 110-2 is electrically connected to the second end of the first resistor 152-1, and both are electrically connected to the drain terminal D of the semiconductor element 100. The second end of the second capacitor 110-2, the first end of the second resistor 152-2 and the cathode D2- of the second diode 130-2 are electrically connected to the same node N2. The first diode 130-1 and the second diode 130-2 are connected in series back to back, and the anode D1+ of the first diode 130-1 is electrically connected to the anode D1+ of the second diode 130-2. The second end of the second resistor 152-2 is grounded or electrically connected to an external circuit.

[0083] Figure 2 is a schematic top view of a local area of ​​a semiconductor element according to an embodiment of the present invention, and its corresponding circuit diagram may be regarded as including or derived from Figure 1 Circuit diagram of Figure 2 As shown, the semiconductor element 100 includes a left-right symmetrical structure. For the sake of brevity, the following mainly describes the left structure. With respect to the left structure of the semiconductor element 100, it at least includes a gate 109G, a dielectric isolation portion 108 connected at the ends or in a ring shape (for example, a first dielectric isolation portion 108-1 and a second dielectric isolation portion 108-2), a plurality of diodes (for example, a first diode (not shown), a second diode 130-2, a fifth diode (not shown), and a sixth diode 130-6), a plurality of base regions 117 (for example, a first base region 117-1 and a second base region 117-2), a drain region 113D, a plurality of contact plugs CT, and a plurality of interconnecting wires M1. For ease of understanding, some of the following paragraphs need to be referred to at the same time. Figure 1 and Figure 2 .

[0084] like Figure 1 and Figure 2 As shown, Figure 2 The gate 109G can correspond to Figure 1 The gate 109G is a gate of the transistor element 150. The gate 109G may be formed by a patterned semiconductor layer.

[0085] Figure 2The base regions 117 and dielectric isolation parts 108 are arranged alternately. The dielectric isolation parts 108, such as the first dielectric isolation part 108-1 and the second dielectric isolation part 108-2, will be respectively arranged in multiple annular grooves, for example, respectively arranged in the first groove and the second groove. Each annular groove can form a closed shape, and the first groove can surround the second groove. Base regions 117 will be arranged between adjacent dielectric isolation parts 108, and each base region 117 can form a closed shape. Field plates (not shown) can be arranged below the first dielectric isolation part 108-1 and the second dielectric isolation part 108-2, and these field plates can respectively form Figure 1 The drain region 113D is surrounded by the body region 117 and the dielectric isolation portion 108.

[0086] Figure 2 The second diode 130-2 and the sixth diode 130-6 shown may be formed by the patterned semiconductor layer 132. According to one embodiment, Figure 2 The second diode 130-2 shown may correspond to Figure 1 The second diode 130-2 is shown, and Figure 2 The sixth diode 130-6 shown is not present in Figure 1 According to one embodiment, the second diode 130-2 is disposed in the active region of the semiconductor device 100, and the sixth diode 130-6 is disposed in the peripheral terminal region of the semiconductor device 100. According to one embodiment, the second diode 130-2 and the sixth diode 130-6 are disposed separately from each other on the top surface of the second dielectric isolation portion 108-2, and are disposed along the longitudinal axis direction of the second dielectric isolation portion 108-2. The cathodes of the second diode 130-2 and the sixth diode 130-6 are electrically connected to each other, and the respective anodes are electrically connected to different regions of the second body region 117-2. The sixth diode 130-6 can be electrically connected in parallel with the second diode 130-2. Figure 2 The multiple contact plugs CT and multiple interconnection wires M1 shown are used to electrically connect different components. For example, one of the multiple interconnection wires M1 can electrically connect the cathode of the second diode 130-2 to the cathode of the sixth diode 130-6, and the other two of the multiple interconnection wires M1 can electrically connect the anode of the second diode 130-2 and the anode of the sixth diode 130-6 to different regions of the second base region 117-2, respectively.

[0087] Figure 3 An embodiment of the present invention is along the Figure 2 The cross-sectional diagram is shown by the A-A' section line. Figure 3As shown, the semiconductor device 100 at least includes a substrate 101, a well region 103, a plurality of trenches (e.g., a first trench 105-1 and a second trench 105-2), a plurality of field plates (e.g., a first field plate 107-1 and a second field plate 107-2) respectively disposed in the plurality of trenches, a diode disposed in the well region 103 (e.g., a first diode 130-1 and a fifth diode 130-5), and a diode disposed on the well region 103 (e.g., a second diode 130-2 and a sixth diode 130-6). The substrate 101 has a first conductivity type, such as a P-type silicon substrate or a P-type silicon carbide substrate. The well region 103 has a second conductivity type and is disposed on the substrate 101, such as a deep n-type well (DNW) or an n-type epitaxial layer (N-epi). According to one embodiment, the semiconductor device 100 may include an epitaxial layer 104 having a first conductivity type, and the well region 103 having a second conductivity type may be disposed on the epitaxial layer 104. In addition, when the well region 103 is formed by performing ion implantation on the epitaxial layer 104 , the well region 103 can also be regarded as being disposed in the epitaxial layer 104 .

[0088] The first trench 105-1 is laterally separated from the second trench 105-2 (e.g., along the X direction). A first field plate 107-1 and a first dielectric layer 106-1 are disposed in the first trench 105-1. The first field plate 107-1 is a trench-shaped field plate, which extends along the Y direction (perpendicular to the X direction and the Z direction in the figure, and the direction into the paper) and is disposed on the substrate 101. A conformal or substantially conformal first dielectric layer 106-1 is disposed on the inner wall of the first trench 105-1, so that the periphery of the first field plate 107-1 is surrounded by the first dielectric layer 106-1. A first dielectric isolation portion 108-1 is disposed in the first trench 105-1 and covers the first field plate 107-1. For the second trench 105-2, a second field plate 107-2 and a second dielectric layer 106-2 are disposed in the second trench 105-2.

[0089] The second field plate 107-2 is a trench-shaped field plate, which extends along the Y direction and is disposed on the substrate 101. A conformal second dielectric layer 106-2 is disposed on the inner wall of the second trench 105-2, so that the periphery of the second field plate 107-2 is surrounded by the second dielectric layer 106-2. A second dielectric isolation portion 108-2 is disposed in the second trench 105-2 and covers the second field plate 107-2.

[0090] Also refer to Figure 1 and Figure 3, the first field plate 107-1 and the adjacent well region 103 may constitute a first capacitor 110-1, and the second field plate 107-2 and the adjacent well region 103 may constitute a second capacitor 110-2. In some embodiments, the first field plate 107-1 and the second field plate 107-2 may be formed of the same conductive material, such as polysilicon, doped polysilicon, metal silicide, metal or other conductive materials. The first dielectric layer 106-1, the second dielectric layer 106-2, the first dielectric isolation portion 108-1 and the second dielectric isolation portion 108-2 may also be formed of the same dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or a dielectric material with a high dielectric constant.

[0091] The semiconductor device 100 further includes a first base region 117-1 and a second base region 117-2 disposed in the well region 103. According to one embodiment, the first base region 117-1 and the second base region 117-2 are disposed in pairs. The first base region 117-1 has a first conductivity type, such as a P type, and is disposed on a first side of the first field plate 107-1. The second base region 117-2 also has a first conductivity type, is disposed in the well region 103 between the first field plate 107-1 and the second field plate 107-2, and is laterally separated from the first base region 117-1. The bottom surface of the first base region 117-1 and the bottom surface of the second base region 117-2 are respectively higher than the top surfaces of the first field plate 107-1 and the second field plate 107-2.

[0092] The P-type second body region 117-2 and the N-type well region 103 are adjacent to form a PN interface of a diode to respectively form a first diode 130-1 and a fifth diode 130-5. Taking the first diode 130-1 as an example, the second body region 117-2 forms an anode D1+ of the first diode 130-1, and a portion of the well region 103 adjacent to the second body region 117-2 forms a cathode D1- of the first diode 130-1. The configuration of the fifth diode 130-5 is similar to the first diode 130-1, and will not be repeated here.

[0093] The second diode 130-2 includes an anode D2+ and a cathode D2-, wherein the anode D2+ of the second diode 130-2 is electrically connected to the anode D1+ of the first diode 130-1 via the contact plug CT_2a, the interconnection wire M1_1 and the contact plug CT_1 in sequence, and the cathode (not shown) of the second diode 130-2 is electrically connected to the second field plate 107-2. Similarly, the anode D6+ of the sixth diode 130-6 is electrically connected to the anode of the fifth diode 130-5 via the contact plug CT_6a, the interconnection wire M1_2 and the contact plug CT_5 in sequence, and the cathode (not shown) of the sixth diode 130-6 is electrically connected to the second field plate 107-2.

[0094] The second diode 130-2 and the sixth diode 130-6 may be respectively disposed on the second dielectric isolation portion 108-2 and laterally separated from the second base region 117-2. The material of the second diode 130-2 and the sixth diode 130-6 may include a patterned semiconductor material, such as conductive polysilicon. The method for manufacturing the second diode 130-2 and the sixth diode 130-6 may include depositing a semiconductor layer on the entire surface directly above the well region 103 and the second field plate 107-2. A doping process is then performed to form an N-type semiconductor region in a selected area (to serve as the cathode of the subsequent diode) and a P-type semiconductor region in another selected area (to serve as the anode of the subsequent diode). Thereafter, a patterning process, such as photolithography and etching process, is performed to produce patterned semiconductor layers 132-2 and 132-6. This patterned semiconductor layer 132-2 and 132-6 can be used as the second diode 130-2 and the sixth diode 130-6. The vertical projection planes of the patterned semiconductor layers 132 - 2 and 132 - 6 are accommodated in the vertical projection plane of the second trench 105 - 2 .

[0095] The semiconductor device 100 further includes a source region 111S and a drain region 113D. The source region 111S is disposed in the first body region 117-1. The drain region 113D is disposed on the second side of the second trench 105-2 and is laterally separated from the second body region 117-2. Figure 3 On the right half of the image, the first base region 117-1, the first trench 105-1, the second base region 117-2, the second trench 105-2 and the drain region 113D are sequentially arranged along a first direction (eg, the X direction).

[0096] The semiconductor device 100 further includes a source electrode (not shown) disposed at a first side of the first trench 105-1 and electrically connected to the source region 111S. The source electrode may be selectively electrically connected to the first field plate 107-1 so that the potentials of the two are the same.

[0097] The semiconductor device 100 further includes a body contact region 118 disposed in the first body region 117 - 1 and electrically connected to the source region 111S. The body contact region 118 has a first conductivity type and a doping concentration higher than that of the first body region 117 - 1.

[0098] The semiconductor device 100 further includes a gate 109G, including a bottom surface and a side surface. The gate 109G is disposed on the well region 103 and partially overlaps the first base region 117-1, so that the source region 111S is located between the gate 109 and the first trench 105-1. When an appropriate positive bias is applied to the gate 109G, a conduction channel can be formed in the first base region 117-1 adjacent to the bottom surface of the gate 109, so that the semiconductor device 100 is turned on. The material of the gate 109G can include a patterned semiconductor material, such as conductive polysilicon, and the gate 109G can be integrated into the process of the second diode 130-2 and the sixth diode 130-6.

[0099] The semiconductor device 100 further includes an interlayer dielectric layer 120 covering the first diode 130 - 1 , the second diode 130 - 2 , the fifth diode 130 - 5 , and the sixth diode 130 - 6 . A plurality of contact plugs CT_1 , CT_2 a , CT_5 , and CT_6 a are disposed in the interlayer dielectric layer 120 .

[0100] According to one embodiment of the present invention, Figure 3 The right side structure of the semiconductor device 100 shown (the structure at least includes the first field plate 107-1, the second field plate 107-2, the gate 109G, the source region 111S, the base contact region 118, the first base region 117-1, the second base region 117-2, the first diode 130-1, and the second diode 130-2) is located in the active area of ​​the semiconductor device 100, which can constitute an active area sub-unit structure.

[0101] The left side structure of the semiconductor device 100 is located in the peripheral terminal region of the semiconductor device 100, and its partial structure is different from the active region sub-unit structure. Therefore, the gate 109G, source region 111S, and substrate contact region 118 are not disposed near the first substrate region 117-1, and it can constitute a peripheral terminal region sub-unit structure.

[0102] According to different requirements, the number of active area sub-unit structures can be 2 or any even number, and every two (or each pair) active area sub-unit structures can form a ring structure together to surround a shared drain region 113D. Each pair of active area sub-unit structures can be arranged along the X direction and present a mirror-symmetrical relationship in the X direction to form an active area unit structure. The number of active area unit structures can be any integer greater than 1 and are repeatedly arranged along the X direction. When the semiconductor element 100 includes a plurality of active area unit structures, each active area unit structure can operate independently or in coordination to become a conducting state or a cut-off state. According to one embodiment of the present invention, the active area corresponding to the center of the semiconductor element 100 can have a plurality of active area sub-unit structures, which are repeatedly arranged along the X and Y directions to form an array arrangement. In contrast, a plurality of peripheral terminal areas are arranged along the periphery of the semiconductor element 100 chip and are arranged close to the outermost side of the active area.

[0103] Figure 4 An embodiment of the present invention is along the Figure 2 The cross-sectional diagram is shown by the B-B' section line. Figure 4 As shown, the second field plate 107-2 is a continuous structure, a portion of which extends along the Y direction, and another portion of which is at an angle to the Y direction, and the second diode 130-2 is disposed on the dielectric isolation portion 108. The anode D2+ of the second diode 130-2 is electrically connected to the interconnect wire M1_1 through the contact plug CT_2a, and as shown in FIG. Figure 3 As shown, the interconnection wire M1_1 is further electrically connected to the anode D1+ of the adjacent first diode 130-1. Figure 4 As shown, the cathode D2- of the second diode 130-2 is electrically connected to the interconnection wire M1_3 through the contact plug CT_2b, and is further electrically connected to the second field plate 107-2 directly therebelow and to the ground.

[0104] The operation process of the semiconductor device 100 is further described below. Since the operation of the fifth diode 130-5 and the sixth diode 130-6 is similar to the operation of the first diode 130-1 and the second diode 130-2, only the operation of the first diode 130-1 and the second diode 130-2 will be described below.

[0105] Also refer to Figures 1 to 4 , when the transistor element 150 (refer to Figure 1 ) is in the off state, the drain input terminal D (refer to Figure 1) will apply a higher positive bias to the drain region 113D, and this positive bias applied to the drain region 113D will further apply a reverse bias to the cathode D1- of the first diode 130-1, causing the first diode 130-1 to generate a reverse current flowing from the cathode D1- to the anode D1+. Since this reverse current is a forward current for the second diode 130-2, and since the cathode D2- of the second diode 130-2 is electrically connected to the second field plate 107-2, the current can further flow to the second field plate 107-2 in the second trench 105-2, and charge the second field plate 107-2, thereby raising the positive potential of the second field plate 107-2. The second field plate 107-2, the second dielectric layer 106-2 and the adjacent well region 103 constitute Figure 1 The second capacitor 110-2.

[0106] In contrast, when the transistor element 150 (see Figure 1 ) is in the on state, the voltage applied to the cathode D1- of the first diode 130-1 will approach the ground voltage of the source of the transistor element 150, so the forward bias voltage applied to the cathode D1- of the first diode 130-1 will be reduced, and the value of the forward bias voltage is lower than the forward bias voltage applied to the cathode D1- when the transistor element 150 is in the off state. Due to the existence of the second diode 130-2, it is not easy for the current to flow from the cathode D2- of the second diode 130-2 to the anode D2+ of the second diode 130-2, so the positive charge stored in the second field plate 107-2 will not be lost immediately, but will be stored in the second field plate 107-2 for a period of time. Therefore, the positive charge stored in the second field plate 107-2 can reduce the on-resistance of the adjacent well region 103, and will not reduce the breakdown voltage of the semiconductor device 100.

[0107] Figure 5 is a simplified circuit diagram of a variation of an embodiment of the present invention including semiconductor components. Figure 5 The circuit diagram is similar to Figure 1 The main difference between the two is that Figure 5 The semiconductor device 100 includes two repeating units, for example, a repeating unit 100-1 and a repeating unit 100-2. The structure of the repeating unit 100-1 is similar to Figure 1 As shown, no further details are given here.

[0108] For the repeating unit 100-2, the repeating unit 100-2 is substantially equal to the repeating unit 100-1. The repeating unit 100-2 also includes a capacitor (such as the third capacitor 110-3), two diodes (such as the third diode 130-3 and the fourth diode 130-4) and two resistors (such as the third resistor 152-3 and the fourth resistor 152-4).

[0109] The second end of the first resistor 152-1, the first end of the second capacitor 110-2, the first end of the third resistor 152-3 and the cathode D3- of the third diode 130-3 are electrically connected to the same node N3. The first end of the third capacitor 110-3 and the second end of the third resistor 152-3 are electrically connected to the drain input terminal D. The second end of the third capacitor 110-3, the first end of the fourth resistor 152-4 and the cathode D4- of the fourth diode 130-4 are electrically connected to the same node N4. The third diode 130-3 and the fourth diode 130-4 are connected in series back to back, and the anode D3+ of the third diode 130-3 is electrically connected to the anode D4+ of the fourth diode 130-4. The other end of the fourth resistor 152-4 is grounded or electrically connected to an external circuit.

[0110] Figure 6 FIG. 1 is a schematic top view of a local area of ​​a semiconductor element according to an embodiment of the present invention. Figure 6 The top view structure shown is similar to Figure 2 The main difference of the top view structure shown is that the dielectric isolation portion 108 includes Figure 2 The dielectric isolation portion 108 shown further includes a third dielectric isolation portion 108-3, and the third dielectric isolation portion 108-3 is surrounded by the second dielectric isolation portion 108-2. The base region 117 further includes a third base region 117-3, and the third base region 117-3 is disposed between the second dielectric isolation portion 108-2 and the third dielectric isolation portion 108-3. The semiconductor device 100 further includes a third diode (not shown), a fourth diode 130-4, a seventh diode (not shown), and an eighth diode 130-8.

[0111] like Figure 6 As shown, the third dielectric isolation portion 108-3 is disposed in an annular trench, such as a third trench. According to one embodiment, the fourth diode 130-4 and the eighth diode 130-8 are disposed separately from each other on the top surface of the third dielectric isolation portion 108-3 and are disposed along the longitudinal axis direction of the third dielectric isolation portion 108-3. The cathodes (not shown) of the fourth diode 130-4 and the eighth diode 130-8 are electrically connected to each other through one of the plurality of interconnecting wires M1, and their anodes are electrically connected to the third base region 117-3 through another of the plurality of interconnecting wires M1.

[0112] Figure 7 An embodiment of the present invention is along the Figure 6 The cross-sectional diagram is shown by the A-A' section line. Figure 7 As shown, Figure 7 The cross-sectional structure shown is similar to Figure 3The main difference of the cross-sectional structure shown is that the semiconductor device 100 further includes a third trench 105-3, a third body region 117-3, a third diode 130-3, a fourth diode 130-4, a fifth diode 130-5, a sixth diode 130-6, a seventh diode 130-7, and an eighth diode 130-8.

[0113] The third trenches 105-3 are arranged in pairs in the well region 103, and a third field plate 107-3 and a third dielectric layer 106-3 are arranged in the third trenches 105-3, and the third dielectric layer 106-3 surrounds the third field plate 107-3. The third base region 117-3, which has a first conductivity type, such as a P type, is arranged in the well region 103 between the second trench 105-2 and the third trench 105-3.

[0114] The P-type third body region 117-3 and the N-type well region 103 are adjacent to form a PN interface of a diode to respectively form a third diode 130-3 and a seventh diode 130-7. Taking the third diode 130-3 as an example, the third body region 117-3 forms an anode D3+ of the third diode 130-3, and a portion of the well region 103 adjacent to the third body region 117-3 forms a cathode D1- of the third diode 130-3. The configuration of the seventh diode 130-7 is similar to that of the third diode 130-3, and will not be repeated here.

[0115] The fourth diode 130-4 includes an anode (not shown) and a cathode D4-, wherein the anode of the fourth diode 130-4 is electrically connected to the anode D3+ of the third diode 130-3, and the cathode D4- of the fourth diode 130-4 is electrically connected to the third field plate 107-3 in the third trench 105-3. Similarly, the eighth diode 130-8 includes an anode (not shown) and a cathode D8-, wherein the anode of the eighth diode 130-8 is electrically connected to the anode of the seventh diode 130-7, and the cathode D8- of the eighth diode 130-8 is electrically connected to the third field plate 107-3 in the third trench 105-3.

[0116] In addition, the anode D1+ of the first diode 130-1 and the anode D5+ of the fifth diode 130-5 are located in different regions of the same annular matrix region, and are therefore electrically connected to each other. Similarly, the anode D3+ of the third diode 130-3 and the anode D7+ of the seventh diode 130-7 are located in different regions of the same annular matrix region, and are therefore electrically connected to each other.

[0117] According to one embodiment of the present invention, Figure 7The right side structure of the semiconductor device 100 shown (the structure at least includes the first field plate 107-1 to the third field plate 107-3, the gate 109G, the source region 111S, the base contact region 118, the first base region 117-1 to the third base region 117-3, the first diode 130-1 to the fourth diode 130-4) is located in the active area of ​​the semiconductor device 100, which can constitute an active area sub-unit structure.

[0118] The left structure of the semiconductor device 100 is located in the peripheral terminal region of the semiconductor device 100 , so the gate 109G, the source region 111S, and the substrate contact region 118 are not disposed near the first substrate region 117 - 1 , which can constitute a peripheral terminal region sub-unit structure.

[0119] According to different requirements, the number of active area sub-unit structures can be 2 or any even number, and every two (or each pair) active area sub-unit structures can form a ring structure together to surround a shared drain region 113D. Each pair of active area sub-unit structures can be arranged along the X direction and present a mirror-symmetrical relationship in the X direction to form an active area unit structure. The number of active area unit structures can be any integer greater than 1 and are repeatedly arranged along the X direction. When the semiconductor element 100 includes a plurality of active area unit structures, each active area unit structure can operate independently or in coordination to become a conducting state or a cut-off state. According to one embodiment of the present invention, the active area corresponding to the center of the semiconductor element 100 can have a plurality of active area sub-unit structures, which are repeatedly arranged along the X and Y directions to form an array arrangement. In contrast, a plurality of peripheral terminal areas are arranged along the periphery of the semiconductor element 100 chip and are arranged close to the outermost side of the active area.

[0120] against Figure 6 The cross-sectional diagram of the B-B' section line is similar to Figure 4 The cross-sectional schematic diagram shown will not be repeated here.

[0121] Figure 8 An embodiment of the present invention is along the Figure 6 The cross-sectional diagram is shown by the C-C' section line. Figure 8 As shown, the fourth diode 130-4 is disposed on the third dielectric isolation portion 108-3, and the vertical projection plane of the fourth diode 130-4 is accommodated in the vertical projection plane of the third trench 105-3. The anode D4+ of the fourth diode 130-4 is electrically connected to the contact plug CT_4a, the interconnection wire M1_4, the contact plug CT_3 in sequence, and is electrically connected to the anode D3+ of the adjacent third diode 130-3.

[0122] Fig. 9 An embodiment of the present invention is along the Figure 6 The cross-sectional diagram is shown by the D-D' section line. Fig. 9 As shown, the third field plate 107-3 is a continuous structure, a portion of which extends along the Y direction, and another portion of which forms an angle with the Y direction, and the fourth diode 130-4 is disposed on the third dielectric isolation portion 108-3. Figure 8 and Fig. 9 , the anode D4+ of the fourth diode 130-4 is electrically connected to the contact plug CT_4a and the interconnection wire M1_4 in sequence, and is electrically connected to the anode D3+ of the adjacent third diode 130-3. Figure 6 , Figure 7 and Fig. 9 The cathode D4- of the fourth diode 130-4 is electrically connected to the contact plug CT_4b and the interconnection wire M1_5 in sequence, and the interconnection wire M1_5 can be further electrically connected to the third field plate 107-3 directly below through the contact plug CT, and grounded through other wires. The cathode D4- of the fourth diode 130-4 is not electrically connected to the cathode of the second diode 130-2.

[0123] The operation process of the semiconductor device 100 is further described below. Since the operation of the fifth diode 130-5 to the eighth diode 130-8 is similar to the operation of the first diode 130-1 to the fourth diode 130-4, only the operation of the first diode 130-1 to the fourth diode 130-4 will be described below.

[0124] Also refer to Figures 5 to 9 When the transistor element 150 of the semiconductor device 100 is in the cut-off state, the drain input terminal D will apply a higher forward bias voltage to the drain region 113D, and the forward bias voltage applied to the drain region 113D will further apply a higher reverse bias voltage to the first diode 130-1 and the third diode 130-3, which is sufficient to cause the first diode 130-1 and the third diode 130-3 to generate a reverse current flowing from the cathode D1-, D3- to the anode D1+, D3+. This reverse current is a forward current for the second diode 130-2 and the fourth diode 130-4, and since the cathode D2- of the second diode 130-2 and the cathode D4- of the fourth diode 130-4 are electrically connected to the second field plate 107-2 and the third field plate 107-3 respectively, the current can further flow to the second field plate 107-2 in the second trench 105-2 and the third field plate 107-3 in the third trench 105-3, and charge the second field plate 107-2 and the third field plate 107-3, thereby raising the positive potential of the second field plate 107-2 and the third field plate 107-3. The third field plate 107-3, the third dielectric layer 106-3 and the adjacent well region 103 constitute Figure 6In addition, since the second capacitor 110-2 is far from the drain input terminal D and the third capacitor 110-3 is closer to the drain input terminal D, the saturated positive potential of the second field plate 107-2 of the second capacitor 110-2 is smaller than the saturated positive potential of the third field plate 107-3 of the third capacitor 110-3.

[0125] In contrast, when the transistor element 150 of the semiconductor element 100 is in the on state, the voltage of the cathode D1- of the first diode 130-1 and the cathode D3- of the third diode 130-3 will approach the ground voltage of the source of the transistor element 150, so the forward bias voltage applied to the cathode D1- of the first diode 130-1 and the cathode D3- of the third diode 130-3 will be reduced, making the value of the forward bias voltage lower than the forward bias voltage applied to the cathodes D1- and D3- when the transistor element 150 is in the off state. Due to the existence of the second diode 130-2 and the fourth diode 130-4, it is not easy for current to flow from the cathode D2- of the second diode 130-2 to the anode D2+ of the second diode 130-2, and it is not easy for current to flow from the cathode D4- of the fourth diode 130-4 to the anode D4+ of the fourth diode 130-4, so the positive charges stored in the second field plate 107-2 of the second capacitor 110-2 and the third field plate 107-3 of the third capacitor 110-3 will not be lost immediately, but will be stored in the second field plate 107-2 of the second capacitor 110-2 and the third field plate 107-3 of the third capacitor 110-3 for a period of time. Therefore, the positive charges stored in the second field plate 107-2 and the third field plate 107-3 can reduce the on-resistance of the adjacent well region 103 without reducing the breakdown voltage of the semiconductor device 100.

[0126] Fig.10 It is a schematic cross-sectional view of a local area of ​​a semiconductor element according to a variant embodiment of the present invention. Fig.10 The structure is similar to Figure 3 The main difference between the two is that Fig.10 The gate 109G of the semiconductor device 100 is disposed in the first trench 105-1 and is separated from the first field plate 107-1 in the longitudinal direction (e.g., in the Z direction). The side surface of the gate 109G overlaps the side surfaces of the first base region 117-1 and the source region 111S. When an appropriate positive bias is applied to the gate 109G, a conduction channel can be formed in the first base region 117-1 adjacent to the side surface of the gate 109G, so that the semiconductor device 100 is turned on.

[0127] Fig.11 It is a schematic cross-sectional view of a local area of ​​a semiconductor element according to a variant embodiment of the present invention. Fig.11 The structure is similar to Figure 7The main difference between the two is that Fig.11 The first field plate 107-1, the second field plate 107-2, and the third field plate 107-3 of the semiconductor element 100 are not disposed in the trench but are disposed on the well region 103. In addition, the positions and structures of the second diode 130-2 and the fourth diode 130-4 are not particularly limited, as long as the anode D2+ of the second diode 130-2 can be electrically connected to the anode D1+ of the first diode 130-1, the cathode D2- of the second diode 130-2 can be electrically connected to the second field plate 107-2, the anode D4+ of the fourth diode 130-4 can be electrically connected to the anode D3+ of the third diode 130-3, and the cathode D4- of the fourth diode 130-4 can be electrically connected to the third field plate 107-3.

[0128] Fig.12 It is a schematic cross-sectional view of a local area of ​​a semiconductor element according to a variant embodiment of the present invention. Fig.12 The structure is similar to Figure 7 The main difference between the two is that Fig.12 The gate 190G of the semiconductor device 100 is disposed in the first trench 105-1 and is longitudinally separated from the first field plate 107-1. The side of the gate 109G overlaps the first body region 117-1 and the source region 111S. When an appropriate positive bias is applied to the gate 109G, a conduction channel can be formed in the first body region 117-1 adjacent to the side of the gate 109G, so that the semiconductor device 100 is turned on.

[0129] Fig.12 and Figure 7 Another difference between Fig.12 The anode D1+ of the first diode 130-1 and the anode D2+ of the second diode 130-2 of the semiconductor element 100 are not arranged in the well region 103, but are arranged in the second trench 105-2 and the third trench 105-3, respectively, and are located on the top surfaces of the second field plate 107-2 and the third field plate 107-3. In addition, the positions and structures of the second diode 130-2 and the fourth diode 130-4 are not particularly limited, as long as the anode D2+ of the second diode 130-2 can be electrically connected to the anode D1+ of the first diode 130-1, the cathode D2- of the second diode 130-2 can be electrically connected to the second field plate 107-2, the anode D4+ of the fourth diode 130-4 can be electrically connected to the anode D3+ of the third diode 130-3, and the cathode D4- of the fourth diode 130-4 can be electrically connected to the third field plate 107-3.

[0130] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor element, characterized in that: include: a substrate having a first conductivity type; a well region having a second conductivity type and disposed on the substrate; a first field plate, disposed on the substrate; a second field plate disposed on the substrate and laterally separated from the first field plate; a first diode comprising an anode and a cathode, wherein the anode of the first diode is adjacent to the well region, and the cathode of the first diode includes a portion of the well region; and A second diode includes an anode and a cathode, wherein the anode of the second diode is electrically connected to the anode of the first diode, and the cathode of the second diode is electrically connected to the second field plate.

2. The semiconductor device according to claim 1, wherein: Also includes: a first base region having the first conductivity type and disposed on the first side of the first field plate; as well as A second body region, having the first conductivity type, is disposed in the well region between the first field plate and the second field plate and laterally separated from the first body region, wherein the second body region is the anode of the first diode.

3. The semiconductor device according to claim 2, wherein: Also includes: a first trench disposed in the well region, wherein the first field plate and a first dielectric layer surrounding the first field plate are disposed in the first trench; as well as A second trench is disposed in the well region, wherein the second field plate and a second dielectric layer surrounding the second field plate are disposed in the second trench, wherein the second trench is laterally separated from the first trench.

4. The semiconductor device according to claim 3, wherein: Also includes: a source region, disposed in the first substrate region; as well as a drain region disposed on a second side of the second trench, The first base region, the first trench, the second base region, the second trench and the drain region are arranged in sequence along a first direction.

5. The semiconductor device according to claim 4, wherein: Also includes: a source electrode disposed on the first side of the first trench; as well as A gate includes a bottom surface and a side surface, and one of the bottom surface and the side surface overlaps the first base region.

6. The semiconductor device according to claim 5, wherein: The potential of the source electrode is the same as the potential of the first field plate.

7. The semiconductor device according to claim 5, wherein: The gate is disposed in the first trench and is longitudinally separated from the first field plate.

8. The semiconductor device according to claim 5, wherein: The gate is disposed on the well region, and the source region is located between the gate and the first trench.

9. The semiconductor device according to claim 3, wherein: The bottom surface of the first base region and the bottom surface of the second base region are respectively higher than the top surfaces of the first field plate and the second field plate.

10. The semiconductor device according to claim 3, wherein: The well region adjacent to the second body region constitutes a cathode of the first diode.

11. The semiconductor device according to claim 3, wherein: The second diode includes a patterned semiconductor layer disposed directly above the second field plate and laterally separated from the second base region.

12. The semiconductor device according to claim 11, wherein A vertical projection plane of the patterned semiconductor layer is contained within a vertical projection plane of the second trench.

13. The semiconductor device according to claim 11, wherein The cathode of the second diode and the second field plate are electrically grounded.

14. The semiconductor device according to claim 11, wherein Also includes: A dielectric isolation portion is disposed in the second trench and located between the patterned semiconductor layer and the second field plate.

15. The semiconductor device according to claim 1, wherein In a top view, the first groove surrounds the second groove, and the first groove and the second groove each have a closed shape.

16. The semiconductor device according to claim 3, wherein: Also includes: a third trench disposed in the well region, wherein a third field plate and a third dielectric layer surrounding the third field plate are disposed in the third trench; a third body region, having the first conductivity type, disposed in the well region between the second trench and the third trench; a third diode comprising an anode and a cathode, wherein the anode of the third body region includes the third body region; and A fourth diode comprises an anode and a cathode, wherein the anode of the fourth diode is electrically connected to the anode of the third diode, and the cathode of the fourth diode is electrically connected to the third field plate in the third trench.

17. The semiconductor device according to claim 16, wherein: Also includes: a source region, disposed in the first substrate region; as well as a drain region disposed on a second side of the third trench, The first base region, the first trench, the second base region, the second trench, the third base region, the third trench and the drain region are arranged in sequence along a first direction.

18. The semiconductor device according to claim 16, wherein: The bottom surface of the third base region is higher than the top surface of the third field plate.

19. The semiconductor device according to claim 16, wherein: The cathode of the third diode includes the well region adjacent to the third body region.

20. The semiconductor device according to claim 16, wherein The fourth diode includes a patterned semiconductor layer, which is disposed directly above the third field plate and laterally separated from the third base region.

21. The semiconductor device according to claim 20, wherein: A vertical projection plane of the patterned semiconductor layer is contained within a vertical projection plane of the third trench.

22. The semiconductor device according to claim 16, wherein: The cathode of the fourth diode and the third field plate are electrically grounded.

23. The semiconductor device according to claim 16, wherein: The cathode of the fourth diode is not electrically connected to the cathode of the second diode.

24. The semiconductor device according to claim 16, wherein: In a top view, the first trench surrounds the second trench and the third trench, and the first trench, the second trench, and the third trench each have a closed shape.

25. The semiconductor device according to claim 1, wherein The first field plate and the second field plate are disposed on the well region.

26. The semiconductor device according to claim 1, wherein The anode of the first diode is disposed on the second field plate.

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