Non-stack CMOS image sensor and forming method of vertical transfer transistor of non-stack CMOS image sensor
By etching trenches and depositing polysilicon on the non-stack CMOS image sensor, combining ion implantation and polysilicon step formation methods, the problem of low-cost preparation of vertical transfer transistors on the non-stack CMOS image sensor is solved, and the process cost reduction and uniform doping of the vertical transfer transistor gate are achieved.
Patent Information
- Application Number
- CN202311041183.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-17
- Publication Date
- 2025-02-25
AI Technical Summary
The prior art is difficult to prepare vertical transfer transistors (VTGs) on non-stack CMOS image sensors at low cost because it is difficult to achieve the fabrication of VTG gates, NMOS gates and PMOS gates in one go.
By etching the trench on the silicon substrate, depositing the polysilicon filled trench, ion implantation and polysilicon step formation, the simultaneous preparation of the vertical transfer transistor gate, NMOS gate and PMOS gate is achieved.
The manufacturing process cost is reduced, the uniform heavy doping concentration of the gate of the vertical transfer transistor is ensured, and it is suitable for the preparation of vertical transfer transistors with different etching depths.
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Figure CN119521809A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a non-stacked CMOS image sensor and a method for forming a vertical transfer transistor thereof. Background Art
[0002] In recent years, CMOS image sensors have been widely used in many fields, such as security monitoring, automotive, consumer electronics, medical equipment, etc. The consumer electronics field has put forward higher requirements for the high resolution of CMOS image sensors, and small-size pixels have been continuously developed. As the pixel size continues to shrink, the distance between the photodiode (PD) and the transistor is gradually reduced, and the risk of punch-through between the PD and the transistor is also increasing. In addition, as the pixel size decreases, the full well capacity of each pixel will also decrease. Therefore, it is hoped that more full well capacity can be obtained by utilizing deeper semiconductor areas.
[0003] Based on the above points, the vertical transfer transistor was developed. With the help of the stronger gate control capability of the vertical transfer transistor, more full hydrazine capacity can be obtained by deepening the PD and utilizing the deeper semiconductor area. At the same time, the spacing between the PD and the transistor is increased, and the isolation between the PD and the transistor is also strengthened.
[0004] Existing vertical transfer transistors VTG are usually used in high-cost stacked CMOS image sensors. Generally, there are only NMOS transistors in the pixel layer. Therefore, the gate of the vertical transfer transistor can be prepared by depositing pre-doped N-type polysilicon at the same time as other transistors in the pixel area. However, the high cost of stacked CMOS image sensors limits their competitiveness.
[0005] Compared with stacked CMOS image sensors, non-stacked CMOS image sensors have a lower manufacturing cost. However, since non-stacked CMOS image sensors usually contain both PMOS and NMOS transistors, it is difficult to simultaneously fill VTG and other peripheral transistors by depositing pre-doped N-type or P-type polysilicon in one go. Therefore, it is still a major challenge to prepare VTG on non-stacked CMOS image sensors at a low cost.
[0006] The statements herein merely provide background art related to the present invention and do not necessarily constitute prior art. Summary of the invention
[0007] The object of the present invention is to provide a non-stacked CMOS image sensor and a method for forming a vertical transfer transistor thereof, which can realize the production of a vertical transfer transistor gate, an NMOS transistor gate and a PMOS transistor gate simultaneously through a single deposition, thereby reducing the manufacturing process cost and ensuring that the vertical transfer transistor gate has a uniform heavy doping concentration.
[0008] In order to achieve the above object, the present invention provides a method for forming a vertical transfer transistor for an image sensor, which at least comprises:
[0009] providing a silicon substrate;
[0010] Etching the silicon substrate to form a groove;
[0011] Depositing polysilicon to fill the trench to form a polysilicon layer;
[0012] Performing a first ion implantation on the polysilicon layer;
[0013] Etching a portion of the polysilicon on the silicon substrate and a portion of the polysilicon in the trench to form a polysilicon step;
[0014] A second ion implantation is performed on the polysilicon step to form a vertical transfer transistor gate.
[0015] The polysilicon is non-doped polysilicon.
[0016] The polysilicon step comprises a recessed portion located in the trench and a polysilicon step portion located above the silicon substrate; the distance between the bottom of the recessed portion and the surface of the silicon substrate is less than 0.2 um.
[0017] Optionally, the method of performing a second ion implantation on the polysilicon step comprises:
[0018] forming a first side wall structure, wherein the first side wall structure is located outside the step portion and inside the groove portion;
[0019] A photoresist is formed on the silicon substrate, and the photoresist is photolithographically developed to expose a portion of the polysilicon step that needs to be ion implanted, and a second ion implantation is performed.
[0020] Optionally, the method of performing a second ion implantation on the polysilicon step comprises:
[0021] Forming a photoresist on the silicon substrate, performing photolithography development on the photoresist to expose a portion of the polysilicon step that needs to be ion implanted, and performing a second ion implantation;
[0022] A first sidewall structure is formed, wherein the first sidewall structure is located outside the polysilicon step portion and inside the groove portion.
[0023] The conductivity type of the first ion implantation and the second ion implantation is consistent, the first ion implantation and the second ion implantation are of the first conductivity type, or the first ion implantation and the second ion implantation are of the second conductivity type.
[0024] After the second ion implantation, a lightly doped drain implantation is performed, and then a lightly doped drain implantation heat treatment is performed;
[0025] Alternatively, a lightly doped drain implantation is performed first, followed by a second ion implantation, and then a lightly doped drain implantation heat treatment is performed.
[0026] The depth of the groove is 0.05um to 1um.
[0027] Before depositing the polysilicon into the trench, a gate oxide layer is deposited on the surface of the trench, and the polysilicon layer is formed on the gate oxide layer.
[0028] The polysilicon layer is 0.05um to 0.2um higher than the surface of the silicon substrate.
[0029] The silicon substrate is pre-processed; the pre-processing at least includes: forming a photosensitive unit.
[0030] The etching of the silicon substrate to form a groove comprises:
[0031] Etching the silicon substrate to form a shallow trench;
[0032] Depositing a dielectric layer to fill the shallow trench to form a shallow trench isolation structure;
[0033] The shallow trench isolation structure and the silicon substrate are etched to form the trench.
[0034] The present invention also provides a vertical transfer transistor, which is prepared by the method for forming the vertical transfer transistor for an image sensor.
[0035] The present invention also provides a method for forming a non-stacked CMOS image sensor, which at least comprises:
[0036] Providing a silicon substrate, dividing a first conductive type MOS transistor region, a second conductive type MOS transistor region and a vertical transfer transistor region on the silicon substrate;
[0037] Etching the silicon substrate to form a groove;
[0038] Depositing polysilicon on the silicon substrate to fill the trench and form a polysilicon layer;
[0039] Performing a first ion implantation on the vertical transfer transistor region and the polysilicon layer of the first conductive type MOS transistor region or the second conductive type MOS transistor region;
[0040] Etching a portion of polysilicon on the silicon substrate and a portion of polysilicon in the trench to form a polysilicon step, a gate of a first conductive type MOS transistor, and a gate of a second conductive type MOS transistor;
[0041] A second ion implantation is performed on the polysilicon step to form a vertical transfer transistor gate.
[0042] The polysilicon is non-doped polysilicon.
[0043] The polysilicon step comprises a recessed portion located in the trench and a polysilicon step portion located above the silicon substrate; the distance between the bottom of the recessed portion and the surface of the silicon substrate is less than 0.2 um.
[0044] Optionally, the method of performing a second ion implantation on the polysilicon step comprises:
[0045] forming a first side wall structure, wherein the first side wall structure is located outside the step portion and inside the groove portion;
[0046] A photoresist is formed on the polysilicon step, and the photoresist is photolithographically developed to expose a portion of the polysilicon step that needs to be ion implanted, and a second ion implantation is performed.
[0047] Optionally, the method of performing a second ion implantation on the polysilicon step comprises:
[0048] forming a photoresist on the polysilicon step, performing photolithography development on the photoresist to expose a portion of the polysilicon step where ion implantation is required, and performing a second ion implantation;
[0049] A first sidewall structure is formed, wherein the first sidewall structure is located outside the polysilicon step portion and inside the groove portion.
[0050] The first ion implantation performed on the vertical transfer transistor region and the second ion implantation performed on the polysilicon step have the same conductivity type, and the conductivity type of the second ion implantation is the first conductivity type or the second conductivity type.
[0051] After the second ion implantation, a lightly doped drain implantation is performed, and then a lightly doped drain implantation heat treatment is performed;
[0052] Alternatively, a lightly doped drain implantation is performed first, followed by a second ion implantation, and then a lightly doped drain implantation heat treatment is performed.
[0053] The depth of the groove is 0.05um to 1um.
[0054] Before depositing the polysilicon into the trench, a gate oxide layer is deposited on the surface of the trench, and the polysilicon layer is formed on the gate oxide layer.
[0055] The polysilicon layer is 0.05um to 0.2um higher than the surface of the silicon substrate.
[0056] The silicon substrate is pre-processed; the pre-processing at least includes: forming a photosensitive unit.
[0057] The etching of the silicon substrate to form a groove comprises:
[0058] Etching the silicon substrate to form a shallow trench;
[0059] Depositing a dielectric layer to fill the shallow trench to form a shallow trench isolation structure;
[0060] The shallow trench isolation structure and the silicon substrate are etched to form the trench.
[0061] The present invention also provides a non-stacked CMOS image sensor, characterized in that it is prepared by the non-stacked CMOS image sensor forming method.
[0062] In the process of preparing a non-stacked CMOS image sensor with a vertical transfer transistor, the present invention realizes the production of a vertical transfer transistor gate, an NMOS transistor gate and a PMOS transistor gate simultaneously through one deposition, which is beneficial to reducing the manufacturing process cost. In addition, the polysilicon step structure of the vertical transfer transistor is obtained by controlling the overetching amount of polysilicon etching in a conventional planar gate preparation process, and secondary ion implantation is performed at the polysilicon step structure, so that a relatively uniform heavily doped polysilicon gate of the vertical transfer transistor can be obtained without adding an additional heat treatment process. Moreover, the process can be used to prepare vertical transfer transistors with different etching depths and has a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS
[0063] Figure 1 is a schematic diagram of preparing a conventional non-stacked CMOS image sensor.
[0064] Figure 2 It is a flow chart of a method for preparing a non-stacked CMOS image sensor in an embodiment of the present invention.
[0065] Figure 3 Schematic diagram of a silicon substrate in an embodiment of the present invention.
[0066] Figure 4 and Figure 5 It is a schematic diagram of etching a silicon substrate to form a groove in an embodiment of the present invention.
[0067] Figure 6 Schematic diagram of filling trenches to form a polysilicon layer in an embodiment of the present invention.
[0068] Figure 7 It is a schematic diagram of the first ion implantation in an embodiment of the present invention.
[0069] Figure 8 It is a schematic diagram of etching to form polysilicon steps in an embodiment of the present invention.
[0070] Fig. 9 and Fig.10 It is a schematic diagram of performing a second ion implantation on a polysilicon step in one embodiment of the present invention.
[0071] Fig.11 It is a schematic diagram of performing a second ion implantation on a polysilicon step in another embodiment of the present invention.
[0072] Fig.12 is a schematic diagram of a non-stacked CMOS image sensor formed in an embodiment of the present invention. DETAILED DESCRIPTION
[0073] The following is based on Figures 1 to 12 , specifically describe the preferred embodiments of the present invention.
[0074] In the conventional non-stacked CMOS image sensor manufacturing process, N-type polysilicon gate and P-type polysilicon gate are usually obtained by first depositing non-doped polysilicon and then performing N-type implantation and P-type implantation respectively. However, due to the deep trench etching depth of the vertical transfer transistor VTG, conventional ion implantation is limited by the implantation depth and easily leads to low doping concentration of the deep VTG gate. Figure 1 As shown, taking N-type ion implantation as an example, when N-type ions are implanted into the deep trench 11' of the vertical transfer transistor VTG using a conventional process, due to the limited implantation depth and diffusion depth of the N-type ions, even with the help of a lightly doped drain implantation process and an annealing process after the ion implantation, it is impossible to help the ions diffuse to a specified depth, resulting in the concentration of the first polysilicon 22' formed in the deep layer of the deep trench 11' being significantly lower than the concentration of the second polysilicon 33' formed in the shallow layer, resulting in a large difference in the upper and lower threshold voltages of the vertical transfer transistor VTG, which has a great impact on the readout of the photodiode PD, and will cause differences in voltages between different vertical transfer transistors VTG, which can easily cause signal differences between different pixels.
[0075] In order to overcome the above defects, Figure 2 As shown, the present invention provides a method for preparing a non-stacked CMOS image sensor, wherein the non-stacked CMOS image sensor comprises a first conductive type MOS tube region, a second conductive type MOS tube region and a vertical transfer transistor region, wherein the first conductive type refers to an N-type conductive type or a P-type conductive type, and correspondingly, the second conductive type refers to a P-type conductive type or an N-type conductive type. In this embodiment, taking the first conductive type as an N-type conductive type and the second conductive type as a P-type conductive type as an example, the method for preparing the non-stacked CMOS image sensor specifically comprises the following steps:
[0076] Step S1: Figure 3 As shown, a pre-processed silicon substrate 1 is provided, and an NMOS transistor region 101, a PMOS transistor region 102 and a vertical transfer transistor region 103 are divided on the pre-processed silicon substrate 1;
[0077] A photosensitive unit can be formed in the silicon substrate 1 through pretreatment, wherein the pretreatment at least includes: forming an active area, forming a P-type well area, forming an N-type well area, forming a photodiode and the like.
[0078] Step S2, etching the pre-treated silicon substrate 1 in the vertical transfer transistor region 103 to form a deep trench 3;
[0079] like Figure 4 As shown, a layer of photoresist 2 or hard mask 2 (such as silicon nitride) is deposited on the silicon substrate 1, and the pattern of the vertical transfer transistor VTG is transferred to the photoresist 2 (or hard mask 2) by photolithography. In one embodiment, the silicon substrate 1 can be etched to form a shallow trench (not shown in the figure), and then a dielectric layer is deposited to fill the shallow trench to form a shallow trench isolation structure (not shown in the figure), and then the shallow trench isolation structure and the silicon substrate 1 are etched to form a deep trench 3. In another embodiment, there is no need to etch the silicon substrate 1 to form a shallow trench first, that is, the silicon substrate 1 is directly etched to form the deep trench 3. Finally, the photoresist 2 (or hard mask 2) remaining on the surface of the silicon substrate 1 is removed to obtain the following Figure 5 The silicon substrate 1 shown has a deep trench 3. In this embodiment, the angle between the sidewall of the deep trench 3 and the vertical direction is 80° to 95°, and the depth of the deep trench 3 can reach 0.05um to 1um, so as to obtain more full hydrazine capacity by utilizing a deeper semiconductor region.
[0080] Step S3, depositing polysilicon on the silicon substrate 1 to fill the deep trench 3, and forming a polysilicon layer 5 in the NMOS transistor region 101, the PMOS transistor region 102 and the vertical transfer transistor region 103;
[0081] like Figure 6 As shown, a gate oxide layer 4 is first deposited on the inner surface of the deep trench 3 and the surface of the silicon substrate 1. The material of the gate oxide layer 4 can be silicon oxide. Then, non-doped polysilicon is deposited on the surface of the gate oxide layer 4. The non-doped polysilicon fills the deep trench 3 and forms a polysilicon layer 5 on the surface of the silicon substrate 1. The thickness of the polysilicon layer 5 from the surface of the silicon substrate 1 is generally between 0.05-0.2um.
[0082] Because the non-stacked image sensor contains both NMOS and PMOS transistors, if pre-doped N-type polysilicon is used, it is necessary to additionally inject excessive P-type doping to compensate for the pre-doped N-type doping ions when forming PMOS, and vice versa. Therefore, the present invention uses non-doped polysilicon to avoid the injection of excessive doping ions in subsequent processes, saving time and cost.
[0083] Step S4, performing a first N-type ion implantation on the polysilicon layer 5 of the vertical transfer transistor region 103 and the NMOS transistor region 101;
[0084] like Figure 7 As shown, a layer of photoresist 7 (or hard mask 7) is first deposited on the polysilicon layer 5 of the PMOS tube region 102 to prevent ion implantation in this region, and then the first N-type ion implantation is performed on the polysilicon layer 5 of the vertical transfer transistor region 103 and the N-type MOS tube region 101 to form a polysilicon N-type implantation region 6.
[0085] Step S5, etching a portion of the polysilicon layer 5 on the silicon substrate 1 and a portion of the polysilicon layer 5 in the deep trench 3 to form a polysilicon step structure 9, a gate 10 of the NMOS tube, and a gate 11 of the PMOS tube;
[0086] like Figure 8 As shown, a layer of photoresist 8 (or hard mask 8) is first deposited on the polysilicon N-type implantation region 6, the photoresist 8 is developed, and then polysilicon etching is performed to etch part of the polysilicon layer 5 in the PMOS tube region to form a gate 11 of the PMOS tube, and part of the polysilicon N-type implantation region 6 and part of the polysilicon layer 5 in the NMOS tube region are etched to form a gate 10 of the NMOS tube, and part of the polysilicon N-type implantation region 6 and part of the polysilicon layer 5 in the vertical transfer transistor region located on the silicon substrate 1 are etched, and the gate 11 of the PMOS tube is formed. Part of the polysilicon layer 5 in the deep trench 3 eventually forms a polysilicon step structure 9 in the vertical transfer transistor area 103. The polysilicon step structure 9 includes a groove portion 901 located in the deep trench 3 and a step portion 902 located above the silicon substrate 1. The over-etching amount needs to be controlled to prevent damage to the gate oxide layer 4 and cause device performance to deteriorate. Therefore, it is necessary to ensure that the bottom of the groove portion 901 is less than 0.2um from the surface of the silicon substrate 1. Finally, the remaining photoresist 7 and photoresist 8 are removed.
[0087] Step S6, performing a second ion implantation on the polysilicon step structure 9 to form a vertical transfer transistor gate; the type of the second ion implantation can be selected from N-type ions or P-type ions, but it is necessary to ensure that the conductivity type of the first ion implantation on the vertical transfer transistor region 103 and the second ion implantation on the polysilicon step structure 9 are consistent. In this embodiment, the first ion implantation on the vertical transfer transistor region 103 is an N-type ion implantation, so the second ion implantation should also be an N-type ion implantation;
[0088] In one embodiment of the present invention, a method for performing a second ion implantation on the polysilicon step structure 9 comprises: first, Fig. 9 As shown, a photoresist (or hard mask) is formed on the polysilicon step structure 9, and the photoresist is developed to expose the area 13 of the polysilicon step structure 9 where the second ion implantation is required, and the remaining photoresist is divided into two parts, which extend from both sides of the deep trench 3 to cover the polysilicon step structure 9, wherein the first part of the photoresist 12-1 covers the gate 10 of the NMOS tube and the step portion 902 of the polysilicon step structure 9, and the edge of the first part of the photoresist 12-1 is aligned with the edge of the deep trench 3, so as to prevent the polysilicon step structure 9 from being implanted. To realize self-aligned ion implantation, the second portion of the photoresist 12-2 covers the gate 11 of the PMOS tube and the silicon substrate 1 on one side of the groove portion 901 of the polysilicon step structure 9, and the second portion of the photoresist 12-2 extends to the bottom of the groove portion 901 to cover the inner side wall of the deep trench 3 to prevent the surface of the silicon substrate 1 from being implanted with additional N-type ions. The implantation region 13 is implanted with N-type ions, and the N-type ion implantation depth is generally between 0 and 0.5 um. The remaining photoresists 12-1 and 12-2 are subsequently removed. Then, as Fig.10 As shown, a first sidewall structure 14 is formed on the polysilicon step structure 9, and a first sidewall structure 14 is also formed on both sides of the gate 10 of the NMOS tube and on both sides of the gate 11 of the PMOS tube, wherein the first sidewall structure 14 is located on the outside of the step portion 902 of the polysilicon step structure 9 and on the inside of the groove portion 901.
[0089] In another embodiment of the present invention, Fig.11As shown, the method for performing a second ion implantation on the polysilicon step structure 9 comprises: first, forming a first sidewall structure 14 on the polysilicon step structure 9, and at the same time, forming a first sidewall structure 14 on both sides of the gate 10 of the NMOS tube and on both sides of the gate 11 of the PMOS tube, wherein the first sidewall structure 14 is located on the outside of the step portion 902 of the polysilicon step structure 9 and the inside of the groove portion 901; then, forming a photoresist (or hard mask) on the polysilicon step structure 9, developing the photoresist to expose the area 13 of the polysilicon step structure 9 where the second ion implantation is required, and the remaining photoresist is divided into two parts, extending from both sides of the deep trench 3 to cover the polysilicon step structure 9. A crystalline silicon step structure 9, wherein a first portion of photoresist 12-1 covers the gate 10 of the NMOS tube and the step portion 902 of the polysilicon step structure 9, the edge of the first portion of photoresist 12-1 is aligned with the edge of the deep trench 3 to achieve self-aligned ion implantation, a second portion of photoresist 12-2 covers the gate 11 of the PMOS tube and the silicon substrate 1 on one side of the groove portion 901 of the polysilicon step structure 9, and the second portion of photoresist 12-2 extends to the first sidewall structure 14 inside the groove portion 901, and N-type ion implantation is performed on the implantation region 13, the N-type ion implantation depth is generally between 0-0.5um, and the remaining photoresists 12-1 and 12-2 are subsequently removed. In this embodiment, a sidewall structure is first formed at the polysilicon step structure 9, and then a second ion implantation is performed, which is beneficial to reducing the risk of additional N-type ions being implanted on the surface of the silicon substrate.
[0090] In this embodiment, when the polysilicon step structure 9 is subjected to secondary ion implantation, the impurity ions implanted by the secondary ion implantation can be diffused to the deep layer of the groove 9 in combination with the lightly doped drain implantation operation and the lightly doped drain implantation heat treatment, so that the groove 9 is doped as a whole into a heavily doped polysilicon region. There is no strict requirement for the sequence of the lightly doped drain implantation operation and the lightly doped drain implantation heat treatment, and the lightly doped drain implantation can be performed after the second ion implantation, and then the lightly doped drain implantation heat treatment can be performed, or the lightly doped drain implantation can be performed first, and then the second ion implantation can be performed, and then the lightly doped drain implantation heat treatment can be performed.
[0091] Through the preparation process of the above steps S1 to S6, and after the steps of source and drain implantation, contact hole deposition, metal connection, etc., the following is obtained: Fig.12 The non-stacked CMOS image sensor shown in the figure forms a vertical transfer transistor 15 , an NMOS transistor 16 and a PMOS transistor 17 on a silicon substrate 1 .
[0092] In the process of preparing a non-stacked CMOS image sensor with a vertical transfer transistor, the present invention realizes the production of a vertical transfer transistor gate, an NMOS transistor gate and a PMOS transistor gate simultaneously through one deposition, which is beneficial to reducing the manufacturing process cost. In addition, the polysilicon step structure of the vertical transfer transistor is obtained by controlling the overetching amount of polysilicon etching in a conventional planar gate preparation process, and secondary ion implantation is performed at the polysilicon step structure, so that a relatively uniform heavily doped polysilicon gate of the vertical transfer transistor can be obtained without adding an additional heat treatment process. Moreover, the process can be used to prepare vertical transfer transistors with different etching depths and has a wide range of applications.
[0093] It should be noted that, in the embodiments of the present invention, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.
[0094] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0095] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.
Claims
1. A method for forming a vertical transfer transistor for an image sensor, characterized in that: At least: providing a silicon substrate; Etching the silicon substrate to form a groove; Depositing polysilicon to fill the trench to form a polysilicon layer; Performing a first ion implantation on the polysilicon layer; Etching a portion of the polysilicon on the silicon substrate and a portion of the polysilicon in the trench to form a polysilicon step; A second ion implantation is performed on the polysilicon step to form a vertical transfer transistor gate.
2. The method for forming a vertical transfer transistor for an image sensor according to claim 1, wherein: The polysilicon is non-doped polysilicon.
3. The method for forming a vertical transfer transistor for an image sensor according to claim 1, wherein: The polysilicon step comprises a recessed portion located in the trench and a polysilicon step portion located above the silicon substrate; the distance between the bottom of the recessed portion and the surface of the silicon substrate is less than 0.2 um.
4. The method for forming a vertical transfer transistor for an image sensor according to claim 3, wherein: The method of performing a second ion implantation on the polysilicon step comprises: forming a first side wall structure, wherein the first side wall structure is located outside the step portion and inside the groove portion; A photoresist is formed on the silicon substrate, and the photoresist is photolithographically developed to expose a portion of the polysilicon step that needs to be ion implanted, and a second ion implantation is performed.
5. The method for forming a vertical transfer transistor for an image sensor according to claim 3, wherein: The method of performing a second ion implantation on the polysilicon step comprises: Forming a photoresist on the silicon substrate, performing photolithography development on the photoresist to expose a portion of the polysilicon step that needs to be ion implanted, and performing a second ion implantation; A first sidewall structure is formed, wherein the first sidewall structure is located outside the polysilicon step portion and inside the groove portion.
6. The method for forming a vertical transfer transistor for an image sensor according to claim 4 or 5, characterized in that: The conductivity type of the first ion implantation and the second ion implantation is consistent, the first ion implantation and the second ion implantation are of the first conductivity type, or the first ion implantation and the second ion implantation are of the second conductivity type.
7. The method for forming a vertical transfer transistor for an image sensor according to claim 6, wherein: After the second ion implantation, a lightly doped drain implantation is performed, and then a lightly doped drain implantation heat treatment is performed; Alternatively, a lightly doped drain implantation is performed first, followed by a second ion implantation, and then a lightly doped drain implantation heat treatment is performed.
8. The method for forming a vertical transfer transistor for an image sensor according to claim 1, wherein: The depth of the groove is 0.05um to 1um.
9. The method for forming a vertical transfer transistor for an image sensor according to claim 1, wherein: Before depositing the polysilicon into the trench, a gate oxide layer is deposited on the surface of the trench, and the polysilicon layer is formed on the gate oxide layer.
10. The method for forming a vertical transfer transistor for an image sensor according to claim 1, wherein: The polysilicon layer is 0.05um to 0.2um higher than the surface of the silicon substrate.
11. The method for forming a vertical transfer transistor for an image sensor according to claim 1, wherein: The silicon substrate is pre-processed; the pre-processing at least includes: forming a photosensitive unit.
12. The method for forming a vertical transfer transistor for an image sensor according to claim 1, wherein: The etching of the silicon substrate to form a groove comprises: Etching the silicon substrate to form a shallow trench; Depositing a dielectric layer to fill the shallow trench to form a shallow trench isolation structure; The shallow trench isolation structure and the silicon substrate are etched to form the trench.
13. A vertical transfer transistor, characterized in that: The method is prepared by the method according to any one of claims 1 to 12.
14. A method for forming a non-stacked CMOS image sensor, characterized in that: At least: Providing a silicon substrate, dividing a first conductive type MOS transistor region, a second conductive type MOS transistor region and a vertical transfer transistor region on the silicon substrate; Etching the silicon substrate to form a groove; Depositing polysilicon on the silicon substrate to fill the trench and form a polysilicon layer; Performing a first ion implantation on the polysilicon layer of the vertical transfer transistor region and the first conductive type MOS transistor region or the second conductive type MOS transistor region; Etching a portion of polysilicon on the silicon substrate and a portion of polysilicon in the trench to form a polysilicon step, a gate of a first conductive type MOS transistor, and a gate of a second conductive type MOS transistor; A second ion implantation is performed on the polysilicon step to form a vertical transfer transistor gate.
15. The method for forming a non-stacked CMOS image sensor according to claim 13, wherein: The polysilicon is non-doped polysilicon.
16. The method for forming a non-stacked CMOS image sensor according to claim 15, wherein: The polysilicon step comprises a recessed portion located in the trench and a polysilicon step portion located above the silicon substrate; the distance between the bottom of the recessed portion and the surface of the silicon substrate is less than 0.2 um.
17. The method for forming a non-stacked CMOS image sensor according to claim 16, wherein: The method of performing a second ion implantation on the polysilicon step comprises: forming a first side wall structure, wherein the first side wall structure is located outside the step portion and inside the groove portion; A photoresist is formed on the polysilicon step, and the photoresist is photolithographically developed to expose a portion of the polysilicon step that needs to be ion implanted, and a second ion implantation is performed.
18. The method for forming a non-stacked CMOS image sensor according to claim 16, wherein: The method of performing a second ion implantation on the polysilicon step comprises: forming a photoresist on the polysilicon step, performing photolithography development on the photoresist to expose a portion of the polysilicon step where ion implantation is required, and performing a second ion implantation; A first sidewall structure is formed, wherein the first sidewall structure is located outside the polysilicon step portion and inside the groove portion.
19. The method for forming a non-stacked CMOS image sensor according to claim 17 or 18, characterized in that: The first ion implantation performed on the vertical transfer transistor region and the second ion implantation performed on the polysilicon step have the same conductivity type, and the conductivity type of the second ion implantation is the first conductivity type or the second conductivity type.
20. The method for forming a non-stacked CMOS image sensor according to claim 19, wherein: After the second ion implantation, a lightly doped drain implantation is performed, and then a lightly doped drain implantation heat treatment is performed; Alternatively, a lightly doped drain implantation is performed first, followed by a second ion implantation, and then a lightly doped drain implantation heat treatment is performed.
21. The method for forming a non-stacked CMOS image sensor according to claim 14, wherein: The depth of the groove is 0.05um to 1um.
22. The method for forming a non-stacked CMOS image sensor according to claim 14, wherein: Before depositing the polysilicon into the trench, a gate oxide layer is deposited on the surface of the trench, and the polysilicon layer is formed on the gate oxide layer.
23. The method for forming a non-stacked CMOS image sensor according to claim 14, wherein: The polysilicon layer is 0.05um to 0.2um higher than the surface of the silicon substrate.
24. The method for forming a non-stacked CMOS image sensor according to claim 14, wherein: The silicon substrate is pre-processed; the pre-processing at least includes: forming a photosensitive unit.
25. The method for forming a non-stacked CMOS image sensor according to claim 14, wherein: The etching of the silicon substrate to form a groove comprises: Etching the silicon substrate to form a shallow trench; Depositing a dielectric layer to fill the shallow trench to form a shallow trench isolation structure; The shallow trench isolation structure and the silicon substrate are etched to form the trench.
26. A non-stacked CMOS image sensor, characterized in that: Prepared by the method according to any one of claims 14 to 25.