Flip light emitting diode chip and preparation method thereof

Abstract

The invention provides a flip light-emitting diode chip and a preparation method thereof, and the method comprises the steps: providing a substrate for growth, and sequentially depositing an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer on the substrate; preparing an N-type conductive through hole and an isolation channel; preparing a current expansion layer; preparing a cutting channel; preparing a first insulating layer and a first insulating layer through hole; preparing a P-type conductive metal layer; preparing a second insulating layer and a second insulating layer through hole; preparing an N-type conductive metal layer; preparing a third insulating layer and a third insulating layer through hole; and preparing an N-type bonding pad and a P-type bonding pad.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a flip-chip light emitting diode chip and a preparation method thereof. Background Art

[0002] In recent years, the light-emitting diode chip technology has developed rapidly under the competition of major manufacturers and has been widely used in various fields such as general lighting, special lighting, direct display screens, backlight display screens, and car lights.

[0003] In the prior art, when the existing flip-chip LED chip is used under ultra-large current, the temperature inside the chip is high and the temperature around it is low. This temperature unevenness makes it impossible to use the flip-chip LED chip as a car lamp. Summary of the invention

[0004] Based on this, the purpose of the present invention is to provide a flip-chip light emitting diode chip and a preparation method thereof, which can effectively solve the deficiencies in the above-mentioned prior art.

[0005] A method for preparing a flip-chip light-emitting diode chip, the method comprising: S1, providing a substrate required for growth, and sequentially depositing an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer on the substrate; S2, coating the surface of the P-type semiconductor layer with photoresist, then removing part of the photoresist by exposure and development process, forming a photoresist isolation road and a photoresist mask of the N-type conductive through hole, exposing part of the P-type semiconductor layer, then removing the exposed part of the P-type semiconductor layer and the active light-emitting layer under the part of the P-type semiconductor layer by inductively coupled plasma etching process, forming an N-type conductive through hole and the isolation road, and then removing the photoresist; In the photoresist coating process, the photoresist is a negative photoresist and has a viscosity greater than 200cp; in the exposure process, the exposure amount is 50mj / cm2-100mj / cm2; in the development process, the substrate surface needs to be heated before development, and the heating temperature is 80°C-90°C; in the inductively coupled plasma etching process, the ratio of the upper substrate power to the lower substrate power is 1:1-3:1, and this ratio gradually decreases as the process proceeds; The bottom width L of the isolation path is less than 1.5um, the angle α of the side wall is 30°-60°, the isolation path divides the entire chip into a number of small light-emitting areas that emit light independently, the area of ​​the small light-emitting area decreases linearly from the center to the periphery, the sum of the areas of the small light-emitting areas in the central area is greater than the sum of the areas of the small light-emitting areas in the peripheral area, and the area of ​​the smallest independent small light-emitting area in the periphery is greater than 10000um²; S3, preparing a current spreading layer on the P-type semiconductor layer, the N-type conductive via and the isolation path; S4, preparing cutting paths on the P-type semiconductor layer, the N-type conductive via, the current spreading layer and the isolation path; S5, preparing a first insulating layer and a first insulating layer through hole on the P-type semiconductor layer, the N-type conductive through hole, the current spreading layer, the isolation path and the cutting path; S6, preparing a P-type conductive metal layer on the first insulating layer and the through hole of the first insulating layer; Wherein, the P-type conductive metal layer is connected to the current spreading layer of each independent small light-emitting area; S7, preparing a second insulating layer and a second insulating layer through hole on the P-type conductive metal layer and the first insulating layer not covered by the P-type conductive metal layer; The second insulating layer through holes include N-type second insulating layer through holes and P-type second insulating layer through holes, and an N-type second insulating layer through hole is disposed above each independent small light-emitting area, and the N-type second insulating layer through holes above the N-type conductive through holes of each independent small light-emitting area have the same area; S8, preparing an N-type conductive metal layer on the second insulating layer and the through hole of the second insulating layer; Wherein, the N-type conductive metal layer is connected to the N-type conductive through hole of each independent small light-emitting area through the N-type second insulating layer through hole, an N-type conductive metal layer through hole is arranged on the N-type conductive metal layer, the N-type conductive metal layer through hole and the P-type second insulating layer through hole are concentric circles, and the N-type conductive metal layer through hole has a larger area than the P-type second insulating layer through hole; S9, preparing a third insulating layer and a third insulating layer through hole on the N-type conductive metal layer and the N-type conductive metal layer through hole; The third insulating layer through hole includes an N-type third insulating layer through hole and a P-type third insulating layer through hole, the P-type third insulating layer through hole and the P-type second insulating layer through hole are concentric circles, and the P-type third insulating layer through hole has a smaller area than the P-type second insulating layer through hole; S10, preparing an N-type pad and a P-type pad on the third insulating layer and the through hole of the third insulating layer; The N-type pad is electrically connected to the N-type conductive metal layer through the N-type third insulating layer through hole, and the P-type pad layer is electrically connected to the P-type conductive metal layer through the P-type third insulating layer through hole.

[0006] Furthermore, the specific process for preparing the current spreading layer is: Indium tin oxide is deposited on the surface of the P-type semiconductor layer, the N-type conductive through hole and the isolation path by using a magnetron sputtering process, and then a photoresist is coated on the surface of the indium tin oxide. Then, part of the photoresist is removed by exposure and development to expose part of the indium tin oxide. Then, the exposed indium tin oxide is removed by an indium tin oxide etching solution, and then the photoresist is removed to form the current spreading layer.

[0007] Furthermore, the specific process for preparing the cutting path is: Photoresist is coated on the P-type semiconductor layer, the N-type conductive via, the current spreading layer and the isolation path, and then a portion of the photoresist is removed by exposure and development to expose the N-type conductive via located around it, and then the exposed N-type conductive via is removed by an ICP etching process to form the cutting path, and then the photoresist is removed.

[0008] Furthermore, the specific process of preparing the first insulating layer and the through hole of the first insulating layer is: A layer of SiO is deposited on the surface of the P-type semiconductor layer, the N-type conductive via, the current spreading layer, the isolation path and the cutting path by using a PECVD process. 2 A thin film is used as the first insulating layer, the thickness of the first insulating layer is greater than 5000Å, and then a photoresist is coated on the surface of the first insulating layer. Then, exposure and development are used to remove part of the photoresist on the surface of the first insulating layer to expose this part of the first insulating layer. Then, a BOE solution is used to remove the exposed first insulating layer to form a through hole in the first insulating layer, and then the photoresist is removed.

[0009] Furthermore, the specific process for preparing the P-type conductive metal layer is: A negative photoresist is coated on the surface of the first insulating layer and in the through holes of the first insulating layer, and then exposed and developed to remove part of the photoresist. Then, an electron beam evaporation process is used to sequentially evaporate Ni metal, Ag metal, Ti metal, Ni metal, Ti metal, Ni metal, Ti metal and Ni metal. Then, a Lift-Off process is used to remove the metal layer above the photoresist, and then the photoresist is removed to form the P-type conductive metal layer.

[0010] Furthermore, the specific process for preparing the second insulating layer and the through hole of the second insulating layer is: Al is first deposited on the surface of the P-type conductive metal layer and the first insulating layer not covered by the P-type conductive metal layer by using an ALD process. 2 O 3 Thin film, then on Al 2 O 3 SiO2 was deposited on the film using PECVD process. 2A film is used as the second insulating layer, and then a photoresist is coated on the surface of the second insulating layer. Then, the photoresist on the surface of a portion of the second insulating layer is removed by exposure and development to expose the portion of the second insulating layer. Then, the exposed second insulating layer is removed by an ICP etching process to form a through hole in the second insulating layer, and then the photoresist is removed.

[0011] Furthermore, the specific process for preparing the N-type conductive metal layer is: A negative photoresist is coated on the surface of the second insulating layer and in the through hole of the second insulating layer, and then part of the photoresist is removed by exposure and development. Then, Cr metal, Al metal, Ti metal, Ni metal, Ti metal, Pt metal and Ti metal are sequentially evaporated using an electron beam evaporation process, and then the metal layer located above the photoresist is removed using a Lift-Off process, and then the photoresist is removed to form the N-type conductive metal layer.

[0012] Furthermore, the specific process for preparing the third insulating layer and the through hole of the third insulating layer is: SiO is deposited in the N-type conductive metal layer and in the through hole of the N-type conductive metal layer by using a PECVD process. 2 A thin film is used as the third insulating layer, and then a photoresist is coated on the surface of the third insulating layer. Then, a part of the photoresist is removed by exposure and development to expose the third insulating layer under the part of the photoresist. Then, an inductively coupled plasma etching process is used to remove the exposed third insulating layer to form a through hole in the third insulating layer, and then the photoresist is removed.

[0013] Furthermore, the specific process for preparing the N-type pad and the P-type pad is as follows: Negative photoresist is coated on the third insulating layer and in the through hole of the third insulating layer, and then exposed and developed to remove part of the photoresist. Then, Al metal, Ti metal, Pt metal, Ti metal, Ni metal and Au metal are sequentially evaporated using an electron beam evaporation process. Then, the metal layer on the photoresist is removed using a Lift-Off process, and then the photoresist is removed to form the N-type pad and the P-type pad.

[0014] The present invention also provides a flip-chip light emitting diode chip, which is prepared by the method for preparing the flip-chip light emitting diode chip as described above.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: after the isolation path is set in the present invention, it is equivalent to removing part of the light-emitting layer, resulting in a loss of the light-emitting area, thereby losing the brightness of the chip. However, by setting the isolation path and the side wall angle of the isolation path being 30°-60°, the total reflection of the light inside the chip on the surface of the P-type semiconductor layer can be reduced, thereby compensating for the brightness loss caused by the removal of part of the light-emitting layer when preparing the isolation path. Therefore, there are two key parameters here. The first is that the bottom width L of the isolation path must be ensured to be less than 1.5um. If it is greater than 1.5um, the brightness improvement due to the reduction of total reflection by the side wall is not enough to compensate for the brightness reduction loss of the light-emitting area. The second is that the side wall angle α of the isolation path must be ensured to be 30°-60°, because only when the side wall angle α of the isolation path is 30°-60° can the total reflection of the light inside the flip-chip light-emitting diode chip on the surface of the P-type semiconductor layer be reduced.

[0016] Among them, in the photoresist coating process, the photoresist is a negative photoresist with a viscosity greater than 200cp; in the exposure process, the exposure amount is 50mj / cm2-100mj / cm2; in the development process, the substrate surface needs to be heated before development, and the heating temperature is 80℃-90℃; in the inductively coupled plasma etching process, the ratio of the upper substrate power to the lower substrate power is 1:1-3:1, and this ratio gradually decreases as the process proceeds. The above four processes together ensure that the angle α of the side wall of the isolation channel is 30°-60° and the bottom width L of the isolation channel is less than 1.5um.

[0017] Therefore, the light-emitting area of ​​the entire flip-chip LED chip is divided into a number of small light-emitting areas of unequal areas by setting an isolation path. The area of ​​the small light-emitting areas after division decreases linearly from the center of the chip to the periphery, and the sum of the areas of the small light-emitting areas in the center area of ​​the flip-chip LED chip after division is greater than the sum of the areas of the small light-emitting areas in the peripheral area of ​​the flip-chip LED chip. Then, through subsequent processes, these several light-emitting areas are connected in parallel, so that the center and periphery temperatures of the flip-chip LED chip are uniform when working under ultra-large current. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a flow chart of a method for preparing a flip-chip light-emitting diode chip in Example 1 of the present invention; Figure 2 is a cross-sectional schematic diagram of a semi-finished product formed through step S2 in Example 1 of the present invention; Figure 3 for Figure 2 A magnified schematic diagram of the local A in the middle; Figure 4 is a top view schematic diagram of a flip-chip light-emitting diode chip in Embodiment 1 of the present invention; Figure 5 is a cross-sectional schematic diagram of a flip-chip light-emitting diode chip in Embodiment 1 of the present invention; Description of main component symbols:

[0019] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0020] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0021] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0023] Example 1 See also Figures 1 to 5 The method for preparing a flip-chip light-emitting diode chip in an embodiment of the present invention comprises: S1, providing a substrate 10 required for growth, and sequentially depositing an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 on the substrate 10; Wherein, the substrate 10 may be a GaN substrate or an Al 2 O 3 substrate or Si substrate.

[0024] S2, coating the surface of the P-type semiconductor layer 113 with photoresist, then removing part of the photoresist by exposure and development process, forming a photoresist isolation road and a photoresist mask of the N-type conductive through hole, exposing part of the P-type semiconductor layer, then removing the exposed part of the P-type semiconductor layer and the active light-emitting layer under the part of the P-type semiconductor layer by inductively coupled plasma etching process, forming an N-type conductive through hole 114 and an isolation road 115, and then removing the photoresist; In the photoresist coating process, the photoresist is a negative photoresist and has a viscosity greater than 200cp; in the exposure process, the exposure amount is 50mj / cm2-100mj / cm2; in the development process, the substrate surface needs to be heated before development, and the heating temperature is 80°C-90°C; in the inductively coupled plasma etching process, the ratio of the upper substrate power to the lower substrate power is 1:1-3:1, and this ratio gradually decreases as the process proceeds; Specifically in this embodiment, in the photoresist coating process, the photoresist is a negative photoresist with a viscosity of 260cp; in the exposure process, the exposure amount is 100mj / cm 2 ; The temperature of the heating treatment in the development process is 90°C; in the inductively coupled plasma etching process, the ratio of the upper substrate power to the lower substrate power is 3:1 at the beginning of the etching process, and the ratio of the upper substrate power to the lower substrate power decreases by 0.15 for every tenth of the total etching process time. At the end of the etching process, the ratio of the upper substrate power to the lower substrate power is 1.5:1.

[0025] The bottom width L of the isolation channel 115 is less than 1.5um, and the angle α of the side wall is 30°-60°. The isolation channel divides the entire chip into a number of small light-emitting areas that emit light independently. The area of ​​the small light-emitting area decreases linearly from the center to the periphery. The sum of the areas of the small light-emitting areas in the central area is greater than the sum of the areas of the small light-emitting areas in the peripheral area, and the area of ​​the smallest independent small light-emitting area in the periphery is greater than 10000um². Specifically in this embodiment, the bottom width L of the isolation channel 115 is 1 um, and the angle α of the side wall is 60°.

[0026] S3, preparing a current spreading layer 12 on the P-type semiconductor layer 113, the N-type conductive via 114 and the isolation channel 115; Furthermore, the specific process for preparing the current spreading layer 12 is as follows: Indium tin oxide is deposited on the surface of the P-type semiconductor layer 113, the N-type conductive via 114 and the isolation path 115 by using a magnetron sputtering process, and then a photoresist is coated on the surface of the indium tin oxide. Then, part of the photoresist is removed by exposure and development to expose part of the indium tin oxide. Then, the exposed indium tin oxide is removed by an indium tin oxide etching solution, and then the photoresist is removed to form the current spreading layer 12.

[0027] S4, preparing a cutting path 116 on the P-type semiconductor layer 113, the N-type conductive via 114, the current spreading layer 12 and the isolation path 115; Furthermore, the specific process of preparing the cutting road 116 is as follows: Photoresist is coated on the P-type semiconductor layer 113, the N-type conductive via 114, the current spreading layer 12 and the isolation path 115, and then a portion of the photoresist is removed by exposure and development to expose the N-type conductive vias located around, and then the exposed N-type conductive vias are removed by ICP etching process to form the cutting path 116, and then the photoresist is removed.

[0028] S5, preparing a first insulating layer 13 and a first insulating layer through hole 131 on the P-type semiconductor layer 113, the N-type conductive through hole 114, the current spreading layer 12, the isolation street 115 and the cutting street 116; Furthermore, the specific process of preparing the first insulating layer 13 and the first insulating layer through hole 131 is: A layer of SiO is deposited on the surface of the P-type semiconductor layer 113, the N-type conductive via 114, the current spreading layer 12, the isolation path 115 and the cutting path 116 by using a PECVD process. 2 The film is used as the first insulating layer 13, the thickness of the first insulating layer 13 is greater than 5000Å, and then a photoresist is coated on the surface of the first insulating layer 13, and then the photoresist on the surface of a part of the first insulating layer is removed by exposure and development to expose this part of the first insulating layer, and then a BOE solution is used to remove the exposed first insulating layer to form the first insulating layer through hole 131, and then the photoresist is removed.

[0029] S6, preparing a P-type conductive metal layer 14 on the first insulating layer 13 and the first insulating layer through hole 131; Wherein, the P-type conductive metal layer 14 is connected to the current spreading layer of each independent small light-emitting area; Furthermore, the specific process for preparing the P-type conductive metal layer 14 is as follows: A negative photoresist is coated on the surface of the first insulating layer 13 and in the through hole 131 of the first insulating layer, and then exposed and developed to remove part of the photoresist. Then, an electron beam evaporation process is used to sequentially evaporate Ni metal, Ag metal, Ti metal, Ni metal, Ti metal, Ni metal, Ti metal and Ni metal. Then, a Lift-Off process is used to remove the metal layer above the photoresist, and then the photoresist is removed to form the P-type conductive metal layer 14.

[0030] S7, preparing a second insulating layer 15 and a second insulating layer through hole on the P-type conductive metal layer 14 and the first insulating layer 13 not covered by the P-type conductive metal layer 14; The second insulating layer through hole includes an N-type second insulating layer through hole 151 and a P-type second insulating layer through hole 152, and an N-type second insulating layer through hole is disposed on each independent small light-emitting area, and the N-type second insulating layer through holes on the N-type conductive through holes of each independent small light-emitting area have the same area; Furthermore, the specific process of preparing the second insulating layer 15 and the second insulating layer through hole is: Al is first deposited on the surface of the P-type conductive metal layer 14 and the first insulating layer 13 not covered by the P-type conductive metal layer 14 by using an ALD process. 2 O 3 Thin film, then on Al 2 O 3 SiO2 was deposited on the film using PECVD process. 2 A thin film is used as the second insulating layer 15, and then a photoresist is coated on the surface of the second insulating layer 15, and then the photoresist on the surface of a portion of the second insulating layer is removed by exposure and development to expose this portion of the second insulating layer, and then the exposed second insulating layer is removed by an ICP etching process to form a through hole in the second insulating layer, and then the photoresist is removed.

[0031] S8, preparing an N-type conductive metal layer 16 on the second insulating layer 15 and the through hole of the second insulating layer; The N-type conductive metal layer 16 is connected to the N-type conductive through hole of each independent small light-emitting area through the N-type second insulating layer through hole 151, and an N-type conductive metal layer through hole 161 is arranged on the N-type conductive metal layer 16. The N-type conductive metal layer through hole 161 and the P-type second insulating layer through hole 152 are concentric circles, and the area of ​​the N-type conductive metal layer through hole 161 is larger than that of the P-type second insulating layer through hole 152; Furthermore, the specific process for preparing the N-type conductive metal layer 16 is as follows: A negative photoresist is coated on the surface of the second insulating layer 15 and in the through holes of the second insulating layer, and then exposed and developed to remove part of the photoresist. Then, an electron beam evaporation process is used to sequentially evaporate Cr metal, Al metal, Ti metal, Ni metal, Ti metal, Pt metal and Ti metal. Then, a Lift-Off process is used to remove the metal layer above the photoresist, and then the photoresist is removed to form the N-type conductive metal layer 16.

[0032] S9, preparing a third insulating layer 17 and a third insulating layer through hole on the N-type conductive metal layer 16 and the N-type conductive metal layer through hole 161; The third insulating layer through hole includes an N-type third insulating layer through hole 171 and a P-type third insulating layer through hole 172, the P-type third insulating layer through hole 172 and the P-type second insulating layer through hole 152 are concentric circles, and the area of ​​the P-type third insulating layer through hole 172 is smaller than that of the P-type second insulating layer through hole 152; S10, preparing an N-type pad 181 and a P-type pad 182 on the third insulating layer 17 and the third insulating layer through hole; The N-type pad 181 is electrically connected to the N-type conductive metal layer 16 through the N-type third insulating layer through hole 171 , and the P-type pad 182 is electrically connected to the P-type conductive metal layer 14 through the P-type third insulating layer through hole 172 .

[0033] Furthermore, the specific process of preparing the N-type pad 181 and the P-type pad 182 is as follows: Negative photoresist is coated on the third insulating layer 17 and the through hole of the third insulating layer, and then exposed and developed to remove part of the photoresist. Then, Al metal, Ti metal, Pt metal, Ti metal, Ni metal and Au metal are sequentially evaporated using an electron beam evaporation process, and then the metal layer on the photoresist is removed using a Lift-Off process. Then, the photoresist is removed to form the N-type pad 181 and the P-type pad 182.

[0034] It is understandable that, after the isolation path 115 is set in the present invention, it is equivalent to removing part of the light-emitting layer, resulting in loss of light-emitting area, thereby losing chip brightness. However, by setting the isolation path 115 and the side wall angle of the isolation path 115 being 30°-60°, the light inside the chip can be reduced from being totally reflected on the surface of the P-type semiconductor layer 113, thereby compensating for the brightness loss caused by the removal of part of the light-emitting layer during the preparation of the isolation path 115. Therefore, there are two key parameters here. The first is that the bottom width L of the isolation path must be ensured to be less than 1.5um. If it is greater than 1.5um, the brightness improvement due to the reduction of total reflection by the side wall is not enough to compensate for the brightness reduction loss of the light-emitting area. The second is that the side wall angle α of the isolation path must be ensured to be 30°-60°, because only when the side wall angle α of the isolation path is 30°-60° can the light inside the flip-chip light-emitting diode chip be reduced from being totally reflected on the surface of the P-type semiconductor layer 113. Among them, in the photoresist coating process, the photoresist is a negative photoresist and the viscosity is greater than 200cp; in the exposure process, the exposure amount is 50mj / cm2-100mj / cm2; in the development process, the substrate surface needs to be heated before development, and the heating temperature is 80℃-90℃; in the inductively coupled plasma etching process, the ratio of the upper substrate power to the lower substrate power is 1:1-3:1, and this ratio gradually decreases as the process proceeds; the above four processes together ensure that the angle α of the side wall of the isolation channel is 30°-60° and the bottom width L of the isolation channel is less than 1.5um; Therefore, by setting the isolation path 115, the light-emitting area of ​​the entire flip-chip LED chip is divided into a number of small light-emitting areas of unequal areas. The area of ​​the small light-emitting areas after division decreases linearly from the center of the chip to the surrounding areas, and the sum of the areas of the small light-emitting areas in the central area of ​​the flip-chip LED chip after division is greater than the sum of the areas of the small light-emitting areas in the peripheral area of ​​the flip-chip LED chip. Then, through subsequent processes, these several light-emitting areas are connected in parallel, so that the center and surrounding temperatures of the flip-chip LED chip are uniform when working under ultra-large current.

[0035] See also Figure 4 - Figure 5 , shown are a top view schematic diagram and a cross-sectional schematic diagram of a flip-chip light-emitting diode chip prepared by the method for preparing a flip-chip light-emitting diode chip in an embodiment of the present invention.

[0036] Example 2 A flip-chip light-emitting diode chip, which is different from the flip-chip light-emitting diode chip prepared in Example 1 in that: In the exposure process, the exposure amount is 50mj / cm 2 , the bottom width L of the isolation channel 115 is 1.5 um.

[0037] Comparative Example 1 A flip-chip light-emitting diode chip, which is different from the flip-chip light-emitting diode chip prepared in Example 1 in that: In the photoresist coating process, the photoresist is a negative photoresist with a viscosity of 275 cp, and a side wall angle α of 65°.

[0038] Comparative Example 2 A flip-chip light-emitting diode chip, which is different from the flip-chip light-emitting diode chip prepared in Example 1 in that: In the photoresist coating process, the photoresist is a negative photoresist with a viscosity of 220cp; in the exposure process, the exposure amount is 50mj / cm 2 ; In the inductively coupled plasma etching process, the ratio of the upper substrate power to the lower substrate power is 2:1 at the beginning of the etching process, and the ratio of the upper substrate power to the lower substrate power decreases by 0.1 for every tenth of the total etching process duration. At the end of the etching process, the ratio of the upper substrate power to the lower substrate power is 1:1. The bottom width L of the isolation channel 115 is 1.5um, and the side wall angle α is 30°.

[0039] Comparative Example 3 A flip-chip light-emitting diode chip, which is different from the flip-chip light-emitting diode chip prepared in Example 1 in that: In the photoresist coating process, the photoresist is a negative photoresist with a viscosity of 220cp; in the exposure process, the exposure amount is 50mj / cm 2 ; In the inductively coupled plasma etching process, the ratio of the upper substrate power to the lower substrate power is 0.8:1, and this ratio will not gradually decrease as the process proceeds; the bottom width L of the isolation channel 115 is 1.5um, and the side wall angle α is 25°.

[0040] Comparative Example 4 A flip-chip light-emitting diode chip, which is different from the flip-chip light-emitting diode chip prepared in Example 1 in that: In the photoresist coating process, the photoresist is a negative photoresist with a viscosity of 180cp; in the exposure process, the exposure amount is 30mj / cm 2 ; In the inductively coupled plasma etching process, the ratio of the upper substrate power to the lower substrate power is 0.8:1, and this ratio will not gradually decrease as the process proceeds; the bottom width L of the isolation channel 115 is 2um, and the side wall angle α is 25°.

[0041] Based on the flip-chip LED chips prepared in the above-mentioned Examples 1 and 2 and the flip-chip LED chips in Comparative Examples 1 to 4, the flip-chip LED chips prepared in Examples 1 and 2 and the flip-chip LED chips in Comparative Examples 1 to 5 were subjected to power-on tests for comparison. A current of 1.5 A was passed through the flip-chip LED chips, and the temperature T of the chips was tested at room temperature of 25° C. The higher the temperature, the more uniform the temperature inside the chip. The corresponding test results are shown in the following table:

[0042]

[0043] It should be noted that in order to ensure the reliability of the verification results, when the flip-chip LED chips prepared in the above-mentioned Examples 1 and 2 of the present invention and the flip-chip LED chips in Comparative Examples 1 to 5 are powered on, other processes and parameters except for the above-mentioned parameters should remain consistent.

[0044] It can be concluded from the above table that, compared with the flip-chip LED chips provided in Comparative Examples 2 to 4, the flip-chip LED chips prepared in Example 1, Example 2 and Comparative Example 1 of the present invention have higher test temperatures and more uniform internal temperatures.

[0045] In summary, the flip-chip light-emitting diode chip and its preparation method in the above-mentioned embodiment of the present invention, because the present invention sets the isolation road, it is equivalent to removing part of the light-emitting layer, resulting in loss of light-emitting area, thereby losing chip brightness, but by setting the isolation road, and the side wall angle of the isolation road is 30°-60°, it can reduce the total reflection of the light inside the chip on the surface of the P-type semiconductor layer, thereby compensating for the brightness loss caused by the removal of part of the light-emitting layer when preparing the isolation road, so there are two key parameters here, the first is that it must ensure that the bottom width L of the isolation road is less than 1.5um, if it is greater than 1.5um, then the brightness improvement due to the reduction of total reflection by the side wall is not enough to compensate for the brightness reduction loss of the light-emitting area, and the second is that it must ensure that the angle α of the side wall of the isolation road is 30°-60°, because only when the angle α of the side wall of the isolation road is 30°-60°, can the total reflection of the light inside the flip-chip light-emitting diode chip on the surface of the P-type semiconductor layer be reduced; Among them, in the photoresist coating process, the photoresist is a negative photoresist and the viscosity is greater than 200cp; in the exposure process, the exposure amount is 50mj / cm2-100mj / cm2; in the development process, the substrate surface needs to be heated before development, and the heating temperature is 80℃-90℃; in the inductively coupled plasma etching process, the ratio of the upper substrate power to the lower substrate power is 1:1-3:1, and this ratio gradually decreases as the process proceeds; the above four processes together ensure that the angle α of the side wall of the isolation channel is 30°-60° and the bottom width L of the isolation channel is less than 1.5um; Therefore, the light-emitting area of ​​the entire flip-chip LED chip is divided into a number of small light-emitting areas of unequal areas by setting an isolation path. The area of ​​the small light-emitting areas after division decreases linearly from the center of the chip to the periphery, and the sum of the areas of the small light-emitting areas in the center area of ​​the flip-chip LED chip after division is greater than the sum of the areas of the small light-emitting areas in the peripheral area of ​​the flip-chip LED chip. Then, through subsequent processes, these several light-emitting areas are connected in parallel, so that the center and periphery temperatures of the flip-chip LED chip are uniform when working under ultra-large current.

[0046] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", "some examples", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0047] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing a flip-chip light-emitting diode chip, characterized in that: The preparation method comprises: S1, providing a substrate required for growth, and sequentially depositing an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer on the substrate; S2, coating the surface of the P-type semiconductor layer with photoresist, then removing part of the photoresist by exposure and development process, forming a photoresist isolation road and a photoresist mask of the N-type conductive through hole, exposing part of the P-type semiconductor layer, then removing the exposed part of the P-type semiconductor layer and the active light-emitting layer under the part of the P-type semiconductor layer by inductively coupled plasma etching process, forming an N-type conductive through hole and the isolation road, and then removing the photoresist; In the photoresist coating process, the photoresist is a negative photoresist and has a viscosity greater than 200cp; in the exposure process, the exposure amount is 50mj / cm2-100mj / cm2; in the development process, the substrate surface needs to be heated before development, and the heating temperature is 80°C-90°C; in the inductively coupled plasma etching process, the ratio of the upper substrate power to the lower substrate power is 1:1-3:1, and this ratio gradually decreases as the process proceeds; The bottom width L of the isolation channel is less than 1.5um, and the angle α of the side wall is 30°-60°. The isolation channel divides the entire chip into a number of small light-emitting areas that emit light independently. The area of ​​the small light-emitting area decreases linearly from the center of the chip to the surroundings, and the area of ​​the smallest independent small light-emitting area at the periphery is greater than 10000um²; S3, preparing a current spreading layer on the P-type semiconductor layer, the N-type conductive via and the isolation path; S4, preparing cutting paths on the P-type semiconductor layer, the N-type conductive via, the current spreading layer and the isolation path; S5, preparing a first insulating layer and a first insulating layer through hole on the P-type semiconductor layer, the N-type conductive through hole, the current spreading layer, the isolation path and the cutting path; S6, preparing a P-type conductive metal layer on the first insulating layer and the through hole of the first insulating layer; Wherein, the P-type conductive metal layer is connected to the current spreading layer of each independent small light-emitting area; S7, preparing a second insulating layer and a second insulating layer through hole on the P-type conductive metal layer and the first insulating layer not covered by the P-type conductive metal layer; The second insulating layer through holes include N-type second insulating layer through holes and P-type second insulating layer through holes, and an N-type second insulating layer through hole is disposed above each independent small light-emitting area, and the N-type second insulating layer through holes above the N-type conductive through holes of each independent small light-emitting area have the same area; S8, preparing an N-type conductive metal layer on the second insulating layer and the through hole of the second insulating layer; Wherein, the N-type conductive metal layer is connected to the N-type conductive through hole of each independent small light-emitting area through the N-type second insulating layer through hole, an N-type conductive metal layer through hole is arranged on the N-type conductive metal layer, the N-type conductive metal layer through hole and the P-type second insulating layer through hole are concentric circles, and the N-type conductive metal layer through hole has a larger area than the P-type second insulating layer through hole; S9, preparing a third insulating layer and a third insulating layer through hole on the N-type conductive metal layer and the N-type conductive metal layer through hole; The third insulating layer through hole includes an N-type third insulating layer through hole and a P-type third insulating layer through hole, the P-type third insulating layer through hole and the P-type second insulating layer through hole are concentric circles, and the P-type third insulating layer through hole has a smaller area than the P-type second insulating layer through hole; S10, preparing an N-type pad and a P-type pad on the third insulating layer and the through hole of the third insulating layer; The N-type pad is electrically connected to the N-type conductive metal layer through the N-type third insulating layer through hole, and the P-type pad is electrically connected to the P-type conductive metal layer through the P-type third insulating layer through hole.

2. The method for preparing a flip-chip light-emitting diode chip according to claim 1, characterized in that: The specific process for preparing the current spreading layer is: Indium tin oxide is deposited on the surface of the P-type semiconductor layer, the N-type conductive through hole and the isolation path by using a magnetron sputtering process, and then a photoresist is coated on the surface of the indium tin oxide. Then, part of the photoresist is removed by exposure and development to expose part of the indium tin oxide. Then, the exposed indium tin oxide is removed by an indium tin oxide etching solution, and then the photoresist is removed to form the current spreading layer.

3. The method for preparing a flip-chip light emitting diode chip according to claim 1, characterized in that: The specific process for preparing the cutting path is: Photoresist is coated on the P-type semiconductor layer, the N-type conductive via, the current spreading layer and the isolation path, and then a portion of the photoresist is removed by exposure and development to expose the N-type conductive via located around it, and then the exposed N-type conductive via is removed by an ICP etching process to form the cutting path, and then the photoresist is removed.

4. The method for preparing a flip-chip light emitting diode chip according to claim 1, characterized in that: The specific process of preparing the first insulating layer and the through hole of the first insulating layer is: A layer of SiO2 film is deposited on the surface of the P-type semiconductor layer, the N-type conductive through hole, the current spreading layer, the isolation path and the cutting path by using the PECVD process as the first insulating layer, and the thickness of the first insulating layer is greater than 5000Å. Then, photoresist is coated on the surface of the first insulating layer, and then the photoresist on the surface of a portion of the first insulating layer is removed by exposure and development to expose this portion of the first insulating layer. Then, a BOE solution is used to remove the exposed first insulating layer to form a through hole in the first insulating layer, and then the photoresist is removed.

5. The method for preparing a flip-chip light emitting diode chip according to claim 1, characterized in that: The specific process for preparing the P-type conductive metal layer is: A negative photoresist is coated on the surface of the first insulating layer and in the through holes of the first insulating layer, and then exposed and developed to remove part of the photoresist. Then, an electron beam evaporation process is used to sequentially evaporate Ni metal, Ag metal, Ti metal, Ni metal, Ti metal, Ni metal, Ti metal and Ni metal. Then, a Lift-Off process is used to remove the metal layer above the photoresist, and then the photoresist is removed to form the P-type conductive metal layer.

6. The method for preparing a flip-chip light emitting diode chip according to claim 1, characterized in that: The specific process of preparing the second insulating layer and the through hole of the second insulating layer is: An Al2O3 film is first deposited on the surface of the P-type conductive metal layer and the first insulating layer not covered by the P-type conductive metal layer using an ALD process, and then a SiO2 film is deposited on the Al2O3 film using a PECVD process as the second insulating layer. Photoresist is then coated on the surface of the second insulating layer, and then the photoresist on the surface of a portion of the second insulating layer is removed by exposure and development to expose the portion of the second insulating layer. The exposed second insulating layer is then removed by an ICP etching process to form a through hole in the second insulating layer, and then the photoresist is removed.

7. The method for preparing a flip-chip light emitting diode chip according to claim 1, characterized in that: The specific process for preparing the N-type conductive metal layer is as follows: A negative photoresist is coated on the surface of the second insulating layer and in the through hole of the second insulating layer, and then part of the photoresist is removed by exposure and development. Then, Cr metal, Al metal, Ti metal, Ni metal, Ti metal, Pt metal and Ti metal are sequentially evaporated using an electron beam evaporation process, and then the metal layer located above the photoresist is removed using a Lift-Off process, and then the photoresist is removed to form the N-type conductive metal layer.

8. The method for preparing a flip-chip light emitting diode chip according to claim 1, characterized in that: The specific process of preparing the third insulating layer and the through hole of the third insulating layer is: A SiO2 film is deposited on the N-type conductive metal layer and in the through hole of the N-type conductive metal layer by using a PECVD process as the third insulating layer, and then a photoresist is coated on the surface of the third insulating layer. Then, a portion of the photoresist is removed by exposure and development to expose the third insulating layer under the portion of the photoresist, and then the exposed third insulating layer is removed by an inductively coupled plasma etching process to form the through hole of the third insulating layer, and then the photoresist is removed.

9. The method for preparing a flip-chip light emitting diode chip according to claim 1, characterized in that: The specific process for preparing the N-type pad and the P-type pad is as follows: Negative photoresist is coated on the third insulating layer and in the through hole of the third insulating layer, and then exposed and developed to remove part of the photoresist. Then, Al metal, Ti metal, Pt metal, Ti metal, Ni metal and Au metal are sequentially evaporated using an electron beam evaporation process. Then, the metal layer on the photoresist is removed using a Lift-Off process, and then the photoresist is removed to form the N-type pad and the P-type pad.

10. A flip-chip light emitting diode chip, characterized in that: The flip-chip light-emitting diode chip is prepared by the method for preparing the flip-chip light-emitting diode chip according to any one of claims 1 to 9.

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