Method of manufacturing semiconductor device

Abstract

The invention provides a method for manufacturing a semiconductor device. The method comprises a step of forming at least one gallium nitride layer or at least one gallium arsenide layer of an undoped gallium nitride layer, an undoped gallium arsenide layer, an N-type gallium nitride layer, an N-type gallium arsenide layer, an active layer, a P-type gallium nitride layer and a P-type gallium arsenide layer on a silicon substrate containing germanium or a substrate on which a silicon layer containing germanium is formed, the process of forming the at least one gallium nitride layer or the at least one gallium arsenide layer includes the steps of: a) sequentially supplying i) a gallium precursor and ii) a nitrogen precursor or an arsenide precursor at 500 DEG C or less to form the gallium nitride layer or the gallium arsenide layer on the silicon substrate or the substrate; and b) exposing the gallium nitride layer or the gallium arsenide layer to a hydrogen-containing plasma wherein steps a) and b) are repeated a plurality of times.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device. Background Art

[0002] Liquid crystal displays (LCDs) and organic light emitting diode (OLED) displays are widely used as display devices. Recently, a technology for manufacturing a high-resolution display device using a micro LED device (micro light emitting diode device) has attracted attention.

[0003] Existing micro LEDs are self-luminous displays equipped with micro LEDs of micrometer (μm) scale at pixel positions of a driving substrate, and have advantages such as high brightness, high power efficiency, long service life, and various form factors. However, the transfer process of placing micro LEDs of micrometer (μm) scale at pixel positions of a driving substrate is performed by a pick-and-place method, which is difficult to ensure productivity and economic feasibility. In particular, other methods are needed to manufacture large-area micro LED displays.

[0004] In addition, a metal organic chemical vapor deposition (MOCVD) method is generally used to form a gallium nitride layer. In such an MOCVD method, the gallium nitride layer is deposited when the temperature of the substrate is adjusted to a high temperature of about 1200 degrees Celsius (°C). That is, while maintaining the substrate at a high temperature of about 1200°C, the gallium nitride layer can be deposited on the substrate.

[0005] However, when the gallium nitride layer is formed while the substrate is heated to a high temperature, the substrate or the layer formed on the substrate may be damaged. This is a factor that causes degradation or defects in the light emission of micro LEDs, and in particular, there is a problem of significantly reducing the quality and reliability of display devices that require stable switching operations. Summary of the invention

[0006] Technical issues

[0007] The present invention is to solve the above-mentioned problems and to provide a manufacturing method that can form a gallium nitride layer and a gallium arsenide layer at a low temperature by an atomic layer deposition (ALD) method.

[0008] Technical Solution

[0009] In order to achieve the above-mentioned purpose, an embodiment of the present invention provides a method for manufacturing a semiconductor device, the method comprising a process of forming at least one gallium nitride layer among an undoped gallium nitride layer, an N-type gallium nitride layer, an active layer and a P-type gallium nitride layer on a silicon substrate containing germanium or a substrate on which a silicon layer containing germanium is formed, the process of forming at least one gallium nitride layer comprising the following steps: a) supplying a gallium precursor and a nitrogen precursor in sequence at a temperature below 500° C. to form a gallium nitride layer on the silicon substrate or the substrate; and b) exposing the gallium nitride layer to a hydrogen-containing plasma, wherein steps a) and b) are repeated multiple times.

[0010] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, the method including a process of forming a gallium nitride layer on a silicon substrate containing germanium or on a substrate on which a silicon layer containing germanium is formed, the process of forming the gallium nitride layer including sequentially supplying a gallium precursor and a nitrogen precursor into a chamber, wherein sequentially supplying the gallium precursor and the nitrogen precursor into the chamber includes the following steps: a) flowing the gallium precursor into the chamber through a gas injector at a temperature below 500° C.; and b) flowing the nitrogen precursor through the gas injector to form gallium nitride on the silicon substrate or the substrate.

[0011] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, the method including a process of forming at least one gallium nitride layer among an undoped gallium nitride layer, an N-type gallium nitride layer, an active layer and a P-type gallium nitride layer on a silicon substrate containing germanium or on a substrate on which a silicon layer containing germanium is formed, the process of forming at least one gallium nitride layer including: supplying a gallium precursor and a nitrogen precursor in sequence at a temperature below 500° C. to form a gallium nitride layer on the silicon substrate or the substrate, wherein plasma is generated when the nitrogen precursor is supplied.

[0012] The method further includes exposing the gallium nitride layer to a plasma containing hydrogen after forming the gallium nitride layer.

[0013] The process of forming the N-type gallium nitride layer further includes supplying a silicon precursor, wherein the process of forming the active layer further includes supplying an indium precursor, wherein the process of forming the P-type gallium nitride layer further includes supplying a magnesium precursor.

[0014] The method further includes generating a plasma containing hydrogen between supplying the gallium precursor and supplying the nitrogen precursor.

[0015] The method further includes exposing the silicon substrate or substrate to a gas containing at least one of fluorine and chlorine to remove oxides and impurities on the silicon substrate or substrate before supplying the gallium precursor.

[0016] Removal of oxides and impurities from the silicon substrate or substrate is performed in the same chamber or system as that used to form the gallium nitride layer.

[0017] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, the method comprising a process of forming at least one of an undoped gallium arsenide layer, an N-type gallium arsenide layer, an active layer and a P-type gallium arsenide layer on a silicon substrate containing germanium or a substrate on which a silicon layer containing germanium is formed, the process of forming at least one gallium arsenide layer comprising the following steps: a) supplying i) a gallium precursor and ii) an arsenide precursor in sequence at a temperature below 500° C. to form a gallium arsenide layer on the silicon substrate or the substrate; and b) exposing the gallium arsenide layer to a hydrogen-containing plasma, wherein steps a) and b) are repeated multiple times.

[0018] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, the method including a process of forming a gallium arsenide layer on a silicon substrate containing germanium or a substrate on which a silicon layer containing germanium is formed, the process of forming the gallium arsenide layer including sequentially supplying a gallium precursor and an arsenide precursor into a chamber, wherein sequentially supplying the gallium precursor and the arsenide precursor into the chamber includes the following steps: a) flowing the gallium precursor into the chamber through a gas injector at 500° C. or below; and b) flowing the arsenide precursor through a gas injector to form a gallium arsenide layer on the silicon substrate or the substrate.

[0019] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, the method including a process of forming at least one gallium arsenide layer of an undoped gallium arsenide layer, an N-type gallium arsenide layer, an active layer, and a P-type gallium arsenide layer on a silicon substrate containing germanium or a substrate on which a silicon layer containing germanium is formed, the process of forming at least one gallium arsenide layer including sequentially supplying a gallium precursor and an arsenide precursor at a temperature below 500° C. to form the gallium arsenide layer on the silicon substrate or the substrate, wherein plasma is generated when the arsenide precursor is supplied.

[0020] The method further includes exposing the gallium arsenide layer to a plasma containing hydrogen after forming the gallium arsenide layer.

[0021] The process of forming the N-type gallium arsenide layer further includes supplying a silicon precursor, wherein the process of forming the active layer further includes supplying an indium precursor, wherein the process of forming the P-type gallium arsenide layer further includes supplying a magnesium precursor.

[0022] The method further includes generating a plasma containing hydrogen between supplying the gallium precursor and supplying the arsenide precursor.

[0023] The method further includes exposing the silicon substrate or substrate to a gas containing at least one of fluorine and chlorine to remove oxides and impurities on the silicon substrate or substrate before supplying the gallium precursor.

[0024] Removal of oxides and impurities on the silicon substrate or substrate is performed in the same chamber or system as that used to form the gallium arsenide layer.

[0025] The method further includes forming an encapsulation layer to prevent moisture or oxygen from penetrating the silicon substrate or the substrate.

[0026] The method also includes forming a pure silicon layer on the silicon substrate or substrate.

[0027] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, the method comprising: loading at least one substrate onto a substrate support located in an atomic layer deposition chamber including a gas injector, the at least one substrate comprising a silicon substrate including germanium or a substrate on which a silicon layer including germanium is formed; maintaining the substrate support at a temperature below 500°C; a) flowing a gallium precursor into the atomic layer deposition chamber through a gas injector; b) flowing a blowing gas for blowing off the gallium precursor into the atomic layer deposition chamber; c) flowing a nitrogen precursor or an arsenide precursor into the atomic layer deposition chamber through a gas injector to form a gallium nitride layer or a gallium arsenide layer on at least one substrate; and d) flowing a hydrogen-containing gas into the atomic layer deposition chamber through a gas injector to generate a hydrogen plasma, wherein steps a) to d) are repeated multiple times.

[0028] Beneficial Effects

[0029] According to the present invention, the following effects can be achieved.

[0030] According to an embodiment of the present invention, the gallium nitride layer and the gallium arsenide layer are formed by a low temperature process, thereby preventing the semiconductor device from being damaged by high temperature heat. In addition, the transfer process of the substrate for forming the gallium nitride layer and the gallium arsenide layer can be omitted, thereby reducing the manufacturing time and manufacturing cost of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a diagram showing a structure of a semiconductor device according to an embodiment of the present invention.

[0032] Figure 2 is a diagram showing a structure of a semiconductor device according to another embodiment of the present invention.

[0033] Figure 3 is a diagram illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

[0034] Figure 4 It shows that according to Figure 3 FIG. 1 is a diagram of a semiconductor device structure of an embodiment of the present invention.

[0035] Figure 5 is a diagram showing a device structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The advantages and features of the present invention and its implementation methods will be explained by the embodiments described below with reference to the accompanying drawings. However, the present invention can be embodied in different forms and should not be understood as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present invention will be thorough and complete, and the scope of the present invention will be fully conveyed to those of ordinary skill in the art. In addition, the present invention is limited only by the scope of the claims.

[0037] The shapes, sizes, proportions, angles and quantities disclosed in the accompanying drawings for describing the embodiments of the present invention are only examples, and therefore the present invention is not limited to the details shown. Throughout the application, similar reference numerals represent similar elements. In the following description, when it is determined that the detailed description of the relevant known technology will unnecessarily obscure the focus of the present invention, such detailed description will be omitted. In the case of using "including", "having" and "comprising" described in this specification, another component may be added unless "only" is used. Unless otherwise stated, terms in the singular may include plural forms.

[0038] When interpreting an element, although the error range is not explicitly described, the element should be interpreted as including the error range.

[0039] When describing a positional relationship, for example, when the positional relationship between two components is described as "on", "above", "below", and "beside", unless "immediately" or "directly" is used, one or more other components may be arranged between the two components.

[0040] When describing a time relationship, for example, when describing a time sequence with "after," "subsequently," "next," and "before," discontinuous cases may be included unless "just" or "directly" is used.

[0041] It will be understood that, although the terms "first", "second", etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present invention, the first element can be named as the second element, and similarly, the second element can be named as the first element.

[0042] The term "at least one" should be understood to include any and all combinations of more than one of the related listed items. For example, "at least one of the first, second, and third items" means a combination of more than two of the first, second, and third items and all items proposed by the first, second, or third items.

[0043] The features of the various embodiments of the present invention may be combined or combined with each other in part or in whole, and may interact with each other in various ways and be technically driven in a manner that is fully understandable to those of ordinary skill in the art. The embodiments of the present invention may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0044] In the following, reference will be made to Figure 1 The semiconductor device structure and the manufacturing method thereof according to the present invention are described in detail.

[0045] Figure 1 is a diagram schematically showing a structure of a semiconductor device such as a green LED or a blue LED according to an embodiment of the present invention.

[0046] The semiconductor device structure according to an embodiment of the present invention may include a substrate 200, an undoped gallium nitride (undoped GaN) layer 210, an N-type gallium nitride (N-type GaN) layer 220, an active layer 230, and a P-type gallium nitride (P-type GaN) layer 240. The semiconductor device structure may include at least one material of InN, GaN, AlN, InP, InAs, InSb, GaAs, and GaSb, and the above materials may be included in different proportions.

[0047] An encapsulation layer may be additionally formed on Figure 1 on at least one of a lower portion and an upper portion of a semiconductor device structure.

[0048] The substrate 200 may be a silicon substrate including germanium (Ge) or a substrate on which a silicon layer including germanium (Ge) is formed.

[0049] Figure 1 The method of manufacturing a semiconductor device structure may include the process of forming at least one of an undoped gallium nitride (undoped GaN) layer 210 , an N-type gallium nitride (N-type GaN) layer 220 , an active layer 230 , and a P-type gallium nitride (P-type GaN) layer 240 .

[0050] The process of forming a gallium nitride layer, especially the process of forming an undoped gallium nitride layer 210 may include step a): forming a gallium nitride layer on a substrate 200 by sequentially supplying a gallium (Ga) precursor and a nitrogen (N2) precursor at a temperature below 500° C. Thereafter, step b) may be further included: exposing the gallium nitride (GaN) layer to a hydrogen-containing plasma. The plasma gas may contain hydrogen, and for example, an inert gas such as helium (He) and argon (Ar) may be used as the plasma gas, preferably, hydrogen may be used as the plasma gas. By exposing the gallium nitride (GaN) layer to a hydrogen-containing plasma, impurities present in the gallium nitride (GaN) layer may be removed, and the film quality may be improved.

[0051] A process of forming a hydrogen-containing plasma may be further added between the process of supplying a gallium (Ga) precursor and the process of supplying a nitrogen (N2) precursor. In this case, since the gallium nitride (GaN) layer is obtained by removing impurities in the gallium (Ga) precursor adsorbed on the substrate 200 through plasma, the film quality of the gallium nitride (GaN) layer may be improved. In this case, helium (He) and argon (Ar) may be used as plasma gas in addition to hydrogen.

[0052] When a nitrogen (N2) precursor is supplied, plasma can also be formed.

[0053] In addition, a step of forming an additional pure silicon layer may be added between the silicon substrate containing germanium (Ge) or the substrate having the silicon layer containing germanium (Ge) and the gallium nitride (GaN) layer. The step of forming the pure silicon layer may include an epitaxial growth (Epi) method of silicon (Si).

[0054] Step a) to step b) may be repeated multiple times. Only step a) may be repeated, or only step b) may be repeated.

[0055] In addition to step a) and step b), the formation of the N-type gallium nitride (N-type GaN) layer 220 may further include supplying a silicon (Si) precursor, and in addition to step a) and step b), the formation of the active layer 230 may further include supplying an indium (In) precursor, and the formation of the P-type gallium nitride (P-type GaN) layer 240 may further include supplying a magnesium (Mg) precursor.

[0056] By sequentially supplying a gallium (Ga) precursor and a nitrogen (N2) precursor, a gallium nitride (GaN) layer may be formed on the substrate 200. This may be performed by using atomic layer deposition (ALD), and specifically, the process of forming the gallium nitride (GaN) layer may include the following steps: a) flowing a precursor containing gallium (Ga) into a chamber through a gas injector; and b) flowing a precursor containing nitrogen (N2) into the chamber through a gas injector.

[0057] In order to prevent moisture or oxygen from penetrating the substrate 200 , an encapsulation layer may be formed on the substrate 200 , for example, under the substrate 200 .

[0058] Furthermore, after the process of forming the gallium nitride (GaN) layer, an encapsulation layer may be additionally formed on the GaN layer to prevent moisture or oxygen from penetrating.

[0059] Before the process of supplying the gallium (Ga) precursor, a step of removing oxides and impurities on the substrate 200 may be added. The step of removing oxides and impurities on the substrate 200 includes exposing the substrate 200 to a gas containing at least one of fluorine F and chlorine Cl. At this time, the step of removing oxides and impurities on the substrate 200 may be performed in the same chamber or system as that used to form the gallium nitride layer.

[0060] Figure 2 FIG. 1 is a diagram showing a structure of a semiconductor device such as a red LED according to another embodiment of the present invention.

[0061] according to Figure 2 The semiconductor device structure may include a substrate 300, an undoped gallium arsenide (undoped GaAs) layer 310, an N-type gallium arsenide (N-type GaAs) layer 320, an active layer 330, and a P-type gallium arsenide (P-type GaAs) layer 340. The semiconductor device structure may include at least one material of InN, GaN, AlN, InP, InAs, InSb, GaAs, and GaSb, and the above materials may be included in different proportions.

[0062] The substrate 300 may be a silicon substrate including germanium (Ge) or a substrate on which a silicon layer including germanium (Ge) is formed.

[0063] A semiconductor device may be manufactured by forming an undoped gallium arsenide (undoped GaAs) layer 310 , an N-type gallium arsenide (N-GaAs) layer 320 , an active layer 330 , and a P-type gallium arsenide (P-GaAs) layer 340 on a substrate 300 .

[0064] The process of forming at least one of the undoped GaAs layer 310, the N-type GaAs layer 320, the active layer 330, and the P-type GaAs layer 340 may include the following steps: c) forming a gallium arsenide (GaAs) layer on the substrate 300 by sequentially supplying a gallium (Ga) precursor and an arsenide (As) precursor at a temperature below 500° C.; and d) exposing the gallium arsenide (GaAs) layer to hydrogen-containing plasma. Steps c) to d) may be repeated multiple times.

[0065] Furthermore, a step of forming an additional pure silicon layer may be added between the silicon substrate containing germanium (Ge) or the substrate having the silicon layer containing germanium (Ge) and the gallium arsenide (GaAs) layer. The step of forming the pure silicon layer may include an epitaxial growth (Epi) method of silicon (Si).

[0066] In addition to step c) and step d), the formation of the N-type gallium arsenide (N-type GaAs) layer 320 may further include supplying a silicon (Si) precursor, and in addition to step c) and step d), the formation of the active layer 330 may further include supplying an indium (In) precursor, and the formation of the P-type gallium arsenide (P-type GaAs) layer 340 may further include supplying a magnesium (Mg) precursor.

[0067] In addition, the process of sequentially supplying a gallium (Ga) precursor and an arsenide (As) precursor to form an undoped gallium arsenide (GaAs) layer 310 on the substrate 300 may include the following steps: a) flowing a precursor containing gallium (Ga) into a chamber through a gas injector; and b) flowing a precursor containing arsenide (As) into the chamber through a gas injector.

[0068] By exposing the gallium arsenide (GaAs) layer to hydrogen-containing plasma, impurities present in the gallium arsenide (GaAs) layer can be removed and film quality can be improved.

[0069] A process of forming a plasma containing hydrogen may be further added between the process of supplying a gallium (Ga) precursor and the process of supplying an arsenide (As) precursor. In this case, since a gallium arsenide (GaAs) layer is obtained by removing impurities in the gallium (Ga) precursor adsorbed on the substrate 300 through plasma, the film quality of the gallium arsenide (GaAs) layer may be improved. In this case, helium (He) and argon (Ar) may also be used as plasma gas in addition to hydrogen.

[0070] Furthermore, when an arsenide (As) precursor is supplied, plasma may be formed.

[0071] An encapsulation layer may be formed on the substrate 300 to prevent moisture or oxygen from penetrating the substrate 300. In addition, after the step of forming the gallium arsenide (GaAs) layer, an encapsulation layer for preventing moisture or oxygen from penetrating may be additionally formed on the gallium arsenide layer.

[0072] Before the process of supplying the gallium (Ga) precursor, a step of removing oxides and impurities on the substrate 300 may be added. The step of removing oxides and impurities on the substrate 300 includes exposing the substrate 300 to a gas containing at least one of fluorine F and chlorine Cl. At this time, the step of removing oxides and impurities on the substrate 300 may be performed in the same chamber or system as that used to form the gallium arsenide layer.

[0073] Figure 3 is a diagram illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

[0074] according to Figure 3The method for manufacturing a semiconductor device can be used to manufacture a transistor. The method includes the following steps: preparing a silicon substrate containing germanium (Ge) or a substrate on which a silicon layer containing germanium (Ge) is formed (S500); a): supplying a gallium precursor and a nitrogen precursor to the substrate in sequence at below 500° C. to form a gallium nitride layer (S510); and b): exposing the gallium nitride layer to a hydrogen-containing plasma (S520). Steps a) to b) (S530) may be repeated multiple times. Alternatively, in step S530, only step a) may be repeated, or only step b) may be repeated.

[0075] In addition, a step of forming an additional pure silicon layer may be added between the silicon substrate containing germanium (Ge) or the substrate having the silicon layer containing germanium (Ge) and the gallium nitride (GaN) layer. The step of forming the pure silicon layer may include an epitaxial growth (Epi) method of silicon (Si).

[0076] In the step of supplying the reaction gas containing the nitrogen precursor, plasma containing hydrogen may be formed.

[0077] The step (S500) of preparing a silicon substrate containing germanium (Ge) or a substrate having a silicon layer containing germanium (Ge) may include transporting the substrate to a substrate to be described later. Figure 5 The substrate transported to the process space may be loaded into a process space described later. Figure 5 Here, the substrate may be one of a silicon substrate including germanium (Ge), a substrate on which a silicon layer including germanium (Ge) is formed, a sapphire substrate, a sapphire substrate on which a silicon layer including germanium (Ge) is formed, a glass substrate, a glass substrate on which a silicon layer including germanium (Ge) is formed, and a silicon wafer.

[0078] In addition, the step of conveying the substrate (S500) may be performed by conveying a substrate having a predetermined functional layer. For example, in the stage of preparing and conveying the substrate (S500), a substrate having a gate electrode disposed on the upper surface of the substrate and a gate insulating film disposed on the gate electrode to cover the gate electrode may be used. Alternatively, a substrate having an encapsulation layer, a drain electrode, and a source electrode may be used.

[0079] Here, the Figure 5 The substrate support 172 may be equipped with an electrostatic chuck to adsorb the substrate, or may be equipped with a vacuum adsorption device or a mechanical fixing element.

[0080] The step a) of sequentially supplying a gallium precursor and a nitrogen precursor to a substrate below 500° C. to form a gallium nitride layer (S510) includes: supplying a gallium precursor and a nitrogen precursor to a substrate to be described later; Figure 5A gallium nitride layer is formed on a substrate in a process space of a chamber 160. Here, the gallium nitride (GaN) layer may constitute at least a portion of an active layer of a thin film transistor (TFT) used as a switching circuit in a semiconductor device or a display device. For example, the gallium nitride layer may form a channel region between a gate and a source / drain.

[0081] In an embodiment of the present invention, step a) of sequentially supplying a gallium precursor and a nitrogen precursor to the substrate at a temperature below 500° C. to form a gallium nitride layer (S510) can be performed in a low temperature process. That is, step a) of sequentially supplying a gallium precursor and a nitrogen precursor to the substrate at a temperature below 500° C. to form a gallium nitride layer (S510) can be performed by controlling the process space of the chamber 160 to a temperature above 50° C. and below 500° C.

[0082] The gallium nitride layer may be formed at a low temperature of 50° C. to 600° C. by an atomic layer growth (ALG) process or an atomic layer deposition (ALD) process, which will be described in more detail below.

[0083] The gallium precursor may include trimethylgallium (TMGa) gas including gallium as a main component. A source gas including the gallium precursor is sprayed onto the substrate to be adsorbed or deposited on the substrate.

[0084] The step of supplying the doping gas to the substrate may be performed simultaneously with the step of supplying the gallium precursor, or after the step of supplying the gallium precursor. As described above, the gallium nitride layer forms at least a portion of the active layer, and the active layer may be formed of a p-type active layer or an n-type active layer, depending on the type of the active layer. Therefore, the step of supplying the p-type doping gas or the n-type doping gas to the substrate may be performed simultaneously with the step of supplying the gallium precursor (that is, the source gas), or after the step of supplying the gallium precursor. The doping gas may be supplied through at least one of the first gas supply path and the second gas supply path, wherein the p-type doping gas may contain bis-cyclopentadienyl magnesium (Cp2Mg) gas, and the N-type doping gas may contain diisopropylaminosilane (DIPAS).

[0085] In this way, a p-type gallium nitride layer or an n-type gallium nitride layer can be formed by supplying a p-type doping gas or an n-type doping gas after supplying a gallium precursor and before spraying a nitrogen precursor. A gallium precursor can be supplied, a purge gas can be supplied, a doping (p-type doping or n-type doping) gas can be supplied, a purge gas can be supplied, a nitrogen precursor can be supplied, and a purge gas can be supplied. Alternatively, a doping (p-type doping or n-type doping) gas can be supplied simultaneously with a gallium precursor, a purge gas can be supplied, a nitrogen precursor can be supplied, and a purge gas can be supplied.

[0086] While sequentially supplying the gallium precursor and the nitrogen precursor, a purge gas may be supplied to exhaust the gas outside the chamber 160 and remove the source gas and the reaction gas remaining in the process space of the chamber 160. The purge gas may be an inert gas such as argon (Ar).

[0087] After the gallium nitride layer is formed, the gallium nitride layer may be exposed to plasma containing hydrogen (H2). At this time, hydrogen may be activated and supplied.

[0088] When the reaction gas (nitrogen) is supplied, the reaction gas can be activated and supplied to effectively react the nitrogen component with the gallium component. The nitrogen-containing gas can be activated into nitrogen radicals to react with the gallium component, and a gallium nitride layer can be formed on the substrate at a lower process temperature. That is, when the reaction gas is activated and supplied to the substrate, the gallium nitride layer can be formed by controlling the chamber for forming the gallium nitride layer at a low temperature.

[0089] After supplying a reaction gas to form a gallium nitride layer, or after exposing the gallium nitride layer to hydrogen-containing plasma, an inert gas such as argon (Ar) may be supplied to purge residual gas in the chamber 160 .

[0090] The amorphous gallium nitride layer may be crystallized by hydrogen (H2) plasma. When the gallium nitride layer is formed by supplying only source gas and reaction gas, the gallium nitride layer may be deposited on the substrate in an amorphous state. As in an embodiment of the present invention, when the hydrogen-containing gas is activated and supplied to the substrate after blowing off the reaction gas, the amorphous gallium nitride layer may be crystallized to have a polycrystalline or single crystal structure. In addition to hydrogen, inert gases Ar gas and He gas may also be used.

[0091] Furthermore, if the temperature inside the chamber 160 or the temperature of the substrate is low, the gallium nitride layer can be formed at a low temperature of, for example, 500° C. or less. Furthermore, by forming hydrogen plasma on the substrate, impurities remaining inside the chamber 160 or impurities included in the gallium nitride layer can be effectively removed.

[0092] Here, step a) and step b) may be repeated multiple times, wherein step a) is to sequentially supply a gallium precursor and a nitrogen precursor at a temperature below 500° C. (S510), and step b) is to expose the gallium nitride layer to a hydrogen-containing plasma (S520) to form a gallium nitride layer of desired thickness and crystallization. Alternatively, step a) may be repeated multiple times before step b) is repeated.

[0093] Figure 4 Schematically shows a transistor manufactured according to an embodiment of the present invention. This embodiment relates to a bottom gate structure, but the present invention may also include a top gate structure. Figure 4 Shown by Figure 3 A transistor including a gallium nitride layer as an active layer 130 is prepared by the manufacturing method.

[0094] according to Figure 4 , the transistor according to an embodiment of the present invention includes: a gate 110; a source 142 and a drain 144, the source 142 and the drain 144 are horizontally spaced apart from each other and are arranged above or below the gate 110; an active layer 130, the active layer 130 is arranged between the gate 110 and the source 142 and between the gate 110 and the drain 144; and a gate insulating film 120, the gate insulating film 120 is arranged between the gate 110 and the active layer 130.

[0095] At least a portion of the active layer 130 is formed of a gallium nitride layer.

[0096] Here, the transistor according to the embodiment of the present invention may be a bottom gate type transistor including a gate 110 formed on a substrate 100, a gate insulating film 120 formed on the gate 110, an active layer 130 formed on the gate insulating film 120, and a source 142 and a drain 144 formed to be spaced apart from each other and disposed on the active layer 130. However, the transistor according to the embodiment of the present invention includes a top gate type transistor in which the gate 110 is disposed above the active layer 130.

[0097] Here, the substrate 100 may include various substrates to form a gallium nitride (GaN) layer. For example, the substrate may be a silicon substrate containing germanium (Ge), a substrate on which a silicon layer containing germanium (Ge) is formed, a sapphire substrate, a sapphire substrate on which a silicon layer containing germanium (Ge) is formed, a glass substrate, a glass substrate on which a silicon layer containing germanium (Ge) is formed, and a silicon wafer. In addition, various substrates such as a transparent substrate or a flexible substrate may be used as the substrate 100.

[0098] The gate 110, the source 142, and the drain 144 may be formed by using a conductive material such as aluminum (Al), neodymium (Nd), silver (Ag), chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo), and copper (Cu) or an alloy thereof. In addition, the gate 110 may be formed of a single layer or a multilayer consisting of a plurality of metal layers. For example, the gate 110 may be formed as a double layer including a metal layer such as chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum (Mo) having excellent physical and chemical properties and a metal layer such as aluminum (Al), silver (Ag), and copper (Cu) having a low specific resistance.

[0099] The gate insulating film 120 is formed on the gate 110. That is, the gate insulating film 120 can be formed on the upper surface of the substrate 100 and on the upper and side portions of the gate 110. The gate insulating film 120 can be formed of one or more of silicon dioxide (SiO2), silicon nitride (SiN), high-K dielectrics, and aluminum oxide (Al2O3) having excellent adhesion to metal materials and excellent insulation resistance. Here, the high-K dielectric is a dielectric having a higher dielectric constant than silicon dioxide (SiO2), and may include hafnium dioxide (HfO2), zirconium dioxide (ZrO2), and the like.

[0100] The active layer 130 is formed on the gate insulating film 120, and at least a portion of the active layer 130 is formed to overlap the gate 110. The active layer 130 may include a gallium nitride layer. As described above, forming the gallium nitride layer may include loading a substrate into a process space of a chamber and forming the gallium nitride layer on the substrate. Forming the gallium nitride layer may include supplying a source gas containing gallium onto the substrate, supplying a reaction gas containing nitrogen onto the substrate, and activating and supplying a post-processing gas containing hydrogen onto the substrate supplied with the reaction gas.

[0101] Although Figure 4 1, but such a gallium nitride layer may be formed directly on the gate insulating film 120, and the buffer layer may be formed on the gate insulating film and the gallium nitride layer may be formed on the buffer layer. Here, the buffer layer is a layer formed before the gallium nitride layer, and may be a seed layer that helps the gallium nitride layer to crystallize more efficiently. That is, when the gallium nitride layer is formed, the buffer layer may be a seed layer that promotes the crystallization of the gallium nitride layer. The buffer layer may be formed of an aluminum nitride (AlN) layer, and may be formed by various layer formation processes such as an atomic layer deposition method or a chemical vapor deposition method.

[0102] The source 142 and the drain 144 are formed above the active layer 130 (that is, the gallium nitride layer) and may partially overlap the gate 110. The source 142 and the drain 144 are spaced apart from each other. The source 142 and the drain 144 may be formed using the same process using the same material, and may be formed using a conductive material such as aluminum (Al), neodymium (Nd), silver (Ag), chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum (Mo) or an alloy thereof. The source 142 and the drain 144 may be formed of the same material as the gate 110, but may be formed of different materials. In addition, the source 142 and the drain 144 may be formed of a single layer or a multilayer of a plurality of metal layers, respectively.

[0103] Furthermore, a step of forming an additional pure silicon layer on a silicon substrate containing germanium (Ge) or a substrate having a silicon layer containing germanium (Ge) may be included. This step may include an epitaxial growth (Epi) method of silicon (Si).

[0104] The LED device may include red, green, and blue light emitting parts, wherein the green and blue light emitting parts may be made of gallium nitride (GaN), and the red light emitting part may be made of gallium arsenide (GaAs).

[0105] Figure 5 is a diagram schematically showing a deposition apparatus according to an embodiment of the present invention.

[0106] Reference Figure 5 , the atomic layer deposition apparatus according to an embodiment of the present invention is a device for depositing a gallium nitride layer, and includes an upper dome 152 and a lower dome 158. Process gases (that is, source gas and reaction gas) may be supplied to the upper dome 152, respectively, and the process gases (that is, source gas and reaction gas) may be exhausted from the upper dome 152. The source gas and the reaction gas may be supplied by a gas injector. The gas injector includes more than one injector, and the process gas may be injected into the process space by more than one injector. The process space may be located below the upper dome 152. By supplying a purge gas to the lower dome 158 and supplying a process gas to the upper dome 152, the deposition of an abnormal layer in the lower dome 158 may be suppressed by preventing the process gas from flowing to the lower dome 158. In addition, without rotating the substrate 174, a uniform plasma may be formed to form a uniform layer.

[0107] In addition, gallium nitride (GaN) and gallium arsenide (GaAs) can be formed as plasma enhanced ALD (PEALD) devices by using an inductively coupled plasma source.

[0108] The atomic layer deposition apparatus equipped with the upper dome 152 and the lower dome 158 is equipped with liners 154, 156 to prevent unnecessary layer deposition on the inner wall of the chamber 160. The liners 154, 156 may be replaced or cleaned periodically.

[0109] The plurality of heating lamps 166 disposed below the lower dome 158 may be ring-shaped heating lamps. The plurality of heating lamps 166 may be independently powered to uniformly heat the substrate 174.

[0110] A high vacuum pump 190 made of a turbomolecular pump (TMP) connected to an exhaust port of the chamber 160 maintains a base vacuum inside the chamber 160 , thereby forming a stable plasma at a pressure below several Torr during a process.

[0111] The atomic layer deposition (ALD) device of the present invention can reduce the performance degradation caused by infrared heating of the antenna 110 set on the upper dome 152 for forming an inductively coupled plasma, and provide infrared rays reflected from the electromagnetic wave shielding shell 130 to the substrate 174 again, thereby forming a uniform layer on the substrate 174 at a high speed.

[0112] according to Figure 5 , an atomic layer deposition (ALD) apparatus 100 according to an embodiment of the present invention includes: a chamber 160 having a side wall; a substrate support 172 disposed inside the chamber and supporting a substrate; an upper dome 152 covering an upper surface of the chamber 160 and made of a transparent dielectric material; an antenna 110 disposed above the upper dome 152 to form an inductively coupled plasma; and an electromagnetic wave shielding shell 130 disposed around the antenna 110. The electromagnetic wave shielding shell 130 may be heated by a heater.

[0113] The antenna 110 includes two single-turn element antennas, and the two single-turn element antennas may be connected to the RF power source 140 in parallel.

[0114] The step of generating hydrogen plasma after the step of supplying the reaction gas and the step of generating plasma between the source gas supplying step and the reaction gas supplying step may be performed by the antenna 110 .

[0115] Source gas and reaction gas may be injected into process spaces within upper dome 152 and lower dome 158 by an injector (not shown). Source gas and reaction gas may be supplied in an upper dome 152 direction or a horizontal direction by the injector and injected into chamber 160.

[0116] The chamber 160 is formed of a conductor, the inner space of the chamber 160 may be cylindrical, and the outer shape of the chamber 160 may be a rectangular parallelepiped shape. The chamber 160 may be cooled by cooling water. The chamber 160, the upper dome 152, and the lower dome 158 are combined to provide a sealed space.

[0117] The substrate inlet 160a may be provided at one side of the chamber 160, and the exhaust port 160b may be provided at the other side of the chamber 160 facing the substrate inlet 160a. The exhaust port 160b may be connected to a high vacuum pump 190. The high vacuum pump 190 may be a turbomolecular pump. The high vacuum pump 190 helps to maintain a low base pressure and maintain a pressure below several Torr even during a process. The upper surface of the exhaust port 160b may be equal to or lower than the upper surface of the substrate inlet 160a.

[0118] The upper dome 152 may be made of quartz, sapphire or ceramic, which are transparent dielectrics. The upper dome 152 may be formed of a ceramic material. The ceramic material has better corrosion resistance than quartz.

[0119] The upper dome 152 may be inserted into a jaw formed on the upper surface of the chamber 160 to be coupled to the chamber 160. The coupling portion of the upper dome 152 coupled to the chamber 160 for vacuum sealing may have a gasket shape. The upper dome 152 may have an arc or elliptical shape. The upper dome 152 may transmit infrared rays incident from the lower portion.

[0120] Infrared rays reflected from the electromagnetic wave shield housing 130 may pass through the upper dome 152 , and may enter the substrate 174 .

[0121] The lower dome 158 is a transparent dielectric and may be formed of quartz or sapphire. The lower dome 158 may include a gasket-shaped coupling portion coupled to a jaw formed on the lower surface of the chamber 160, a funnel-shaped lower dome body extending below the coupling portion, and a cylindrical tube extending downward from the center of the lower dome body. The lower dome 158 may be inserted into the jaw formed on the lower surface of the chamber 160 and coupled to the chamber 160. The coupling portion of the lower dome 158 coupled to the chamber 160 for vacuum sealing may have a gasket shape.

[0122] The driving shaft of the first lifting member 184 and the driving shaft of the second lifting member 182 may be inserted and disposed in the cylindrical tube of the lower dome 158. The purge gas supplied through the lower dome 158 may be supplied through a flow path. The flow path may be the cylindrical tube of the lower dome 158. The purge gas may be an inert gas such as argon.

[0123] The upper pad 154 may be made of a transparent dielectric. For example, the upper pad 154 may be made of quartz, alumina, sapphire, or aluminum nitride. The upper pad 154 may be made of a material that inhibits abnormal layer deposition.

[0124] The heat insulating portion 162 may be disposed between the lower surface of the chamber 160 and the reflector 161 and may have a ring shape. The heat insulating portion 162 may reduce heat transfer from the heated reflector 161 to the chamber 160. The heat insulating portion 162 may be made of a ceramic material. The upper surface of the heat insulating portion 162 may have a jaw. The jaw of the heat insulating portion 162 and the jaw of the lower surface of the chamber 160 may accommodate a gasket-shaped joint of the lower dome 158 and make the interior vacuum-sealed.

[0125] The concentric ring-shaped heating lamps 166 may include a plurality of concentric ring-shaped heating lamps and may be connected to the power supply 164. The plurality of concentric ring-shaped heating lamps 166 are arranged along the inclined surface of the lower dome 158 at fixed intervals, and the concentric heating lamps 166 may be divided into three groups to receive power independently of each other. The concentric ring-shaped heating lamps 166 may be inserted into an annular groove formed on the inclined surface of the reflector 161 and aligned therewith.

[0126] For example, the concentric heating lamps 166 may be halogen heating lamps, and eight concentric heating lamps 166 may be applied. The three heating lamps at the bottom may form a first group, the two heating lamps in the middle may form a second group, and the three heating lamps at the top may form a third group. The first group may be connected to a first power supply 164a, the second group may be connected to a second power supply 164b, and the third group may be connected to a third power supply 164c. The first power supply 164a to the third power supply 164c may be independently controlled to uniformly heat the substrate.

[0127] The RF power supply 140 can supply RF power to the antenna 110 through an impedance matching box (IMB) 142 and a power supply line 143. The antenna 110 through which the RF current flows has a sufficient cross-sectional area for high current, and it is desirable to form a closed loop to form sufficient magnetic flux. The antenna 110 can use a vertically erected strip line to minimize the increase in resistance caused by heating caused by absorbing infrared rays incident from its upper or lower part. The antenna 110 provides high transmittance to infrared rays.

[0128] In addition, the antenna 110 may be coated with gold (Au) or silver (Ag) to increase infrared reflection. In addition, in order to ensure sufficient magnetic flux, a two-layer structure of the antenna 110 may be used.

[0129] The lower dome 158 covers the lower surface of the chamber 160, is formed of a transparent dielectric material, and may have the same curvature as the upper dome 152. The heating lamp 166 may be disposed on the lower surface of the lower dome 158. The reflector 161 may be disposed on the lower surface of the heating lamp 166.

[0130] In addition, a controller (not shown) for controlling the RF power source 140 may be further included. Here, for example, a source gas supply path (not shown) for supplying a raw material gas and a reaction gas supply path (not shown) may be independently formed.

[0131] Meanwhile, a silicon substrate containing germanium (Ge) may be loaded into the chamber 160 to perform a layer forming process on the substrate support 172. The substrate 174 may include various substrates to form a gallium nitride (GaN) layer. For example, the substrate 174 may be one of a silicon substrate containing germanium (Ge), a substrate on which a silicon layer containing germanium (Ge) is formed, a sapphire substrate, a sapphire substrate on which a silicon layer containing germanium (Ge) is formed, a glass substrate, a glass substrate on which a silicon layer containing germanium (Ge) is formed, and a silicon wafer.

[0132] The substrate support 172 may be equipped with an electrostatic chuck to adsorb the substrate 174 by electrostatic force, or may be equipped with a vacuum adsorption device or a mechanical fixing element.

[0133] The clamp 150 may be provided to cover the edge of the upper dome 152. The clamp 150 is formed of a conductor and may be cooled by cooling water. The lower surface of the clamp 150 may have a jaw to be coupled to a washer-shaped coupling portion of the upper dome 152, and may include a bent portion 150a to cover a portion of the bent portion of the upper dome 152. The bent portion 150a of the clamp 150 may be plated with gold to reflect infrared rays. The inner diameter of the clamp 150 may be substantially the same as the inner diameter of the upper pad 154. In addition, the inner diameter of the clamp 150 may be the same as the diameter of the antenna housing 130.

[0134] The chamber housing 132 may be disposed on the jig 150 , and may be disposed to cover the antenna housing 130 .

[0135] At the same time, it can be configured that a gas containing gallium (Ga) can be supplied as a source gas, and a gas containing nitrogen (N) can be supplied as a reaction gas. Here, the source gas, for example, the gas containing gallium can include trimethyl gallium (TMGa) gas, and the reaction gas, for example, the gas containing nitrogen can include ammonia (NH3).

[0136] In the above, embodiments of the present invention have been described in more detail with reference to the accompanying drawings, but the present invention is not limited to these embodiments, and various modifications can be made without departing from the technical spirit of the present invention. Therefore, it should be understood that the above embodiments are exemplary and non-restrictive in all aspects. It should be explained that the scope of the present invention is defined by the claims described below, rather than by the embodiments, and the scope and meaning of the claims and all changes or modifications derived from the equivalent concepts of the claims are included in the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of forming at least one gallium nitride layer or at least one gallium arsenide layer among an undoped gallium nitride layer, an undoped gallium arsenide layer, an N-type gallium nitride layer, an N-type gallium arsenide layer, an active layer, a P-type gallium nitride layer and a P-type gallium arsenide layer on a silicon substrate containing germanium or a substrate on which a silicon layer containing germanium is formed, The process of forming the at least one gallium nitride layer or the at least one gallium arsenide layer comprises the following steps: a) supplying i) a gallium precursor and ii) a nitrogen precursor or an arsenide precursor in sequence at a temperature below 500° C. to form a gallium nitride layer or a gallium arsenide layer on the silicon substrate or the substrate; and b) exposing the gallium nitride layer or the gallium arsenide layer to a plasma containing hydrogen, in, Repeat steps a) and b) multiple times.

2. A method for manufacturing a semiconductor device, comprising the step of forming a gallium nitride layer or a gallium arsenide layer on a silicon substrate containing germanium or a substrate on which a silicon layer containing germanium is formed, The process of forming the gallium nitride layer or the gallium arsenide layer includes: i) a gallium precursor and ii) a nitrogen precursor or an arsenide precursor are sequentially supplied into the chamber, and The step of sequentially supplying i) the gallium precursor and ii) the nitrogen precursor or the arsenide precursor into the chamber comprises the following steps: a) flowing the gallium precursor into the chamber through a gas injector at a temperature below 500° C.; and b) flowing the nitrogen precursor or the arsenide precursor through the gas injector to form the gallium nitride layer or the gallium arsenide layer on the silicon substrate or the substrate.

3. A method for manufacturing a semiconductor device, comprising the steps of forming at least one gallium nitride layer or at least one gallium arsenide layer among an undoped gallium nitride layer, an undoped gallium arsenide layer, an N-type gallium nitride layer, an N-type gallium arsenide layer, an active layer, a P-type gallium nitride layer and a P-type gallium arsenide layer on a silicon substrate containing germanium or a substrate on which a silicon layer containing germanium is formed, The process of forming the at least one gallium nitride layer or the at least one gallium arsenide layer comprises: supplying i) a gallium precursor and ii) a nitrogen precursor or an arsenide precursor in sequence at a temperature below 500° C. to form a gallium nitride layer or a gallium arsenide layer on the silicon substrate or the substrate, Wherein, when the nitrogen precursor or the arsenide precursor is supplied, plasma is generated.

4. The method for manufacturing a semiconductor device according to claim 2 or 3, further comprising: After forming the gallium nitride layer or the gallium arsenide layer, the gallium nitride layer or the gallium arsenide layer is exposed to a plasma containing hydrogen.

5. The method for manufacturing a semiconductor device according to claim 1 or 3, wherein: The process of forming the N-type gallium nitride layer or the N-type gallium arsenide layer further includes supplying a silicon precursor, The process of forming the active layer further comprises supplying an indium precursor, and Wherein, the process of forming the P-type gallium nitride layer or the P-type gallium arsenide layer further includes supplying a magnesium precursor.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, further comprising: A plasma containing hydrogen is generated between supplying the gallium precursor and supplying the nitrogen precursor or the arsenide precursor.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, further comprising: Before supplying the gallium precursor, the silicon substrate or the substrate is exposed to a gas including at least one of fluorine and chlorine to remove oxides and impurities on the silicon substrate or the substrate.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: Removing the silicon substrate or oxides and impurities on the substrate is performed in the same chamber or system as that used to form the gallium nitride layer or the gallium arsenide layer.

9. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, further comprising: An encapsulation layer is formed to prevent moisture or oxygen from penetrating the silicon substrate or the substrate.

10. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, further comprising: A pure silicon layer is formed on the silicon substrate or on the substrate.

11. A method for manufacturing a semiconductor device, comprising: loading at least one substrate onto a substrate support in an atomic layer deposition chamber including a gas injector, the at least one substrate including a silicon substrate including germanium or a substrate having a silicon layer including germanium formed thereon; maintaining the substrate support below 500° C.; a) flowing a gallium precursor into the atomic layer deposition chamber through the gas injector; b) flowing a purge gas for blowing away the gallium precursor into the atomic layer deposition chamber; c) flowing a nitrogen precursor or an arsenide precursor into the atomic layer deposition chamber through the gas injector to form a gallium nitride layer or a gallium arsenide layer on the at least one substrate; and d) flowing a hydrogen-containing gas into the atomic layer deposition chamber through the gas injector to generate a hydrogen plasma, Wherein, steps a) to d) are repeated multiple times.

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