Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a technique with which it is possible to improve the voltage resistance of a semiconductor device having a semiconductor region or a semiconductor layer that includes a crystalline oxide semiconductor containing gallium, even without relying on a p-type semiconductor region or semiconductor layer. A semiconductor device includes a semiconductor layer in which a depletion layer extends, and an electrode disposed on the semiconductor layer directly or via another layer. The semiconductor layer has a first region containing a crystalline oxide semiconductor containing gallium as a main component and a second region containing an oxide containing gallium as a main component, and the second region has a linear crystal defect region in a cross section perpendicular to the upper surface of the semiconductor layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Patent Document 1 discloses a Schottky barrier diode having a p-type high resistance region. The p-type high resistance region is composed of a β-Ga2O3 system single crystal that has been ion-implanted with Mg or Be and annealed. In addition, it is not considered to be a prior art simply because it is described in the background art.

[0003] Patent Document 1: Japanese Patent Publication No. 2016-039194 Summary of the invention

[0004] The problem to be solved by the present disclosure is to provide a technology capable of improving the withstand voltage of a semiconductor device having a semiconductor region or semiconductor layer including a crystalline oxide semiconductor containing gallium without relying on a p-type semiconductor region or semiconductor layer.

[0005] According to one embodiment of the present disclosure, a semiconductor device comprises: a semiconductor layer having an extended depletion layer; and an electrode disposed on the semiconductor layer directly or via other layers. The semiconductor layer comprises: a first region including a crystalline oxide semiconductor containing gallium as a main component; and a second region including an oxide containing gallium as a main component, wherein the second region has a linear crystal defect in a cross section perpendicular to an upper surface of the semiconductor layer.

[0006] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device includes the following steps: forming a semiconductor layer, the semiconductor layer including a crystalline oxide semiconductor containing gallium as a main component and including an n-type dopant; ion implanting an impurity element from the upper surface of the semiconductor layer into a portion of the semiconductor layer; and forming an electrode directly on the semiconductor layer or via another layer without performing a process to activate the ion implanted element. The ion implantation step forms a first region and a second region, and in a cross section perpendicular to the upper surface of the semiconductor layer, linear crystal defects are formed in the second region, the first region including a crystalline oxide semiconductor containing gallium as a main component, and the second region including an oxide containing gallium as a main component.

[0007] According to the present disclosure, a semiconductor device and a method for manufacturing such a semiconductor device can be provided that can improve voltage resistance without using a p-type semiconductor region or semiconductor layer, wherein the semiconductor region or semiconductor layer includes a crystalline oxide semiconductor containing gallium. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.

[0009] Figure 2 This is a flowchart showing the method for manufacturing the semiconductor device according to the first embodiment.

[0010] Figure 3 It is a schematic cross-sectional view illustrating a semiconductor device according to a second embodiment.

[0011] Figure 4 It is a schematic cross-sectional view illustrating a semiconductor device according to a third embodiment.

[0012] Figure 5 It is a schematic cross-sectional view illustrating a semiconductor device according to a fourth embodiment.

[0013] Figure 6 It is a schematic cross-sectional view illustrating a semiconductor device according to a fifth embodiment.

[0014] Figure 7 This is a block diagram showing an example of a control system using a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 8 This is a circuit diagram showing an example of a control system using a semiconductor device according to an embodiment of the present disclosure.

[0016] Fig. 9 This is a block diagram showing an example of a control system using a semiconductor device according to an embodiment of the present disclosure.

[0017] Fig.10 This is a circuit diagram showing an example of a control system using a semiconductor device according to an embodiment of the present disclosure.

[0018] Fig.11 This is a graph showing the relationship between voltage (V) and current (A) when a reverse voltage is applied to the semiconductor device in Example 1.

[0019] Fig.12 The diagram shows the results of SEM observation of the semiconductor device in Example 1.

[0020] Fig.13 The diagram shows the results of SEM observation of the semiconductor device in Example 1.

[0021] Fig.14 This is a diagram showing the observation results of the semiconductor device in Example 1 using a scanning ion microscope (SIM).

[0022] Fig.15 1 is a diagram showing the results of SIM observation of the semiconductor device in Example 1.

[0023] Fig.16 It is a calculation result of the numerical calculation code (SRIM / TRIM) which shows the relationship between the depth from the upper surface of the semiconductor layer and the density of crystal defects or the concentration of impurity elements in Example 1.

[0024] Fig.17 The results of secondary ion mass spectrometry (SIMS) in Examples 2 to 5 show the relationship between the depth from the upper surface of the semiconductor layer and the concentration of impurities. DETAILED DESCRIPTION

[0025] Below, the embodiments of the semiconductor device disclosed in the present invention are described using the accompanying drawings, but the invention involved in the claims is not limited to these embodiments. In addition, all combinations of structures described in the embodiments are not limited to the combinations necessary for solving the problem. In addition, each structure of the present invention is described within the scope that does not hinder the solution of the problem disclosed in the present invention. In addition, the same structural elements are marked with the same figure marks, and repeated descriptions are omitted.

[0026] In addition, as will be apparent to those skilled in the art, the features shown in the drawings are not necessarily depicted to scale, even if not described in this specification. In addition, please note that a feature in one embodiment may also be used in another embodiment. Records of well-known components and processing techniques may be omitted to avoid unnecessarily obscuring the embodiments of the present disclosure. The purpose of the examples used in this specification is merely to aid in understanding the present disclosure and to enable those skilled in the art to implement the embodiments of the present disclosure. Therefore, the embodiments and examples in this specification are not to be construed as limited to the scope of the present disclosure, but are only to be defined by the claims and applicable laws.

[0027] Although the terms "first", "second", etc. are used to describe various elements used in this specification, the elements are not limited to these terms. The terms first, second, etc. are used only to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and a second element may be referred to as a first element. As used in this specification, the term "and / or" includes a combination of one item, multiple items, or all items listed.

[0028] In the present disclosure, one side in a direction parallel to the depth direction of the semiconductor layer is referred to as "upper" and the other side is referred to as "lower". Figure 1When observing the n-type semiconductor layer 13 of the semiconductor device 10, the Schottky electrode 14 side is set to the top, and when observing from the n+ type semiconductor layer 12, the ohmic electrode 11 side is set to the bottom to define "up" and "down". The surface located above the two main surfaces of the layer, substrate or other components is set as the upper surface, and the surface located below is set as the lower surface for description. These "up" and "down" directions are not limited to the direction of gravity or the installation direction of the substrate, etc. when the semiconductor device is installed. In addition, in the present disclosure, the direction orthogonal to the depth direction of the semiconductor layer is set to the horizontal direction for description. In addition, this specification uses the phrase "looking down" for description, but it can also be said to be overlooking.

[0029] It should be understood that when an element such as a layer, a region or a substrate is expressed as being “on” or “under” another element, it may be directly above or below the other element, or there may be intervening elements. It should be understood that when an element is expressed as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element, or there may be intervening elements.

[0030] The terms used in this specification are intended to describe specific solutions only and are not intended to limit the present disclosure. "Having" and "including" used in this specification indicate the presence of the described elements, and do not exclude the presence of one or more other elements.

[0031] If not otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used in this specification are interpreted as having meanings that do not conflict with the context of this specification and the meanings in the relevant technology. In addition, it should be understood that if there is no definition in this specification, the terms used in this specification should not be interpreted as idealized or overly formalized meanings.

[0032] The semiconductor device involved in the present disclosure is suitable for various semiconductor elements, especially for power devices. In addition, the semiconductor element can be classified into: a lateral element (lateral device), in which the electrode is formed on a single side of the semiconductor layer, and the current flows in the film thickness direction of the semiconductor layer and the in-plane direction of the film plane; and a vertical element (vertical device), which has electrodes on the front and back sides of the semiconductor layer, and the current flows in the film thickness direction of the semiconductor layer. In the embodiment of the present disclosure, the semiconductor element can be appropriately used for lateral devices and vertical devices, but it is preferably used for vertical devices. As the semiconductor element, for example, Schottky barrier diodes (SBD), junction barrier Schottky diodes (JBS), metal semiconductor field effect transistors (MESFET), metal insulator film semiconductor field effect transistors (MISFET), metal oxide semiconductor field effect transistors (MOSFET), high electron mobility transistors (HEMT) or light emitting diodes can be listed. In the embodiment of the present disclosure, the semiconductor device is preferably a diode, and more preferably a Schottky barrier diode (SBD). In addition, in the embodiment of the present disclosure, the semiconductor device is preferably a MOSFET.

[0033] (First Embodiment)

[0034] Figure 1 1 is a schematic cross-sectional view illustrating a semiconductor device 10 according to the first embodiment. The semiconductor device 10 according to the first embodiment is, for example, an SBD (Schottky barrier diode). Figure 1 As shown, the semiconductor device 10 includes an ohmic electrode 11, an n+ type semiconductor layer 12, an n- type semiconductor layer 13, and a Schottky electrode 14. Although not shown in the figure, a supporting substrate of a conductor made of a known material may be disposed below the ohmic electrode 11.

[0035] The ohmic electrode 11 is an electrode that makes ohmic contact with the n+ type semiconductor layer 12. The constituent material of the ohmic electrode 11 may be the same as the constituent material of the Schottky electrode 14 described in detail below, or may be a known material.

[0036] The n+ type semiconductor layer 12 is located on the ohmic electrode 11. The n+ type semiconductor layer 12 is an n type semiconductor layer having a carrier density greater than that of the n- type semiconductor layer 13. The n+ type semiconductor layer 12 includes a crystalline oxide semiconductor as a main component.

[0037] As the crystalline oxide semiconductor included in the n+ type semiconductor layer 12, for example, metal oxides including one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt and iridium can be listed. In the embodiment of the present disclosure, the crystalline oxide semiconductor preferably includes at least one metal selected from aluminum, indium and gallium, more preferably includes at least gallium, and most preferably is α-Ga2O3 or a mixed crystal thereof. According to the present disclosure, even when using a semiconductor with a large band gap such as gallium oxide or a mixed crystal thereof, the leakage current can be well reduced.

[0038] As the crystal structure of the crystalline oxide semiconductor included in the n+ type semiconductor layer 12, for example, a corundum structure, a β-gallia structure, a hexagonal structure (for example, an ε-type structure, etc.), an orthorhombic structure (for example, a κ-type structure, etc.), a cubic structure or a tetragonal structure, etc. can be cited. In the embodiment of the present disclosure, it is preferred that the crystalline oxide semiconductor has a corundum structure, a β-gallia structure or a hexagonal structure (for example, an ε-type structure, etc.), and more preferably has a corundum structure. In addition, the so-called "main component" means that relative to the total components of the n+ type semiconductor layer 12, in terms of atomic ratio, it is preferred that more than 50% of the crystalline oxide semiconductor is included, more preferably more than 70%, and further preferably more than 90%, and the content of the crystalline oxide semiconductor may also be 100%.

[0039] The thickness of the n+ type semiconductor layer 12 may be 1 μm or less, or 1 μm or more. In the embodiment of the present disclosure, the thickness of the n+ type semiconductor layer 12 is preferably 1 μm or more and preferably 3 μm or less. In addition, the thickness of the n+ type semiconductor layer 12 may be 3 μm or more.

[0040] The area of ​​the n+ type semiconductor layer 12 in a plan view may be 1 mm 2 Above, can also be 1mm 2 The area is preferably 2 mm 2 ~300cm 2 In addition, in the present embodiment, the n + -type semiconductor layer 12 is single crystal, but may be polycrystalline.

[0041] The carrier density of the n+ type semiconductor layer 12 can be appropriately set by adjusting the doping amount. The n+ type semiconductor layer 12 preferably includes a dopant. The dopant may be a known dopant. In the embodiment of the present disclosure, when the n+ type semiconductor layer 12 is mainly composed of a crystalline oxide semiconductor containing gallium, suitable examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium or niobium. In the embodiment of the present disclosure, the n-type dopant is preferably Sn, Ge or Si. In the composition of the semiconductor layer, the content of the dopant is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic %, and most preferably 0.00001 atomic % to 10 atomic %. In addition, the carrier density of the n+ type semiconductor layer is generally about 1×10 17 / cm 3 ~1×10 22 / cm 3 In the embodiments of the present disclosure, about 1×10 20 / cm 3 In the embodiment of the present disclosure, it is preferred to make 1×10 17 / cm 3 The above carrier density includes the dopant.

[0042] The n-type semiconductor layer 13 is located on the n+ type semiconductor layer 12. The upper surface of the n-type semiconductor layer 13 makes Schottky contact with the Schottky electrode 14. The n-type semiconductor layer 13 is an n-type semiconductor layer having a carrier density less than that of the n+ type semiconductor layer 12. The n-type semiconductor layer 13 is a layer in which a depletion layer extends when a reverse voltage is applied to the semiconductor device 10. The carrier density of the n-type semiconductor layer 13 is generally 1.0×10 14 / cm 3 ~1.0×10 17 / cm 3 within the range.

[0043] The thickness of the n-type semiconductor layer 13 may be 1 μm or less, or 1 μm or more, but in the embodiment of the present disclosure, it is preferably 3 μm or more. The area of ​​the n-type semiconductor layer 13 when viewed from above is not particularly limited, and may be 1 mm 2 Above, can also be 1mm 2 Below, but preferably 2mm 2 ~300cm 2 .

[0044] The n-type semiconductor layer 13 has a first region 13a and a second region 13b. In addition, the n-type semiconductor layer 13 may also have other regions. The second region 13b is an example of a second region or an impurity added region.

[0045] The upper surface of the first region 13a forms a Schottky junction with the Schottky electrode 14. The first region 13a is, for example, a region where the second region 13b is removed from the n-type semiconductor layer 13. Figure 1 As shown, the first region 13 a constitutes the lower surface of the n-type semiconductor layer 13 , a portion of the upper surface of the n-type semiconductor layer 13 , and a portion of the side surface of the n-type semiconductor layer 13 .

[0046] The first region 13a is a semiconductor region including a crystalline oxide semiconductor as a main component. The crystalline oxide semiconductor includes at least gallium, and most preferably α-Ga2O3 or a mixed crystal thereof. In addition, in the embodiment of the present disclosure, the crystalline oxide semiconductor as the main component of the n+ type semiconductor layer 12 and the crystalline oxide semiconductor as the main component of the first region 13a may be the same or different.

[0047] As the crystal structure of the crystalline oxide semiconductor included in the first region 13a, for example, a corundum structure, a β-gallia structure, a hexagonal structure (for example, an ε-type structure, etc.), a right-angle structure (for example, a κ-type structure, etc.), a cubic structure or a tetragonal structure, etc. can be listed. In the embodiment of the present disclosure, it is preferred that the crystalline oxide semiconductor has a corundum structure, a β-gallia structure or a hexagonal structure (for example, an ε-type structure, etc.), and more preferably has a corundum structure. In addition, the so-called "main component" means that, for example, when the crystalline oxide semiconductor is Ga2O3, Ga2O3 is included in the first region 13a at a ratio of 0.5 or more in the atomic ratio of gallium in all metal elements in the first region 13a. In the present disclosure, it is preferred that the atomic ratio of gallium in all metal elements in the first region 13a is 0.7 or more, and more preferably 0.9 or more. In the present embodiment, the first region 13a is a single crystal, but it can also be a polycrystalline.

[0048] The carrier density of the first region 13a is less than that of the n+ type semiconductor layer 12. The carrier density of the first region 13a can be appropriately set by adjusting the doping amount of the n-type semiconductor layer 13. A dopant may be included in the first region 13a. The dopant may be a well-known dopant. In the embodiment of the present disclosure, in particular, when the first region 13a is mainly composed of a crystalline oxide semiconductor containing gallium, suitable examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium or niobium. In the embodiment of the present disclosure, the n-type dopant is preferably Sn, Ge or Si. In the composition of the first region 13a, the content of the dopant is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic %, and most preferably 0.00001 atomic % to 10 atomic %. More specifically, the concentration of the dopant can generally be about 1×10 16 / cm 3 ~1×10 22 / cm 3 , and the concentration of the dopant can be set to about 1×10 17 / cm 3 In addition, the dopant in this specification refers to an element that realizes donor or acceptor.

[0049] The second region 13b is, for example, a region extending downward from a portion of the upper surface of the n-type semiconductor layer 13 to a depth of 1.0 μm or more in the n-type semiconductor layer 13. The depth may be 1.0 μm, but is preferably 1.2 μm or more or 1.5 μm or more. A portion of the second region 13b overlaps with the peripheral portion 33 of the n-type semiconductor layer 13 when viewed from above. The peripheral portion 33 is a region that is within a prescribed range from the side to the inside and the side of the n-type semiconductor layer 13. The prescribed range refers to, for example, a range that does not overlap with the lower surface of the Schottky electrode 14 when viewed from above. In addition, the upper surface of the second region 13b is an example of the upper end of the second region 13b. In the present embodiment, since the upper surface of the second region 13b is included in the upper surface of the n-type semiconductor layer 13, the depth of the second region 13b in the n-type semiconductor layer 13 can also be said to be the thickness of the second region 13b.

[0050] A portion of the upper surface of the second region 13b contacts a portion of the lower surface of the Schottky electrode 14. For example, a portion of the second region 13b overlaps with the periphery of the lower surface of the Schottky electrode 14 and a portion within a predetermined range from the periphery to the inside in a plan view. In addition, in the present embodiment, the second region 13b is continuous with the first region 13a, but another region may be provided between these regions. In addition, when the first region 13a and the second region 13b are continuous, there may be no clear boundary.

[0051] The second region 13b is preferably uninterrupted when viewed from above. The second region 13b may be, for example, ring-shaped, rectangular frame-shaped, or rod-shaped when viewed from above. In addition, the second region 13b may not be uninterrupted when viewed from above, and may be composed of multiple non-continuous regions. In this case, the second region 13b may be stripe-shaped, L-shaped, or dot-shaped when viewed from above.

[0052] The second region 13b is a region including an oxide as a main component. As the oxide, it is more preferred to include at least gallium, and most preferably Ga2O3 or a composite oxide of Ga2O3 and other metal oxides or a mixed crystal of Ga2O3 and other metal oxides. The oxide may be a crystalline oxide semiconductor, but it is preferred that the oxide is microcrystalline, and more preferably amorphous. It is preferred that the oxide includes amorphous or the oxide is amorphous. In addition, the crystalline semiconductor and the amorphous may also be mixed in the second region 13b.

[0053] When the oxide included as the main component in the second region 13b includes a crystalline oxide semiconductor, the crystal structure of the crystalline oxide can be, for example, a corundum structure, a β-gallia structure, a hexagonal structure (for example, an ε-type structure, etc.), a right-angle structure (for example, a κ-type structure, etc.), a cubic structure or a tetragonal structure, etc. In the embodiment of the present disclosure, it is preferred that the crystalline oxide semiconductor has a corundum structure, a β-gallia structure or a hexagonal structure (for example, an ε-type structure, etc.), and more preferably has a corundum structure. The crystal structure of the crystalline oxide semiconductor is the same as the crystal structure of the crystalline oxide semiconductor in the first region 13a. In addition, the so-called "main component" means that, for example, in the case where the oxide is Ga2O3, Ga2O3 is included in the second region 13b at a ratio of 0.5 or more in the atomic ratio of gallium among all metal elements in the second region 13b. In the present disclosure, the atomic ratio of gallium among all metal elements in the second region 13b is preferably 0.7 or more, and more preferably 0.9 or more.

[0054] In addition, the main component of the n-type semiconductor layer 13 may be a crystalline oxide semiconductor. The crystalline oxide semiconductor included in the n-type semiconductor layer 13 may be only the crystalline oxide semiconductor included in the first region 13a, or may be a combination of the crystalline oxide semiconductor included in the first region 13a and the crystalline oxide semiconductor included in the second region 13b. The so-called "main component" means that the crystalline oxide semiconductor preferably includes more than 50% of the total components of the n-type semiconductor layer 13, more preferably includes more than 70%, and further preferably includes more than 90%, and the content of the crystalline oxide semiconductor may also be 100%.

[0055] The carrier density of the second region 13b is less than that of the first region 13a. The second region 13b may include the same dopant as that of the first region 13a. The dopant may be a well-known dopant. In the embodiment of the present disclosure, as examples of the dopant, n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium or niobium may be listed. In the embodiment of the present disclosure, in the composition of the second region 13b, the content of the dopant may be greater than 0.00001 atomic %, for example, 0.00001 atomic % to 20 atomic % or 0.00001 atomic % to 10 atomic %. More specifically, the concentration of the dopant may be about 1×10 16 / cm 3 ~1×10 22 / cm 3 , and the concentration of the dopant can be set to about 1×10 17 / cm 3 The following low concentrations.

[0056] The second region 13b includes, in addition to the dopant, for example, ion-implanted impurities. The impurities are elements different from the element constituting the main component of the second region 13b, and the concentration thereof is generally 1.0×10 15 / cm 3 ~1.0×10 22 / cm s In addition, in the present disclosure, the word "impurity" is sometimes described as an impurity element. The elements included in the second region 13b other than the impurity element may be the same as the elements included in the first region 13a.

[0057] In the present disclosure, the impurity element may be a compound, for example, the impurity element is included in the second region 13b in the form of a monomer. A variety of elements may be selected as the impurities for ion implantation, but in the present embodiment, one element is selected. The impurities are preferably selected from elements that do not play a donor or acceptor role on gallium oxide. It is preferred that when ion implanting impurities, it is easier to adjust the amount of damage to the crystalline oxide semiconductor containing gallium. The main reasons for the change in the amount of damage include the mass number of the impurity element and the value of the injection energy. In the case where the mass number of the impurity element is too small, the ion-implanted impurities hardly cause damage to the area through which the impurities pass in the crystal with gallium oxide as the main component, so that the area that can cause damage is separated from the lower surface of the Schottky electrode 14, and the pressure resistance of the semiconductor device cannot be improved. In the case where the mass number of the impurity element is too large, crystal defects are excessively generated with the increase in the amount of damage, which may deteriorate the pressure resistance of the semiconductor device. In addition, the larger the mass number of the impurity element, the greater the required injection energy, resulting in load and structural constraints on the device for ion implantation, which is industrially disadvantageous.

[0058] The preferred impurity element is a metal element having a mass number greater than that of Mg, and more preferably aluminum (Al). The ion implantation may be a box profile or a simple profile. According to the present disclosure, even a simple profile can improve the withstand voltage of the semiconductor device.

[0059] The maximum value of the concentration of the impurity element included in the second region 13b is located at a depth of 1.0 μm or more from the upper surface of the n-type semiconductor layer 13 (see Examples 1 to 5 and Fig.16 , Fig.17 ). The maximum value of the concentration of the impurity element is greater than the maximum value of the impurity concentration included in the first region 13a. In the present disclosure, the concentration of the impurity element is sometimes referred to as the impurity concentration. For example, the maximum value of the impurity concentration is measured using secondary ion mass spectrometry (SIMS). In the present embodiment, for example, the depth is 2.0 μm or less. The maximum value of the impurity concentration is 1.0×10 17 / cm 3 In addition, the maximum value may be a peak value. In addition, in the embodiment of the present disclosure, it is preferred that the maximum value of the impurity concentration in the second region 13b is greater than the concentration of the dopant. The peak of the ion-implanted impurity may be located at the lower end of the second region 13b.

[0060] The maximum value of the concentration of the impurity element in the second region 13b is determined by secondary ion mass spectrometry (SIMS) as described above, but can also be determined or observed by known devices, data, analysis methods or analytical methods, such as transmission electron microscopy (TEM), energy dispersive X-ray spectroscopy (TEM-EDX), other secondary ion mass spectrometry methods (NanoSIMS) or numerical calculation codes (SRIM / TRIM).

[0061] In the present disclosure, a projection range indicating the depth of ion implantation into the n-type semiconductor layer 13 is defined as Rp, and a standard deviation is defined as ΔRp. Rp+ΔRp is, for example, greater than 1.1 μm.

[0062] The second region 13b may include, for example, crystal defects formed by ion implantation from the upper surface of the n-type semiconductor layer 13. For example, the crystal defects may be observed through a cross-sectional TEM (transmission electron microscope) image or a cross-sectional SEM (scanning electron microscope) image. The crystal defects may be observed in a state where a majority of them are diffused approximately equally in the second region 13b, or in a state where a majority of them are diffused in a planar or linear manner at the upper end or the lower end of the second region 13b.

[0063] In the present embodiment, for example, in an image showing a cross section perpendicular to the upper surface of the semiconductor layer, a crystal defect region 21 including crystal defects at a relatively high density is observed as a line, and the region including the crystal defect region 21 is the second region 13b. The crystal defect region 21 can also be observed as a high resistance region. It is sufficient that at least a portion of the second region 13b is the crystal defect region 21. In the present embodiment, for example, the depth of the lower end of the second region 13b from the upper surface of the n-type semiconductor layer 13 is deeper than the lower end of the crystal defect region 21. A portion of the second region 13b may not be observed in the image, for example, a portion from the lower end of the second region 13b to the upper side is not observed in the image.

[0064] The linear crystal defect region 21 in the present disclosure is observed as a two-dimensional region having a certain area. In the present embodiment, the linear crystal defect region 21 extends along the upper surface of the n-type semiconductor layer 13, that is, extends parallel to the upper surface of the n-type semiconductor layer 13. The crystal defect region 21 has a certain thickness, which is, for example, greater than 1.0 μm. The thickness may also be greater than 1.2 μm. In addition, the linear shape in the present embodiment may also be in other words, rod-shaped or ribbon-shaped, referred to as elongated. In addition, the crystal defect region 21 is, for example, in a straight line, but at least a portion may also be in a curved line.

[0065] For example, in an image showing a cross section perpendicular to the upper surface of the semiconductor layer, part of the crystal defect region 21 is located directly below the horizontal end of the Schottky electrode 14. It can be seen that part of the crystal defect region 21 and the Schottky electrode 14 share a common boundary.

[0066] The density of crystal defects in the crystal defect region 21 is, for example, 1.0×10 19 / cm 3 The density is more preferably 1.0×10 20 / cm 3 The density can be 1.0×10 18 / cm 3 More than to less than 1.0×10 20 / cm 3 In addition, the maximum value of the density is, for example, 1.0×10 21 / cm 3 The density of crystal defects in the first region 13a excluding the crystal defect region 21 is, for example, less than 1.0×10 18 / cm 3 , or less than 1.0×10 18 / cm 3 Small value.

[0067] The surface density of crystal defects in the second region 13 b of the n-type semiconductor layer 13 when viewed from above is, for example, 5×10 16 / cm 2 The surface density is more preferably 1×10 17 / cm 2 above.

[0068] The Schottky electrode 14 is arranged on the n-type semiconductor layer 13. The Schottky electrode 14 can form a Schottky junction with the n-type semiconductor layer 13. The constituent material of the Schottky electrode 14 can be a conductive inorganic material or a conductive organic material. In the embodiment of the present disclosure, the constituent material of the Schottky electrode 14 is preferably a metal. As the metal, for example, at least one metal selected from Groups 4 to 10 of the periodic table can be appropriately listed. As metals of Group 4 of the periodic table, for example, titanium (Ti), zirconium (Zr), hafnium (Hf), etc. can be listed. As metals of Group 5 of the periodic table, for example, vanadium (V), niobium (Nb), and tantalum (Ta) can be listed. As metals of Group 6 of the periodic table, for example, chromium (Cr), molybdenum (Mo) and tungsten (W) can be listed. As metals of Group 7 of the periodic table, for example, manganese (Mn), technetium (Tc), and rhenium (Re) can be listed. As metals of Group 8 of the periodic table, for example, iron (Fe), ruthenium (Ru), and osmium (Os) can be listed. As metals of Group 9 of the periodic table, for example, cobalt (Co), rhodium (Rh), and iridium (Ir) can be listed. As metals of Group 10 of the periodic table, for example, nickel (Ni), palladium (Pd), and platinum (Pt) can be listed. The thickness of the Schottky electrode is not particularly limited, preferably 0.1nm to 10μm, more preferably 5nm to 500nm, and most preferably 10nm to 200nm. In an embodiment of the present disclosure, the Schottky electrode 14 may include a first electrode layer disposed on the n-type semiconductor layer 13 and a second electrode layer disposed on the first electrode layer. In addition, in an embodiment of the present invention, it is preferred that the thickness of the first electrode layer is thinner than the thickness of the second electrode layer. In addition, in an embodiment of the present disclosure, it is preferred that the work function of the first electrode layer is greater than the work function of the second electrode layer. By setting the first electrode layer to such a preferred structure, not only a semiconductor device with better Schottky characteristics can be obtained, but also the effect of improving the reverse withstand voltage can be better demonstrated. In addition, in the embodiment of the present disclosure, the Schottky electrode 14 may be a single layer, or may be composed of two or more metal layers.

[0069] According to such a structure, the withstand voltage can be improved without using a p-type semiconductor region. In addition, according to such a structure, the electric field concentration at the outer peripheral end of the Schottky electrode 14 can be alleviated.

[0070] Below, refer to Figure 1 and Figure 2 , an example of a method for manufacturing the semiconductor device 10 is described. Figure 2 This is a flowchart showing an example of a method for manufacturing a semiconductor device according to the present disclosure.

[0071] like Figure 2As shown, the manufacturing method of the semiconductor device 10 includes, for example: step S1, stacking an n-type semiconductor layer 13 on a substrate 15; step S2, stacking an n+ type semiconductor layer 12 on the n-type semiconductor layer 13; step S3, stacking an ohmic electrode 11 on the n+ type semiconductor layer 12; step S4, bonding a supporting substrate to the ohmic electrode 11; step S5, removing the substrate 15 from the n-type semiconductor layer 13; step S6, forming a second region 13b on the n-type semiconductor layer 13; and step S7, stacking a Schottky electrode 14 on the n-type semiconductor layer 13.

[0072] In step S1, the n-type semiconductor layer 13 is stacked on the substrate 15 by, for example, a mist CVD method. In addition, the n-type semiconductor layer 13 can also be stacked on the substrate 15 by a known method. As a method for forming the n-type semiconductor layer 13, in addition to the mist CVD method, for example, CVD method, MOCVD method, MOVPE method, mist epitaxy method, MBE method, HVPE method, pulse growth method or ALD method can be cited. In the embodiment of the present disclosure, the method for forming the n-type semiconductor layer 13 is preferably a mist CVD method or a mist epitaxy method. In the atomized CVD method or the atomized epitaxial method, for example, the raw material solution is atomized (atomization process) to make the droplets float, and after atomization, the obtained atomized droplets are transported to a substrate by a carrier gas (transportation process), and then the atomized droplets are thermally reacted near the substrate to stack a semiconductor film including a crystalline oxide semiconductor as a main component on a substrate 15 (film formation process), thereby forming an n-type semiconductor layer 13.

[0073] The substrate 15 is, for example, a plate-shaped sapphire substrate. The substrate 15 only needs to be a substrate that can support a semiconductor film. The substrate 15 can be an insulating substrate, a semiconductor substrate, a metal substrate, or a conductive substrate, but the substrate 15 is preferably an insulating substrate, and is also preferably a substrate having a metal film on the surface. As the substrate 15, for example, a base substrate including a substrate material having a corundum structure as a main component, a base substrate including a substrate material having a β-gallia structure as a main component, or a base substrate including a substrate material having a hexagonal crystal structure as a main component can be listed. Here, the so-called "main component" means that relative to the total components of the substrate material, in terms of atomic ratio, preferably including more than 50% of the substrate material having a specific crystal structure, more preferably including more than 70%, and further preferably including more than 90%, and the content of the substrate material having a specific crystal structure can also be 100%.

[0074] The substrate material can be a known material. As the substrate material having a corundum structure, for example, α-Al2O3 (sapphire substrate) or α-Ga2O3 can be appropriately listed. As more appropriate examples, a-plane sapphire substrate, m-plane sapphire substrate, r-plane sapphire substrate, c-plane sapphire substrate, α-type gallium oxide substrate (a-plane, m-plane or r-plane) can be listed. As a base substrate with a substrate material having a β-gallia structure as the main component, for example, a β-Ga2O3 substrate, or a mixed crystal substrate including Ga2O3 and Al2O3 and Al2O3 more than 0wt% and less than 60wt% can be listed. In addition, as a base substrate with a substrate material having a hexagonal structure as the main component, for example, a SiC substrate, a ZnO substrate, a GaN substrate, etc. can be listed.

[0075] In step S2, the n+ type semiconductor layer 12 is stacked on the n- type semiconductor layer 13, for example, by an atomized CVD method. The n+ type semiconductor layer 12 can be stacked in the same way as the n- type semiconductor layer 13. In addition, the n+ type semiconductor layer 12 can also be stacked on the substrate 15 by a known method in the same way as the n- type semiconductor layer 13. In the embodiment of the present disclosure, the method for forming the n+ type semiconductor layer 12 is preferably an atomized CVD method or an atomized epitaxial method. In the atomized CVD method or the atomized epitaxial method, for example, a raw material solution is atomized (atomization process) to float droplets, and after atomization, the obtained atomized droplets are transported to a substrate by a carrier gas (transportation process), and then the atomized droplets are thermally reacted near the substrate to stack a semiconductor film including a crystalline oxide semiconductor as a main component on the n- type semiconductor layer 13 (film formation process), thereby forming the n+ type semiconductor layer 12.

[0076] In step S3, an ohmic electrode 11 is stacked on the n+ type semiconductor layer 12. The method for forming the ohmic electrode 11 may be a known method. As the method for forming the ohmic electrode 11, for example, a dry method or a wet method may be cited. As the dry method, for example, sputtering, vacuum evaporation, CVD, etc. may be cited. As the wet method, for example, screen printing or die coating may be cited.

[0077] In step S4, a support substrate is bonded to the ohmic electrode 11. In addition, the support substrate can use a known substrate. The support substrate is, for example, a metal support substrate. In addition, a known conductive adhesive layer is used to bond the support substrate and the ohmic electrode 11. The conductive adhesive layer is, for example, an Ag sintered layer.

[0078] In step S5, the substrate 15 is removed from the n-type semiconductor layer 13. At this time, a known method of peeling the n-type semiconductor layer 13 from the substrate 15 is used.

[0079] In step S6, the second region 13b is formed on the n-type semiconductor layer 13. In step S6, an impurity element is ion-implanted into the n-type semiconductor layer 13 from the upper surface of the n-type semiconductor layer 13 to a depth of 1.0 μm or more. The element to be ion-implanted is, for example, Al. At this time, the implantation energy is, for example, 1500 to 3000 keV. The dose of Al is, for example, 1.0×10 13 atoms / cm 2 ~4.0×10 14 atoms / cm 2 The implantation beam current is, for example, 140 to 260 nA. The implantation time is, for example, 83.0 to 253.0 sec. The device used is, for example, a device with a maximum implantation energy of 8 MeV. In addition, the element implanted by ion implantation may not be Al, but an element with a mass number greater than that of Mg may be used.

[0080] In the present embodiment, the region where the ions are implanted and the region where the ion-implanted elements pass in the n-type semiconductor layer 13 is the second region 13b. The region other than the region where the ions are implanted and the region where the ion-implanted elements pass in the n-type semiconductor layer 13 is the first region 13a. In step S6, the maximum value of the concentration of the impurity element included in the second region 13b is made greater than the maximum value of the concentration of the impurity element included in the first region 13a. In step S6, the linear crystal defect region 21 observed in the cross section perpendicular to the upper surface of the n-type semiconductor layer 13 is formed in the second region 13b.

[0081] For example, Fig.17 As shown in FIG. 1 , when the concentration of the impurity element varies at a depth from the upper surface of the n-type semiconductor layer 13, it is understood that the second region 13b is included. In particular, Fig.17 As shown in FIG. 1 , when the distribution of impurities has a local maximum (peak), the depth at which the slope of the distribution is substantially 0 at a position deeper than the local maximum can be appropriately set as the boundary between the lower end of the second region 13b and the upper end of the first region 13a. On the other hand, when the distribution of impurities such as a box-shaped distribution does not have a local maximum, the depth at which the slope of the distribution is substantially 0 at a position deeper than the maximum can also be appropriately set as the boundary between the lower end of the second region 13b and the upper end of the first region 13a.

[0082] In step S7, a Schottky electrode 14 is stacked on the n-type semiconductor layer 13. The method for forming the Schottky electrode 14 may be a known method. As the method for forming the Schottky electrode 14, for example, a dry method or a wet method may be listed. As a dry method, for example, sputtering, vacuum evaporation, CVD, etc. may be listed. As a wet method, for example, screen printing or die coating may be listed. In the case where a material including a crystalline oxide semiconductor (for example, α-Ga2O3) of a metastable phase is used as the n-type semiconductor layer 13, in step S7, no matter which formation method is used, the n-type semiconductor layer 13 can be kept at a temperature of less than 800°C. In addition, from step S6 of forming the second region 13b to step S7 of forming the Schottky electrode 14, the temperature of the n-type semiconductor layer 13 is less than 800°C. When α-Ga2O3 is used as the n-type semiconductor layer 13, the temperature is preferably less than 600°C. In the present embodiment, the Schottky electrode 14 is formed without performing a process for activating the ion-implanted impurity element.

[0083] According to such a manufacturing method, it is possible to manufacture a semiconductor device 10 that can improve voltage resistance without using a p-type semiconductor region and can alleviate electric field concentration at the peripheral end of the Schottky electrode 14. In addition, according to such a manufacturing method, it is also possible to manufacture a semiconductor device 10 having a first region 13a including a crystalline oxide semiconductor having a corundum structure as a main component.

[0084] (Second Embodiment)

[0085] Figure 3 2 is a schematic cross-sectional view illustrating a semiconductor device 210 according to the second embodiment. The semiconductor device 210 is a Schottky barrier diode (SBD) having an insulating layer 204. Figure 1 The difference between the SBD of the present invention is that the end of the Schottky electrode 14 is located on the insulator layer 204. By making such a structure, the withstand voltage characteristics of the semiconductor device can be made better. The constituent material of the insulator layer 204 can be a known material. The constituent material of the insulator layer 204 can include, for example, SiO2 film, phosphorus-added SiO2 film (PSG film), boron-added SiO2 film, and phosphorus-added boron SiO2 film (BPSG film). The method for forming the insulator layer 204 can be a known method. The method for forming the insulator layer 204 can include, for example, a method of forming a film by vacuum evaporation, CVD, sputtering, various coating techniques, and then patterning by photolithography, or a method of directly patterning using printing technology, etc.

[0086] (Third Embodiment)

[0087] Figure 4is a schematic cross-sectional view illustrating a semiconductor device 310 according to the third embodiment. The semiconductor device 310 is a device having a Figure 1 The second region 13b shown in FIG. 1 is a Schottky barrier diode (SBD) of a second region 313 having a different shape from the second region 13b. The second region 313 has a region 313a located on the inner side of the n-type semiconductor layer 13 in the horizontal direction and a region 313b located on the outer side of the n-type semiconductor layer 13 in the horizontal direction than the region 313a. The region 313a is formed from the upper surface of the n-type semiconductor layer 13 to a depth position in the n-type semiconductor layer 13 that is closer to the region 313b. The region 313b is formed, for example, at the peripheral portion of the n-type semiconductor layer 13 excluding the outer peripheral end of the n-type semiconductor layer 13. The region 313b overlaps with the outer peripheral end of the Schottky electrode 14 when viewed from above, for example. The region 313a and the region 313b are formed by ion implantation as in the second region 13b.

[0088] (Fourth Embodiment)

[0089] Figure 5 4 is a schematic cross-sectional view illustrating a semiconductor device 410 according to the fourth embodiment. The semiconductor device 410 is a semiconductor device that replaces Figure 1 The second region 13b shown in the figure has a Schottky barrier diode (SBD) having a second region 413. The second region 413 has a region 413a arranged at a position overlapping with the periphery of the Schottky electrode 14 when viewed from above, and a region 413b arranged at a position overlapping with the outer peripheral end of the n-type semiconductor layer 13 when viewed from above. The region 413a and the region 413b are arranged to be discontinuous and separated from each other. The region 413a and the region 413b can be formed by ion implantation in the same manner as the second region 13b. With such a structure, the voltage resistance can also be improved without using a p-type semiconductor region. In addition, with such a structure, the electric field concentration at the outer peripheral end of the Schottky electrode 14 can also be alleviated.

[0090] (Fifth Embodiment)

[0091] Figure 6 1 is a schematic cross-sectional view illustrating a semiconductor device 510 according to the fifth embodiment. The semiconductor device 510 is a semiconductor device that replaces Figure 1 The semiconductor device 510 has a drain electrode 511, an n+ type semiconductor layer 512, an n- type semiconductor layer (drift layer) 513, a gate insulating film 515, a gate electrode 516 and a source electrode 517.

[0092] exist Figure 6In the MOSFET, an n+ type semiconductor layer 512 and an n− type semiconductor layer 513 are sequentially stacked on a drain electrode 511 .

[0093] The n-type semiconductor layer 513 includes a first region 513a, a second region 513b, an oxide semiconductor layer 518a and an oxide semiconductor layer 518b which are p-well layers disposed on the upper portion. Figure 6 The MOSFET further includes an n+-type oxide semiconductor layer 519 in the p-type oxide semiconductor layer 518 a.

[0094] The first region 513a is a region of the n-type semiconductor layer 513 excluding the second region 513b and the oxide semiconductor layers 518 and 519. The upper surface of the first region 513a is in contact with the lower surface of the source electrode 517. The first region 513a includes the crystalline oxide semiconductor described in the first region 13a.

[0095] The second region 513b is arranged on the side of the n-type semiconductor layer 513. The second region 513b overlaps with the peripheral portion 533 of the n-type semiconductor layer 513 when viewed from above. The peripheral portion 533 is a region within a predetermined range from the side to the inside with the side of the n-type semiconductor layer 513. The predetermined range refers to, for example, a range that does not overlap with the oxide semiconductor layer 518 when viewed from above.

[0096] At least a portion of the upper surface of the second region 513b is in contact with a portion of the lower surface of the source electrode 517. For example, a portion of the second region 513b overlaps with the periphery of the lower surface of the source electrode 517 and a portion within a predetermined range from the periphery to the inside when viewed from above. The lower surface of the second region 513b is, for example, located above the lower surface of the n-type semiconductor layer 513 and is separated from the upper surface of the n+ type semiconductor layer 512 without contact. In addition, the second region 513b includes the oxide described in the second region 13b.

[0097] A gate electrode 516 is provided over the oxide semiconductor layer 518a via a gate insulating film 515. In addition, a source electrode 517 is provided so as to be in contact with the n + -type oxide semiconductor layer 519 and the oxide semiconductor layer 518b.

[0098] In addition, Figure 6 In the MOSFET, the oxide semiconductor layer 518a and the n-type semiconductor layer 513 form a main junction. Figure 6 The MOSFET of is a MOSFET with a built-in diode, and has a parasitic PN junction composed of the p-type oxide semiconductor layer 518a and the n-type semiconductor layer 513 and a built-in Schottky barrier diode (SBD) composed of the source electrode 517 and the n-type semiconductor layer 513. Figure 6When the MOSFET is turned on, a gate voltage higher than the threshold voltage is applied, and a groove is formed in the range of the p-type oxide semiconductor layer 518a that is connected to the gate electrode 516 through the gate insulating film 515, and current flows from the drain electrode 511 to the source electrode 517. In addition, when it is turned off, the applied voltage between the drain electrode and the source electrode is blocked by the PN junction constructed between the p-type oxide semiconductor layer 518a and the n-type semiconductor layer 513. When a positive voltage relative to the drain electrode 511 is applied to the source electrode 517, current flows through the built-in SBD. When an excess current flows, holes can be injected from the p-type oxide semiconductor layer (p-well layer) 518, so that a large current can flow with a low conduction voltage in a bipolar mode. In addition, when a negative voltage relative to the drain electrode 511 is applied to the source electrode 517, the applied voltage between the drain electrode and the source electrode is blocked by the parasitic PN junction and the built-in SBD. In addition, with regard to Figure 6 Although the planar gate type MOSFET is described as an example, in the embodiment of the present invention, Figure 6 The MOSFET can also be of the trench gate type.

[0099] exist Figure 6 In the MOSFET, the bottom surface of the p-type oxide semiconductor layer 518a is located closer to the n-type oxide semiconductor layer (n-type semiconductor layer 513, n+-type semiconductor layer 512) in the stacking direction of the semiconductor device (the up-down direction in the figure) than the bottom surface of the p-type oxide semiconductor layer 518b. By making such a structure, even if, for example, the band gap of the p-type oxide semiconductor layer 518b is smaller than the band gap of the p-type oxide semiconductor layer 518a, avalanche suppression when a reverse bias is applied to the PN junction constructed between the p-type oxide semiconductor layer 518a and the n-type semiconductor layer 513 can be better prevented, and excellent semiconductor characteristics can be exhibited.

[0100] In addition, the hole carrier density of the p-type oxide semiconductor layer 518b is preferably greater than the hole carrier density of the p-type oxide semiconductor layer 518a. By setting the hole carrier density to such a preferred range, when excess current flows through the built-in Schottky barrier diode, holes can be injected from the p-type oxide semiconductor layer 518b, thereby allowing a large current to flow with a low on-voltage in a bipolar mode. In addition, the ohmic contact resistance with the source electrode 517 can be reduced, and the avalanche current at the time of shutdown can be escaped to the outside of the element to prevent element damage.

[0101] Furthermore, a plurality of embodiments of the present disclosure described above may be combined, or some structural elements may be applied to other embodiments, and such embodiments also belong to the embodiments of the present disclosure.

[0102] (Application Examples of Semiconductor Devices 10, 210, 310, 410, and 510)

[0103] The semiconductor device involved in the above-mentioned embodiment of the present invention can be applied to power conversion devices such as inverters and converters to achieve the above-mentioned functions. More specifically, it can be applied as a diode built into the inverter and converter, a thyristor as a switching element, a power transistor, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), etc. Figure 7 is a block diagram showing an example of a control system using a semiconductor device according to an embodiment of the present invention. Figure 8 This is a circuit diagram of the control system, and is particularly suitable for a control system installed in an electric vehicle.

[0104] like Figure 7 As shown, the control system 500 includes a battery (power source) 501, a boost converter 502, a buck converter 503, an inverter 504, a motor (driven object) 505, and a drive control unit 506, which are mounted on an electric vehicle. The battery 501 is composed of a storage battery such as a nickel-hydrogen battery and a lithium-ion battery, and can store power through charging at a power supply station or regenerative energy during deceleration, and can output a DC voltage required for the operation of the driving system and electrical system of the electric vehicle. The boost converter 502 is, for example, a voltage conversion device equipped with a chopper circuit, and can boost a DC voltage of, for example, 200V supplied from the battery 501 to, for example, 650V through the switching operation of the chopper circuit, and output it to the driving system such as the motor. The buck converter 503 is also a voltage conversion device equipped with a chopper circuit, but can output the DC voltage of, for example, 200V supplied from the battery 501 to, for example, about 12V, and then output it to the electric window and electric steering system or the electrical system including the on-board electrical equipment.

[0105] The inverter 504 converts the DC voltage supplied from the boost converter 502 into a three-phase AC voltage by switching operation and outputs it to the motor 505. The motor 505 is a three-phase AC motor constituting the driving system of the electric vehicle, and is rotationally driven by the three-phase AC voltage output from the inverter 504, and its rotational driving force is transmitted to the wheels of the electric vehicle through a transmission, etc., not shown.

[0106] On the other hand, various sensors not shown are used to measure the measured values ​​of the rotation speed and torque of the wheels, the amount of stepping on the accelerator pedal (acceleration), etc. from the electric vehicle in motion, and these stepping on amount signals are input to the drive control unit 506. In addition, the output voltage value of the inverter 504 is also input to the drive control unit 506 at the same time. The drive control unit 506 has the function of a controller having a computing unit such as a CPU (Central Processing Unit) and a data storage unit such as a memory, so that a control signal is generated by using the input measurement signal, and it is output to the inverter 504 as a feedback signal, thereby controlling the switching operation of the switching element. Thus, the AC voltage provided by the inverter 504 to the motor 505 can be corrected in real time, so that the operation control of the electric vehicle can be correctly performed, and the safe and comfortable operation of the electric vehicle can be achieved. In addition, the voltage output to the inverter 504 can also be controlled by providing the feedback signal from the drive control unit 506 to the boost converter 502.

[0107] Figure 8 It means to remove Figure 7 The circuit structure after the buck converter 503 in the figure is a circuit structure that only shows the structure for driving the motor 505. As shown in the figure, the semiconductor device of the present invention is used in the boost converter 502 and the inverter 504 as a Schottky barrier diode, so as to provide switching control. In the boost converter 502, it is inserted in the chopper circuit to perform chopper control, and in the inverter 504, it is inserted in the switching circuit including the IGBT to perform switching control. In addition, the current is stabilized by installing an inductor (coil, etc.) at the output end of the battery 501, and the voltage is stabilized by installing a capacitor (electrolytic capacitor, etc.) between the battery 501, the boost converter 502, and the inverter 504.

[0108] In addition, as in Figure 8 As shown by the dotted line in the figure, a calculation unit 507 composed of a CPU (Central Processing Unit) and a storage unit 508 composed of a non-volatile memory are provided in the drive control unit 506. The signal input to the drive control unit 506 is provided to the calculation unit 507, and a feedback signal to each semiconductor element is generated by performing the required calculation. In addition, the storage unit 508 temporarily holds the calculation results of the calculation unit 507, accumulates the physical constants and functions required for the drive control in a table form, and outputs them to the calculation unit 507 as appropriate. The calculation unit 507 and the storage unit 508 can adopt a known structure, and their processing capabilities can also be arbitrarily selected.

[0109] like Figure 7 or Figure 8As shown, in the control system 500, diodes and thyristors, power transistors, IGBTs, MOSFETs, etc. as switching elements are used for the switching operations of the boost converter 502, the buck converter 503, and the inverter 504. By using gallium oxide (Ga2O3), especially corundum gallium oxide (α-Ga2O3) as its material in these semiconductor elements, the switching characteristics are greatly improved. Furthermore, by applying the semiconductor device involved in the present invention, etc., extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 500 can be achieved. That is, the boost converter 502, the buck converter 503, and the inverter 504 can each expect the effect of the present invention, and any one of them, or a combination of any two or more, or a form that also includes a drive control unit 506 can expect the effect of the present invention.

[0110] Furthermore, the control system 500 can be applied not only to the semiconductor device of the present invention in the control system of an electric vehicle, but also to control systems for all purposes such as stepping up and down the power from a DC power source or converting power from DC to AC. In addition, a power source such as a solar cell can also be used as a battery.

[0111] Fig. 9 is a block diagram showing another example of a control system using a semiconductor device according to an embodiment of the present invention. Fig.10 This is a circuit diagram of the control system, which is suitable for being installed in infrastructure equipment and home appliances operated by power from an AC power source.

[0112] like Fig. 9As shown, the control system 600 is used to input power supplied from the outside, such as a three-phase AC power supply (power supply) 601, and has an AC / DC converter 602, an inverter 604, a motor (driven object) 605 and a drive control unit 606, which can be mounted on various devices (described later). The three-phase AC power supply 601 is, for example, a power generation facility (thermal power plant, hydroelectric power plant, geothermal power plant, atomic power plant, etc.) of an electric power company, and its output is supplied as an AC voltage while being stepped down by a substation. In addition, the three-phase AC power supply 601 is also installed in a building and nearby facilities in the form of a private generator, and is supplied with power through a cable. The AC / DC converter 602 is a voltage conversion device that converts an AC voltage into a DC voltage, and is used to convert an AC voltage of 100V or 200V supplied from the three-phase AC power supply 601 into a specified DC voltage. Specifically, it is converted into a commonly used desired DC voltage such as 3.3V, 5V or 12V by voltage conversion. In the case where the driven object is a motor, it is converted to 12V, for example. In addition, a single-phase AC power supply may be used instead of a three-phase AC power supply. In this case, if the AC / DC converter is set to a single-phase input, the same system configuration can be configured.

[0113] The inverter 604 converts the DC voltage supplied from the AC / DC converter 602 into a three-phase AC voltage by switching operation and outputs it to the motor 605. The motor 604 has a different form depending on the control object, but it is a three-phase AC motor that drives wheels when the control object is a train, drives pumps and various power sources when the control object is factory equipment, and drives compressors and the like when the control object is a household appliance. The motor 604 is rotationally driven by the three-phase AC voltage output from the inverter 604, and its rotational driving force is transmitted to a driving object not shown.

[0114] In addition, for example, in household appliances, there are many driving objects that can directly receive the DC voltage output from the AC / DC converter 602 (such as personal computers, LED lighting equipment, video equipment, audio equipment, etc.). In this case, the control system 600 does not need the inverter 604. Fig. 9 As shown, a DC voltage is supplied to the driven object from the AC / DC converter 602. In this case, for example, a 3.3V DC voltage is supplied to a personal computer or the like, and a 5V DC voltage is supplied to an LED lighting device or the like.

[0115] On the other hand, various sensors not shown in the figure are used to measure the measured values ​​of the rotation speed and torque of the driven object or the temperature and flow rate of the surrounding environment of the driven object, and these measurement signals are input to the drive control unit 606. In addition, the output voltage value of the inverter 604 is also input to the drive control unit 606 at the same time. Based on these measurement signals, the drive control unit 606 provides a feedback signal to the inverter 604 to control the switching action of the switching element. Thus, the AC voltage provided by the inverter 604 to the motor 605 can be corrected in real time, so that the operation control of the driven object can be correctly performed, and the stable operation of the driven object can be achieved. In addition, as mentioned above, in the case where the driven object can be driven by a DC voltage, the feedback to the inverter can also be replaced to perform feedback control on the AC / DC converter 602.

[0116] Fig.10 To express Fig. 9 FIG. 1 is a diagram showing an example of a circuit structure of a device. As shown in the figure, the semiconductor device of the present invention is used in an AC / DC converter 602 and an inverter 604 as, for example, a Schottky barrier diode, thereby providing switching control. As the AC / DC converter 602, a converter is used in which, for example, a circuit of a Schottky barrier diode is configured in a bridge shape, and a DC conversion is performed by converting and rectifying the negative voltage portion of the input voltage into a positive voltage. In addition, in the inverter 604, a switching control is performed by inserting an IGBT in the switching circuit. In addition, a capacitor (electrolytic capacitor, etc.) is installed between the AC / DC converter 602 and the inverter 604 to stabilize the voltage.

[0117] In addition, as in Fig.10 As shown by the dotted line in the figure, a calculation unit 607 composed of a CPU and a storage unit 608 composed of a non-volatile memory are provided in the drive control unit 606. The signal input to the drive control unit 606 is provided to the calculation unit 607, and a feedback signal to each semiconductor element is generated by performing the required calculation. In addition, the storage unit 608 temporarily holds the calculation results of the calculation unit 607, accumulates the physical constants and functions required for the drive control in a table form, and outputs them to the calculation unit 607 as appropriate. The calculation unit 607 and the storage unit 608 can adopt a known structure, and their processing capabilities can also be arbitrarily selected.

[0118] In such a control system 600, Figure 7 and Figure 8Similarly, the control system 500 shown uses diodes and thyristors, power transistors, IGBTs, MOSFETs, etc. as switching elements for the rectification operation and switching operation of the AC / DC converter 602 and the inverter 604. By using gallium oxide (Ga2O3), especially corundum gallium oxide (α-Ga2O3) as its material in these semiconductor elements, the switching characteristics are improved. Furthermore, by applying the semiconductor film and semiconductor device involved in the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 600 can be achieved. That is, the AC / DC converter 602 and the inverter 604 can each expect the effect of the present invention, and any one or combination of them, or the form that also includes the drive control unit 606 can expect the effect of the present invention.

[0119] In addition, Fig. 9 and Fig.10 In the example of the driven object, the motor 605 is shown as the driven object, but the driven object is not necessarily limited to the object operated mechanically, and many devices requiring AC voltage can be used as the object. For the control system 600, as long as the power is input from the AC power supply to drive the driven object, it can be applied, and can be installed for driving and controlling such devices as basic equipment (such as power equipment in buildings and factories, communication equipment, traffic control equipment, water treatment equipment, system equipment, labor-saving equipment, trams, etc.) and household appliances (such as refrigerators, washing machines, personal computers, LED lighting equipment, video equipment, audio equipment, etc.).

[0120] (Other Modifications)

[0121] When each crystalline oxide semiconductor and / or each oxide is a mixed crystal, they can be mixed with indium and aluminum separately or in combination to form a mixed crystal to control the band gap. Such a mixed crystal structure is an extremely attractive material system for InAlGaO-based semiconductors. Here, InAlGaO-based semiconductors refer to InAlGaO-based semiconductors. X Al Y Ga Z O3 (0≤X≤2, 0≤Y≤2, 0≤Z≤2, X+Y+Z=1.5~2.5) can be regarded as the same material system containing gallium oxide.

[0122] In the above-mentioned embodiment, the impurity is defined as an element different from the element constituting the main component of the second region 13b, 313, 413, 513b, but when the dopant concentrations of the first region 13a and the second region 13b, 313, 413, 513b are the same, the impurity may be defined as an element whose concentration in the second region 13b, 313, 413, 513b is higher than that in the first region 13a. For example, the crystalline oxide semiconductor included as the main component in the first region 13a and the oxide included as the main component in the second region 13b, 313, 413, 513b may be a mixed crystal of gallium and aluminum, and the impurity may be aluminum. In this case, with respect to the concentration of aluminum, the concentration in the second region 13b, 313, 413, 513b is higher than that in the first region 13a.

[0123] The second region 13b, 313, 413, 513b may overlap only a portion of the periphery of the Schottky electrode 14 when viewed from above. In addition, the second region 13b may overlap the inner side of the n-type semiconductor layer 13 without overlapping the outer peripheral end when viewed from above. The second region 13b may overlap the outer peripheral end of the n-type semiconductor layer 13 and not overlap the outer peripheral end of the Schottky electrode 14 when viewed from above. Similarly, either the region 413a or 413b may not be provided.

[0124] The second region 13b, 313, 413, 513b is entirely located inside each n-type semiconductor layer 13, 513, and a portion thereof may not be exposed from the n-type semiconductor layer 13, 513. The thickness of the second region 13b, 313, 413, 513b may be 1.0 μm or more, for example, 1.5 μm or more.

[0125] As long as the semiconductor device involved in the present disclosure can be manufactured, the order of each process may be different from the order of the above-mentioned embodiment. In the above-mentioned embodiment, the ohmic electrode 11 is formed before the Schottky electrode 14 is formed, but the Schottky electrode 14 may be formed before the ohmic electrode 11 is formed. At this time, in the process of forming the ohmic electrode 11, the temperature of the n-type semiconductor layer 13 is less than 800°C. In addition, the position of the components such as the substrate removed during the manufacturing process may be different for the semiconductor layers 12 and 13. For example, the semiconductor device involved in the present disclosure can be manufactured by the following sequence and method: that is, stacking an n+ type semiconductor layer 12 on a substrate 15, stacking an n- type semiconductor layer 13 on the n+ type semiconductor layer 12, removing the substrate 15 from the n+ type semiconductor layer 12 (a variant of process S5), stacking an ohmic electrode 11 on the n+ type semiconductor layer 12 (process S3), bonding a supporting substrate to the ohmic electrode 11 (process S4), forming a second region 13b on the n- type semiconductor layer 13 (process S6), and stacking a Schottky electrode 14 on the n- type semiconductor layer 13 (process S7). The semiconductor device involved in the present disclosure can also be manufactured by the following sequence and method: that is, stacking an n+ type semiconductor layer 12 on a substrate 15, stacking an n- type semiconductor layer 13 on the n+ type semiconductor layer 12, forming a second region 13b on the n- type semiconductor layer 13 (process S6), removing the substrate 15 from the n+ type semiconductor layer 12 (a variation of process S5), stacking an ohmic electrode 11 on the n+ type semiconductor layer 12 (process S3), bonding a supporting substrate to the ohmic electrode 11 (process S4), and stacking a Schottky electrode 14 on the n- type semiconductor layer 13 (process S7).

[0126] In addition, in an embodiment of the present disclosure, the semiconductor film may be directly disposed on the substrate or the substrate, or the semiconductor film may be disposed across other layers such as a stress relief layer (e.g., a buffer layer, an ELO layer, etc.), a stripping sacrificial layer, etc. The formation method of each layer is not particularly limited, and may be a known method, but in an embodiment of the present invention, an atomized CVD method is preferred. In an embodiment of the present disclosure, the semiconductor film may be used as the semiconductor layer for a semiconductor device after a known method such as stripping from the substrate, etc. is adopted for the semiconductor film, or the semiconductor film may be directly used as the semiconductor layer for a semiconductor device.

[0127] In addition, an additional semiconductor layer may be provided between the n-type semiconductor layer 13 and the Schottky electrode 14. In this case, the additional semiconductor layer is stacked after the second region 13b is provided on the n-type semiconductor layer 13.

[0128] In an embodiment of the present disclosure, an annealing treatment may be performed after the film forming process. The annealing treatment temperature is, for example, 300°C to 650°C, preferably 350°C to 550°C. In addition, the annealing treatment time is, for example, 1 minute to 48 hours, preferably 10 minutes to 24 hours, and more preferably 30 minutes to 12 hours. In addition, the annealing treatment may be performed in any atmosphere. It may be in a non-oxygen atmosphere or in an oxygen atmosphere. As the non-oxygen atmosphere, for example, an inert gas atmosphere (for example, a nitrogen atmosphere) or a reducing gas atmosphere may be listed, but in an embodiment of the present disclosure, it is preferably an inert gas atmosphere, and more preferably a nitrogen atmosphere.

[0129] Example

[0130] Below, Example 1 and Comparative Example 1 are listed and referred to Figure 1 and Fig.11 The semiconductor device of the present disclosure is described. Fig.11 Graph showing the relationship between voltage (V) and current (A) when a reverse voltage is applied to the semiconductor devices in Example 1 and Comparative Example 1. Fig.11 In the figure, the horizontal axis represents the magnitude of the voltage (V) when the reverse voltage is applied, and the absolute value of the voltage (V) increases from the right side to the left side. Fig.11 In the figure, the vertical axis represents the magnitude of the value of the current (A), and the current value increases from the lower side to the upper side.

[0131] Produced by the manufacturing method of embodiment 1 Figure 1 The semiconductor device shown in the figure is referred to as Example 1. In Example 1, Al element is implanted as an impurity at an implantation energy of 2000 keV and 3.0×10 13 atoms / cm 2 Ions were implanted into the n-type semiconductor layer 13 with a dose of 100 MeV. In Example 1, an apparatus with a maximum implantation energy of 8 MeV was used. A semiconductor device was fabricated in the same manner as in Embodiment 1 except that the second region 13 b was not provided, and this was used as Comparative Example 1.

[0132] The reverse voltage in each semiconductor device obtained was evaluated. The evaluation was performed by applying a reverse voltage of 0 to 1200 V to each semiconductor device obtained, stopping the application of the reverse voltage when a current of 0.2 μA or more flows, and measuring the voltage when a current of 0.1 μA flows. The device used was a power device analyzer B1505A manufactured by Keysight Technologies.

[0133] like Fig.11As shown in FIG. 1 , compared with Comparative Example 1, even if the reverse voltage value (absolute value) increases, the increase in the current value is controlled, so it can be understood that the voltage resistance of the semiconductor device is improved by providing the second region 13b. -7 The absolute value of the reverse voltage at A in Example 1 is about twice that in Comparative Example 1.

[0134] The obtained semiconductor device was observed by SEM, and the results were as follows: Fig.12 and Fig.13 Results shown. Fig.12 and Fig.13 A cross section perpendicular to the upper surface of the semiconductor layer of the obtained semiconductor device is shown. Fig.12 An image on the inner side than the periphery of the Schottky electrode 14 is shown. Fig.13 The image including the periphery of the Schottky electrode 14 is shown. A linear region with high resistance is observed in the n-type semiconductor layer 13. This region extends along the upper surface.

[0135] The obtained semiconductor device was observed by SIM, and the results were as follows: Fig.14 and Fig.15 Results shown. Fig.14 and Fig.15 A cross section perpendicular to the upper surface of the semiconductor layer of the obtained semiconductor device is shown. Fig.14 The image including the periphery of the Schottky electrode 14 is shown. A linear region with high resistance is observed in the n-type semiconductor layer 13. This region extends along the upper surface. Fig.15 The image of the center of the Schottky electrode 14 in the horizontal direction is shown. Fig.15 In the embodiment, the portion not including the second region 13b is observed. Fig.15 In the figure, no linear region with high resistance was observed.

[0136] In addition, in SEM observation and SIM observation, it can be observed that the high resistance region is thinner than the thickness of the second region 13b measured by secondary ion mass spectrometry (SIMS). In other words, in SEM observation and SIM observation, a part of the second region 13b, especially the lower end, may not be observed.

[0137] The relationship between the depth from the upper surface of the semiconductor layer and the density of crystal defects or the concentration of impurity elements is the result calculated by a numerical calculation code (SRIM / TRIM). Fig.16 shown. Fig.16The density of crystal defects of gallium (Ga) at a depth from the upper surface of the semiconductor layer, the density of crystal defects of oxygen (O), and the density of crystal defects of gallium and oxygen (Ga+O) are shown, and the depth and density of aluminum (Al) element (impurity element of Example 1) from the upper surface of the semiconductor layer are shown. The depth of the impurity element is calculated based on the results calculated by the numerical calculation code (SRIM / TRIM), so the range of the second region 13b at a depth from the upper surface of the semiconductor layer can be determined.

[0138] The maximum value of the density of the crystal defects is located at a depth from the upper surface of the semiconductor layer at a position closer to the lower end than the upper end of the second region. The maximum value of the density of the crystal defects is shallower than the maximum value of the concentration of the impurity element included in the second region at a depth from the upper surface of the semiconductor layer, and the positions of both of these maximum values ​​at a depth from the upper surface of the semiconductor layer are located at a position closer to the lower end than the upper end of the second region. The concentration of the aluminum (Al) element becomes the maximum concentration at the depth of 1.3 to 1.4 μm, and is the same as the dopant concentration of the n-type semiconductor layer 13 at the depth of 1.6 to 1.7 μm. In this way, the boundary between the second region 13b and the first region 13a can also be calculated by this numerical calculation code. That is, the boundary between the second region 13b and the first region 13a can also be defined as the depth at which the concentration of the impurity element included in the second region 13b is deeper than the maximum value and is the same as the dopant concentration of the n-type semiconductor layer 13. In addition, regarding the TRIM program, a part of the program group known as SRIM can be obtained from http: / / www.srim.org.

[0139] Below, examples 2 to 7 are listed and referenced. Fig.17 The semiconductor device of the present disclosure is described. Fig.17 The results of secondary ion mass spectrometry (SIMS) showing the relationship between the depth from the upper surface of the n-type semiconductor layer 13 and the concentration of impurities in Examples 2 to 5. Fig.17 The horizontal axis of represents the depth from the upper surface of the n-type semiconductor layer 13 , and the unit is μm. Fig.17 The vertical axis represents the concentration (N) of the impurity element (Al element), with the unit being cm -3 .

[0140] A semiconductor device was manufactured by the manufacturing method of Embodiment 1 except that each element was ion-implanted into the entire upper surface of the n-type semiconductor layer 13. The impurity elements and ion implantation conditions in Examples 2 to 5 are as follows.

[0141] (Example 2)

[0142] In Example 2, Al element was implanted at an energy of 1500 keV and a 13 atoms / cm 2 The ion implantation was performed into the n-type semiconductor layer 13 with a dose of 8 MeV. In Example 2, a device with a maximum implantation energy of 8 MeV was used. The obtained semiconductor device was subjected to secondary ion mass spectrometry (SIMS), and the results were as follows: Fig.17 As shown, the maximum value of the concentration of the Al element is located at a position at a depth of 1.0 μm or slightly deeper than 1.0 μm from the upper surface of the n-type semiconductor layer 13 .

[0143] (Example 3)

[0144] In Example 3, Al element was implanted at an energy of 2000 keV and 3.0×10 13 atoms / cm 2 The ion implantation was performed into the n-type semiconductor layer 13 with a dose of 8 MeV. In Example 3, a device with a maximum implantation energy of 8 MeV was used. The obtained semiconductor device was subjected to secondary ion mass spectrometry (SIMS), and the results were as follows: Fig.17 As shown, the maximum value of the concentration of the Al element is located at a depth of about 1.25 μm from the upper surface of the n-type semiconductor layer 13 .

[0145] (Example 4)

[0146] In Example 4, Al element was implanted at an energy of 3000 keV and 3.0×10 13 atoms / cm 2 The ion implantation was performed into the n-type semiconductor layer 13 with a dose of 8 MeV. In Example 4, a device with a maximum implantation energy of 8 MeV was used. The obtained semiconductor device was subjected to secondary ion mass spectrometry (SIMS), and the results were as follows: Fig.17 As shown, the maximum value of the concentration of the Al element is located at a depth of about 1.55 μm from the upper surface of the n-type semiconductor layer 13 .

[0147] (Example 5)

[0148] In Example 5, Al element was implanted at an energy of 2000 keV and a 13 atoms / cm 2 The ion implantation was performed with a dose of 8 MeV into the n-type semiconductor layer 13. In Example 5, a device with a maximum implantation energy of 8 MeV was used. The obtained semiconductor device was subjected to secondary ion mass spectrometry (SIMS), and the result showed that the maximum concentration of the Al element at a depth from the upper surface of the n-type semiconductor layer 13 was the same as that in Example 3.

[0149] (Example 6)

[0150] In Example 6, the Mg element was implanted at an energy of 600 keV and 4.0×10 14 atoms / cm 2 Ions of a dose of 100 keV are implanted into the n-type semiconductor layer 13 by double charges. In Example 6, an apparatus with a maximum implantation energy of 400 keV is used.

[0151] (Example 7)

[0152] In Example 7, the B element was implanted at an energy of 600 keV and 4.0×10 14 atoms / cm 2 Ions of a dose of 100 keV are implanted into the n-type semiconductor layer 13 by double charges. In Example 7, an apparatus with a maximum implantation energy of 400 keV is used.

[0153] The reverse voltage in each semiconductor device obtained was evaluated. The evaluation was performed by applying a reverse voltage of 0 to 1200 V to each semiconductor device obtained, stopping the application of the reverse voltage when a current of 0.2 μA or more flows, and measuring the voltage when a current of 0.1 μA flows. The device used was a power device analyzer B1505A manufactured by Keysight Technologies.

[0154] Current value exceeds 1.0×10 -8 The absolute value of the reverse voltage of each embodiment at A is greater than 800V in embodiment 2, greater than 950V in embodiment 4, and greater than 1000V in embodiments 3 and 4. In addition, the absolute value is 650V to 700V in embodiment 6, and 550V to 600V in embodiment 7. Therefore, it can be understood that the voltage resistance of the semiconductor device is improved in the embodiments. In addition, it can be understood that the impurity is more preferably Al having a mass number greater than the mass number of Mg.

[0155] For Examples 2 to 7, the relationship between the distance Rp+ΔRp (μm) obtained by adding the projected range Rp representing the depth of ion implantation into the n-type semiconductor layer 13 and the standard deviation ΔRp and the dielectric withstand voltage (V) was evaluated. In Examples 2 to 5, the dielectric withstand voltage exceeded 800V, and the preferred dielectric withstand voltage can also be obtained from this relationship. In Examples 6 and 7, Rp+ΔRp was less than 1.0μm, and the dielectric withstand voltage was deteriorated compared with the examples in which the Al element was ion implanted.

[0156] Next, additional notes are given to the above-mentioned embodiment.

[0157] (Note 1)

[0158] A semiconductor device comprising:

[0159] a semiconductor layer having an extended depletion layer; and

[0160] an electrode disposed on the semiconductor layer directly or via other layers,

[0161] The semiconductor layer includes: a first region including a crystalline oxide semiconductor containing gallium as a main component; and a second region including an oxide containing gallium as a main component,

[0162] The second region has a linear crystal defect region in a cross section perpendicular to an upper surface of the semiconductor layer.

[0163] (Note 2)

[0164] The semiconductor device according to Supplementary Note 1, wherein the density of crystal defects in the crystal defect region is 1.0×10 19 / cm 3 above.

[0165] (Note 3)

[0166] The semiconductor device according to Supplement 1 or 2, wherein the surface density of crystal defects in the second region when viewed from above is 5×10 16 / cm 2 above.

[0167] (Note 4)

[0168] The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the crystal defect region extends along the upper surface.

[0169] (Note 5)

[0170] A semiconductor device according to any one of Supplementary Notes 1 to 4, wherein a maximum value of the density of crystal defects in the crystal defect region is located at a position lower than an upper end of the second region at a depth from an upper surface of the semiconductor layer.

[0171] (Note 6)

[0172] A semiconductor device according to any one of Supplementary Notes 1 to 5, wherein:

[0173] The semiconductor layer includes an impurity element,

[0174] a concentration of the impurity element included in the second region is higher than a concentration of the impurity element included in the first region,

[0175] The maximum value of the density of crystal defects in the crystal defect region is shallower than the maximum value of the concentration of the impurity element included in the second region at a depth from the upper surface of the semiconductor layer.

[0176] The positions of both the maximum values ​​at a depth from the upper surface of the semiconductor layer are located closer to the lower end side than the upper end side of the second region.

[0177] (Note 7)

[0178] The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein the thickness of the second region is 1.5 μm or more.

[0179] (Note 8)

[0180] The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein at least a portion of the second region overlaps with a periphery of a lower surface of the electrode in a plan view.

[0181] (Note 9)

[0182] The semiconductor device according to Supplementary Note 7, wherein the second region overlapping with the periphery of the lower surface is in contact with the lower surface.

[0183] (Note 10)

[0184] The semiconductor device according to any one of Supplementary Notes 1 to 9, wherein at least a portion of the second region overlaps with a peripheral portion of the semiconductor layer in a plan view.

[0185] (Note 11)

[0186] The semiconductor device according to any one of Supplementary Notes 1 to 10, wherein the second region includes a single body of an element having a mass number greater than a mass number of Mg.

[0187] (Note 12)

[0188] The semiconductor device according to Supplementary Note 10, wherein the element is Al.

[0189] (Note 13)

[0190] The semiconductor device according to any one of Supplementary Notes 1 to 12, wherein a concentration of the element in the second region is higher than a concentration of the element in the first region.

[0191] (Note 14)

[0192] The semiconductor device according to any one of Supplementary Notes 1 to 13, wherein the crystalline oxide semiconductor has a corundum structure.

[0193] (Note 15)

[0194] The semiconductor device according to any one of Supplementary Notes 1 to 14, wherein the oxide is amorphous.

[0195] (Note 16)

[0196] The semiconductor device according to any one of Supplementary Notes 1 to 15, wherein the crystalline oxide semiconductor includes aluminum and / or indium.

[0197] (Note 17)

[0198] The semiconductor device according to any one of Supplementary Notes 1 to 16, wherein the semiconductor device is a diode.

[0199] (Note 18)

[0200] The semiconductor device according to any one of Supplementary Notes 1 to 17, wherein the semiconductor device is a power device.

[0201] (Note 19)

[0202] A power conversion device using the semiconductor device according to any one of Supplementary Notes 1 to 18.

[0203] (Note 20)

[0204] A control system using the semiconductor device described in any one of Supplementary Notes 1 to 18.

[0205] (Note 21)

[0206] A method for manufacturing a semiconductor device comprises the following steps:

[0207] forming a semiconductor layer including a crystalline oxide semiconductor containing gallium as a main component and including an n-type dopant;

[0208] ion implanting an impurity element from an upper surface of the semiconductor layer into a portion of the semiconductor layer; and

[0209] forming an electrode directly on the semiconductor layer or via another layer without performing a process for activating the ion-implanted element,

[0210] The ion implantation process forms a first region and a second region, and in a cross section perpendicular to the upper surface of the semiconductor layer, a linear crystal defect region is formed in the second region, the first region includes a crystalline oxide semiconductor containing gallium as a main component, and the second region includes an oxide containing gallium as a main component.

[0211] (Note 22)

[0212] The method for manufacturing a semiconductor device according to Supplementary Note 21, wherein after the ion implantation step and until the electrode formation step, the temperature of the semiconductor layer is kept lower than 800°C.

[0213] Description of Reference Numerals

[0214] 10, 210, 310, 410, 510 semiconductor devices

[0215] 11 ohm electrode

[0216] 12. 512n+ type semiconductor layer

[0217] 13. 513n-type semiconductor layer

[0218] 13a, 513a first area

[0219] 13b, 313, 413, 513b Second area

[0220] 14 Schottky electrode

[0221] 15 substrates

[0222] 21 Crystal defect region

[0223] 33 Peripheral

[0224] 204 insulator layer

[0225] Areas 313a, 313b, 413a, 413b

[0226] 500, 600 control system

[0227] 501 battery (power source)

[0228] 502 Boost Converter

[0229] 503 Buck Converter

[0230] 504, 604 inverter

[0231] 505, 605 motor

[0232] 506, 606 drive control unit

[0233] 507, 607 Operation Department

[0234] 508, 608 storage unit

[0235] 601 three-phase AC power supply (power supply)

[0236] 602AC / DC Converter

[0237] 511 Drain electrode

[0238] 515 Gate insulation film

[0239] 516 Gate electrode

[0240] 517 Source Electrode

[0241] 518, 518a, 518b oxide semiconductor layer

[0242] 519n+ type oxide semiconductor layer

[0243] 533 Peripheral

Claims

1. A semiconductor device comprising: a semiconductor layer having an extended depletion layer; and an electrode disposed on the semiconductor layer directly or via other layers, The semiconductor layer includes: a first region including a crystalline oxide semiconductor containing gallium as a main component; and a second region including an oxide containing gallium as a main component, The second region has a linear crystal defect region in a cross section perpendicular to an upper surface of the semiconductor layer.

2. The semiconductor device according to claim 1, wherein The density of crystal defects in the crystal defect region is 1.0×10 19 / cm 3 above.

3. The semiconductor device according to claim 1, wherein The surface density of crystal defects in the second region when viewed from above is 5×10 16 / cm 2 above.

4. The semiconductor device according to claim 1, wherein The crystal defect region extends along the upper surface.

5. The semiconductor device according to claim 1, wherein A maximum value of the density of crystal defects in the crystal defect region is located at a position closer to the lower end side than the upper end side of the second region at a depth from the upper surface of the semiconductor layer.

6. The semiconductor device according to claim 1, wherein The semiconductor layer includes an impurity element, a concentration of the impurity element included in the second region is higher than a concentration of the impurity element included in the first region, The maximum value of the density of crystal defects in the crystal defect region is shallower than the maximum value of the concentration of the impurity element included in the second region at a depth from the upper surface of the semiconductor layer. The positions of both the maximum values ​​at a depth from the upper surface of the semiconductor layer are located on the lower end side than the upper end side of the second region.

7. The semiconductor device according to claim 1, wherein The thickness of the second region is greater than or equal to 1.5 μm.

8. The semiconductor device according to claim 1, wherein At least a portion of the second region overlaps with a peripheral edge of the lower surface of the electrode in a plan view.

9. The semiconductor device according to claim 7, wherein: The second region overlapping with the periphery of the lower surface is in contact with the lower surface.

10. The semiconductor device according to claim 1, wherein At least a portion of the second region overlaps with a peripheral portion of the semiconductor layer in a plan view.

11. The semiconductor device according to claim 1, wherein The second region includes a single body of an element having a mass number greater than that of Mg.

12. The semiconductor device according to claim 10, wherein: The element is Al.

13. The semiconductor device according to claim 1, wherein The concentration of the element in the second region is higher than the concentration of the element in the first region.

14. The semiconductor device according to claim 1, wherein The crystalline oxide semiconductor has a corundum structure.

15. The semiconductor device according to claim 1, wherein The oxide is amorphous.

16. The semiconductor device according to claim 1, wherein The crystalline oxide semiconductor includes aluminum and / or indium.

17. The semiconductor device according to claim 1, wherein: The semiconductor device is a diode.

18. The semiconductor device according to claim 1, wherein The semiconductor device is a power device.

19. A power conversion device using the semiconductor device according to claim 1.

20. A control system using the semiconductor device according to claim 1.

21. A method for manufacturing a semiconductor device, comprising the following steps: forming a semiconductor layer including a crystalline oxide semiconductor containing gallium as a main component and including an n-type dopant; ion implanting an impurity element from an upper surface of the semiconductor layer into a portion of the semiconductor layer; and forming an electrode directly on the semiconductor layer or via another layer without performing a process for activating the ion-implanted element, The ion implantation process forms a first region and a second region, and in a cross section perpendicular to the upper surface of the semiconductor layer, a linear crystal defect region is formed in the second region, the first region includes a crystalline oxide semiconductor containing gallium as a main component, and the second region includes an oxide containing gallium as a main component.

22. The method for manufacturing a semiconductor device according to claim 21, wherein: After the ion implantation step and until the electrode formation step, the temperature of the semiconductor layer is kept lower than 800° C.

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