Batch automatic test method and system for flip chip interconnection connection condition

Abstract

The invention discloses a batch automatic test method and system for flip chip interconnection connection conditions. The method comprises the steps of performing calibration setting on target adjustment parameters according to a preset alignment position and a preset needle insertion position; sending a starting signal to the control device, so that the control device generates a test signal in response to the received starting signal; the following steps are iteratively executed until all the alternative chips to be tested in the chip carrier are tested: a test signal sent by the control device is received, the test signal comprises information of a target chip to be tested, and the target chip to be tested is any one of the batch of alternative chips to be tested; according to a pre-generated automatic identification template, the target to-be-tested chip information and the target adjustment parameters, moving until a reading circuit bonding pad of the target to-be-tested chip is in contact with a probe on the probe card to obtain electrical connection test data of the target to-be-tested chip; and sending the test data to the control device. The test efficiency can be greatly improved, the time cost is saved, and the test consistency is improved.

Description

Technical Field

[0001] The present application belongs to the field of infrared detector technology, and in particular, relates to a batch automatic testing method and system for the connectivity of flip-chip interconnections. Background Art

[0002] The third generation of focal plane infrared detectors are developing in the direction of high integration, light weight and low cost. As the core component of the focal plane infrared detector, the infrared focal plane chip is mainly composed of an infrared focal plane array and a readout circuit. As the scale of the pixel array continues to expand, the flip-chip interconnection process has become a key process technology in the manufacturing process of infrared focal plane chips. In order to increase the yield of infrared focal plane chips, the introduction of electrical testing after the flip-chip interconnection process can quickly and accurately determine the connectivity of the chip flip-chip interconnection, and effectively detect qualified chips suitable for assembly and use. At the same time, the problems existing in the flip-chip interconnection process can be effectively monitored and feedback can be provided, providing an effective detection method for the technical analysis of the quality of the flip-chip interconnection process.

[0003] However, in the current electrical connectivity test process of flip-chip interconnections of infrared focal plane chips, a large number of chips are aligned one by one by the human eye with the probes and the corresponding pad positions on the chip readout circuit, and physical contact is achieved by manual needle insertion. This will undoubtedly increase the probability of chip damage, poor test consistency, and reduce test efficiency, which cannot meet the needs of efficient testing of large quantities of chips. Summary of the invention

[0004] The embodiments of the present application provide a method and system for batch automatic testing of the connectivity of flip-chip interconnects, which are used to at least solve the problems in the related art of poor test consistency, low test efficiency, and inability to meet the needs of efficient testing of large quantities of chips.

[0005] In the first aspect, the embodiment of the present application provides a batch automatic testing method for the connectivity of flip-chip interconnection, which is applied to a probe station, wherein the probe station is a four-axis motion mechanism, and the probe station includes a chip carrier, and the chip carrier includes a plurality of position slots, and a batch of candidate chips to be tested of the same type are respectively fixed in each position slot, and the candidate chips to be tested correspond to the position slots one by one, and the candidate chips to be tested are infrared focal plane chips after completing the flip-chip interconnection process;

[0006] The method comprises:

[0007] Calibrate and set the target adjustment parameters according to the preset alignment position and acupuncture position;

[0008] sending a start signal to a control device so that the control device generates a test signal in response to receiving the start signal;

[0009] Iterate the following steps until all candidate chips in the chip carrier have completed testing:

[0010] Receiving a test signal sent by the control device, wherein the test signal includes information of a target chip to be tested, and the target chip to be tested is any one of the batch of candidate chips to be tested;

[0011] According to the pre-generated automatic recognition template, the target chip to be tested information and the target adjustment parameters, the readout circuit pad of the target chip to be tested is moved to contact the probe on the probe card to obtain the electrical connectivity test data of the target chip to be tested, wherein the probe card is arranged above the probe station, and the probe card matches the type of the candidate chip to be tested;

[0012] The test data is sent to the control device.

[0013] In a second aspect, an embodiment of the present application provides a batch automatic testing system for the connectivity of flip-chip interconnects, including:

[0014] The probe station is a four-axis motion mechanism, including a chip carrier, the chip carrier includes a plurality of position slots, batches of the same type of candidate chips to be tested are fixed in each position slot, the candidate chips to be tested correspond to the position slots one by one, and the candidate chips to be tested are infrared focal plane chips after completing the flip-chip interconnection process;

[0015] A probe card is arranged above the probe station, the probe card matches the type of the candidate chip to be tested, and probes are arranged on the probe card;

[0016] Control devices;

[0017] A signal processing interface board, connected to the probe card and the control device respectively;

[0018] The probe station is used to: calibrate and set target adjustment parameters according to preset alignment positions and needle insertion positions; send a start signal to a control device so that the control device generates a test signal in response to receiving the start signal; iteratively perform the following steps until all candidate chips to be tested in the chip carrier are tested: receive a test signal sent by the control device, the test signal includes target chip information to be tested, and the target chip to be tested is any one of the batch of candidate chips to be tested; according to a pre-generated automatic recognition template, target chip information to be tested and target adjustment parameters, move to the readout circuit pad of the target chip to be tested to contact the probe on the probe card to obtain electrical connectivity test data of the target chip to be tested; and send the test data to the control device.

[0019] The batch automatic testing method and system for the connectivity of flip-chip interconnections of the embodiments of the present application are based on pre-generated automatic recognition templates and adjustment parameters, and control the probe station to perform testing through a control device, automatically aligning the chip position, contacting the probe with the chip, and outputting the test data of the chip; after the current chip has completed the test, the control device sends a signal to the probe station, and the probe station moves again so that the next chip can be automatically aligned and contacted with the probe, thereby iteratively implementing batch automatic testing until all the chips to be tested in the chip carrier have been tested, greatly improving test efficiency and yield; and, it can effectively avoid manual physical contact between the probe and the chip readout circuit one by one, reduce the probability of chip damage, and have good test consistency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 is a schematic diagram of an exemplary chip carrier provided in an embodiment of the present application;

[0022] Figure 2 It is a flow chart of a method for batch automatic testing of the connectivity of flip-chip interconnects provided in an embodiment of the present application;

[0023] Figure 3 This is a schematic diagram of the contact between the chip to be tested and the probe provided in the embodiment of the present application;

[0024] Figure 4 is an imaging grayscale image of a test result of a target chip to be tested provided in an exemplary embodiment of the present application;

[0025] Figure 5 It is a structural schematic diagram of a batch automatic testing system for the connectivity of flip-chip interconnections provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0027] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0028] The third generation of focal plane infrared detectors are developing in the direction of high integration, light weight and low cost. As the core component of the focal plane infrared detector, the infrared focal plane chip is mainly composed of an infrared focal plane array and a readout circuit. As the scale of the pixel array continues to expand, the flip-chip interconnection process has become a key process technology in the manufacturing process of infrared focal plane chips. In order to increase the yield of infrared focal plane chips, the introduction of electrical testing after the flip-chip interconnection process can quickly and accurately determine the connectivity of the chip flip-chip interconnection, and effectively detect qualified chips suitable for assembly and use. At the same time, the problems existing in the flip-chip interconnection process can be effectively monitored and feedback can be provided, providing an effective detection method for the technical analysis of the quality of the flip-chip interconnection process.

[0029] However, in the current electrical connectivity test process of flip-chip interconnections of infrared focal plane chips, a large number of chips are aligned one by one by the human eye with the probes and the corresponding pad positions on the chip readout circuit, and physical contact is achieved by manual needle insertion. This will undoubtedly increase the probability of chip damage, poor test consistency, and reduce test efficiency, which cannot meet the needs of efficient testing of large quantities of chips.

[0030] In order to solve the problems of the related art, the embodiments of the present application provide a method and system for batch automatic testing of the connectivity of flip-chip interconnections.

[0031] The following, in conjunction with the accompanying drawings, describes in detail the batch automatic testing method for the connectivity of chip flip-chip interconnections provided in the embodiment of the present application through specific embodiments and their application scenarios.

[0032] It should be noted that, in the embodiment of the present application, the chips to be automatically tested in batches are infrared focal plane chips that have completed the flip-chip interconnection process and are chips of the same type, which are simply referred to as candidate chips to be tested in the following description.

[0033] It should be noted that the batch automatic testing method for the connectivity of flip-chip interconnections in the embodiment of the present application is applied to a probe station.

[0034] Optionally, the probe station is a four-axis motion mechanism. That is, the probe station includes a first movable workbench corresponding to the horizontal plane (XY plane) formed by the first directional axis (X axis) and the second directional axis (Y axis), a second movable workbench corresponding to the third directional axis (Z axis), and a third movable workbench corresponding to the θ axis. Among them, the first directional axis (X axis), the second directional axis (Y axis) and the third directional axis (Z axis) are perpendicular to each other. Specifically, the direction of the third directional axis (Z axis) is consistent with the vertical direction, the third directional axis (Z axis) is perpendicular to the horizontal plane (XY plane), and the first directional axis (X axis) and the second directional axis (Y axis) intersect and both intersect with the vertical direction.

[0035] Optionally, the probe station includes a chip carrier.

[0036] refer to Figure 1 , is a schematic diagram of an exemplary chip carrier according to an embodiment of the present application. Figure 1 As shown, the chip carrier includes a plurality of position slots ( Figure 1 The chip carrier is a 6×4 array), and the same type of candidate chips to be tested are fixed in each position slot, and the candidate chips to be tested correspond to the position slots one by one. It can be understood that the tooling can be detached, and the chip carrier can also be replaced with 2×6, 4×3, etc., which is not specifically limited in this embodiment.

[0037] Optionally, a probe card is provided above the probe station, and the probe card matches the type of the alternative chip to be tested. Taking the mercury cadmium telluride 640×512 array infrared focal plane chip provided in the embodiment of the present application as an example, the probe card has a circuit corresponding to the chip and is designed according to the circuit. It should be noted that the types of chips and probe cards can be replaced accordingly according to actual usage, and this embodiment does not specifically limit this.

[0038] Based on the probe station, Figure 2 The flowchart of the batch automatic testing method for the connectivity of the flip chip interconnection of the embodiment of the present application is shown. Figure 2 As shown, the batch automatic testing method for the connectivity of flip-chip interconnections may specifically include the following steps:

[0039] S201, calibrating and setting target adjustment parameters according to preset alignment positions and acupuncture positions;

[0040] S202, sending a start signal to the control device, so that the control device generates a test signal in response to receiving the start signal;

[0041] S203, iteratively executing the following steps until all candidate chips to be tested in the chip carrier are tested:

[0042] Receiving a test signal sent by the control device, wherein the test signal includes information of a target chip to be tested, and the target chip to be tested is any one of the batch of candidate chips to be tested;

[0043] According to the pre-generated automatic recognition template, the target chip to be tested information and the target adjustment parameters, the readout circuit pad of the target chip to be tested is moved to contact the probe on the probe card to obtain the electrical connectivity test data of the target chip to be tested, wherein the probe card is arranged above the probe station, and the probe card matches the type of the candidate chip to be tested;

[0044] The test data is sent to the control device.

[0045] Therefore, based on the pre-generated automatic recognition template and adjustment parameters, the control device controls the probe station to perform testing, automatically realizes chip position alignment, probe and chip contact, and outputs the test data of the chip; after the current chip completes the test, the control device sends a signal to the probe station, and the probe station moves again to make the next chip automatically align and contact the probe, thereby iteratively realizing batch automatic testing until all the chips to be tested in the chip carrier are tested, greatly improving test efficiency and yield; and, it can effectively avoid manual physical contact between the probe and the chip readout circuit one by one, reduce the probability of chip damage, and have good test consistency.

[0046] The specific implementation methods of the above steps are introduced below.

[0047] As an optional embodiment, Figure 1 As shown, each position slot is provided with a vacuum adsorption hole. In addition, a vacuum pump is provided under the probe station. Thus, before S201, a batch of candidate chips to be tested of the same type can be taken into each position slot with a suction pen, so that the candidate chips to be tested cover the vacuum adsorption hole; the vacuum pump is operated to fix the candidate chips to be tested in the position slot by pressure adsorption. In this way, the batch of candidate chips to be tested can be firmly adsorbed in their respective corresponding position slots.

[0048] In some embodiments, in S201, the real-time position information of the probe station is determined by a detection device; the first mobile workbench is adjusted according to the real-time position information so that the position of at least one alternative chip to be tested conforms to a pre-set alignment position, and the second mobile workbench and the third mobile workbench are adjusted so that the position of at least one alternative chip to be tested conforms to the needle insertion position; when the alignment position and the needle insertion position are conformed, the target adjustment parameters are determined.

[0049] In addition, in some embodiments, the first size information of the candidate chip to be tested and the second size information of the chip carrier can be determined by a detection device; an automatic recognition template is generated based on the first size information, the second size information and the array information of the chip carrier, and the array information of the chip carrier includes the number of rows and columns of the arrangement of several position slots in the chip carrier.

[0050] Optionally, a detection device is disposed above the probe card, including a microscope or a recognition camera.

[0051] During specific implementation, through camera observation, the semi-automatic probe station is operated to move the chip placed on the chip carrier of the probe station to the alignment position, and the height of the probe station in the Z-axis direction is adjusted to complete the positioning of the chip; the number of rows / columns of the chip carrier is set according to the carrier used, and a template for automatic chip recognition is created; and the parameter measurement setting of the chip size X / Y and the parameter measurement setting of the chip carrier X / Y are completed through the recognition camera, that is, the first size information and the second size information are determined.

[0052] During the specific implementation, the alignment position is set, that is, the position of the first chip to start measurement; the needle insertion position is set, that is, the corresponding contact position between the probe and the readout circuit pad; the probe station is observed and operated to rise through a microscope, and the probe station θ axis is adjusted to achieve precise alignment and contact between the probe and the chip readout circuit pad, and then the contact height parameters are fixed, that is, the target adjustment parameters are determined.

[0053] refer to Figure 3 , is a schematic diagram of the contact between the chip to be tested and the probe. Figure 3 As shown, the probe card is provided with probes corresponding to the positions of the chip readout circuit pads, and the probe table is moved to ensure that the probes are precisely aligned and contacted with the chip readout circuit pads. Otherwise, the contact position is inaccurate, affecting the test accuracy.

[0054] In this way, by aligning an alternative chip to be tested, the target adjustment parameters are determined and an automatic recognition template is established, so that other chips can be automatically identified, aligned and needled subsequently.

[0055] In some embodiments, in S202, the probe station sends a start signal to the control module of the control device to start the test, so that the test software platform of the control device generates a test signal and sends the test signal to the probe station. Then, the test software platform controls the probe station to start the test, that is, specifically executes S203.

[0056] In some embodiments, in S203, the chips may be tested in the order of their arrangement positions or not. For example, if it is found that the chip corresponding to the position slot in the first row and second column of the chip carrier may have a test abnormality caused by an operation error, the test may be performed again after the current test chip is tested, jumping back to the abnormal chip. That is, the target chip to be tested contained in the test signal sent by the control device may be the position information (i.e., the row and column) corresponding to any one of the batch of candidate chips to be tested.

[0057] In specific implementation, if the test is performed according to the arrangement order of the chips, Figure 1 Taking the 6×4 array chip carrier used as an example, the probe station is controlled to automatically move six chips in a row horizontally in sequence according to the pre-generated automatic recognition template, and then moves to the next row for automatic recognition.

[0058] In specific implementation, the moving distance in each direction each time can be determined based on the pre-generated automatic recognition template, target chip information and target adjustment parameters, that is, the adjustment information corresponding to the first mobile workbench, the second mobile workbench and the third mobile workbench respectively each time.

[0059] During specific implementation, the control module of the control device provides bias voltage and working pulse for the chip under test. Specifically, voltage is applied to the chip under test through the signal processing interface board; the output of the chip under test after the voltage is applied (i.e., test data) is transmitted to the control device through the signal processing interface board.

[0060] Furthermore, in some embodiments, after S203, the control device can perform imaging display according to the test data to obtain an imaging grayscale image corresponding to the target chip to be tested; based on the imaging grayscale image, it is determined whether the target chip to be tested is a qualified chip suitable for assembly and use.

[0061] refer to Figure 4 , is an exemplary grayscale image of the test result of a target chip under test. Figure 4 As shown, the marked circles represent the areas that failed the test, so that it is possible to determine whether the target chip to be tested is qualified according to the number and size of the unqualified areas. Therefore, based on the judgment result, the chip is taken out for subsequent process processing.

[0062] In another embodiment, another batch automatic testing method for the connectivity of flip-chip interconnections is provided. Specifically, the batch automatic testing method for the connectivity of flip-chip interconnections includes the following steps.

[0063] After the infrared focal plane chip completes the flip-chip interconnection process, a batch of the same type of chips to be tested are taken to the position slot of the chip carrier with a suction pen and fixed; the vacuum pump is operated to make the chip firmly adsorbed in the chip position slot; the probe card corresponding to the chip type is fixed on the top of the probe station and connected to the signal processing interface board; through camera observation, the semi-automatic probe station is operated to move the chip placed on the probe station carrier to the alignment position, and the height of the sample stage in the Z-axis direction is adjusted to complete the position positioning of the chip; the number of rows / columns of the chip carrier is set according to the carrier used, and a template for automatic chip identification is created, and then the chip size X / Y parameter measurement setting and chip carrier X / Y parameter measurement setting are completed through the identification camera; the alignment position is set, that is, the position of the first chip to be measured; the needle position is set, that is, the corresponding contact position between the probe and the readout circuit pad, and the probe station is operated to rise through a microscope, and the probe and the chip readout circuit pad are precisely aligned and contacted by adjusting the probe station θ axis, and then the contact height parameter is fixed.

[0064] Next, the probe station and the control device are connected through the serial port, and the probe station sends a start signal to the control module of the control device to start the test; the test software platform in the control device controls the probe station to start the test, automatically realizes the chip position alignment and the contact between the probe and the chip, and the data acquisition module will output the chip data, and the software will perform imaging display; after the current chip test is completed, the control device sends a signal to the probe station to separate the probe and the chip, and then move to the next chip position to automatically align and contact the probe, and so on to realize batch automatic testing until all the chips to be tested in the carrier are tested; after the batch test is completed, the chip is judged whether it is qualified according to the test result chart, and the chip is taken out for subsequent process processing.

[0065] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0066] Based on the same technical concept, corresponding to any of the above-mentioned embodiments and methods, the present application also provides a batch automatic testing system for the connectivity of flip-chip interconnections.

[0067] like Figure 5 As shown, the batch automatic testing system for the connectivity of flip-chip interconnections includes: a probe station, a probe card, a control device and a signal processing interface board.

[0068] In some embodiments, the probe station is a four-axis motion mechanism, including a chip carrier, the chip carrier includes a plurality of position slots, batches of the same type of candidate chips to be tested are respectively fixed in each position slot, the candidate chips to be tested correspond one-to-one to the position slots, and the candidate chips to be tested are infrared focal plane chips after completing the flip-chip interconnection process.

[0069] In some embodiments, a probe card is disposed above the probe station, the probe card matches the type of the candidate chip to be tested, and probes are disposed on the probe card.

[0070] In some embodiments, a signal processing interface board is connected to the probe card and the control device, respectively.

[0071] Specifically, the probe station is used to: calibrate and set the target adjustment parameters according to the preset alignment position and needle insertion position; send a start signal to the control device so that the control device generates a test signal in response to receiving the start signal; iteratively perform the following steps until all the candidate chips to be tested in the chip carrier are tested: receive the test signal sent by the control device, the test signal includes the target chip to be tested information, the target chip to be tested is any one of the batch of candidate chips to be tested; according to the pre-generated automatic recognition template, the target chip to be tested information and the target adjustment parameters, move to the readout circuit pad of the target chip to be tested to contact the probe on the probe card to obtain the electrical connectivity test data of the target chip to be tested; send the test data to the control device.

[0072] In some optional embodiments, the control device includes a control module, a host chassis, a processor board, a display and a test software platform. The control module is used to provide bias voltage and working pulses for the candidate chip to be tested; the test software platform is used to control the automatic test progress of the probe station, for example but not limited to, by sending commands to control the automatic test progress of the probe station.

[0073] Optionally, the control device uses an acquisition card to convert the analog signal output by the received chip into a digital signal for processing and display.

[0074] In some optional embodiments, the batch automatic test system for the connectivity of flip-chip interconnection further includes a detection device disposed above the probe card. Specifically, the detection device is used to determine the real-time position information of the probe station; determine the first size information of the candidate chip to be tested and the second size information of the chip carrier.

[0075] Optionally, the detection device includes a microscope or a recognition camera.

[0076] In another embodiment, the probe station is composed of an X-table, a Y-table, a Z-table, a θ-table, a microscope, a recognition camera and other auxiliary mechanisms to form a basic four-axis motion mechanism, which can automatically move the chip placed on the probe station to the alignment station and the probe card position, and control the probe to precisely contact the chip readout circuit.

[0077] Optionally, a one-plate multi-chip type chip carrier (replaceable according to actual use requirements) is provided with position grooves and vacuum suction holes.

[0078] Optionally, a probe card (the type of probe card can be changed according to actual usage requirements) is provided with probes corresponding to the positions of the chip readout circuit pads.

[0079] Optionally, one end of the probe card is used to contact the chip readout circuit pad, and the other end is connected to the signal processing interface board.

[0080] Therefore, the batch automatic testing system for the connectivity of flip-chip interconnections of the embodiment of the present application can realize batch automatic testing for the connectivity of flip-chip interconnections of infrared focal plane chips with high precision, simple operation and good test consistency.

[0081] In other words, the batch automatic test system using the chip flip-chip interconnection connectivity can solve the following problems in related technologies: In the current electrical connectivity test process after the infrared focal plane chip flip-chip interconnection process is completed, the probe is aligned with the corresponding pad position on the chip readout circuit one by one by the human eye, and physical contact is achieved by manual needle insertion, which increases the probability of chip damage; the degree of contact between the probe and the chip readout circuit pad is manually controlled, and the test consistency is poor; the test efficiency for large quantities of chips of the same type is low. It can be seen that the batch automatic test system using the chip flip-chip interconnection connectivity can greatly improve test efficiency, save time costs, and improve test consistency.

[0082] It should be noted that, for the convenience of description, the above device is described in various modules according to their functions. Of course, when implementing this application, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0083] The device of the above embodiment is used to implement the batch automatic testing method of the connectivity of the corresponding chip flip-chip interconnection in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0084] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0085] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0086] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0087] The above reference is according to the method of the embodiment of the present application, the flow chart of the device (system) and the computer program product and / or the block diagram described various aspects of the present application.It should be understood that each square box in the flow chart and / or the block diagram and the combination of each square box in the flow chart and / or the block diagram can be realized by computer program instructions.These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the realization of the function / action specified in one or more square boxes of the flow chart and / or the block diagram.Such a processor can be but is not limited to a general-purpose processor, a special-purpose processor, a special application processor or a field programmable logic circuit.It can also be understood that each square box in the block diagram and / or the flow chart and the combination of the square boxes in the block diagram and / or the flow chart can also be realized by the dedicated hardware that performs the specified function or action, or can be realized by the combination of dedicated hardware and computer instructions.

[0088] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A batch automatic testing method for the connectivity of flip-chip interconnects, characterized in that: Applied to a probe station, the probe station is a four-axis motion mechanism, the probe station includes a chip carrier, the chip carrier includes a plurality of position slots, batches of the same type of candidate chips to be tested are respectively fixed in each position slot, the candidate chips to be tested correspond to the position slots one by one, and the candidate chips to be tested are infrared focal plane chips after completing the flip-chip interconnection process; The method comprises: Calibrate and set the target adjustment parameters according to the preset alignment position and acupuncture position; sending a start signal to a control device so that the control device generates a test signal in response to receiving the start signal; Iterate the following steps until all candidate chips in the chip carrier have completed testing: Receiving a test signal sent by the control device, wherein the test signal includes information of a target chip to be tested, and the target chip to be tested is any one of the batch of candidate chips to be tested; According to the pre-generated automatic recognition template, the target chip to be tested information and the target adjustment parameters, the readout circuit pad of the target chip to be tested is moved to contact the probe on the probe card to obtain the electrical connectivity test data of the target chip to be tested, wherein the probe card is arranged above the probe station, and the probe card matches the type of the candidate chip to be tested; The test data is sent to the control device.

2. The method according to claim 1, characterized in that The probe station includes a first movable workbench corresponding to a horizontal plane formed by a first direction axis and a second direction axis, a second movable workbench corresponding to a third direction axis, and a third movable workbench corresponding to the θ axis, wherein the first direction axis, the second direction axis and the third direction axis are perpendicular to each other; The calibration and setting of the target adjustment parameters according to the preset alignment position and acupuncture position includes: Determine the real-time position information of the probe station by a detection device; According to the real-time position information, the first movable workbench is adjusted so that the position of at least one candidate chip to be tested conforms to a preset alignment position, and the second movable workbench and the third movable workbench are adjusted so that the position of at least one candidate chip to be tested conforms to a needle insertion position; Under the condition that the alignment position and the needle insertion position are met, the target adjustment parameters are determined.

3. The method according to claim 1, characterized in that: A vacuum pump is provided below the probe station, and each position slot is provided with a vacuum adsorption hole; Before calibrating and setting the target adjustment parameters according to the preset alignment position and acupuncture position, the method further includes: Using a suction pen, a batch of candidate chips to be tested of the same type are respectively taken into each position slot, so that the candidate chips to be tested cover the vacuum adsorption holes; The vacuum pump is operated to fix the candidate chip to be tested in the position groove by pressure adsorption.

4. The method according to claim 1, characterized in that: After calibrating and setting the target adjustment parameters according to the preset alignment position and acupuncture position, and before sending a start signal to the control device, the method further includes: Determine the first size information of the candidate chip to be tested and the second size information of the chip carrier by a detection device; An automatic recognition template is generated according to the first size information, the second size information and array information of the chip carrier, wherein the array information of the chip carrier includes the number of rows and columns of arrangement of a plurality of position slots in the chip carrier.

5. The method according to claim 1, characterized in that After sending the test data to the control device, the method further includes: The control device performs imaging display according to the test data to obtain an imaging grayscale image corresponding to the target chip to be tested; According to the imaging grayscale image, it is determined whether the target chip to be tested is a qualified chip suitable for assembly and use.

6. A batch automatic testing system for the connectivity of flip-chip interconnects, characterized in that: The system comprises: The probe station is a four-axis motion mechanism, including a chip carrier, the chip carrier includes a plurality of position slots, batches of the same type of candidate chips to be tested are fixed in each position slot, the candidate chips to be tested correspond to the position slots one by one, and the candidate chips to be tested are infrared focal plane chips after completing the flip-chip interconnection process; A probe card is arranged above the probe station, the probe card matches the type of the candidate chip to be tested, and probes are arranged on the probe card; Control devices; A signal processing interface board, connected to the probe card and the control device respectively; The probe station is used to: calibrate and set target adjustment parameters according to preset alignment positions and needle insertion positions; send a start signal to a control device so that the control device generates a test signal in response to receiving the start signal; iteratively perform the following steps until all candidate chips to be tested in the chip carrier are tested: receive a test signal sent by the control device, the test signal includes target chip information to be tested, and the target chip to be tested is any one of the batch of candidate chips to be tested; according to a pre-generated automatic recognition template, target chip information to be tested and target adjustment parameters, move to the readout circuit pad of the target chip to be tested to contact the probe on the probe card to obtain electrical connectivity test data of the target chip to be tested; and send the test data to the control device.

7. The system according to claim 6, characterized in that The control device includes a control module, a host chassis, a processor board, a display and a test software platform; The control module is used to provide bias voltage and working pulse for the candidate chip to be tested; The test software platform is used to control the automatic test progress of the probe station.

8. The system according to claim 6, characterized in that The system further includes a detection device disposed above the probe card; The detection device is used to determine the real-time position information of the probe station; determine the first size information of the candidate chip to be tested and the second size information of the chip carrier.

9. The system according to claim 8, characterized in that The detection device includes a microscope or a recognition camera.

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