Starting circuit for band-gap reference circuit

Abstract

The invention discloses a starting circuit for a band-gap reference circuit, the band-gap reference circuit is a current mode band-gap base conversion circuit and comprises an error amplifier, a first branch, a second branch, a first MOS tube and a first resistor, the first end of the first MOS tube is connected with power supply voltage, the second end of the first MOS tube is connected with a first output node, and the second end of the first MOS tube is connected with a second output node; the first end of the first resistor is connected with a first output node, the second end of the first resistor is connected with a reference potential, the first output node is used for outputting band-gap reference voltage VBG, and the starting circuit is connected between power supply voltage and the reference potential and connected with the band-gap reference circuit. The pull-up module is used for pulling up the voltage VINN on the first input end of the error amplifier or pulling down the voltage VINP on the second input end of the error amplifier so as to reduce the voltage VEA on the output end of the error amplifier. The band-gap reference circuit can be separated from a degeneracy point, and the problem of overshoot of the band-gap reference voltage VBG in the starting process cannot be caused.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a start-up circuit for a bandgap reference circuit. Background Art

[0002] With the upgrading of integrated circuit manufacturing technology, the power supply voltage of the chip is getting lower and lower, and more and more chips use current mode bandgap reference circuit to generate the target bandgap reference voltage V BG However, the working state of the current-mode bandgap reference circuit is not unique, and there is a problem of degeneracy points.

[0003] Ginseng Figure 1 The current mode bandgap reference circuit in the prior art is shown, including a main circuit 10' and a startup circuit 20'. The current mode bandgap reference circuit has two degenerate points:

[0004] First degenerate point: V INN '=V INP '=0, there is no current in the main circuit 10', V BG ' = 0;

[0005] Second degenerate point: V INN '=V INP ' <V BEQ1 ', there is no current in transistors Q1' and Q2', but there is current in resistors R1' and R3'. At this time, V BG ' is less than the target bandgap reference voltage V BG .

[0006] The working principle of the start-up circuit 20' is: when the main circuit 10' is at the degenerate point, V INN ' <V THM4 ', MOS tube M4' is turned off, the start voltage Vstart' is pulled up to the power supply voltage AVDD' by resistor R5', MOS tube M5' is turned on, and pulls down the voltage V on the output end of the error amplifier EA' EA ', the MOS tube M1' and the MOS tube M2' are turned on, and the main circuit 10' leaves the degeneracy point.

[0007] The shortcomings of the prior art are:

[0008] 1. Over-reliance on the accuracy of the PDK (Process Design Kit). If the MOS tube M4' conduction threshold voltage is less than the forward conduction voltage V of the transistor Q1, BE ', the main circuit 10' will not be able to escape from the second degeneracy point;

[0009] 2. MOS tube M5' directly acts on the control end of MOS tube M3'. The pull-down capability of MOS tube M5' is too strong, which will cause VBG If an overshoot occurs, the pull-down capability of the MOS tube M5' is too weak, which will cause the main circuit 10' to be unable to escape from the degeneracy point.

[0010] Therefore, in view of the above technical problems, it is necessary to provide a startup circuit for a bandgap reference circuit. Summary of the invention

[0011] The object of the present invention is to provide a startup circuit for a bandgap reference circuit, which can make the bandgap reference circuit escape from the degeneracy point and will not cause the bandgap reference voltage V BG Overshoot problem.

[0012] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows:

[0013] A start-up circuit for a bandgap reference circuit, the bandgap reference circuit is a current-mode bandgap base conversion circuit, comprising an error amplifier, a first branch, a second branch, a first MOS tube and a first resistor, the first branch comprising a first bipolar transistor, a first matching resistor and a first PMOS tube, the second branch comprising a second bipolar transistor, a second matching resistor, a third matching resistor and a second PMOS tube, the first input end and the second input end of the error amplifier are respectively connected to the first branch and the second branch, the output end is connected to the control end of the first MOS tube, the first end of the first MOS tube is connected to a power supply voltage, the second end is connected to a first output node, the first end of the first resistor is connected to the first output node, the second end is connected to a reference potential, and the first output node is used to output a bandgap reference voltage V BG ,

[0014] The startup circuit is connected between the power supply voltage and the reference potential, and is connected to the bandgap reference circuit, and is used to pull up the voltage V on the first input terminal of the error amplifier. INN Or pull down the voltage V on the second input of the error amplifier INP , to reduce the voltage V at the output of the error amplifier EA .

[0015] In one or more embodiments of the present invention, the startup circuit includes a first soft start circuit; wherein,

[0016] The first soft start circuit comprises a start control unit and a first adjustment unit. The start control unit is connected between the power supply voltage and the reference potential and is connected to the first output node for adjusting the power supply voltage based on the bandgap reference voltage V BG Generate a first startup current, the first regulating unit is connected to the startup control unit and to the first input terminal of the error amplifier, and is used to pull up the voltage V on the first input terminal of the error amplifier based on the first startup current INN ;or,

[0017] The first soft start circuit includes a start control unit and a second adjustment unit. The start control unit is connected between the power supply voltage and the reference potential and is connected to the first output node for adjusting the start of the soft start circuit based on the bandgap reference voltage V BG The first startup current is generated, and the second regulating unit is connected to the startup control unit and to the second input terminal of the error amplifier, and is used to pull down the voltage V on the second input terminal of the error amplifier based on the first startup current. INP .

[0018] In one or more embodiments of the present invention, the startup control unit includes a second MOS tube, a third MOS tube and a second resistor; wherein,

[0019] The control end of the second MOS tube is connected to the first output node, the first end is connected to the reference potential, the second end is connected to the second end of the second resistor, and the first end of the second resistor is connected to the power supply voltage;

[0020] The control end of the third MOS tube is connected to the second end of the second MOS tube, the first end is connected to the reference potential, and the second end is connected to the first regulating unit and generates a first starting current.

[0021] In one or more embodiments of the present invention, the first regulating unit includes a fourth MOS tube and a fifth MOS tube; wherein,

[0022] The second end of the fourth MOS tube is short-circuited with the control end, the second end is connected to the start control unit, and the first end is connected to the power supply voltage;

[0023] The control end of the fifth MOS tube is connected to the control end of the fourth MOS tube, the first end is connected to the power supply voltage, and the second end is connected to the first input end of the error amplifier.

[0024] In one or more embodiments of the present invention, the second adjustment unit includes a first replication unit and a second replication unit; wherein,

[0025] The first copy unit is connected to the start control unit and is used to copy the first start current to generate the first current;

[0026] The second copy unit is connected to the first copy unit and to the second input terminal of the error amplifier, and is used for copying the first current to generate the second current.

[0027] In one or more embodiments of the present invention, the startup circuit includes a second soft-start circuit; the second soft-start circuit includes a reference voltage generating unit and a comparing unit; wherein,

[0028] The reference voltage generating unit is connected between the power supply voltage and the reference potential and is connected to the output terminal of the error amplifier, and is used to generate a reference voltage at the second output node based on the voltage at the output terminal of the error amplifier;

[0029] The comparison unit is connected to the second output node and the second input terminal of the error amplifier, and is used to compare the reference voltage with the voltage V on the second input terminal of the error amplifier. INP And generate a comparison signal.

[0030] In one or more embodiments of the present invention, the second soft start circuit further includes a third regulating unit, which is connected to the output end of the comparison unit and to the first input end of the error amplifier, and is used to pull up the voltage V on the first input end of the error amplifier based on the comparison signal. INN ;or,

[0031] The second soft start circuit further includes a fourth regulating unit, which is connected to the output end of the comparison unit and to the second input end of the error amplifier, and is used to pull down the voltage V on the second input end of the error amplifier based on the comparison signal. INP .

[0032] In one or more embodiments of the present invention, the reference voltage generating unit includes a tenth MOS tube and a third resistor; wherein,

[0033] The control end of the tenth MOS tube is connected to the output end of the error amplifier, the first end is connected to the power supply voltage, and the second end is connected to the second output node;

[0034] The first end of the third resistor is connected to the second output node, and the second end is connected to the reference potential.

[0035] In one or more embodiments of the present invention, the emitter of the first bipolar transistor is connected to the first input terminal of the error amplifier, the base and the collector are short-circuited and connected to a reference potential, the first end of the first matching resistor is connected to the first input terminal of the error amplifier, and the second end is connected to the reference potential, the first end of the first PMOS tube is connected to the power supply voltage, the second end is connected to the first input terminal of the error amplifier, and the control end is connected to the output terminal of the error amplifier, the emitter of the second bipolar transistor is connected to the second end of the second matching resistor, the base and the collector are short-circuited and connected to the reference potential, the first end of the second matching resistor is connected to the second input terminal of the error amplifier, the first end of the third matching resistor is connected to the second input terminal of the error amplifier, and the second end is connected to the reference potential, the first end of the second PMOS tube is connected to the power supply voltage, the second end is connected to the second input terminal of the error amplifier, and the control end is connected to the output terminal of the error amplifier;

[0036] The channel width-to-length ratio of the tenth MOS tube is equal to the channel width-to-length ratio of the second PMOS tube, and the third resistor is less than or equal to the third matching resistor; or,

[0037] The channel width-to-length ratio of the tenth MOS tube is less than or equal to the channel width-to-length ratio of the second PMOS tube, and the third resistor is equal to the third matching resistor.

[0038] In one or more embodiments of the present invention, the third regulating unit includes an eleventh MOS tube, a first end of the eleventh MOS tube is connected to the power supply voltage, a control end is connected to the output end of the comparison unit, and a second end is connected to the first input end of the error amplifier, and the eleventh MOS tube is used to generate a second starting current.

[0039] In one or more embodiments of the present invention, the fourth regulating unit includes an eleventh MOS tube and a third replicating unit; wherein,

[0040] The first end of the eleventh MOS tube is connected to the power supply voltage, the control end is connected to the output end of the comparison unit, and the second end is connected to the third replication unit. The eleventh MOS tube is used to generate a second startup current;

[0041] The third copy unit is connected to the second input terminal of the error amplifier and is used for copying the second startup current and generating a third current.

[0042] In one or more embodiments of the present invention, the comparison unit includes a hysteresis comparator, and the hysteresis comparator includes a current source, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube, a twenty-second MOS tube and an output node; wherein,

[0043] The first end of the thirteenth MOS transistor is connected to the second end of the current source, the control end is connected to the second input end of the error amplifier, the second end is connected to the second end of the fifteenth MOS transistor, and the first end of the current source is connected to the power supply voltage;

[0044] The first end of the fourteenth MOS tube is connected to the second end of the current source, the control end is connected to the second output node, and the second end is connected to the second end of the eighteenth MOS tube;

[0045] The first end of the fifteenth MOS tube is connected to the reference potential, and the control end is short-circuited with the second end; the first end of the sixteenth MOS tube is connected to the reference potential, the control end is connected to the control end of the fifteenth MOS tube, and the second end is connected to the second end of the fourteenth MOS tube;

[0046] The first end of the seventeenth MOS tube is connected to the reference potential, the control end is connected to the control end of the eighteenth MOS tube, and the second end is connected to the second end of the thirteenth MOS tube;

[0047] The first end of the eighteenth MOS tube is connected to the reference potential, and the control end is short-circuited with the second end;

[0048] The first end of the nineteenth MOS tube is connected to the reference potential, the control end is connected to the second end of the thirteenth MOS tube, and the second end is connected to the second end of the twenty-first MOS tube;

[0049] The first end of the 20th MOS tube is connected to the reference potential, the control end is connected to the second end of the 14th MOS tube, and the second end is connected to the output node of the hysteresis comparator;

[0050] The first end of the twenty-first MOS tube is connected to the power supply voltage, the control end is short-circuited with the second end, the first end of the twenty-second MOS tube is connected to the reference potential, the control end is connected to the control end of the twenty-first MOS tube, and the second end is connected to the output node of the hysteresis comparator.

[0051] In one or more embodiments of the present invention, the channel width-to-length ratio of the fifteenth MOS tube is greater than the channel width-to-length ratio of the sixteenth MOS tube; and / or,

[0052] The channel width-to-length ratio of the seventeenth MOS tube is greater than the channel width-to-length ratio of the eighteenth MOS tube.

[0053] In one or more embodiments of the present invention,

[0054] Compared with the prior art, the startup circuit for the bandgap reference circuit of the present invention pulls up the voltage V on the first input terminal of the error amplifier. INN Or pull down the voltage V on the second input of the error amplifier INP , indirectly reducing the voltage V at the output of the error amplifier EA It does not need to rely on the accuracy of the process design kit, can effectively make the bandgap reference circuit out of the degeneracy point, and solves the problem of bandgap reference voltage overshoot during the power-on process of the startup circuit, avoids false triggering caused by bandgap reference voltage overshoot, and improves the reliability and stability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0056] Figure 1 It is a schematic diagram of a current-type bandgap reference circuit in the prior art;

[0057] Figure 2 Schematic diagram of a startup circuit for a bandgap reference circuit in Embodiment 1 of the present invention;

[0058] Figure 3 is a voltage variation curve diagram of the starting circuit in Example 1 of the present invention;

[0059] Figure 4 is a schematic diagram of a hysteresis comparator of a startup circuit in Embodiment 1 of the present invention;

[0060] Figure 5 is a voltage transfer curve diagram of the hysteresis comparator in Example 1 of the present invention;

[0061] Figure 6 Schematic diagram of a startup circuit for a bandgap reference circuit in Embodiment 1 of the present invention;

[0062] Figure 7 Schematic diagram of a startup circuit for a bandgap reference circuit in Embodiment 1 of the present invention;

[0063] Figure 8 is a schematic diagram of a startup circuit for a bandgap reference circuit in Embodiment 2 of the present invention;

[0064] Fig. 9 Schematic diagram of a startup circuit for a bandgap reference circuit in Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0065] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0066] The term "coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purpose, such as connection through circuits or components such as switches and follower circuits. In addition, in the present invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0067] The present invention discloses a start-up circuit for a bandgap reference circuit, wherein the bandgap reference circuit is a current-mode bandgap base conversion circuit, comprising an error amplifier, a first branch, a second branch, a first MOS tube and a first resistor, wherein the first branch comprises a first bipolar transistor, a first matching resistor and a first PMOS tube, and the second branch comprises a second bipolar transistor, a second matching resistor, a third matching resistor and a second PMOS tube, wherein the first input end and the second input end of the error amplifier are respectively connected to the first branch and the second branch, and the output end is connected to the control end of the first MOS tube, the first end of the first MOS tube is connected to a power supply voltage, and the second end is connected to a first output node, the first end of the first resistor is connected to the first output node, and the second end is connected to a reference potential, and the first output node is used to output a bandgap reference voltage V BG .

[0068] The startup circuit is connected between the power supply voltage and the reference potential, and is connected to the current mode bandgap reference circuit 10, and is used to pull up the voltage V on the first input terminal of the error amplifier. INN Or pull down the voltage V on the second input of the error amplifier INP , to reduce the voltage V at the output of the error amplifier EA .

[0069] The present invention is further described below in conjunction with specific embodiments.

[0070] Embodiment 1:

[0071] like Figure 2 As shown, the bandgap reference circuit 10 in this embodiment is a current-mode bandgap reference circuit, including an error amplifier EA, a first branch, a second branch, a first MOS transistor M1 and a first resistor R1.

[0072] The control end of the first MOS tube M1 is connected to the output end of the error amplifier, the first end is connected to the power supply voltage AVDD, and the second end is connected to the first output node P1. The first end of the first resistor R1 is connected to the first output node P1, and the second end is connected to the reference potential AVSS. The current mode bandgap reference circuit is used to generate a bandgap reference voltage V at the first output node P1. BG The first input terminal INN and the second input terminal INP of the error amplifier are connected to the first branch and the second branch respectively, and the output terminal is connected to the control terminal of the first MOS tube M1. In this embodiment, the first input terminal INN of the error amplifier is an inverting input terminal, and the second input terminal INP is a non-inverting input terminal.

[0073] The first branch includes a first bipolar transistor Q1, a first matching resistor Ra and a first PMOS transistor MP1. The second branch includes a second bipolar transistor Q2, a second matching resistor Rb, a third matching resistor Rc and a second PMOS transistor MP2.

[0074] Specifically, the emitter of the first bipolar transistor Q1 is connected to the first input terminal INN of the error amplifier, the base and the collector are short-circuited, and the base and the collector are connected to the reference potential AVSS, the first end of the first matching resistor Ra is connected to the first input terminal INN of the error amplifier, and the second end is connected to the reference potential AVSS, the first end of the first PMOS tube MP1 is connected to the power supply voltage AVDD, the second end is connected to the first input terminal INN of the error amplifier, and the control end is connected to the output end of the error amplifier.

[0075] The emitter of the second bipolar transistor Q2 is connected to the second end of the second matching resistor Rb, the base and the collector are short-circuited, and the base and the collector are connected to the reference potential AVSS, the first end of the second matching resistor Rb is connected to the second input terminal INP of the error amplifier, the first end of the third matching resistor Rc is connected to the second input terminal INP of the error amplifier, and the second end is connected to the reference potential AVSS, the first end of the second PMOS transistor MP2 is connected to the power supply voltage AVDD, the second end is connected to the second input terminal INP of the error amplifier, and the control end is connected to the output end of the error amplifier. Among them, Q1 and Q2 are described by taking NPN transistors as an example, and PNP transistors can also be used in other embodiments.

[0076] The first end of the MOS tube involved in this embodiment is a source, the second end is a drain, and the control end is a gate. In this embodiment, the first MOS tube M1 is a PMOS tube.

[0077] The current-type bandgap reference circuit generates a bandgap reference voltage V BG The principle is already in the prior art and will not be described in detail in the present invention.

[0078] like Figure 2 As shown, the start-up circuit 20 includes a first soft start circuit 21 , and the first soft start circuit 21 includes a start-up control unit 211 and a first adjustment unit 212 .

[0079] The startup control unit 211 is connected between the power supply voltage AVDD and the reference potential AVSS, and is connected to the first output node P1, and is used to generate a voltage based on the bandgap reference voltage V BG Generate the first starting current I S1 .

[0080] The first regulating unit 212 is connected to the startup control unit 211 and to the first input terminal INN of the error amplifier, and is used for adjusting the first startup current I S1 The voltage V on the first input of the pull-up error amplifier INN .

[0081] like Figure 2 As shown, the startup control unit 211 in this embodiment includes a second MOS transistor M2, a third MOS transistor M3 and a second resistor R2. In this embodiment, the second MOS transistor M2 is an NMOS transistor, and the third MOS transistor M3 is an NMOS transistor.

[0082] The control end of the second MOS transistor M2 is connected to the first output node P1, the first end is connected to the reference potential AVSS, the second end is connected to the second end of the second resistor R2, and the first end of the second resistor R2 is connected to the power supply voltage AVDD. Optionally, the control end of the second MOS transistor M2 can also be connected to the first input end INN of the error amplifier or the second input end INP of the error amplifier.

[0083] The control end of the third MOS tube M3 is connected to the second end of the second MOS tube M2, the first end is connected to the reference potential AVSS, and the second end is connected to the first regulating unit 212. The current flowing through the third MOS tube M3 is the first starting current I S1 .

[0084] like Figure 2 As shown, the first regulating unit 212 in this embodiment includes a fourth MOS transistor M4 and a fifth MOS transistor M5. The fourth MOS transistor M4 and the fifth MOS transistor M5 form a current mirror to adjust the first startup current I S1 The fourth MOS tube M4 and the fifth MOS tube M5 are PMOS tubes.

[0085] The second end of the fourth MOS transistor M4 is short-circuited with the control end, and the second end is connected to the startup control unit 211 and receives the first startup current I S1The control end of the fifth MOS tube M5 is connected to the control end of the fourth MOS tube M4, the first end is connected to the power supply voltage AVDD, and the second end is connected to the first input end INN of the error amplifier.

[0086] When the bandgap reference circuit 10 is at the first degenerate point, the voltage V on the first input terminal of the error amplifier INN , the voltage V on the second input terminal of the error amplifier INP And the bandgap reference voltage V BG are all 0, so the second MOS tube M2 is turned off, and the second resistor R2 pulls up the control terminal voltage of the third MOS tube M3 to turn on the third MOS tube M3 and generate the first startup current I S1 .

[0087] The third MOS tube M3 after being turned on pulls down the control terminal voltage of the fourth MOS tube M4, and the fourth MOS tube M4 and the fifth MOS tube M5 are turned on, and the first startup current I S1 The voltage at the second end of the fifth MOS tube M5 is pulled up because the second end of the fifth MOS tube M5 is connected to the first input end INN of the error amplifier, that is, the fifth MOS tube M5 injects current to the first input end INN of the error amplifier. The voltage V INN According to the working principle of the error amplifier loop, the voltage V EA is pulled low, so the first PMOS transistor MP1, the second PMOS transistor MP2 and the first MOS transistor M1 begin to conduct, so that the bandgap reference circuit 10 is separated from the first degenerate point.

[0088] After the bandgap reference circuit 10 works normally, the bandgap reference voltage V BG At this time, the second MOS tube M2 is turned on, the control end of the third MOS tube M3 is pulled down by the second MOS tube M2, the third MOS tube M3 is turned off, and then the fourth MOS tube M4 and the fifth MOS tube M5 are turned off, and the first soft start circuit 21 will not affect the normal operation of the bandgap reference circuit 10.

[0089] like Figure 2 As shown, the start-up circuit 20 includes a second soft start circuit 22 , and the second soft start circuit 22 includes a reference voltage generating unit 221 , a comparing unit 222 and a third adjusting unit 223 .

[0090] The reference voltage generating unit 221 is connected between the power supply voltage AVDD and the reference potential AVSS, and is connected to the output terminal of the error amplifier, and is used to generate a reference voltage based on the voltage V EA The reference voltage Vsense is generated at the second output node P2.

[0091] The input terminal of the comparison unit 222 is connected to the second output node P2 and the second input terminal INP of the error amplifier, and is used to compare the reference voltage Vsense with the voltage V INP The third adjustment unit 223 is connected to the output end of the comparison unit 22 and to the first input end INN of the error amplifier, and is used to pull up the voltage V on the first input end of the error amplifier based on the comparison signal. INN .

[0092] like Figure 2 As shown, in this embodiment, the reference voltage generating unit 221 includes a tenth MOS tube M10 and a third resistor R3. Among them, the control end of the tenth MOS tube M10 is connected to the output end of the error amplifier, the first end is connected to the power supply voltage AVDD, and the second end is connected to the second output node P2. The first end of the third resistor R3 is connected to the second output node P2, and the second end is connected to the reference potential AVSS. Therefore, the reference voltage Vsense = the leakage current I of the tenth MOS tube M10 DM10 *R3.

[0093] Furthermore, the reference voltage generating unit 221 in this embodiment is set with a proportional relationship with the first branch and the second branch of the bandgap reference circuit 10. When the first bipolar transistor Q1 and the second bipolar transistor Q2 are in the off state, the product of the third resistor R3 and the leakage current of the tenth MOS tube M10 is less than or equal to the product of the third matching resistor Rc and the leakage current of the second PMOS tube MP2.

[0094] When the bandgap reference circuit 10 is at the second degenerate point, the voltage V on the first input terminal of the error amplifier INN and the voltage V on the second input of the error amplifier INP is equal to and less than the turn-on voltage V of the first bipolar transistor Q1 BEQ1 , the first bipolar transistor Q1 and the second bipolar transistor Q2 are in the off state, that is, there is no current in the first bipolar transistor Q1 and the second bipolar transistor Q2, at this time, there is current on the first matching resistor Ra and the third matching resistor Rc, and the bandgap reference voltage V BG is less than the target bandgap reference voltage (e.g., 1.2V). At this time, the voltage V INP = leakage current I of the second PMOS tube MP2 DMP2 * The third matching resistor Rc.

[0095] The control terminals of the first PMOS transistor MP1, the second PMOS transistor MP2 and the tenth MOS transistor M10 are all connected to the output terminal of the error amplifier. In this embodiment, the channel width-to-length ratios of the first PMOS transistor MP1, the second PMOS transistor MP2 and the tenth MOS transistor M10 are set to be the same, and the third resistor R3 is less than or equal to the third matching resistor Rc. Preferably, the resistance value of the third resistor R3 is R3=90%*the third matching resistor Rc, that is, when the bandgap reference circuit is at the second degenerate point, Vsense=90%*VINP. Or in this embodiment, the channel width-to-length ratios of the first PMOS transistor and the second PMOS transistor are set to be less than or equal to the channel width-to-length ratio of the tenth MOS transistor M10, and the third resistor R3 is equal to the third matching resistor Rc. Preferably, the channel width-to-length ratios of the first PMOS transistor MP1 and the second PMOS transistor MP2 are set to be 90%*the channel width-to-length ratio of the tenth MOS transistor M10, that is, when the bandgap reference circuit 10 is at the second degenerate point, Vsense=90%*V INP .

[0096] like Figure 2 As shown, the third regulating unit 223 in this embodiment includes an eleventh MOS transistor M11, a first end of the eleventh MOS transistor M11 is connected to the power supply voltage AVDD, a control end is connected to the output end of the comparison unit 222, and a second end is connected to the first input end INN of the error amplifier. The eleventh MOS transistor M11 is used to generate a second startup current I S2 When the comparison signal output by the comparison unit is high, the eleventh MOS tube M11 is turned off, and when the comparison signal output by the comparison unit is low, the eleventh MOS tube M11 is turned on and generates a second startup current I S2 , and based on the second starting current I S2 A current is sunk into the first input terminal INN of the error amplifier.

[0097] like Figure 3 As shown, when the bandgap reference circuit 10 is at the second degenerate point (0-T1), the reference voltage Vsense and the voltage V on the first input terminal of the error amplifier are INN Linearly increase, the current flowing through the third resistor R3 and the third matching resistor Rc is the same, Vsense = 90% * V INP , the comparison signal is at a low level, at this time the eleventh MOS tube M11 is turned on, and the voltage V INN The voltage V at the output of the error amplifier EA is raised. EA The current flowing through the first PMOS transistor MP1, the second PMOS transistor MP2 and the first MOS transistor M1 increases. At this time, there is current in the first bipolar transistor Q1 and the second bipolar transistor Q2. The bandgap reference circuit 10 breaks away from the second degenerate point and works normally.

[0098] After the bandgap reference circuit 10 works normally (at time T1), the first bipolar transistor Q1 and the second bipolar transistor Q2 are turned on, and the voltage V INN and the voltage V on the second input terminal of the error amplifier INP Clamped by Q1 and Q2. The current flowing through the third resistor R3 is greater than the current flowing through the third matching resistor Rc, Vsense>V INP , the output of the comparison unit 222 is high (at time T2), the eleventh MOS transistor M11 is turned off, and the second soft start circuit 22 does not affect the normal operation of the bandgap reference circuit 10 at this time.

[0099] The comparison unit 222 in this embodiment includes a hysteresis comparator.

[0100] like Figure 4 As shown, the hysteresis comparator includes a current source CS, a thirteenth MOS tube M13, a fourteenth MOS tube M14, a fifteenth MOS tube M15, a sixteenth MOS tube M16, a seventeenth MOS tube M17, an eighteenth MOS tube M18, a nineteenth MOS tube M19, a twentieth MOS tube M20, a twenty-first MOS tube M21, a twenty-second MOS tube M22 and an output node OUT.

[0101] The thirteenth MOS tube M13, the fourteenth MOS tube M14, the twenty-first MOS tube M21 and the twenty-second MOS tube M22 are PMOS tubes, and the fifteenth MOS tube M15, the sixteenth MOS tube M16, the seventeenth MOS tube M17, the eighteenth MOS tube M18, the nineteenth MOS tube M19 and the twentieth MOS tube M20 are NMOS tubes.

[0102] The first end of the thirteenth MOS tube M13 is connected to the second end of the current source CS, the control end is connected to the second input end INP of the error amplifier, the second end is connected to the second end of the fifteenth MOS tube M15, and the first end of the current source CS is connected to the power supply voltage AVDD. The first end of the fourteenth MOS tube M14 is connected to the second end of the current source, the control end is connected to the second output node P2, and the second end is connected to the second end of the eighteenth MOS tube M18. The first end of the fifteenth MOS tube M15 is connected to the reference potential AVSS, and the control end is short-circuited with the second end. The first end of the sixteenth MOS tube M16 is connected to the reference potential AVSS, the control end is connected to the control end of the fifteenth MOS tube M15, and the second end is connected to the second end of the fourteenth MOS tube M14.

[0103] The first end of the seventeenth MOS transistor M17 is connected to the reference potential AVSS, the control end is connected to the control end of the eighteenth MOS transistor M18, and the second end is connected to the second end of the thirteenth MOS transistor M13. The first end of the eighteenth MOS transistor M18 is connected to the reference potential AVSS, and the control end is short-circuited with the second end. The first end of the nineteenth MOS transistor M19 is connected to the reference potential AVSS, the control end is connected to the second end of the thirteenth MOS transistor M13, and the second end is connected to the second end of the twenty-first MOS transistor M21. The first end of the twentieth MOS transistor M20 is connected to the reference potential AVSS, the control end is connected to the second end of the fourteenth MOS transistor M14, and the second end is connected to the output node OUT of the hysteresis comparator. The first end of the twenty-first MOS transistor M21 is connected to the power supply voltage AVDD, and the control end is short-circuited with the second end. The first end of the twenty-second MOS transistor M22 is connected to the reference potential AVSS, the control end is connected to the control end of the twenty-first MOS transistor M21, and the second end is connected to the output node OUT of the hysteresis comparator.

[0104] like Figure 5 As shown, Figure 4 The hysteresis comparator shown has two feedback paths, the first is a negative feedback path, and the second is a positive feedback path. When the positive feedback coefficient is less than the negative feedback coefficient, the entire circuit will be negative feedback and lose the hysteresis effect; when the positive feedback coefficient is greater than the negative feedback coefficient, the entire circuit will show positive feedback, and hysteresis will appear in the voltage transmission curve. In this embodiment, the channel width-to-length ratio (W / L) 15 of the fifteenth MOS tube M15 is set to be greater than the channel width-to-length ratio (W / L) 16 of the sixteenth MOS tube M16 to ensure that the comparator has hysteresis.

[0105] Furthermore, in this embodiment, the channel width-to-length ratio (W / L) 15 of the fifteenth MOS tube M15 is set to be greater than the channel width-to-length ratio (W / L) 16 of the sixteenth MOS tube M16, and the channel width-to-length ratio (W / L) 17 of the seventeenth MOS tube M17 is greater than the channel width-to-length ratio (W / L) 18 of the eighteenth MOS tube M18, thereby avoiding the influence of offset in the process manufacturing process, resulting in that at the second degenerate point, the hysteresis comparator output is in an indeterminate state.

[0106] Figure 4 Medium Vsense <V INP When the hysteresis comparator output OUT is low, Vsense is higher than V INP When it is higher than VTRP, the hysteresis comparator output OUT is high. In this embodiment, the hysteresis window VTRP of the hysteresis comparator is:

[0107]

[0108] In the formula, I cs is the current generated by the current source CS, is the channel width-to-length ratio of the thirteenth MOS tube M13, is the channel width-to-length ratio of the seventeenth MOS tube M17, is the channel width-to-length ratio of the eighteenth MOS tube M18. It can be seen that by increasing the channel width-to-length ratio of the seventeenth MOS tube M17 The hysteresis window VTRP of the hysteresis comparator can be increased.

[0109] When the bandgap reference circuit 10 is at the second degenerate point, Vsense = 90%*V INP , the hysteresis comparator output is low, so that the eleventh MOS tube M11 is turned on, and the bandgap reference circuit 10 is out of the second degenerate point. After the bandgap reference circuit 10 works normally, V INP =I R30 *Rc,I Rc is the current flowing through the third matching resistor Rc, Vsense=I R3 *R3=I R3 *0.9*Rc=0.9*(I Rc +I CEQ2 )*Rc,I R3 is the current flowing through the third resistor R3, I CEQ2 is the current of the second bipolar transistor Q2 after the bandgap reference circuit 10 works normally. Therefore, 0.9*(I Rc +I CEQ2 )*Rc-(I Rc *Rc)>VTRP can make the hysteresis comparator output turn high, ensuring that the twentieth MOS transistor M20 does not affect the normal operation of the bandgap reference circuit 10.

[0110] It can be understood that the bandgap reference voltage V BG (or the voltage V on the first input terminal of the error amplifier INN =0, or the voltage V INP =0), the second MOS tube M2 is turned off, and the first soft start circuit 21 can make the bandgap reference circuit 10 escape from the first degenerate point, which has nothing to do with the accuracy of the PDK (Process Design Kit). EA The voltage on the second input terminal of the error amplifier is V INP Clamped by the forward conduction Vbe of the first bipolar transistor Q1 while Vsense increases exponentially, the second soft-start circuit 22 causes the bandgap reference circuit 10 to escape from the second degeneracy point, regardless of PDK accuracy.

[0111] like Figure 6 As shown, it should be understood that in other embodiments, the start-up circuit 20 may only be provided with the first soft start circuit 21, or as Figure 7As shown, in other embodiments, the start-up circuit 20 may also only be provided with the second soft start circuit 22 .

[0112] Embodiment 2:

[0113] like Figure 8 As shown, the difference from the embodiment 1 is that the first soft start circuit 21 in the embodiment includes a start control unit 211 and a second adjustment unit 213, the start control unit 211 is connected between the power supply voltage AVDD and the reference potential AVSS, and is connected to the first output node P1, and is used to adjust the power supply voltage V BG Generate the first starting current I S1 The second regulating unit 213 is connected to the startup control unit 211 and is connected to the second input terminal INP of the error amplifier, and is used to adjust the first startup current I S1 Pull down the voltage V on the second input of the error amplifier INP .

[0114] From the above analysis, we can see that the voltage V on the second input terminal of the error amplifier can be pulled down. INP , pull down the voltage on the output terminal to make the bandgap reference circuit 10 escape from the first degeneracy point. Therefore, the second regulating unit in this embodiment can adjust the first startup current I S1 The current is copied twice to draw current at the second input terminal INP of the error amplifier.

[0115] like Figure 8 As shown, the startup control unit 211 in this embodiment includes a second MOS transistor M2, a third MOS transistor M3, and a second resistor R2. The control end of the second MOS transistor M2 is connected to the first output node P1, the first end is connected to the reference potential AVSS, the second end is connected to the second end of the second resistor R2, and the first end of the second resistor R2 is connected to the power supply voltage AVDD. The control end of the third MOS transistor M3 is connected to the second end of the second MOS transistor M2, the first end is connected to the reference potential AVSS, and the second end is connected to the second adjustment unit 213. The current flowing through the third MOS transistor M3 is the first startup current I S1 .

[0116] like Figure 8 As shown, the second regulating unit 213 includes a first replicating unit and a second replicating unit, wherein the first replicating unit is connected to the starting control unit 211 and is used to adjust the first starting current I S1 The first current I1 is copied to generate the first current I1. The second copy unit is connected to the first copy unit and to the second input terminal of the error amplifier, and is used to copy the first current I1 to generate the second current I2.

[0117] Specifically, the first copy unit includes a sixth MOS transistor M6 and a seventh MOS transistor M7, and the second copy unit includes an eighth MOS transistor M8 and a ninth MOS transistor M9. The second end of the sixth MOS transistor M6 is short-circuited with the control end, and the second end is connected to the second end of the third MOS transistor M3 in the startup control unit 211, and the first end is connected to the power supply voltage AVDD, the control end of the seventh MOS transistor M7 is connected to the control end of the sixth MOS transistor M6, the first end is connected to the power supply voltage AVDD, and the second end is connected to the second copy unit.

[0118] The second end of the eighth MOS tube M8 is short-circuited with the control end, and the second end of the eighth MOS tube M8 is connected to the second end of the seventh MOS tube M7 in the first copy unit, the first end of the eighth MOS tube M8 is connected to the reference potential AVSS, the control end of the ninth MOS tube M9 is connected to the control end of the eighth MOS tube M8, the first end of the ninth MOS tube M9 is connected to the reference potential AVSS, and the second end of the ninth MOS tube M9 is connected to the second input end INP of the error amplifier.

[0119] When the bandgap reference circuit 10 is at the first degenerate point, the voltage V on the first input terminal of the error amplifier INN , the voltage V on the second input terminal of the error amplifier INP And the bandgap reference voltage V BG are all 0, so the second MOS tube M2 is turned off, and the second resistor R2 pulls up the control terminal voltage of the third MOS tube M3 to turn on the third MOS tube M3 and generate the first startup current I S1 Further, the turned-on third MOS tube M3 pulls down the control terminal voltage of the sixth MOS tube M6, and the sixth MOS tube M6 and the seventh MOS tube M7 are turned on, and the first startup current I S1 The first current I1 is copied and generated, and the voltage at the second end of the seventh MOS tube M7 is pulled up, so the first current I1 of the second current copy unit is copied and generated into the second current I2. Because the second end of the ninth MOS tube M9 is connected to the second input end INP of the error amplifier, that is, the ninth MOS tube M9 draws current at the second input end INP of the error amplifier, the voltage V INP Pulled down, according to the working principle of the error amplifier loop, the voltage on the output end of the error amplifier will be pulled down at this time, so the first PMOS tube MP1, the second PMOS tube MP2 and the first MOS tube M1 start to conduct, and the bandgap reference circuit 10 leaves the first degenerate point.

[0120] Embodiment 3:

[0121] like Fig. 9As shown, the difference from the embodiment 1 is that the fourth regulating unit 224 includes an eleventh MOS transistor M11 and a third replica unit. The first end of the eleventh MOS transistor M11 is connected to the power supply voltage AVDD, the control end is connected to the output end of the comparison unit 222, and the second end is connected to the third replica unit. The eleventh MOS transistor M11 is used to generate a second startup current I S2 .

[0122] The third replica unit is connected to the second input terminal INP of the error amplifier and is used to S2 The third current I3 is copied and generated.

[0123] The third copy unit in this embodiment includes a twenty-third MOS transistor M23 and a twenty-fourth MOS transistor M24. The first end of the twenty-third MOS transistor M23 is connected to the reference potential AVSS, the control end is short-circuited with the second end, and the second end is connected to the second end of the eleventh MOS transistor M11. The first end of the twenty-fourth MOS transistor M24 is connected to the reference potential AVSS, the control end is connected to the control end of the twenty-third MOS transistor M23, and the second end is connected to the second input end INP of the error amplifier.

[0124] The fourth regulating unit 224 in this embodiment can perform a current replication on the second startup current to draw current from the second input terminal INP of the error amplifier. When the bandgap reference circuit 10 is at the second degenerate point, the current flowing through the third resistor R3 and the third matching resistor Rc is the same, Vsense = 90% * V INP , the comparison signal is at a low level, at this time the eleventh MOS tube M11 is turned on and generates a second starting current I S2 , the third replica unit has a second startup current I S2 The third current I3 is copied and generated to pull down the voltage V on the second input terminal of the error amplifier. INP , pull down the voltage on the output terminal to make the bandgap reference circuit 10 escape from the second degeneracy point, and the voltage V on the output terminal of the error amplifier EA The current flowing through the first PMOS transistor, the second PMOS transistor and the first MOS transistor M1 increases. At this time, there is current in the first bipolar transistor Q1 and the second bipolar transistor Q2, and the bandgap reference circuit 10 is out of the second degenerate point.

[0125] After the bandgap reference circuit 10 works normally, the second bipolar transistor Q2 is turned on, the current flowing through the third resistor R3 is greater than the current flowing through the third matching resistor Rc, and Vsense>V INP , the comparison signal output by the comparison unit 222 is high, the eleventh MOS transistor M11 is turned off, and the second soft start circuit 22 does not affect the normal operation of the bandgap reference circuit 10 at this time.

[0126] It can be seen from the above technical solutions that the present invention has the following beneficial effects:

[0127] The startup circuit for the bandgap reference circuit of the present invention pulls up the voltage V on the first input terminal of the error amplifier. INN Or pull down the voltage V on the second input of the error amplifier INP , indirectly reducing the voltage V at the output of the error amplifier EA It does not need to rely on the accuracy of the process design kit, can effectively make the bandgap reference circuit out of the degeneracy point, and solves the problem of bandgap reference voltage overshoot during the power-on process of the startup circuit, avoids false triggering caused by bandgap reference voltage overshoot, and improves the reliability and stability of the circuit.

[0128] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0129] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A start-up circuit for a bandgap reference circuit, the bandgap reference circuit is a current-mode bandgap base conversion circuit, comprising an error amplifier, a first branch, a second branch, a first MOS tube and a first resistor, the first branch comprising a first bipolar transistor, a first matching resistor and a first PMOS tube, the second branch comprising a second bipolar transistor, a second matching resistor, a third matching resistor and a second PMOS tube, the first input end and the second input end of the error amplifier are respectively connected to the first branch and the second branch, the output end is connected to the control end of the first MOS tube, the first end of the first MOS tube is connected to a power supply voltage, the second end is connected to a first output node, the first end of the first resistor is connected to the first output node, the second end is connected to a reference potential, and the first output node is used to output a bandgap reference voltage V BG , characterized in that, The startup circuit is connected between the power supply voltage and the reference potential, and is connected to the bandgap reference circuit, and is used to pull up the voltage V on the first input terminal of the error amplifier. INN Or pull down the voltage V on the second input of the error amplifier INP , to reduce the voltage V at the output of the error amplifier EA .

2. The startup circuit for a bandgap reference circuit according to claim 1, characterized in that: The startup circuit includes a first soft start circuit; wherein, The first soft start circuit comprises a start control unit and a first adjustment unit. The start control unit is connected between the power supply voltage and the reference potential and is connected to the first output node for adjusting the power supply voltage based on the bandgap reference voltage V BG Generate a first startup current, the first regulating unit is connected to the startup control unit and to the first input terminal of the error amplifier, and is used to pull up the voltage V on the first input terminal of the error amplifier based on the first startup current INN ;or, The first soft start circuit includes a start control unit and a second adjustment unit. The start control unit is connected between the power supply voltage and the reference potential and is connected to the first output node for adjusting the start of the soft start circuit based on the bandgap reference voltage V BG The first startup current is generated, and the second regulating unit is connected to the startup control unit and to the second input terminal of the error amplifier, and is used to pull down the voltage V on the second input terminal of the error amplifier based on the first startup current. INP .

3. The startup circuit for a bandgap reference circuit according to claim 2, characterized in that: The startup control unit includes a second MOS tube, a third MOS tube and a second resistor; wherein, The control end of the second MOS tube is connected to the first output node, the first end is connected to the reference potential, the second end is connected to the second end of the second resistor, and the first end of the second resistor is connected to the power supply voltage; The control end of the third MOS tube is connected to the second end of the second MOS tube, the first end is connected to the reference potential, and the second end is connected to the first regulating unit and generates a first starting current.

4. The startup circuit for a bandgap reference circuit according to claim 2, characterized in that: The first regulating unit includes a fourth MOS tube and a fifth MOS tube; wherein, The second end of the fourth MOS tube is short-circuited with the control end, the second end is connected to the start control unit, and the first end is connected to the power supply voltage; The control end of the fifth MOS tube is connected to the control end of the fourth MOS tube, the first end is connected to the power supply voltage, and the second end is connected to the first input end of the error amplifier.

5. The startup circuit for a bandgap reference circuit according to claim 2, characterized in that: The second adjustment unit includes a first replication unit and a second replication unit; wherein, The first copy unit is connected to the start control unit and is used to copy the first start current to generate the first current; The second copy unit is connected to the first copy unit and to the second input terminal of the error amplifier, and is used for copying the first current to generate the second current.

6. The startup circuit for a bandgap reference circuit according to any one of claims 1 to 5, characterized in that: The startup circuit includes a second soft-start circuit, and the second soft-start circuit includes a reference voltage generating unit and a comparing unit; wherein, The reference voltage generating unit is connected between the power supply voltage and the reference potential and is connected to the output terminal of the error amplifier, and is used to generate a reference voltage at the second output node based on the voltage at the output terminal of the error amplifier; The comparison unit is connected to the second output node and the second input terminal of the error amplifier, and is used to compare the reference voltage with the voltage V on the second input terminal of the error amplifier. INP And generate a comparison signal.

7. The startup circuit for a bandgap reference circuit according to claim 6, characterized in that: The second soft start circuit further includes a third regulating unit, which is connected to the output end of the comparison unit and to the first input end of the error amplifier, and is used to pull up the voltage V on the first input end of the error amplifier based on the comparison signal. INN ;or, The second soft start circuit further includes a fourth regulating unit, which is connected to the output end of the comparison unit and to the second input end of the error amplifier, and is used to pull down the voltage V on the second input end of the error amplifier based on the comparison signal. INP .

8. The startup circuit for a bandgap reference circuit according to claim 6, characterized in that: The reference voltage generating unit includes a tenth MOS tube and a third resistor; wherein, The control end of the tenth MOS tube is connected to the output end of the error amplifier, the first end is connected to the power supply voltage, and the second end is connected to the second output node; The first end of the third resistor is connected to the second output node, and the second end is connected to the reference potential.

9. The startup circuit for a bandgap reference circuit according to claim 8, characterized in that: The emitter of the first bipolar transistor is connected to the first input terminal of the error amplifier, the base and the collector are short-circuited and connected to the reference potential, the first end of the first matching resistor is connected to the first input terminal of the error amplifier, and the second end is connected to the reference potential, the first end of the first PMOS tube is connected to the power supply voltage, the second end is connected to the first input terminal of the error amplifier, and the control end is connected to the output terminal of the error amplifier, the emitter of the second bipolar transistor is connected to the second end of the second matching resistor, the base and the collector are short-circuited and connected to the reference potential, the first end of the second matching resistor is connected to the second input terminal of the error amplifier, the first end of the third matching resistor is connected to the second input terminal of the error amplifier, and the second end is connected to the reference potential, the first end of the second PMOS tube is connected to the power supply voltage, the second end is connected to the second input terminal of the error amplifier, and the control end is connected to the output terminal of the error amplifier; The channel width-to-length ratio of the tenth MOS tube is equal to the channel width-to-length ratio of the second PMOS tube, and the third resistor is less than or equal to the third matching resistor; or, The channel width-to-length ratio of the tenth MOS tube is less than or equal to the channel width-to-length ratio of the second PMOS tube, and the third resistor is equal to the third matching resistor.

10. The startup circuit for a bandgap reference circuit according to claim 7, characterized in that: The third regulating unit includes an eleventh MOS tube, a first end of the eleventh MOS tube is connected to the power supply voltage, a control end is connected to the output end of the comparison unit, and a second end is connected to the first input end of the error amplifier. The eleventh MOS tube is used to generate a second starting current.

11. The startup circuit for a bandgap reference circuit according to claim 7, characterized in that: The fourth regulating unit includes an eleventh MOS tube and a third replicating unit; wherein, The first end of the eleventh MOS tube is connected to the power supply voltage, the control end is connected to the output end of the comparison unit, and the second end is connected to the third replication unit. The eleventh MOS tube is used to generate a second startup current; The third copy unit is connected to the second input terminal of the error amplifier and is used for copying the second startup current and generating a third current.

12. The startup circuit for a bandgap reference circuit according to claim 7, characterized in that: The comparison unit includes a hysteresis comparator, and the hysteresis comparator includes a current source, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube, a twenty-second MOS tube and an output node; wherein, The first end of the thirteenth MOS transistor is connected to the second end of the current source, the control end is connected to the second input end of the error amplifier, the second end is connected to the second end of the fifteenth MOS transistor, and the first end of the current source is connected to the power supply voltage; The first end of the fourteenth MOS tube is connected to the second end of the current source, the control end is connected to the second output node, and the second end is connected to the second end of the eighteenth MOS tube; The first end of the fifteenth MOS tube is connected to the reference potential, and the control end is short-circuited with the second end; the first end of the sixteenth MOS tube is connected to the reference potential, the control end is connected to the control end of the fifteenth MOS tube, and the second end is connected to the second end of the fourteenth MOS tube; The first end of the seventeenth MOS tube is connected to the reference potential, the control end is connected to the control end of the eighteenth MOS tube, and the second end is connected to the second end of the thirteenth MOS tube; The first end of the eighteenth MOS tube is connected to the reference potential, and the control end is short-circuited with the second end; The first end of the nineteenth MOS tube is connected to the reference potential, the control end is connected to the second end of the thirteenth MOS tube, and the second end is connected to the second end of the twenty-first MOS tube; The first end of the 20th MOS tube is connected to the reference potential, the control end is connected to the second end of the 14th MOS tube, and the second end is connected to the output node of the hysteresis comparator; The first end of the twenty-first MOS tube is connected to the power supply voltage, the control end is short-circuited with the second end, the first end of the twenty-second MOS tube is connected to the reference potential, the control end is connected to the control end of the twenty-first MOS tube, and the second end is connected to the output node of the hysteresis comparator.

13. The startup circuit for a bandgap reference circuit according to claim 12, characterized in that: The channel width-to-length ratio of the fifteenth MOS tube is greater than the channel width-to-length ratio of the sixteenth MOS tube; and / or, The channel width-to-length ratio of the seventeenth MOS tube is greater than the channel width-to-length ratio of the eighteenth MOS tube.

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