Multi-path calculator circuit, method for executing multiple calculation tasks by multi-path calculator circuit, and electronic chip

Abstract

The invention provides a multi-channel calculator circuit, which comprises a processing unit used for configuring calculation parameter information and calculation channel information, reading and storing the calculation parameter information and the calculation channel information according to a calculation mark signal, and reading calculation result information according to a corresponding channel completion signal; the parameter unit generates calculation parameter information, calculation channel information and detection trigger signals according to the configuration information; the detection unit is used for protecting the calculation parameter information and the calculation channel information according to the detection trigger signal, generating a calculation trigger signal and generating a calculation mark signal according to the state of the calculation unit; the calculation unit calculates the calculation parameter information according to the calculation trigger signal and generates calculation result information and a calculation completion signal; and the storage unit stores the calculation result information into a corresponding storage channel according to the calculation channel information and the calculation completion signal and generates a corresponding channel completion signal. The problem that in the prior art, a chip is large in occupied area or low in processing speed is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to a multi-channel calculator circuit and a method and electronic chip for executing multiple calculation tasks. Background Art

[0002] Many chips contain calculation functions such as multiplication, division, and square root. These calculation functions are generally implemented by software calculation or hardware calculation. The disadvantage of using software calculation is that the calculation time is long and the calculation speed is slow, which is not friendly to applications with strict time requirements. The disadvantage of using hardware calculation is that a calculator (multiplier, divider or square root calculator, etc.) can only perform one calculation task. When faced with multiple calculation tasks at the same time, multiple independent calculators need to be designed, which will greatly increase the chip area.

[0003] The specific analysis is as follows: When a calculator is used to process multiple calculation tasks at the same time, there are two situations in which calculation errors may occur. Take the 2-level division calculation task as an example to illustrate:

[0004] In the first case, when the division calculation task in the main function (i.e., level 1 division calculation task) is being calculated and enters the interrupt function, the division calculation task in the interrupt function (i.e., level 2 division calculation task) is triggered. At this time, the division calculation task in the interrupt function will interrupt and overwrite the division calculation task in the main function, resulting in calculation errors in the division calculation task in the main function.

[0005] In the second case, when the division calculation task in the main function (i.e., the level 1 division calculation task) has been configured with the dividend or divisor but has not started calculation, it enters the interrupt function, and the division calculation task in the interrupt function (i.e., the level 2 division calculation task) is triggered. At this time, the dividend and divisor of the division calculation task in the interrupt function will overwrite the dividend and divisor of the division calculation task in the main function, resulting in calculation errors in the division calculation task in the main function.

[0006] Therefore, no matter it is software calculation or hardware calculation, in order to ensure the calculation accuracy, usually several independent calculators are needed for several levels of calculation tasks. For example, a level 1 division calculation task requires 1 division operator, a level 2 division calculation task requires 2 division operators, a level 3 division calculation task requires 3 division operators, and so on.

[0007] However, for hardware calculations, the more calculators there are in the hardware, the larger the area occupied; for software calculations, the more calculators there are in the software, the longer the calculation time, the slower the calculation speed, and the more CPU resources occupied. In view of this, how to use a calculator to process multiple calculation tasks at the same time while taking into account the occupied area and calculation speed is a technical problem that technicians in this field urgently need to solve. Summary of the invention

[0008] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a multi-channel calculator circuit and a method and electronic chip for performing multiple computing tasks, which are used to solve the problem that the hardware computing solution or software computing solution of the existing chip cannot process multiple computing tasks simultaneously through one calculator, resulting in a large chip area or slow processing speed.

[0009] To achieve the above-mentioned object and other related objects, the present invention provides a multi-channel calculator circuit, the multi-channel calculator circuit comprising: a processing unit, a parameter unit, a detection unit, a calculation unit and a storage unit;

[0010] The processing unit is used to configure the calculation parameter information and the calculation channel information, read and store the calculation parameter information and the calculation channel information from the parameter unit according to the calculation flag signal, and read the calculation result information from the corresponding storage channel of the storage unit according to the corresponding channel completion signal, wherein the calculation flag signal includes a trigger busy flag signal and a calculation busy flag signal;

[0011] The parameter unit is connected to the processing unit and is used to generate the calculation parameter information, the calculation channel information and the detection trigger signal according to the configuration information;

[0012] The detection unit is connected to the parameter unit, and is used to protect the calculation parameter information and the calculation channel information according to the detection trigger signal and generate a calculation trigger signal, and generate the trigger busy flag signal and the calculation busy flag signal according to the state of the calculation unit;

[0013] The calculation unit is connected to the detection unit, and is used to calculate the calculation parameter information according to the calculation trigger signal and generate the calculation result information and the calculation completion signal;

[0014] The storage unit is connected to the detection unit and the calculation unit, and is used to store the calculation result information in the corresponding storage channel and generate the corresponding channel completion signal according to the calculation channel information and the calculation completion signal.

[0015] Optionally, the processing unit generates a corresponding parameter configuration signal when configuring each calculation parameter in the calculation parameter information, and generates a corresponding parameter reading signal when reading each calculation parameter in the calculation parameter information; the detection unit includes: a calculation channel module, M calculation parameter modules, a trigger generation module and a flag generation module, where M is an integer greater than or equal to 1;

[0016] The calculation channel module is connected to the parameter unit and is used to protect the calculation channel information according to the detection trigger signal;

[0017] M of the calculation parameter modules are connected to the parameter unit, and are used to protect each calculation parameter in the calculation parameter information according to the detection trigger signal;

[0018] The trigger generation module is connected to the parameter unit and is used to generate the calculation trigger signal according to the detection trigger signal;

[0019] The flag generation module is connected to the processing unit, the trigger generation module and the calculation unit, and is used to generate the trigger busy flag signal and the calculation busy flag signal, wherein the trigger busy flag signal is triggered by any of the parameter configuration signals, and the trigger busy flag signal is cleared by the calculation trigger signal or any of the parameter reading signals, and the calculation busy flag signal is triggered by the calculation trigger signal, and the calculation busy flag signal is cleared by the calculation completion signal.

[0020] Optionally, the calculation channel module includes: a first multiplexer and a first register, the selection end of the first multiplexer is connected to the detection trigger signal, the first input end is connected to the output end of the first register, the second input end is connected to the calculation channel information, the output end is connected to the input end of the first register, and the output end of the first register outputs the calculation channel information.

[0021] Optionally, the calculation parameter module includes: a second multiplexer and a second register, the selection end of the second multiplexer is connected to the detection trigger signal, the first input end is connected to the output end of the second register, the second input end is connected to the corresponding calculation parameter, the output end is connected to the input end of the second register, and the output end of the second register outputs the corresponding calculation parameter.

[0022] Optionally, the trigger generation module includes a D flip-flop.

[0023] Optionally, the flag generation module includes: a first OR gate, a second OR gate, a first RS trigger and a second RS trigger; the input end of the first OR gate is connected to each of the parameter configuration signals, and the output end is connected to the set end of the first RS trigger; the reset end of the first RS trigger is connected to the output end of the second OR gate, and the output end generates the trigger busy flag signal; the input end of the second OR gate is connected to the calculation trigger signal and each of the parameter reading signals; the set end of the second RS trigger is connected to the calculation trigger signal, the reset end is connected to the calculation completion signal, and the output end generates the calculation busy flag signal.

[0024] Optionally, the storage unit includes: an information conversion module and N storage channels, where N is an integer greater than 1;

[0025] The information conversion module is connected to the detection unit and is used to convert the calculation channel information into a channel selection signal, wherein the channel selection signal is a set of N-bit binary codes;

[0026] The N storage channels are connected to the calculation unit and the information conversion module, and are used to store the calculation result information into the corresponding storage channel and generate a corresponding channel completion signal according to the calculation completion signal and the channel selection signal.

[0027] Optionally, the processing unit generates a corresponding channel read signal when reading the calculation result information in the corresponding storage channel; the storage channel includes: an AND gate, a third multiplexer, a third register and a third RS flip-flop; the first input end of the AND gate is connected to the calculation completion signal, the second input end is connected to the corresponding bit of the channel selection signal, and the output end is connected to the selection end of the third multiplexer and the set end of the third RS flip-flop; the first input end of the third multiplexer is connected to the output end of the third register, the second input end is connected to the calculation result information, the output end is connected to the input end of the third register, and the output end of the third register outputs the calculation result information; the reset end of the third RS flip-flop is connected to the corresponding channel read signal, and the output end generates a corresponding channel completion signal.

[0028] The present invention also provides an electronic chip, comprising: a multi-channel calculator circuit as described in any one of the above.

[0029] The present invention further provides a method for a multi-channel calculator circuit as described in any one of the above items to perform multiple computing tasks, the method comprising:

[0030] Step 1) executing the previous level calculation task, the processing unit configures the previous level calculation parameter information and the previous level calculation channel information, the parameter unit generates the previous level calculation parameter information and the previous level calculation channel information according to the configuration information, and triggers the detection unit to protect the previous level calculation parameter information and the previous level calculation channel information, and the calculation unit calculates the previous level calculation parameter information;

[0031] When the next level of computing task arrives, the processing unit determines whether the trigger busy flag signal is valid; if valid, the previous level of computing parameter information and the previous level of computing channel information are read and stored from the parameter unit, and the next level of computing parameter information and the next level of computing channel information are configured. The parameter unit generates the next level of computing parameter information and the next level of computing channel information according to the configuration information, and triggers the detection unit to protect the next level of computing parameter information and the next level of computing channel information. The computing unit calculates the next level of computing parameter information, and then waits for the next level of computing task to be completed. The processing unit reads the calculation result information of the corresponding storage channel and then executes step 2); if invalid, executes step 3);

[0032] Step 2) the processing unit is reconfigured according to the stored previous level calculation parameter information and the previous level calculation channel information, the parameter unit generates the previous level calculation parameter information and the previous level calculation channel information according to the configuration information, and triggers the detection unit to protect the previous level calculation parameter information and the previous level calculation channel information, the calculation unit calculates the previous level calculation parameter information, and then waits for the previous level calculation task to be completed, and the processing unit reads the calculation result information of the corresponding storage channel;

[0033] Step 3) The processing unit determines whether the calculation busy flag signal is valid; if valid, wait for the previous level calculation task to be completed and read the calculation result information of the corresponding storage channel before executing step 4); if invalid, directly execute step 4);

[0034] Step 4) The processing unit configures the next level calculation parameter information and the next level calculation channel information, the parameter unit generates the next level calculation parameter information and the next level calculation channel information according to the configuration information, and triggers the detection unit to protect the next level calculation parameter information and the next level calculation channel information, the calculation unit calculates the next level calculation parameter information, and then waits for the next level calculation task to be completed, and the processing unit reads the calculation result information of the corresponding storage channel.

[0035] As described above, the multi-channel calculator circuit of the present invention and the method and electronic chip for performing multiple calculation tasks can perform on-site protection and on-site recovery of calculation parameter information and calculation channel information through the design of the processing unit, parameter unit, detection unit, calculation unit and storage unit, so that multiple calculation tasks can be performed simultaneously by only one calculator; the circuit of the present invention occupies a small area, has a fast calculation speed, occupies less CPU resources, and is simple and convenient to operate, and is suitable for single-level or multi-level calculation tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1Shown is a structural schematic diagram of the multi-channel calculator circuit of the present invention.

[0037] Figure 2 Shown is a schematic structural diagram of the detection unit of the present invention.

[0038] Figure 3 Shown is a schematic structural diagram of the storage unit of the present invention.

[0039] Figure 4 Shown is a flow chart of a method for a multi-channel calculator circuit of the present invention to perform multiple computing tasks.

[0040] Component number description

[0041] 10 Multi-channel calculator circuit

[0042] 100 Processing Units

[0043] 200 parameter units

[0044] 300 Detection Units

[0045] 310 Calculation channel module

[0046] 320 Calculation parameter module

[0047] 330 Trigger Generation Module

[0048] 340 Logo generation module

[0049] 400 computing units

[0050] 500 storage units

[0051] 510 Information conversion module

[0052] 520 storage channels DETAILED DESCRIPTION

[0053] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] See also Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0055] like Figure 1 As shown, this embodiment provides a multi-channel calculator circuit 10, including: a processing unit 100, a parameter unit 200, a detection unit 300, a calculation unit 400 and a storage unit 500.

[0056] The processing unit 100 is used to configure the calculation parameter information and the calculation channel information, read and store the calculation parameter information and the calculation channel information from the parameter unit 200 according to the calculation flag signal, and read the calculation result information from the corresponding storage channel of the storage unit 400 according to the corresponding channel completion signal; wherein the calculation flag signal includes a trigger busy flag signal TrigBusy and a calculation busy flag signal CalcBusy. As an example, the processing unit 100 is implemented by a processor.

[0057] In this embodiment, the processing unit 100 may configure the calculation parameter information and the calculation channel information for a single-level or multi-level calculation task. When configuring the calculation parameter information and the calculation channel information for a multi-level calculation task:

[0058] Since it is impossible to determine the time when the next level of computing task arrives, the processing unit 100 needs to determine the stage of the previous level of computing task according to the trigger busy flag signal TrigBusy and the calculation busy flag signal CalcBusy, such as the stage of being calculated, the stage of starting configuration or configuration completion but not yet starting calculation, the stage of calculation completion, the stage of not yet starting configuration, etc.;

[0059] If it is determined that the previous level computing task is currently in the computing stage, the processing unit 100 waits for the previous level computing task to be completed before configuring the computing parameter information and computing channel information required for the next level computing task;

[0060] If it is determined that the previous level computing task is currently in the stage of starting configuration or the configuration is completed but the calculation has not yet started, the processing unit 100 reads and stores the computing parameter information and computing channel information required for the previous level computing task from the parameter unit 200 for on-site protection, and then configures the computing parameter information and computing channel information required for the next level computing task. After the next level computing task is completed, the computing parameter information and computing channel information required for the previous level computing task are reconfigured based on the stored computing parameter information and computing channel information for on-site recovery.

[0061] If it is determined that the previous level computing task is currently in the computing completion stage or has not yet started the configuration stage, the processing unit 100 directly configures the computing parameter information and computing channel information required for the next level computing task.

[0062] It should be noted that, regardless of whether it is a single-level computing task or a multi-level computing task, the number of computing parameters in the computing parameter information involved in each level of computing task should be set according to actual needs. For example, if the computing task is a square root operation, the number of computing parameters is 1; if the computing task is a multiplication operation, division operation, etc., the number of computing parameters is greater than or equal to 2.

[0063] Taking the example that the number of storage channels in the multi-channel calculator circuit 10 of the present embodiment is N (N≥2), the storage channels are marked as 1 to N in sequence; regardless of whether it is a single-level computing task or a multi-level computing task, the computing channel information involved in each level of computing task can be any one of 1 to N; however, for multi-level computing tasks, the computing channel information involved in each level of computing tasks cannot be repeated, and is generally set in an increasing or decreasing order.

[0064] Furthermore, the processing unit 100 generates a corresponding parameter configuration signal when configuring each calculation parameter in the calculation parameter information (e.g., generating a first parameter configuration signal Data1Wr when configuring the first calculation parameter CalcData1, generating a second parameter configuration signal Data2Wr when configuring the second calculation parameter CalcData2, etc.), generates a corresponding parameter read signal when reading each calculation parameter in the calculation parameter information (e.g., generating a first parameter read signal Data1Rd when reading the first calculation parameter CalcData1, generating a second parameter read signal Data2Rd when reading the second calculation parameter CalcData2, etc.); generates a corresponding channel read signal when reading calculation result information from the corresponding storage channel (e.g., generating a first channel read signal Result1Rd when reading the calculation result information Result1 in the first storage channel, generating a second channel read signal Result2Rd when reading the calculation result information Result2 in the second storage channel, etc.).

[0065] The parameter unit 200 is connected to the processing unit 100, and is used to generate calculation parameter information, calculation channel information and a detection trigger signal DeteTrig according to the configuration information; wherein the detection trigger signal DeteTrig is generated after the calculation parameter information and the calculation channel information are generated.

[0066] The detection unit 300 is connected to the parameter unit 200 , and is used to protect the calculation parameter information and the calculation channel information according to the detection trigger signal DeteTrig and generate the calculation trigger signal CalcTrig, and generate the trigger busy flag signal TrigBusy and the calculation busy flag signal CalcBusy according to the state of the calculation unit 400 .

[0067] Specifically, Figure 2As shown, the detection unit 300 includes: a calculation channel module 310, M calculation parameter modules 320, a trigger generation module 330 and a flag generation module 340, wherein M is an integer greater than or equal to 1.

[0068] The calculation channel module 310 is connected to the parameter unit 200 and is used to protect the calculation channel information according to the detection trigger signal DeteTrig to prevent erroneous operation from changing the calculation channel information in the calculation, thereby preventing the calculation result from being stored incorrectly.

[0069] As an example, the calculation channel module 310 includes: a first multiplexer and a first register; wherein, the selection end (C end) of the first multiplexer is connected to the detection trigger signal DeteTrig, the first input end (S1 end) is connected to the output end (Q end) of the first register, the second input end (S2 end) is connected to the calculation channel information CalcNum, and the output end (D end) is connected to the input end (IN end) of the first register; the output end (Q end) of the first register outputs the calculation channel information CalcNum.

[0070] It should be noted that the enable terminals of the first multiplexer and the first register are not shown in the figure, but the first multiplexer and the first register should also include respective enable terminals, which are enabled by connecting corresponding enable signals. This is a known technology in the art and will not be described in detail.

[0071] In this embodiment, the detection trigger signal DeteTrig is valid at a high level; when the detection trigger signal DeteTrig is at a low level, the C terminal of the first multiplexer is connected to "0", at which time the S1 terminal of the first multiplexer is connected to the D terminal; when the detection trigger signal DeteTrig is at a high level, the C terminal of the first multiplexer is connected to "1", at which time the S2 terminal of the first multiplexer is connected to the D terminal; in this way, when the detection trigger signal DeteTrig is valid, the calculation channel information CalcNum is stored in the first register for protection.

[0072] M calculation parameter modules 320 are connected to the parameter unit 200, and are used to protect the calculation parameters CalcData1 to CalcDatam in the calculation parameter information according to the detection trigger signal DeteTrig, so as to prevent the calculation parameters in the calculation from being changed by erroneous operation, thereby preventing calculation errors. It should be noted that the number M of the calculation parameter modules 320 is determined by the number of calculation parameters in the calculation parameter information, and the two are equal; and the number of calculation parameters in the calculation parameter information should be set according to actual needs, and this embodiment does not limit this.

[0073] As an example, the calculation parameter module 320 includes: a second multiplexer and a second register; the selection end (C end) of the second multiplexer is connected to the detection trigger signal DeteTrig, the first input end (S1 end) is connected to the output end (Q end) of the second register, the second input end (S2 end) is connected to the corresponding calculation parameter, and the output end (D end) is connected to the input end (IN end) of the second register; the output end (Q end) of the second register outputs the corresponding calculation parameter.

[0074] It should be noted that the enable end of the second multiplexer and the second register is not shown in the figure, but the second multiplexer and the second register should also include respective enable ends, and the operation is enabled by connecting the corresponding enable signal. This is a well-known technology in the art and is therefore not described in detail.

[0075] In this embodiment, the detection trigger signal DeteTrig is valid at a high level; when the detection trigger signal DeteTrig is at a low level, the C terminal of the second multiplexer is connected to "0", at which time the S1 terminal of the second multiplexer is connected to the D terminal; when the detection trigger signal DeteTrig is at a high level, the C terminal of the second multiplexer is connected to "1", at which time the S2 terminal of the second multiplexer is connected to the D terminal; in this way, when the detection trigger signal DeteTrig is valid, each calculation parameter CalcData1~CalcDatam in the calculation parameter information is respectively stored in the second register in the corresponding calculation parameter module 320 for protection.

[0076] The trigger generation module 330 is connected to the parameter unit 200 and is used to generate a calculation trigger signal CalcTrig according to the detection trigger signal DeteTrig.

[0077] As an example, the trigger generation module 330 includes a D flip-flop; wherein the data terminal (D terminal) of the D flip-flop is connected to the detection trigger signal DeteTrig, and the output terminal (Q terminal) generates the calculation trigger signal CalcTrig. It should be noted that the clock terminal of the D flip-flop is not shown in the figure, but the D flip-flop should also include a clock terminal for providing a working clock, which is a well-known technology in the art and is therefore not described in detail.

[0078] In this embodiment, the detection trigger signal DeteTrig is valid at a high level; when the detection trigger signal DeteTrig is at a low level, the D flip-flop will output a low level when the next clock arrives, which is equivalent to not generating the calculation trigger signal CalcTrig; when the detection trigger signal DeteTrig is at a high level, the D flip-flop will output a high level when the next clock arrives, which is equivalent to generating the calculation trigger signal CalcTrig.

[0079] The flag generation module 340 is connected to the processing unit 100, the trigger generation module 330 and the calculation unit 400, and is used to generate a trigger busy flag signal TrigBusy and a calculation busy flag signal CalcBusy; wherein, the trigger busy flag signal TrigBusy is triggered by any parameter configuration signal, and the trigger busy flag signal TrigBusy is cleared by the calculation trigger signal CalcTrig or any parameter reading signal, and the calculation busy flag signal CalcBusy is triggered by the calculation trigger signal CalcTrig, and the calculation busy flag signal CalcBusy is cleared by the calculation completion signal CalcEnd.

[0080] As an example, the flag generation module 340 includes: a first OR gate, a second OR gate, a first RS trigger and a second RS trigger; the input end of the first OR gate is connected to the parameter configuration signals Data1Wr~DatamWr, and the output end is connected to the set end (S end) of the first RS trigger; the reset end (R end) of the first RS trigger is connected to the output end of the second OR gate, and the output end (Q end) generates the trigger busy flag signal TrigBusy; the input end of the second OR gate is connected to the calculation trigger signal CalcTrig and the parameter reading signals Data1Rd~DatamRd; the set end (S end) of the second RS trigger is connected to the calculation trigger signal CalcTrig, the reset end (R end) is connected to the calculation completion signal CalcEnd, and the output end (Q end) generates the calculation busy flag signal CalcBusy.

[0081] It should be noted that the clock terminals of the first RS trigger and the second RS trigger are not shown in the figure, but the first RS trigger and the second RS trigger should also include respective clock terminals for providing working clocks. This is a well-known technology in the art and will not be described in detail.

[0082] Wherein, the number of input terminals of the first OR gate and the second OR gate is determined by the number of calculation parameters in the calculation parameter information;

[0083] When the number of calculation parameters in the calculation parameter information is M=1, the number of input terminals of the first OR gate is (M+1), that is, 2, wherein one input terminal is connected to the parameter configuration signal and the other input terminal is connected to the low level; the number of input terminals of the second OR gate is (M+1), that is, 2, wherein one input terminal is connected to the calculation trigger signal and the other input terminal is connected to the parameter reading signal;

[0084] When the number of calculation parameters M ≥ 2 in the calculation parameter information, the number of input terminals of the first OR gate is M, wherein the M input terminals are correspondingly connected to M parameter configuration signals Data1Wr~DatamWr; the number of input terminals of the second OR gate is (M+1), wherein one input terminal is connected to the calculation trigger signal CalcTrig, and the remaining M input terminals are correspondingly connected to M parameter read signals Data1Rd~DatamRd.

[0085] In this embodiment, each parameter configuration signal Data1Wr~DatamWr and each parameter reading signal Data1Rd~DatamRd are high level valid. When any one of the parameter configuration signals Data1Wr~DatamWr is "1", the first OR gate outputs "1", and the output of the first RS flip-flop is set to 1, that is, the busy flag signal TrigBusy is triggered to be "1", and the trigger busy flag signal is triggered; and when the calculation trigger signal CalcTrig is "1" or any one of the parameter reading signals Data1Rd~DatamRd is "1", the second OR gate outputs "1", and the output of the first RS flip-flop is cleared to zero, that is, the busy flag signal TrigBusy is triggered to be "0", and the trigger busy flag signal is cleared to zero;

[0086] Among them, the trigger busy flag signal TrigBusy is "1", indicating that the processing unit 100 has started to configure the calculation parameter information, but the calculation unit 400 has not started the calculation. At this time, if the next-level calculation task arrives, the processing unit 100 needs to read out the calculation parameter information and calculation channel information required for the previous-level calculation task and store them (protect the scene) before configuring the calculation parameter information and calculation channel information required for the next-level calculation task. After the next-level calculation task is completed, the stored calculation parameter information and calculation channel information required for the previous-level calculation task shall be reconfigured (restoring the scene) to avoid calculation errors caused by the previous-level calculation task being overwritten by the configuration.

[0087] When the calculation trigger signal CalcTrig is "1", the output of the second RS flip-flop is set to 1, that is, the calculation busy flag signal CalcBusy is "1", and the calculation busy flag signal CalcBusy is triggered; and when the calculation completion signal CalcEnd is "1", the output of the second RS flip-flop is cleared, that is, the calculation busy flag signal CalcBusy is "0", and the calculation busy flag signal CalcBusy is cleared;

[0088] Among them, the calculation busy flag signal CalcBusy is "1" indicating that the calculation unit 400 is calculating. At this time, if a next-level calculation task arrives, the processing unit 100 needs to wait until the previous-level calculation task is completed before configuring the calculation parameter information and calculation channel information required for the next-level calculation task. Otherwise, the previous-level calculation task will have a calculation error due to the configuration being overwritten.

[0089] The calculation unit 400 is connected to the detection unit 300, and is used to calculate the calculation parameter information according to the calculation trigger signal CalcTrig and generate calculation result information and a calculation completion signal CalcEnd.

[0090] Among them, the calculation unit 400 can be a functional unit that performs multiplication, division, addition, subtraction, square root or compound operation on each calculation parameter in the calculation parameter information. The specific operation performed has no substantial impact on this embodiment.

[0091] In this embodiment, the calculation unit 400 is triggered to work by the calculation trigger signal CalcTrig, performs a specific operation on each calculation parameter in the calculation parameter information to generate calculation result information, and generates a calculation completion signal CalcEnd after the calculation is completed.

[0092] The storage unit 500 is connected to the detection unit 300 and the calculation unit 400, and is used to store the calculation result information in the corresponding storage channel and generate the corresponding channel completion signal according to the calculation channel information CalcNum and the calculation completion signal CalcEnd.

[0093] Specifically, Figure 3 As shown, the storage unit 500 includes: an information conversion module 510 and N storage channels 520, where N is an integer greater than 1.

[0094] The information conversion module 510 is connected to the detection unit 300 and is used to convert the calculation channel information CalcNum into a channel selection signal, wherein the channel selection signal is a set of N-bit binary codes, such as Sele1~Selen; during conversion, the binary code of the corresponding bit is set to 1 according to the calculation channel information, and the binary codes of the remaining bits are set to 0.

[0095] The N storage channels 520 are connected to the calculation unit 400 and the information conversion module 510, and are used to store the calculation result information into the corresponding storage channel and generate the corresponding channel completion signal according to the calculation completion signal CalcEnd and the channel selection signal.

[0096] As an example, the storage channel 520 includes: an AND gate, a third multiplexer, a third register and a third RS flip-flop; the first input terminal of the AND gate is connected to the calculation completion signal CalcEnd, the second input terminal is connected to the corresponding bit of the channel selection signal, and the output terminal is connected to the selection terminal (C terminal) of the third multiplexer and the set terminal (S terminal) of the third RS flip-flop; the first input terminal (S1 terminal) of the third multiplexer is connected to the output terminal (Q terminal) of the third register, the second input terminal (S2 terminal) is connected to the calculation result information, the output terminal (D terminal) is connected to the input terminal (IN terminal) of the third register, and the output terminal (Q terminal) of the third register outputs the calculation result information; the reset terminal (R terminal) of the third RS flip-flop is connected to the corresponding channel read signal, and the output terminal (Q terminal) generates the corresponding channel completion signal.

[0097] It should be noted that the enable end of the third multiplexer and the third memory and the clock end of the third RS trigger are not shown in the figure, but the third multiplexer and the third memory should also include their own enable ends, which are enabled by connecting the corresponding enable signals. The third RS trigger should also include a clock end for providing a working clock. This is a well-known technology in the art and will not be described in detail.

[0098] In this embodiment, when the storage unit 500 receives the calculation completion signal CalcEnd output by the calculation unit 400 (the calculation completion signal CalcEnd is high level valid), if the calculation channel information CalcNum=1, the channel selection signals Sele1~Selen are 1000..., at this time, the AND gate in the first storage channel 520 outputs "1", and the AND gates in the other storage channels 520 output "0", so that the C end of the third multiplexer in the first storage channel 520 is connected to "1", the S2 end is connected to the D end, the calculation result information is stored in the third register in the first storage channel 520 and then output, and at the same time, the output of the third RS flip-flop in the first storage channel 520 is set to 1, that is, the first channel completion signal OK1 is generated; at this time, the processing unit 100 reads the calculation result information Result1 from the third register of the first storage channel according to the first channel completion signal OK1 and generates the first channel read signal Result1Rd, and the first channel read signal Result1Rd can clear the output of the third RS flip-flop in the first storage channel 520. The working principles of other storage channels are the same, and will not be repeated here. A channel mode is established to store the calculation result information of each level of calculation tasks separately. For example, the calculation result information of each level of calculation tasks is stored in different storage channels respectively, which can avoid the problem of calculation result information of multiple calculation tasks being overwritten and storage confusion.

[0099] Correspondingly, such as Figure 4As shown, this embodiment also provides a method for the multi-channel calculator circuit 10 as described above to perform multiple computing tasks, the method comprising the following steps:

[0100] Step 1) Execute the previous level calculation task, the processing unit 100 configures the previous level calculation parameter information and the previous level calculation channel information, the parameter unit 200 generates the previous level calculation parameter information and the previous level calculation channel information according to the configuration information, and triggers the detection unit 300 to protect the previous level calculation parameter information and the previous level calculation channel information, and the calculation unit 400 calculates the previous level calculation parameter information;

[0101] When the next level of computing task arrives, the processing unit 100 determines whether the trigger busy flag signal TrigBusy is valid; if it is valid, it means that the circuit is in the stage of starting configuration or configuration is completed but calculation has not yet started, then the processing unit 100 reads and stores the previous level of computing parameter information and the previous level of computing channel information from the parameter unit 200 for on-site protection, configures the next level of computing parameter information and the next level of computing channel information, the parameter unit 200 generates the next level of computing parameter information and the next level of computing channel information according to the configuration information, and triggers the detection unit 300 to protect the next level of computing parameter information and the next level of computing channel information, the computing unit 400 calculates the next level of computing parameter information, and then waits for the next level of computing task to be completed, the processing unit 100 reads the calculation result information of the corresponding storage channel and executes step 2); if it is invalid, it means that the circuit is in the stage of not yet starting configuration, the stage of computing or the stage of computing completion, then executes step 3).

[0102] Step 2) The processing unit 100 is reconfigured according to the stored previous level calculation parameter information and the previous level calculation channel information for on-site recovery, the parameter unit 200 generates the previous level calculation parameter information and the previous level calculation channel information according to the configuration information, and triggers the detection unit 300 to protect the previous level calculation parameter information and the previous level calculation channel information, the calculation unit 400 calculates the previous level calculation parameter information, and then waits for the previous level calculation task to be completed, and the processing unit 100 reads the calculation result information of the corresponding storage channel.

[0103] Step 3) The processing unit 100 determines whether the calculation busy flag signal CalcBusy is valid; if it is valid, it means that the circuit is in the calculation stage, and the processing unit 100 waits for the previous level calculation task to be completed and reads the calculation result information of the corresponding storage channel before executing step 4); if it is invalid, it means that the circuit is in the stage where the configuration has not yet started or the calculation is completed, and step 4) is directly executed.

[0104] Step 4) The processing unit 100 configures the next level calculation parameter information and the next level calculation channel information, the parameter unit 200 generates the next level calculation parameter information and the next level calculation channel information according to the configuration information, and triggers the detection unit 300 to protect the next level calculation parameter information and the next level calculation channel information, the calculation unit 400 calculates the next level calculation parameter information, and then waits for the next level calculation task to be completed, and the processing unit 100 reads the calculation result information of the corresponding storage channel.

[0105] In the above steps, the parameter unit 200 generates the detection trigger signal DeteTrig after generating the calculation parameter information and calculation channel information of any level. The detection unit 300 protects the calculation parameter information and calculation channel information of the current level according to the detection trigger signal DeteTrig and generates the calculation trigger signal CalcTrig. The calculation unit 400 calculates the calculation parameter information of the current level according to the calculation trigger signal CalcTrig to generate calculation result information and a calculation completion signal. The storage unit 500 stores the calculation result information in the corresponding storage channel according to the calculation channel information and the calculation completion signal and generates a corresponding channel completion signal. The processing unit 100 then reads the calculation result information from the corresponding storage channel according to the corresponding channel completion signal.

[0106] Below, the specific process of the multi-channel calculator circuit 10 performing multiple computing tasks is explained through different examples; here only a three-level division computing task (involving a total of three storage channels and each level of division computing task involves two computing parameters) is taken as an example, and there is no restriction on the number of levels of multi-computing tasks, the number of storage channels and the number of computing parameters.

[0107] First example:

[0108] Step 1: Execute the first-level division calculation task. The processing unit 100 configures the first-level calculation parameter information (such as CalcData11 and CalcData21) and the first-level calculation channel information (such as CalcNum=1). The parameter unit 200 generates CalcData11, CalcData21, and CalcNum=1 according to the configuration information and triggers the detection unit 300 to protect CalcData11, CalcData21, and CalcNum=1. The calculation unit 400 performs a division operation on CalcData11 and CalcData21.

[0109] When the second-level division calculation task arrives, the processing unit 100 determines that the trigger busy flag signal TrigBusy is "0", and then the processing unit 100 continues to determine whether the calculation busy flag signal CalcBusy is "1". If it is "1", the processing unit 100 waits for the first channel completion signal OK1 to be "1" and reads the calculation result information Result1 of the first storage channel before executing the second step, otherwise it directly executes the second step;

[0110] Step 2: The processing unit 100 configures the second-level calculation parameter information (such as CalcData12 and CalcData22) and the second-level calculation channel information (such as CalcNum=2), the parameter unit 200 generates CalcData12, CalcData22, and CalcNum=2 according to the configuration information and triggers the detection unit 300 to protect CalcData12, CalcData22, and CalcNum=2, and the calculation unit 400 performs a division operation on CalcData12 and CalcData22;

[0111] When the third-level division calculation task arrives, the processing unit 100 determines that the trigger busy flag signal TrigBusy is "0", and then the processing unit 100 continues to determine whether the calculation busy flag signal CalcBusy is "1". If it is "1", the processing unit 100 waits for the second channel completion signal OK2 to be "1" and reads the calculation result information Result2 of the second storage channel before executing the third step, otherwise it directly executes the third step;

[0112] Step 3: The processing unit 100 configures the third-level calculation parameter information (such as CalcData13 and CalcData23) and the third-level calculation channel information (such as CalcNum=3), the parameter unit 200 generates CalcData13, CalcData23, CalcNum=3 according to the configuration information and triggers the detection unit 300 to protect CalcData13, CalcData23, CalcNum=3, the calculation unit 400 performs division operation on CalcData13 and CalcData23, and then the processing unit 100 waits for the third channel completion signal OK3 to be "1" and reads the calculation result information Result3 of the third storage channel.

[0113] Second example:

[0114] Step 1: Execute the first-level division calculation task. The processing unit 100 configures the first-level calculation parameter information (such as CalcData11 and CalcData21) and the first-level calculation channel information (such as CalcNum=1). The parameter unit 200 generates CalcData11, CalcData21, and CalcNum=1 according to the configuration information and triggers the detection unit 300 to protect CalcData11, CalcData21, and CalcNum=1. The calculation unit 400 performs a division operation on CalcData11 and CalcData21.

[0115] When the second-level division calculation task arrives, the processing unit 100 determines that the trigger busy flag signal TrigBusy is "0", and then the processing unit 100 continues to determine whether the calculation busy flag signal CalcBusy is "1". If it is "1", the processing unit 100 waits for the first channel completion signal OK1 to be "1" and reads the calculation result information Result1 of the first storage channel before executing the second step, otherwise it directly executes the second step;

[0116] Step 2: The processing unit 100 configures the second-level calculation parameter information (such as CalcData12 and CalcData22) and the second-level calculation channel information (such as CalcNum=2), the parameter unit 200 generates CalcData12, CalcData22, and CalcNum=2 according to the configuration information and triggers the detection unit 300 to protect CalcData12, CalcData22, and CalcNum=2, and the calculation unit 400 performs a division operation on CalcData12 and CalcData22;

[0117] When the third-level division calculation task arrives, the processing unit 100 determines that the trigger busy flag signal TrigBusy is "1", then the processing unit 100 reads and stores CalcData12, CalcData22, and CalcNum=2 from the parameter unit 200 for on-site protection, configures the third-level calculation parameter information (such as CalcData13 and CalcData23) and the third-level calculation channel information (such as CalcNum=3), the parameter unit 200 generates CalcData13, CalcData23, and CalcNum=3 according to the configuration information and triggers the detection unit 300 to protect CalcData13, CalcData23, and CalcNum=3, the calculation unit 400 performs division operation on CalcData13 and CalcData23, and then the processing unit 100 waits for the third channel completion signal OK to be "0". 1" and reads the calculation result information Result3 of the third storage channel; finally, the processing unit 100 reconfigures the relevant information of the second-level division calculation task (such as the second-level calculation parameter information and the second-level calculation channel information) according to the stored CalcData12, CalcData22, and CalcNum=2 for on-site recovery, the parameter unit 200 generates CalcData12, CalcData22, and CalcNum=2 according to the configuration information and triggers the detection unit 300 to protect CalcData12, CalcData22, and CalcNum=2, the calculation unit 400 performs a division operation on CalcData12 and CalcData22, that is, executes the second-level division calculation task, and then the processing unit 100 waits for the second channel completion signal OK2 to be "1" and reads the calculation result information Result2 of the second storage channel.

[0118] The third example:

[0119] Step 1: Execute the first-level division calculation task. The processing unit 100 configures the first-level calculation parameter information (such as CalcData11 and CalcData21) and the first-level calculation channel information (such as CalcNum=1). The parameter unit 200 generates CalcData11, CalcData21, and CalcNum=1 according to the configuration information and triggers the detection unit 300 to protect CalcData11, CalcData21, and CalcNum=1. The calculation unit 400 performs a division operation on CalcData11 and CalcData21.

[0120] When the second-level division calculation task arrives, the processing unit 100 determines that the trigger busy flag signal TrigBusy is "1", the processing unit 100 reads and stores CalcData11, CalcData21, and CalcNum=1 from the parameter unit 200 for on-site protection, configures the second-level calculation parameter information (such as CalcData12 and CalcData22) and the second-level calculation channel information (such as CalcNum=2), the parameter unit 200 generates CalcData12, CalcData22, and CalcNum=2 according to the configuration information, and triggers the detection unit 300 to protect CalcData12, CalcData22, and CalcNum=2, and the calculation unit 400 performs a division operation on CalcData12 and CalcData22;

[0121] When the third-level division calculation task arrives, the processing unit 100 determines that the trigger busy flag signal TrigBusy is "0", and then the processing unit 100 continues to determine whether the calculation busy flag signal CalcBusy is "1". If it is "1", the processing unit 100 waits for the second channel completion signal OK2 to be "1" and reads the calculation result information Result2 of the second storage channel before executing the second step, otherwise it directly executes the second step;

[0122] Step 2: The processing unit 100 configures the third-level calculation parameter information (such as CalcData13 and CalcData23) and the third-level calculation channel information (such as CalcNum=3), the parameter unit 200 generates CalcData13, CalcData23, CalcNum=3 according to the configuration information and triggers the detection unit 300 to protect CalcData13, CalcData23, CalcNum=3, the calculation unit 400 performs a division operation on CalcData13 and CalcData23, and then the processing unit 100 waits for the third channel completion signal OK3 to be "1" and reads the calculation result information Result3 of the third storage channel; finally, the processing unit 100 performs a calculation according to the stored CalcData13. Data11, CalcData21, CalcNum=1 reconfigure the relevant information of the first-level division calculation task (such as the first-level calculation parameter information and the first-level calculation channel information) for on-site recovery, the parameter unit 200 generates CalcData11, CalcData21, CalcNum=1 according to the configuration information and triggers the detection unit 300 to protect CalcData11, CalcData21, CalcNum=1, the calculation unit 400 performs division operation on CalcData11 and CalcData21, that is, executes the first-level division calculation task, after which the processing unit 100 waits for the first channel completion signal OK1 to be "1" and reads the calculation result information Result1 of the first storage channel.

[0123] Fourth example:

[0124] Step 1: Execute the first-level division calculation task. The processing unit 100 configures the first-level calculation parameter information (such as CalcData11 and CalcData21) and the first-level calculation channel information (such as CalcNum=1). The parameter unit 200 generates CalcData11, CalcData21, and CalcNum=1 according to the configuration information and triggers the detection unit 300 to protect CalcData11, CalcData21, and CalcNum=1. The calculation unit 400 performs a division operation on CalcData11 and CalcData21.

[0125] When the second-level division calculation task arrives, the processing unit 100 determines that the trigger busy flag signal TrigBusy is "1", the processing unit 100 reads and stores CalcData11, CalcData21, and CalcNum=1 from the parameter unit 200 for on-site protection, configures the second-level calculation parameter information (such as CalcData12 and CalcData22) and the second-level calculation channel information (such as CalcNum=2), the parameter unit 200 generates CalcData12, CalcData22, and CalcNum=2 according to the configuration information, and triggers the detection unit 300 to protect CalcData12, CalcData22, and CalcNum=2, and the calculation unit 400 performs a division operation on CalcData12 and CalcData22;

[0126] When the third-level division calculation task arrives, the processing unit 100 determines that the trigger busy flag signal TrigBusy is "1", the processing unit 100 reads and stores CalcData12, CalcData22, and CalcNum=2 from the parameter unit 200 for field protection, configures the third-level calculation parameter information (such as CalcData13 and CalcData23) and the third-level calculation channel information (such as CalcNum=3), and the parameter unit 200 generates CalcData13, CalcData23, and CalcNum=3 according to the configuration information and triggers the detection unit 300 to process CalcData13, CalcData23, and CalcNum=3. lcData23, CalcNum=3 are protected, the calculation unit 400 performs a division operation on CalcData13 and CalcData23, and then the processing unit 100 waits for the third channel completion signal OK3 to be "1" and reads the calculation result information Result3 of the third storage channel; then, the processing unit 100 reconfigures the relevant information of the second-level division calculation task (such as the second-level calculation parameter information and the second-level calculation channel information) according to the stored CalcData12, CalcData22, CalcNum=2 for on-site recovery, and the parameter unit 200 generates CalcData13 according to the configuration information. 12, CalcData22, CalcNum=2 and trigger the detection unit 300 to protect CalcData12, CalcData22, CalcNum=2, the calculation unit 400 divides CalcData12 and CalcData22, that is, executes the second-level division calculation task, after which the processing unit 100 waits for the second channel completion signal OK2 to be "1" and reads the calculation result information Result2 of the second storage channel; finally, the processing unit 100 reconfigures the first-level division calculation task according to the stored CalcData11, CalcData21, CalcNum=1 The parameter unit 200 generates CalcData11, CalcData21, and CalcNum=1 according to the configuration information and triggers the detection unit 300 to protect CalcData11, CalcData21, and CalcNum=1. The calculation unit 400 performs a division operation on CalcData11 and CalcData21, that is, executes the first-level division calculation task. After that, the processing unit 100 waits for the first channel completion signal OK1 to be "1" and reads the calculation result information Result1 of the first storage channel.

[0127] Accordingly, this embodiment also provides an electronic chip, including: the multi-channel calculator circuit 10 as described above; of course, the electronic chip may also include other functional circuits, which has no substantial impact on this embodiment. It should be noted that the electronic chip can be any chip with computing function, and this embodiment does not limit this.

[0128] In summary, the multi-channel calculator circuit and its method and electronic chip for performing multiple calculation tasks of the present invention can perform on-site protection and on-site recovery of calculation parameter information and calculation channel information through the design of processing unit, parameter unit, detection unit, calculation unit and storage unit, so as to realize that multiple calculation tasks can be performed simultaneously by only one calculator; the circuit of the present invention occupies a small area, has a fast calculation speed, occupies less CPU resources, and is simple and convenient to operate, and is suitable for single-level or multi-level calculation tasks. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0129] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A multi-channel calculator circuit, characterized in that: The multi-channel calculator circuit comprises: a processing unit, a parameter unit, a detection unit, a calculation unit and a storage unit; The processing unit is used to configure the calculation parameter information and the calculation channel information, read and store the calculation parameter information and the calculation channel information from the parameter unit according to the calculation flag signal, and read the calculation result information from the corresponding storage channel of the storage unit according to the corresponding channel completion signal, wherein the calculation flag signal includes a trigger busy flag signal and a calculation busy flag signal; The parameter unit is connected to the processing unit and is used to generate the calculation parameter information, the calculation channel information and the detection trigger signal according to the configuration information; The detection unit is connected to the parameter unit, and is used to protect the calculation parameter information and the calculation channel information according to the detection trigger signal and generate a calculation trigger signal, and generate the trigger busy flag signal and the calculation busy flag signal according to the state of the calculation unit; The calculation unit is connected to the detection unit, and is used to calculate the calculation parameter information according to the calculation trigger signal and generate the calculation result information and the calculation completion signal; The storage unit is connected to the detection unit and the calculation unit, and is used to store the calculation result information in the corresponding storage channel and generate the corresponding channel completion signal according to the calculation channel information and the calculation completion signal.

2. The multi-channel calculator circuit according to claim 1, characterized in that: The processing unit generates a corresponding parameter configuration signal when configuring each calculation parameter in the calculation parameter information, and generates a corresponding parameter reading signal when reading each calculation parameter in the calculation parameter information; the detection unit includes: a calculation channel module, M calculation parameter modules, a trigger generation module and a flag generation module, where M is an integer greater than or equal to 1; The calculation channel module is connected to the parameter unit and is used to protect the calculation channel information according to the detection trigger signal; M of the calculation parameter modules are connected to the parameter unit, and are used to protect each calculation parameter in the calculation parameter information according to the detection trigger signal; The trigger generation module is connected to the parameter unit and is used to generate the calculation trigger signal according to the detection trigger signal; The flag generation module is connected to the processing unit, the trigger generation module and the calculation unit, and is used to generate the trigger busy flag signal and the calculation busy flag signal, wherein the trigger busy flag signal is triggered by any of the parameter configuration signals, and the trigger busy flag signal is cleared by the calculation trigger signal or any of the parameter reading signals, and the calculation busy flag signal is triggered by the calculation trigger signal, and the calculation busy flag signal is cleared by the calculation completion signal.

3. The multi-channel calculator circuit according to claim 2, characterized in that: The calculation channel module includes: a first multiplexer and a first register, wherein the selection end of the first multiplexer is connected to the detection trigger signal, the first input end is connected to the output end of the first register, the second input end is connected to the calculation channel information, the output end is connected to the input end of the first register, and the output end of the first register outputs the calculation channel information.

4. The multi-channel calculator circuit according to claim 2 or 3, characterized in that: The calculation parameter module includes: a second multiplexer and a second register, the selection end of the second multiplexer is connected to the detection trigger signal, the first input end is connected to the output end of the second register, the second input end is connected to the corresponding calculation parameter, the output end is connected to the input end of the second register, and the output end of the second register outputs the corresponding calculation parameter.

5. The multi-channel calculator circuit according to claim 2, characterized in that: The trigger generation module includes a D flip-flop.

6. The multi-channel calculator circuit according to claim 2, characterized in that: The flag generation module includes: a first OR gate, a second OR gate, a first RS trigger and a second RS trigger; the input end of the first OR gate is connected to each of the parameter configuration signals, and the output end is connected to the set end of the first RS trigger; the reset end of the first RS trigger is connected to the output end of the second OR gate, and the output end generates the trigger busy flag signal; the input end of the second OR gate is connected to the calculation trigger signal and each of the parameter reading signals; the set end of the second RS trigger is connected to the calculation trigger signal, the reset end is connected to the calculation completion signal, and the output end generates the calculation busy flag signal.

7. The multi-channel calculator circuit according to claim 1, characterized in that: The storage unit includes: an information conversion module and N storage channels, where N is an integer greater than 1; The information conversion module is connected to the detection unit and is used to convert the calculation channel information into a channel selection signal, wherein the channel selection signal is a set of N-bit binary codes; The N storage channels are connected to the calculation unit and the information conversion module, and are used to store the calculation result information into the corresponding storage channel and generate a corresponding channel completion signal according to the calculation completion signal and the channel selection signal.

8. The multi-channel calculator circuit according to claim 7, characterized in that: The processing unit generates a corresponding channel read signal when reading the calculation result information in the corresponding storage channel; the storage channel includes: an AND gate, a third multiplexer, a third register and a third RS flip-flop; the first input end of the AND gate is connected to the calculation completion signal, the second input end is connected to the corresponding bit of the channel selection signal, and the output end is connected to the selection end of the third multiplexer and the set end of the third RS flip-flop; the first input end of the third multiplexer is connected to the output end of the third register, the second input end is connected to the calculation result information, the output end is connected to the input end of the third register, and the output end of the third register outputs the calculation result information; the reset end of the third RS flip-flop is connected to the corresponding channel read signal, and the output end generates a corresponding channel completion signal.

9. An electronic chip, characterized in that: The electronic chip comprises: a multi-channel calculator circuit as described in any one of claims 1-8.

10. A method for executing multiple computing tasks using a multi-channel calculator circuit as claimed in any one of claims 1 to 8, characterized in that: The method comprises: Step 1) executing the previous level calculation task, the processing unit configures the previous level calculation parameter information and the previous level calculation channel information, the parameter unit generates the previous level calculation parameter information and the previous level calculation channel information according to the configuration information, and triggers the detection unit to protect the previous level calculation parameter information and the previous level calculation channel information, and the calculation unit calculates the previous level calculation parameter information; When the next level of computing task arrives, the processing unit determines whether the trigger busy flag signal is valid; if valid, the previous level of computing parameter information and the previous level of computing channel information are read and stored from the parameter unit, and the next level of computing parameter information and the next level of computing channel information are configured. The parameter unit generates the next level of computing parameter information and the next level of computing channel information according to the configuration information, and triggers the detection unit to protect the next level of computing parameter information and the next level of computing channel information. The computing unit calculates the next level of computing parameter information, and then waits for the next level of computing task to be completed. The processing unit reads the calculation result information of the corresponding storage channel and then executes step 2); if invalid, executes step 3); Step 2) the processing unit is reconfigured according to the stored previous level calculation parameter information and the previous level calculation channel information, the parameter unit generates the previous level calculation parameter information and the previous level calculation channel information according to the configuration information, and triggers the detection unit to protect the previous level calculation parameter information and the previous level calculation channel information, the calculation unit calculates the previous level calculation parameter information, and then waits for the previous level calculation task to be completed, and the processing unit reads the calculation result information of the corresponding storage channel; Step 3) The processing unit determines whether the calculation busy flag signal is valid; if valid, wait for the previous level calculation task to be completed and read the calculation result information of the corresponding storage channel before executing step 4); if invalid, directly execute step 4); Step 4) The processing unit configures the next level calculation parameter information and the next level calculation channel information, the parameter unit generates the next level calculation parameter information and the next level calculation channel information according to the configuration information, and triggers the detection unit to protect the next level calculation parameter information and the next level calculation channel information, the calculation unit calculates the next level calculation parameter information, and then waits for the next level calculation task to be completed, and the processing unit reads the calculation result information of the corresponding storage channel.

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