A method and device for evaluating the accuracy of an in-memory computing system based on a memristor array

Abstract

The present application relates to the field of semiconductor technology, and provides a method and device for evaluating the accuracy of an in-memory computing system based on a memristor array, by establishing a baseline model for evaluating the computational accuracy of the in-memory computing system; obtaining multiple model write weights of the memristor array based on the baseline model; writing the multiple model write weights into the memristor array to obtain an in-memory computing model; inputting an initial input into the baseline model to obtain a baseline model output; inputting the initial input into the memristor array through the peripheral circuit to obtain an in-memory computing output; and evaluating the computational accuracy of the in-memory computing model based on the baseline model output and the in-memory computing output. This method can solve the problem that there is currently a lack of methods for accurately evaluating the accuracy of in-memory computing, which leads to the inability to accurately design in-memory computing chips, and can accurately evaluate the computational accuracy of in-memory computing, thereby providing a basis for designing in-memory computing chips.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method and device for evaluating the accuracy of an in-memory computing system based on a memristor array. Background Art

[0002] Compute-in-memory is the process of embedding computing tasks directly into data storage for processing, thereby avoiding the frequent data transmission and complex memory management in traditional computing models and improving computing efficiency and performance. However, there is currently a lack of methods to accurately evaluate the accuracy of in-memory computing, which makes it impossible to accurately design in-memory computing chips. Summary of the invention

[0003] The embodiments of the present application provide a method and device for evaluating the accuracy of an in-memory computing system based on a memristor array, which can solve the problem that there is currently a lack of methods for accurately evaluating the accuracy of in-memory computing, resulting in the inability to accurately design in-memory computing chips.

[0004] In a first aspect, an embodiment of the present application provides a method for evaluating the accuracy of an in-memory computing system based on a memristor array, wherein the in-memory computing system includes a memristor array and a peripheral circuit connected to the memristor array;

[0005] The method for evaluating the accuracy of an in-memory computing system based on a memristor array comprises:

[0006] Establishing a baseline model for evaluating the computational accuracy of the in-memory computing system;

[0007] Obtaining a plurality of model write weights of the memristor array based on the baseline model;

[0008] Writing a plurality of model write weights into the memristor array to obtain an in-memory computing model;

[0009] Inputting an initial input into the baseline model to obtain a baseline model output;

[0010] Inputting the initial input into the memristor array through the peripheral circuit to obtain an in-memory calculation output;

[0011] The computational accuracy of the in-memory computation model is evaluated based on the baseline model output and the in-memory computation output.

[0012] In some embodiments, establishing a baseline model for evaluating the computational accuracy of the in-memory computing system includes:

[0013] Get the MNIST dataset;

[0014] Preprocessing the MNIST data set to obtain a target data set;

[0015] The target data set is used to train the neural network model to be trained and quantized to obtain the baseline model.

[0016] In some embodiments, the preprocessing of the MNIST data set to obtain a target data set includes:

[0017] Eliminate edge areas of the data images in the MNIST data set to obtain a preliminary data set;

[0018] The characteristic size of the data images in the preliminary data set is adjusted to a preset size to obtain the target data set.

[0019] In some embodiments, obtaining a plurality of model write weights of the memristor array based on the baseline model includes:

[0020] Obtaining multiple model weights within the baseline model;

[0021] Modeling the resistance change of a memristor device , where R* is the actual resistance, R is the ideal resistance, and σ is the lognormal distribution parameter;

[0022] Setting a resistance offset correction amount based on the resistance change model;

[0023] A plurality of the model writing weights are obtained based on the resistance offset correction amount and the plurality of the model weights.

[0024] In some embodiments, writing the plurality of model write weights into the memristor array to obtain an in-memory computing model comprises:

[0025] Setting the number of memristor units corresponding to a write weight of the model;

[0026] Dividing the memristor array into a plurality of weight regions based on the number of memristor units;

[0027] The weights of the multiple models are written into the multiple weight areas one by one to obtain the in-memory computing model.

[0028] In some embodiments, the method for evaluating the accuracy of an in-memory computing system based on a memristor array further includes:

[0029] Adjusting the lognormal distribution parameters and obtaining the adjusted output of the in-memory computing model;

[0030] The accuracy of the device change impact of the in-memory calculation model is obtained based on the baseline model output and the output after resistance adjustment.

[0031] In some embodiments, the method for evaluating the accuracy of an in-memory computing system based on a memristor array further includes:

[0032] Adjusting the memory failure rate of the memristor array, and obtaining the adjusted post-fault adjustment output of the in-memory computing model;

[0033] The failure rate impact accuracy of the in-memory computing model is obtained based on the baseline model output and the fault-adjusted output.

[0034] In some embodiments, the peripheral circuit includes a digital-to-analog converter, and / or an analog-to-digital converter;

[0035] The in-memory computing system accuracy evaluation method based on the memristor array further includes:

[0036] Quantizing the in-memory computing model to obtain a quantized in-memory computing model;

[0037] The resolution of the digital-to-analog converter and / or the analog-to-digital converter is adjusted, and the accuracy of the quantization in-memory calculation model after the adjustment is measured.

[0038] In a second aspect, an embodiment of the present application provides an in-memory computing system accuracy evaluation device based on a memristor array, wherein the in-memory computing system includes a memristor array and a peripheral circuit connected to the memristor array;

[0039] The in-memory computing system accuracy evaluation device based on a memristor array comprises:

[0040] A baseline establishment module, used to establish a baseline model for evaluating the calculation accuracy of the in-memory computing system;

[0041] A weight calculation module, used for obtaining a plurality of model write weights of the memristor array based on the baseline model;

[0042] A model building module, used for writing a plurality of model write weights into the memristor array to obtain an in-memory computing model;

[0043] A model input module, used to input an initial input into the baseline model to obtain a baseline model output; input the initial input into the memristor array through the peripheral circuit to obtain an in-memory calculation output;

[0044] A model evaluation module is used to evaluate the calculation accuracy of the in-memory calculation model based on the baseline model output and the in-memory calculation output.

[0045] In a third aspect, an embodiment of the present application provides an electronic device, comprising an in-memory computing system accuracy assessment device based on a memristor array as described in any embodiment of the second aspect.

[0046] Compared with the prior art, the method and device for evaluating the accuracy of an in-memory computing system based on a memristor array provided in the present application establish a baseline model for evaluating the computational accuracy of the in-memory computing system; obtain multiple model write weights of the memristor array based on the baseline model; write the multiple model write weights into the memristor array to obtain an in-memory computing model; input an initial input into the baseline model to obtain a baseline model output; input the initial input into the memristor array through the peripheral circuit to obtain an in-memory computing output; and evaluate the computational accuracy of the in-memory computing model based on the baseline model output and the in-memory computing output. This can solve the problem that there is currently a lack of methods for accurately evaluating the accuracy of in-memory computing, which leads to the inability to accurately design in-memory computing chips, and can accurately evaluate the computational accuracy of in-memory computing, thereby providing a basis for designing in-memory computing chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Hereinafter, the present invention will be described in more detail based on embodiments and with reference to the accompanying drawings.

[0048] Figure 1 is a flow chart of an accuracy evaluation method for an in-memory computing system based on a memristor array provided by an embodiment of the present invention;

[0049] Figure 2 is a schematic diagram of a 1T1R memristor array provided by an embodiment of the present invention;

[0050] Figure 3 is a schematic diagram of a 2T2R memristor array provided by an embodiment of the present invention;

[0051] Figure 4 is a curve diagram showing the effect of device variation on accuracy provided by an embodiment of the present invention;

[0052] Figure 5 is a graph showing the effect of memory failure rate on accuracy provided by an embodiment of the present invention;

[0053] Figure 6 It is a schematic diagram of an in-memory computing system accuracy evaluation device based on a memristor array provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The present invention will be further described below in conjunction with the accompanying drawings.

[0055] In-memory computing is a computing model that places computing tasks directly inside the data memory for processing, avoiding overhead such as data transmission and memory management, while maximizing the parallelism of memory computing units. In traditional computing models, on the one hand, processors often need to access memory through a bus or network to obtain data, which leads to increased latency and decreased performance. On the other hand, as machine learning models become larger and larger, the computational workload during model inference increases dramatically, which requires advanced parallel computing architectures. Compute in memory (CIM) based on memristor array structures provides a promising solution to these problems. Memristor array structures inherently provide huge opportunities for parallelism.

[0056] Nowadays, Deep Neural Networks (DNN) have shown remarkable effectiveness in a wide range of tasks such as image recognition, target detection, language understanding and text generation. The main workload of DNN is matrix-vector multiplication (MVM). However, since memristor array computing is analog computing, it is usually performed in the form of current and is easily affected by non-ideal characteristics such as device changes and memory failures. It is also easily affected by peripheral circuits, thus affecting the computational accuracy of the in-memory computing system. The accuracy of in-memory computing directly determines the feasibility of in-memory computing chips. At present, there is a lack of methods to accurately evaluate the accuracy of in-memory computing, which makes it impossible to accurately design in-memory computing chips.

[0057] First, as Figure 1 As shown, an embodiment of the present application provides an accuracy evaluation method for an in-memory computing system based on a memristor array, wherein the in-memory computing system includes a memristor array and a peripheral circuit connected to the memristor array;

[0058] The method for evaluating the accuracy of an in-memory computing system based on a memristor array comprises:

[0059] S101: Establishing a baseline model for evaluating the calculation accuracy of the in-memory computing system;

[0060] In some embodiments, establishing a baseline model for evaluating the computational accuracy of the in-memory computing system includes:

[0061] Get the MNIST dataset;

[0062] Preprocessing the MNIST data set to obtain a target data set;

[0063] The target data set is used to train the neural network model to be trained and quantized to obtain the baseline model.

[0064] It should be noted that the baseline model refers to a simple, easy-to-implement benchmark model for comparison with more complex machine learning models. The MNIST dataset is a widely used handwritten digit recognition dataset, which contains thousands of digital images and is usually used to train and test image processing, machine learning and deep learning models. After training the neural network model to be trained using the target dataset, a preliminary baseline model can be obtained. The preliminary baseline model can be a two-layer MLP (Multilayer Perceptron) with a hidden layer size of 256. The preliminary baseline model is then quantized into INT8 format (i.e., the quantization process) to obtain the baseline model. The baseline model achieves an accuracy of 96.44% on the MNIST dataset.

[0065] In some embodiments, the preprocessing of the MNIST data set to obtain a target data set includes:

[0066] Eliminate edge areas of the data images in the MNIST data set to obtain a preliminary data set;

[0067] The characteristic size of the data images in the preliminary data set is adjusted to a preset size to obtain the target data set.

[0068] It should be noted that the preset size can be 512. By eliminating the edge area of ​​the data image and adjusting the feature size of the data image to the preset size, the amount of calculation during training can be reduced and the training speed can be improved. The edge area is a blank edge area in the data image without digital information. These blank edge areas are useless information and can be eliminated through image processing methods (such as cropping and normalization).

[0069] S102: Obtaining a plurality of model write weights of the memristor array based on the baseline model;

[0070] In some embodiments, obtaining a plurality of model write weights of the memristor array based on the baseline model includes:

[0071] Obtaining multiple model weights within the baseline model;

[0072] Modeling the resistance change of a memristor device , where R* is the actual resistance, R is the ideal resistance, and σ is the lognormal distribution parameter;

[0073] Setting a resistance offset correction amount based on the resistance change model;

[0074] A plurality of the model writing weights are obtained based on the resistance offset correction amount and the plurality of the model weights.

[0075] It should be noted that after obtaining the baseline model, the model weights in the baseline model can be obtained. However, considering that the resistance of the memristor device in the memristor array is not completely consistent with the set resistance, but there is a certain resistance offset, when writing weights to the memristor array, it is necessary to consider the influence of the resistance offset. By setting the resistance offset correction amount, the model weights in the baseline model can be corrected, thereby reducing the inaccuracy caused by the resistance offset of the memristor device. The resistance offset correction amount can be set according to the specific situation. According to experiments, σ ​​varies between 0.1 and 0.5, and the resistance change of the memristor device follows a log-normal distribution.

[0076] S103: writing a plurality of model write weights into the memristor array to obtain an in-memory computing model;

[0077] In some embodiments, writing the plurality of model write weights into the memristor array to obtain an in-memory computing model comprises:

[0078] Setting the number of memristor units corresponding to a write weight of the model;

[0079] Dividing the memristor array into a plurality of weight regions based on the number of memristor units;

[0080] The weights of the multiple models are written into the multiple weight areas one by one to obtain the in-memory computing model.

[0081] It should be noted that the number of memristor units corresponding to a model write weight can be set according to actual needs, such as Figure 2 As shown, in the 1T1R memristor array structure, two parallel memristor units can be used to represent a model write weight, such as Figure 3 As shown, in the 2T2R memristor array structure, a memristor unit includes two memristors, one representing the positive part and the other representing the negative part, which are arranged in sequence along the column, wherein the upper two memristors represent the positive part and the lower two memristors represent the negative part.

[0082] S104: inputting the initial input into the baseline model to obtain a baseline model output;

[0083] S105: inputting the initial input into the memristor array through the peripheral circuit to obtain an in-memory calculation output;

[0084] S106: Evaluate the computational accuracy of the in-memory computation model based on the baseline model output and the in-memory computation output.

[0085] It should be noted that when the initial input is input into the memristor array through the peripheral circuit, the peripheral circuit converts the initial digital input into an analog voltage in the memristor array, and then performs matrix-vector multiplication (MVM) in the memristor array. The calculation result is then output to the peripheral circuit and post-processed to obtain the in-memory calculation output. The calculation accuracy of the in-memory calculation model can be determined by comparing the baseline model output with the in-memory calculation output.

[0086] In some embodiments, the method for evaluating the accuracy of an in-memory computing system based on a memristor array further includes:

[0087] Adjusting the lognormal distribution parameters and obtaining the adjusted output of the in-memory computing model;

[0088] The accuracy of the device change impact of the in-memory calculation model is obtained based on the baseline model output and the output after resistance adjustment.

[0089] It should be noted that the resistance of a memristor device may change during use (device variation includes cycle-to-cycle variation, CCV, and device-to-device variation, DDV. CCV means that the resistance of the same memristor device is different when the same programming voltage is applied multiple times; DDV means that the resistance of two memristor devices is different under the same programming voltage). Figure 4 is a device variation impact accuracy curve diagram provided by an embodiment of the present invention; wherein, Figure 4 (a) is the output distribution of 2T2R with σ=0.5; Figure 4 (b) in the figure is the accuracy of 1T1R for various σ; Figure 4 (c) in the figure is the accuracy of 2T2R for various σ. Figure 4 As shown in (a), it is the distribution of MVM output in 2T2R memristor array when σ=0.5, where the slash is the case when the actual output is equal to the ideal output. When σ=0.5, the actual output slope of the memristor array is greater than the ideal output slope, which is due to the skewed logarithmic normal distribution characteristics of the resistance value of the memristor device. Figure 4 In (a), we can see that the actual output of the memristor array varies around the ideal output, and this variation does not significantly affect the calculation accuracy. Figure 4 (b) Figure 4As shown in (c) in Figure 1, although the computational accuracy of the memristor array decreases as σ increases, the worst accuracy drop is only 1% when σ = 0.5. The reason is that the prediction of the machine learning model is based on the index of the largest value in the final output, which is usually several times larger than the second largest value. Therefore, relatively small changes will not be affected much.

[0090] In some embodiments, the method for evaluating the accuracy of an in-memory computing system based on a memristor array further includes:

[0091] Adjusting the memory failure rate of the memristor array, and obtaining the adjusted post-fault adjustment output of the in-memory computing model;

[0092] The failure rate impact accuracy of the in-memory computing model is obtained based on the baseline model output and the fault-adjusted output.

[0093] It should be noted that due to the immaturity of manufacturing technology, memory failures are inevitable in large-scale memristor arrays. Among these failures, stuck-at failures are the most harmful. Stuck-at failures can be divided into two categories: resistance stuck at zero (SA0) and resistance stuck at one (SA1). SA0 means that the resistance of the memristor device is stuck at the lowest level and the conductance is correspondingly at the highest level; on the contrary, SA1 means that the resistance is always high and the conductance is always low. Previous studies have shown that the ratio of SA1 to SA0 is 9.04:1.74, which almost follows a random distribution. Therefore, when setting the memory failure rate, it is set to a ratio of SA1 to SA0 of 9.04:1.74, and the memory failure rate is adjusted to see the corresponding accuracy drop (that is, the failure affects the accuracy). Figure 5 is a graph showing the effect of memory failure rate on accuracy provided by an embodiment of the present invention; wherein, Figure 5 (a) is the output distribution of 1% failure rate in 2T2R; Figure 5 (b) shows the accuracy of 1T1R under various failure rates; Figure 5 (c) in the figure is the accuracy of 2T2R under various failure rates; Figure 5 (d) in the figure is the weight distribution of the baseline model; Figure 5 (e) in the figure is the accuracy of 1T1R at various SA0 rates; Figure 5 (f) in the figure is the accuracy of 1T1R at various SA1 rates. Figure 5 (b) Figure 5As shown in (c) in the figure, when the failure rate of the memory increases, the accuracy of the in-memory computing model decreases rapidly, showing a trend different from the change of the memristor device. The reason is still the computing mode of the machine learning model. When a stuck fault occurs, the weight is forced to be set to zero (SA1) or the maximum value (SA0), which may deviate significantly from the original value. This may cause the index of the maximum value in the final output to change, resulting in incorrect predictions. By further studying the decomposition effects of SA1 and SA0, which only contain one type of fault, it is found that SA0 is more harmful than SA1, as shown in Figure 2. Figure 5 (e) Figure 5 As shown in (f) in the figure, (the result of 2T2R memristor array is shown, and 1T1R is almost the same), the reason is that the weights of a well-trained model roughly follow a normal distribution or Laplace distribution with mean zero, for example, the weight distribution of the baseline model (such as Figure 5 As shown in (d) in the figure), in this case, SA0 (weights are stuck at the maximum value) tends to cause more significant weight changes than SA1, resulting in more serious accuracy degradation.

[0094] In some embodiments, the peripheral circuit includes a digital-to-analog converter, and / or an analog-to-digital converter;

[0095] The in-memory computing system accuracy evaluation method based on the memristor array further includes:

[0096] Quantizing the in-memory computing model to obtain a quantized in-memory computing model;

[0097] The resolution of the digital-to-analog converter and / or the analog-to-digital converter is adjusted, and the accuracy of the quantization in-memory calculation model after the adjustment is measured.

[0098] It should be noted that the quantization accuracy of the in-memory computing model needs to match the resolution of the ADC / DAC (i.e., the analog-to-digital converter, the digital-to-analog converter), that is, the accuracy of the ADC / DAC must meet the accuracy requirements of the input / output after the model is quantized, so as to avoid the loss of numerical information due to insufficient resolution. As shown in Table 1, as the resolution of the ADC / DAC decreases, the accuracy of the in-memory computing model first remains almost unchanged, which means that the numerical accuracy is still sufficient for accurate calculations, and then when the resolution is lower than 4 bits, the accuracy drops rapidly, so at least a 4-bit ADC / DAC is required.

[0099] Table 1 Accuracy table of different ADC / DAC resolutions

[0100]

[0101] In summary, the method and device for evaluating the accuracy of an in-memory computing system based on a memristor array provided in the present application establish a baseline model for evaluating the computational accuracy of the in-memory computing system; obtain multiple model write weights of the memristor array based on the baseline model; write the multiple model write weights into the memristor array to obtain an in-memory computing model; input an initial input into the baseline model to obtain a baseline model output; input the initial input into the memristor array through the peripheral circuit to obtain an in-memory computing output; and evaluate the computational accuracy of the in-memory computing model based on the baseline model output and the in-memory computing output. This can solve the problem that there is currently a lack of methods for accurately evaluating in-memory computing accuracy, which leads to the inability to accurately design in-memory computing chips.

[0102] Second, as Figure 6 As shown, an embodiment of the present application provides an in-memory computing system accuracy evaluation device based on a memristor array, wherein the in-memory computing system includes a memristor array and a peripheral circuit connected to the memristor array;

[0103] The in-memory computing system accuracy evaluation device based on a memristor array comprises:

[0104] A baseline establishing module 210, for establishing a baseline model for evaluating the calculation accuracy of the in-memory computing system;

[0105] A weight calculation module 220, configured to obtain a plurality of model write weights of the memristor array based on the baseline model;

[0106] A model building module 230, used for writing a plurality of model write weights into the memristor array to obtain an in-memory computing model;

[0107] A model input module 240 is used to input an initial input into the baseline model to obtain a baseline model output; input the initial input into the memristor array through the peripheral circuit to obtain an in-memory calculation output;

[0108] The model evaluation module 250 is used to evaluate the calculation accuracy of the in-memory calculation model based on the baseline model output and the in-memory calculation output.

[0109] In a third aspect, an embodiment of the present application provides an electronic device, comprising an in-memory computing system accuracy assessment device based on a memristor array as described in any embodiment of the second aspect.

[0110] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems, or apparatuses), and / or computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0111] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0112] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0113] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for evaluating the accuracy of an in-memory computing system based on a memristor array, characterized in that: The in-memory computing system includes a memristor array and a peripheral circuit connected to the memristor array; The method for evaluating the accuracy of an in-memory computing system based on a memristor array comprises: Establishing a baseline model for evaluating the computational accuracy of the in-memory computing system; Obtaining a plurality of model write weights of the memristor array based on the baseline model; Writing a plurality of model write weights into the memristor array to obtain an in-memory computing model; Inputting an initial input into the baseline model to obtain a baseline model output; Inputting the initial input into the memristor array through the peripheral circuit to obtain an in-memory calculation output; The computational accuracy of the in-memory computation model is evaluated based on the baseline model output and the in-memory computation output.

2. The method for evaluating the accuracy of an in-memory computing system based on a memristor array according to claim 1, characterized in that: The establishing of a baseline model for evaluating the computational accuracy of the in-memory computing system comprises: Get the MNIST dataset; Preprocessing the MNIST data set to obtain a target data set; The target data set is used to train the neural network model to be trained and quantized to obtain the baseline model.

3. The method for evaluating the accuracy of an in-memory computing system based on a memristor array according to claim 2, characterized in that: The preprocessing of the MNIST data set to obtain a target data set includes: Eliminate edge areas of the data images in the MNIST data set to obtain a preliminary data set; The characteristic size of the data images in the preliminary data set is adjusted to a preset size to obtain the target data set.

4. The method for evaluating the accuracy of an in-memory computing system based on a memristor array according to claim 1, characterized in that: The step of obtaining a plurality of model write weights of the memristor array based on the baseline model includes: Obtaining multiple model weights within the baseline model; Modeling the resistance change of a memristor device , where R* is the actual resistance, R is the ideal resistance, and σ is the lognormal distribution parameter; Setting a resistance offset correction amount based on the resistance change model; A plurality of the model writing weights are obtained based on the resistance offset correction amount and the plurality of the model weights.

5. The method for evaluating the accuracy of an in-memory computing system based on a memristor array according to claim 1, characterized in that: The step of writing the plurality of model write weights into the memristor array to obtain an in-memory computing model comprises: Setting the number of memristor units corresponding to a write weight of the model; Dividing the memristor array into a plurality of weight regions based on the number of memristor units; The weights of the multiple models are written into the multiple weight areas one by one to obtain the in-memory computing model.

6. The method for evaluating the accuracy of an in-memory computing system based on a memristor array according to claim 4, characterized in that: Also includes: Adjusting the lognormal distribution parameters and obtaining the adjusted output of the in-memory computing model; The accuracy of the device change impact of the in-memory calculation model is obtained based on the baseline model output and the output after resistance adjustment.

7. The method for evaluating the accuracy of an in-memory computing system based on a memristor array according to claim 1, characterized in that: Also includes: Adjusting the memory failure rate of the memristor array, and obtaining the adjusted post-fault adjustment output of the in-memory computing model; The failure rate impact accuracy of the in-memory computing model is obtained based on the baseline model output and the fault-adjusted output.

8. The method for evaluating the accuracy of an in-memory computing system based on a memristor array according to claim 1, characterized in that: The peripheral circuit includes a digital-to-analog converter and / or an analog-to-digital converter; The in-memory computing system accuracy evaluation method based on the memristor array further includes: Quantizing the in-memory computing model to obtain a quantized in-memory computing model; The resolution of the digital-to-analog converter and / or the analog-to-digital converter is adjusted, and the accuracy of the quantization in-memory calculation model after the adjustment is measured.

9. An in-memory computing system accuracy evaluation device based on a memristor array, characterized in that: The in-memory computing system includes a memristor array and a peripheral circuit connected to the memristor array; The in-memory computing system accuracy evaluation device based on a memristor array comprises: A baseline establishment module, used to establish a baseline model for evaluating the calculation accuracy of the in-memory computing system; A weight calculation module, used for obtaining a plurality of model write weights of the memristor array based on the baseline model; A model building module, used for writing a plurality of model write weights into the memristor array to obtain an in-memory computing model; A model input module, used to input an initial input into the baseline model to obtain a baseline model output; input the initial input into the memristor array through the peripheral circuit to obtain an in-memory calculation output; A model evaluation module is used to evaluate the calculation accuracy of the in-memory calculation model based on the baseline model output and the in-memory calculation output.

10. An electronic device, characterized in that: It includes the in-memory computing system accuracy evaluation device based on the memristor array as described in claim 9.

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