Communication address generation circuit, circuit system and electronic equipment

Abstract

The invention provides a communication address generation circuit, a circuit system and electronic equipment. The circuit comprises a first voltage division circuit, a first comparison circuit, a second comparison circuit and a latch circuit, a first voltage division circuit outputs a corresponding voltage signal according to an address selection circuit, a first comparison circuit compares the voltage signal with a first reference voltage signal to generate a first logic state signal, and a second comparison circuit compares the voltage signal with a second reference voltage signal to generate a second logic state signal. Performing state latching on the first logic state signal and the second logic state signal by using a latch circuit, and outputting a first logic state value and a second logic state value; the first logic state value and the second logic state value are used for forming a logic state sequence, and the logic state sequence is used for representing the communication address of the target chip. The communication addresses of different chips can be obtained according to different address selection signals, so that the MCU can flexibly select the addresses of the chips for communication.

Description

Technical Field

[0001] The present application relates to the technical field of power management chips, and in particular to a communication address generation circuit, a circuit system, and an electronic device. Background Art

[0002] When a microcontroller unit (MCU) communicates with a chip, the chip needs to provide a chip address in order to establish normal communication between the MCU and the chip.

[0003] When an MCU needs to communicate with multiple identical chips, this application mainly targets the case where an MCU communicates with two or three identical chips. In the first case, when the same chip has a fixed chip address, since the addresses of two or three identical chips are the same, it is impossible to provide multiple different addresses, making it impossible for an MCU to communicate with two or three identical chips at the same time. In the second case, the target address is written before the chip leaves the factory. An MCU can only communicate with the chip with the target address written, and it is impossible to flexibly select the chip address from two or three identical chips for communication. In the third case, see Figure 1 , Figure 1 A schematic diagram of an address generation circuit provided for related technology, such as Figure 1 As shown, by multiplexing two pins of the chip, a pull-up resistor, namely Rup1 and Rup2, is connected to each of the two pins. By setting different resistance values ​​of the pull-up resistors Rup1 and Rup2, different addresses are generated. Figure 1 The method in can provide multiple different addresses, but this method relies on the accuracy of the internal detection circuit and requires accurate detection of the resistance value of the pull-up resistor. When an error occurs in the measurement of the resistance value of the pull-up resistor, normal communication may not be possible, and the stability of this method is poor. In addition, Figure 1 The method requires two high-precision pull-down current sources, namely S1 and S2, which makes the circuit scale more complicated. Summary of the invention

[0004] The present application provides a communication address generation circuit, a circuit system, and an electronic device for providing multiple different addresses, so that an MCU can flexibly select the address of the chip when communicating with two or three identical chips. The specific technical solution is as follows:

[0005] In a first aspect, the present application provides a communication address generation circuit, which is applied to a target chip and used to generate a communication address of the target chip; characterized in that the communication address generation circuit comprises: a first voltage divider circuit, a first comparison circuit, a second comparison circuit and a latch circuit;

[0006] The first voltage divider circuit is used to receive an address selection signal, and output a corresponding voltage signal according to the address selection signal, and output the voltage signal to the first comparison circuit and the second comparison circuit respectively;

[0007] The first comparison circuit is used to receive a first reference voltage signal and generate a first logic state signal according to the voltage signal and the first reference voltage signal;

[0008] The second comparison circuit is used to receive a second reference voltage signal and generate a second logic state signal according to the voltage signal and the second reference voltage signal;

[0009] The latch circuit is used to latch the first logic state signal and the second logic state signal, and output a first logic state value corresponding to the first logic state signal and a second logic state value corresponding to the second logic state signal;

[0010] The first logic state value and the second logic state value are used to form a logic state sequence, and the logic state sequence is used to represent the communication address of the target chip.

[0011] In a possible design, the first voltage divider circuit includes: a first resistor, a second resistor, a first signal terminal, and a second signal terminal;

[0012] The first end of the first resistor is used to receive a supply voltage; the second end of the first resistor is electrically connected to the first end of the second resistor, and the second end of the second resistor is grounded;

[0013] The input end of the first signal terminal is the input end of the first voltage divider circuit, which is used to receive the address selection signal; the output end of the first signal terminal is electrically connected to the second end of the first resistor; the input end of the second signal terminal is electrically connected to the second end of the first resistor, and the output end of the second signal terminal is the output end of the first voltage divider circuit, which is used to output the voltage signal.

[0014] In one possible design, the address selection signal includes a first address selection signal;

[0015] The first voltage divider circuit is used to receive the first address selection signal, output a first voltage signal according to the first address selection signal, and output the first voltage signal to the first comparison circuit and the second comparison circuit respectively;

[0016] The first comparison circuit is used to receive a first reference voltage signal and generate a first level signal according to the first voltage signal and the first reference voltage signal;

[0017] The second comparison circuit is used to receive a second reference voltage signal and generate a second level signal according to the first voltage signal and the second reference voltage signal.

[0018] In one possible design, the address selection signal includes a second address selection signal;

[0019] The first voltage divider circuit is used to receive the second address selection signal, output a second voltage signal according to the second address selection signal, and output the second voltage signal to the first comparison circuit and the second comparison circuit respectively;

[0020] The first comparison circuit is used to receive a first reference voltage signal and generate a third level signal according to the second voltage signal and the first reference voltage signal;

[0021] The second comparison circuit is used to receive a second reference voltage signal and generate a fourth level signal according to the second voltage signal and the second reference voltage signal.

[0022] In one possible design, the address selection signal includes a third address selection signal;

[0023] The first voltage divider circuit is used to receive the third address selection signal, output a third voltage signal according to the third address selection signal, and output the third voltage signal to the first comparison circuit and the second comparison circuit respectively;

[0024] The first comparison circuit is used to receive a first reference voltage signal and generate a fifth level signal according to the third voltage signal and the first reference voltage signal;

[0025] The second comparison circuit is used to receive a second reference voltage signal and generate a sixth level signal according to the third voltage signal and the second reference voltage signal.

[0026] In one possible design, the communication address generation circuit further includes: a reference voltage generation circuit;

[0027] The reference voltage generating circuit is used to generate the first reference voltage signal and the second reference voltage signal.

[0028] In one possible design, the first comparison circuit includes a first comparator, and the second comparison circuit includes a second comparator;

[0029] The non-inverting input terminal of the first comparator is used to receive the first reference voltage signal, the inverting input terminal of the first comparator is electrically connected to the output terminal of the first voltage divider circuit, the output terminal of the first comparator is electrically connected to the first input terminal of the latch circuit, and the enable terminal of the first comparator is used to receive a first enable signal;

[0030] The non-inverting input terminal of the second comparator is used to receive the second reference voltage signal, the inverting input terminal of the second comparator is electrically connected to the output terminal of the first voltage divider circuit, the output terminal of the second comparator is electrically connected to the second input terminal of the latch circuit, and the enable terminal of the second comparator is used to receive the first enable signal.

[0031] In one possible design, the latch circuit includes: a first D flip-flop and a second D flip-flop;

[0032] The input end of the first D flip-flop is electrically connected to the output end of the first comparison circuit, the output end of the first D flip-flop is the first output end of the latch circuit, and the enable end of the first D flip-flop is used to receive a second enable signal;

[0033] The input end of the second D flip-flop is electrically connected to the output end of the second comparison circuit, the output end of the second D flip-flop is the second output end of the latch circuit, and the enable end of the second D flip-flop is used to receive the second enable signal;

[0034] The first output end of the latch circuit is used to output the first logic state value; the second output end of the latch circuit is used to output the second logic state value.

[0035] In a second aspect, the present application provides a circuit system, the circuit system comprising: a microprocessor and a plurality of chips with the same specifications, each of the chips comprising the communication address generation circuit as described in the first aspect above;

[0036] The first output terminal of the latch circuit and the second output terminal of the latch circuit are both electrically connected to the microprocessor;

[0037] Each of the chips is used to transmit a logic state sequence consisting of the first logic state value and the second logic state value to the microprocessor;

[0038] The microprocessor is used to obtain the communication address of the chip according to the logic state sequence.

[0039] In a third aspect, the present application provides an electronic device, comprising: a circuit system as described in the second aspect above.

[0040] Beneficial effects of the embodiments of the present application:

[0041] The present application provides a communication address generation circuit, which includes: a first voltage divider circuit, a first comparison circuit, a second comparison circuit and a latch circuit; the first voltage divider circuit outputs a corresponding voltage signal according to the address selection circuit, the first comparison circuit compares the voltage signal with the first reference voltage signal to generate a first logic state signal, the second comparison circuit compares the voltage signal with the second reference voltage signal to generate a second logic state signal, and then the latch circuit latches the first logic state signal and the second logic state signal to obtain a logic state sequence for characterizing the communication address of the target chip. The communication address generation circuit can obtain the communication address of the target chip according to the address selection signal, and can obtain the communication addresses of different chips for different address selection signals, so that when an MCU communicates with two or three identical chips, it can flexibly select the chip address for communication.

[0042] The beneficial effects provided in the above-mentioned second aspect and various possible designs of the above-mentioned second aspect can refer to the beneficial effects brought about by the above-mentioned first aspect and various possible implementation methods of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0044] Figure 1 A structural schematic diagram of an address generation circuit provided for related technology;

[0045] Figure 2 A schematic diagram of the structure of a communication address generation circuit provided in an embodiment of the present application;

[0046] Figure 3 A circuit diagram of a communication address generation circuit provided in an embodiment of the present application;

[0047] Figure 4 A circuit diagram of a reference voltage generating circuit provided in an embodiment of the present application;

[0048] Figure 5 A driving timing diagram provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0050] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0051] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0052] In the related art, when an MCU communicates with two or three identical chips, there is a problem that the chip addresses cannot be flexibly selected for communication.

[0053] To this end, the present application provides a communication address generation circuit, a circuit system, and an electronic device.

[0054] The communication address generating circuit may be a chip or a circuit module.

[0055] Among them, the communication address generation circuit can be integrated into the chip.

[0056] Among them, the circuit system includes a chip.

[0057] In this application, electronic devices may include, but are not limited to, tablet computers, smart home devices, vehicles, and wearable devices.

[0058] See also Figure 2 , Figure 2 A communication address generation circuit 1000 is provided in one embodiment of the present application, such as Figure 2 As shown, the communication address generation circuit 1000 may include: a first voltage divider circuit 100 , a first comparison circuit 200 , a second comparison circuit 300 , and a latch circuit 400 .

[0059] The first voltage divider circuit 100 is used to receive an address selection signal, and output a corresponding voltage signal according to the address selection signal, and output the voltage signal to the first comparison circuit 200 and the second comparison circuit 300 respectively.

[0060] The first comparison circuit 200 is used to receive a first reference voltage signal and generate a first logic state signal according to the voltage signal and the first reference voltage signal.

[0061] The second comparison circuit 300 is used to receive a second reference voltage signal and generate a second logic state signal according to the voltage signal and the second reference voltage signal.

[0062] The latch circuit 400 is used to latch the first logic state signal and the second logic state signal, and output a first logic state value corresponding to the first logic state signal and a second logic state value corresponding to the second logic state signal.

[0063] The first logic state value and the second logic state value are used to form a logic state sequence, and the logic state sequence is used to represent the communication address of the target chip.

[0064] The chip that can communicate with the MCU usually includes a clock signal pin SCL, a data signal pin SDA, and an address detection signal pin ADDR. When the MCU communicates with the chip, the address detection is performed through the address detection signal pin ADDR, and the data is transmitted through the clock signal pin SCL and the data signal pin SDA. In the hardware circuit, the address detection signal pin ADDR can be connected in different ways. The address detection signal pin ADDR can be connected to a high-level signal, a low-level signal, or left hanging. Different connection methods of the address detection signal pin ADDR correspond to different address selection signals. According to the address selection signal, a voltage signal corresponding to the address selection signal can be obtained. Different address selection signals correspond to different voltage signals.

[0065] The values ​​of the first reference voltage and the second reference voltage are not fixed and can be set according to the voltage signal output by the first voltage divider circuit. The specific values ​​here will be described in detail in the following specific embodiments. The voltage signal and the first reference voltage signal are compared by the first comparison circuit to output a first logic state signal; the voltage signal and the second reference voltage signal are compared by the second comparison circuit to output a second logic state signal.

[0066] Before the MCU communicates with the chip, it will first establish communication based on the chip address. The MCU only detects the chip address at the initial power-on moment. Therefore, in actual operation, the latch circuit only works at the initial power-on moment to latch the output results of the first comparison circuit and the second comparison circuit. By latching the first logic state signal and the second logic state signal, the MCU can always select the target chip for communication.

[0067] The first logic state value corresponds to the first logic state signal, the second logic state value corresponds to the second logic state signal, the first logic state value and the second logic state value are used to form a logic state sequence, and the logic state sequence is used to characterize the communication address of the target chip. In an example, the first logic state value is 0, the second logic state value is 1, and the logic state sequence composed of the first logic state value and the second logic state value is 01, then the communication address of the target chip is 01.

[0068] In the embodiment of the present application, the first voltage divider circuit outputs a corresponding voltage signal according to the address selection circuit, the first comparison circuit compares the voltage signal with the first reference voltage signal to generate a first logic state signal, the second comparison circuit compares the voltage signal with the second reference voltage signal to generate a second logic state signal, and then the first logic state signal and the second logic state signal are latched by the latch circuit to obtain a logic state sequence for characterizing the communication address of the target chip. The communication address generation circuit can obtain the communication address of the target chip according to the address selection signal, and the communication addresses of different chips can be obtained for different address selection signals, so that when an MCU communicates with two or three identical chips, it can flexibly select the chip address for communication.

[0069] In one possible embodiment, see Figure 3 , Figure 3 A circuit diagram of a communication address generation circuit provided in an embodiment of the present application, such as Figure 3 As shown, the first voltage divider circuit 100 includes: a first resistor R1, a second resistor R2, a first signal terminal and a second signal terminal.

[0070] The first end of the first resistor R1 is used to receive the power supply voltage VIN; the second end of the first resistor R1 is electrically connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded.

[0071] The input end of the first signal terminal is the input end of the first voltage divider circuit 200, which is used to receive the address selection signal; the output end of the first signal terminal is electrically connected to the second end of the first resistor R1; the input end of the second signal terminal is electrically connected to the second end of the first resistor R1, and the output end of the second signal terminal is the output end of the first voltage divider circuit, which is used to output a voltage signal.

[0072] The address detection signal pin ADDR outputs an address selection signal, and the address detection signal pin ADDR is connected between the first resistor R1 and the second resistor R2. The voltage division ratio between the first resistor R1 and the second resistor R2 can be adjusted according to the different resistance values ​​of the first resistor R1 and the second resistor R2. In an example, when the address detection signal pin ADDR is suspended, R1 is 10K, and R2 is 10K, the first voltage divider circuit performs 1 / 2VIN voltage division.

[0073] The address detection signal pin ADDR includes three connection modes: the address detection signal pin ADDR is connected to a high level signal, a low level signal or is suspended. According to the three different connection modes of the address detection signal pin ADDR, there are three different states, namely, high, grounded and suspended. By detecting the three different states, three different addresses are obtained.

[0074] The following will explain in detail the specific working principle of obtaining three different addresses according to the three different states of the address detection signal pin ADDR, namely high, grounded and floating.

[0075] In a possible embodiment, the address selection signal includes a first address selection signal.

[0076] The first voltage divider circuit is used to receive a first address selection signal, output a first voltage signal according to the first address selection signal, and output the first voltage signal to the first comparison circuit and the second comparison circuit respectively.

[0077] The first comparison circuit is used to receive a first reference voltage signal and generate a first level signal according to the first voltage signal and the first reference voltage signal.

[0078] The second comparison circuit is used to receive a second reference voltage signal and generate a second level signal according to the first voltage signal and the second reference voltage signal.

[0079] See also Figure 3When the user connects the address detection signal pin ADDR to high during the address detection time, it is equivalent to the pull-up resistor R1 inside the chip being short-circuited, and the voltage of the address detection signal pin ADDR is VIN, that is, the first address selection signal is VIN, and the first voltage divider circuit outputs the first voltage signal VIN according to the first address selection signal VIN. The first comparison circuit compares the first reference voltage signal with VIN and outputs a first level signal, and the second comparison circuit compares the second reference voltage signal with VIN and outputs a second level signal. In a specific embodiment, since the power supply voltage VIN is greater than the first reference voltage signal and the second reference voltage signal, the first level signal output by the first comparison circuit is 0, and the second level signal output by the second comparison circuit is 0.

[0080] In an embodiment of the present application, when the address detection signal pin ADDR is connected high, the state of the address detection signal pin ADDR is detected by the first voltage divider circuit, the first comparison circuit and the second comparison circuit, and the first logic state signal is 0 and the second logic state signal is 0.

[0081] In a possible embodiment, the address selection signal includes a second address selection signal.

[0082] The first voltage divider circuit is used for receiving the second address selection signal, outputting a second voltage signal according to the second address selection signal, and outputting the second voltage signal to the first comparison circuit and the second comparison circuit respectively.

[0083] The first comparison circuit is used to receive the first reference voltage signal and generate a third level signal according to the second voltage signal and the first reference voltage signal.

[0084] The second comparison circuit is used to receive the second reference voltage signal and generate a fourth level signal according to the second voltage signal and the second reference voltage signal.

[0085] See also Figure 3 When the user grounds the address detection signal pin ADDR during the address detection time, it is equivalent to the pull-down resistor R2 inside the chip being short-circuited, and the voltage of the address detection signal pin ADDR is 0, that is, the second address selection signal is 0, and the first voltage divider circuit outputs the second voltage signal 0 according to the second address selection signal 0, and the first comparison circuit compares the first reference voltage signal with 0 and outputs a third level signal, and the second comparison circuit compares the second reference voltage signal with 0 and outputs a fourth level signal. In a specific embodiment, since the first reference voltage signal and the second reference voltage signal are both greater than the second voltage signal 0, the third level signal output by the first comparison circuit is 1, and the fourth level signal output by the second comparison circuit is 1.

[0086] In an embodiment of the present application, when the address detection signal pin ADDR is grounded, the state of the address detection signal pin ADDR is detected by the first voltage divider circuit, the first comparison circuit and the second comparison circuit, and the first logic state signal is 1 and the second logic state signal is 1.

[0087] In a possible embodiment, the address selection signal includes a third address selection signal.

[0088] The first voltage divider circuit is used to receive a third address selection signal, output a third voltage signal according to the third address selection signal, and output the third voltage signal to the first comparison circuit and the second comparison circuit respectively.

[0089] The first comparison circuit is used to receive the first reference voltage signal and generate a fifth level signal according to the third voltage signal and the first reference voltage signal.

[0090] The second comparison circuit is used to receive the second reference voltage signal and generate a sixth level signal according to the third voltage signal and the second reference voltage signal.

[0091] See also Figure 3 , when the user leaves the address detection signal pin ADDR floating during the address detection time, the voltage of the address detection signal pin ADDR is related to the voltage division ratio of the first voltage divider circuit, that is, it is related to the resistance values ​​of R1 and R2. In an example, when R1 is 10K and R2 is 10K, the first voltage divider circuit performs 1 / 2VIN voltage division, the first reference voltage signal can be set to 1 / 3VIN, and the second selection signal can be set to 2 / 3VIN. The first voltage divider circuit outputs a third voltage signal of 1 / 2VIN according to the third address selection signal 1 / 2VIN, and the first comparison circuit compares the first reference voltage signal with 1 / 3VIN and outputs a fifth level signal, and the second comparison circuit compares the second reference voltage signal with 2 / 3VIN and outputs a sixth level signal. In a specific embodiment, since the first reference voltage signal 1 / 3VIN is less than the third voltage signal 1 / 2VIN, and the second reference voltage signal 2 / 3VIN is greater than the third voltage signal 1 / 2VIN, the fifth level signal output by the first comparison circuit is 0, and the sixth level signal output by the second comparison circuit is 1.

[0092] In an embodiment of the present application, when the address detection signal pin ADDR is suspended, the state of the address detection signal pin ADDR is detected by the first voltage divider circuit, the first comparison circuit and the second comparison circuit, and the first logic state signal is 0 and the second logic state signal is 1.

[0093] In the embodiment of the present application, according to three different connection modes of the address detection signal pin ADDR, three different states correspond, namely, high connection, ground connection and floating. The three different states are detected by the first voltage divider circuit, the first comparison circuit and the second comparison circuit to obtain three different results, namely, 00, 11 and 01, and three different communication addresses are obtained according to the three different results.

[0094] In one possible embodiment, see Figure 4 , Figure 4 A circuit diagram of a reference voltage generating circuit provided in an embodiment of the present application, such as Figure 4 As shown, the communication address generating circuit 1000 further includes: a reference voltage generating circuit 500 .

[0095] The reference voltage generating circuit 500 is used to generate a first reference voltage signal Vref1 and a second reference voltage signal Vref2.

[0096] For an example, see Figure 4 , through the third resistor R3, the fourth resistor R4 and the fifth resistor R5 connected in series between VIN and ground, when the resistance values ​​of the third resistor R3, the fourth resistor R4 and the fifth resistor R5 are the same, the first reference voltage signal Vref1 is 1 / 3VIN, and the second reference voltage signal Vref2 is 2 / 3VIN.

[0097] When the address detection signal pin ADDR is connected to high, the voltage signal corresponding to the address selection signal output is VIN. No matter what the value relationship between the first reference voltage signal Vref1 and the second reference voltage signal Vref2 is, VIN is always greater than the first reference voltage signal Vref1 and the second reference voltage signal Vref2; when the address detection signal pin ADDR is grounded, the voltage signal corresponding to the address selection signal output is 0. No matter what the value relationship between the first reference voltage signal Vref1 and the second reference voltage signal Vref2 is, the first reference voltage signal Vref1 and the second reference voltage signal Vref2 are always greater than 0; when the address detection signal pin ADDR is floating, the voltage signal corresponding to the address selection signal output is related to the voltage division ratio of the first voltage divider circuit. In actual project applications, one of the first reference voltage signal Vref1 and the second reference voltage signal Vref2 is usually set to be lower than the voltage division ratio of the first voltage divider circuit, and the other is set to be higher than the voltage division ratio of the first voltage divider circuit, so that the first logic state signal and the second logic state signal output by the first comparison circuit and the second comparison circuit are different signals.

[0098] In an embodiment of the present application, a first reference voltage signal and a second reference voltage signal are generated by a reference voltage generating circuit, so that when the address detection signal pin ADDR is floating, the first logic state signal and the second logic state signal output by the first comparison circuit and the second comparison circuit are different signals.

[0099] In one possible embodiment, see Figure 3 The first comparison circuit 200 includes a first comparator U1, and the second comparison circuit 300 includes a second comparator U2.

[0100] The non-inverting input terminal of the first comparator U1 is used to receive the first reference voltage signal Vref1, the inverting input terminal of the first comparator U1 is electrically connected to the output terminal of the first voltage divider circuit 100, the output terminal of the first comparator U1 is electrically connected to the first input terminal of the latch circuit 400, and the enable terminal EN1 of the first comparator U1 is used to receive the first enable signal EN_ADDR.

[0101] The non-inverting input terminal of the second comparator U2 is used to receive the second reference voltage signal Vref2, the inverting input terminal of the second comparator U2 is electrically connected to the output terminal of the first voltage divider circuit 100, the output terminal of the second comparator U2 is electrically connected to the second input terminal of the latch circuit 400, and the enable terminal EN2 of the second comparator U2 is used to receive the first enable signal EN_ADDR.

[0102] In one possible embodiment, see Figure 3 , the latch circuit 400 includes: a first D flip-flop Q1 and a second D flip-flop Q2.

[0103] An input terminal of the first D flip-flop Q1 is electrically connected to an output terminal of the first comparison circuit 200 , an output terminal of the first D flip-flop Q1 is a first output terminal of the latch circuit 400 , and an enable terminal EN3 of the first D flip-flop Q1 is used to receive a second enable signal ENZ_DFF_CLK.

[0104] The input terminal of the second D flip-flop Q2 is electrically connected to the output terminal of the second comparison circuit 300 , the output terminal of the second D flip-flop Q2 is the second output terminal of the latch circuit 400 , and the enable terminal EN4 of the second D flip-flop Q2 is used to receive the second enable signal ENZ_DFF_CLK.

[0105] The first output terminal of the latch circuit 400 is used to output a first logic state value VOH; the second output terminal of the latch circuit is used to output a second logic state value VOL.

[0106] The latch circuit uses the first D flip-flop and the second D flip-flop to latch the output results of the first comparison circuit and the second comparison circuit, and outputs the first logic state value VOH and the second logic state value VOL. The first logic state value VOH and the second logic state value VOL are used to form a logic state sequence, and the logic state sequence is used to represent the communication address of the target chip.

[0107] Specifically, according to the three different connection modes of the address detection signal pin ADDR, three different states correspond, namely, high connection, ground connection and floating. The three different states are detected by the first voltage divider circuit, the first comparison circuit and the second comparison circuit to obtain three different results, namely, 00, 11 and 01. Then, the three different results, namely, 00, 11 and 01, are latched by the latch circuit to obtain three different communication addresses, thereby realizing flexible address selection.

[0108] In addition, the communication address generation circuit provided in the present application can obtain three different communication addresses by only detecting the state of the address detection signal pin ADDR, thereby realizing flexible address selection, which is different from the related art (such as Figure 1 Compared with the two pins of the multiplexing chip of ), the communication address generation circuit provided by the present application has fewer multiplexing chip pins and a simpler circuit. Figure 1 ), which requires accurate detection of the resistance value of the pull-up resistor, the communication address generation circuit provided by the present application only needs to detect according to the state of the address detection signal pin ADDR, without the need to detect the accurate resistance value of the resistor, and has a higher fault tolerance, better robustness, and higher stability. Based on the advantages of simpler circuits and higher stability, the communication address generation circuit provided by the present application has higher portability and can be transplanted to any chip that needs to communicate with the MCU.

[0109] See also Figure 5 , Figure 5 A driving timing diagram provided in an embodiment of the present application, wherein EN is an enable signal connected to the enable terminal of a chip integrated with a communication address generation circuit, the first enable signal EN_ADDR is an enable signal connected to the enable terminals EN1 and EN2 of the first comparator and the second comparator, and the second enable signal ENZ_DFF_CLK is an enable signal connected to the enable terminals EN3 and EN4 of the first D flip-flop and the second D flip-flop. Those skilled in the art can understand that when the enable signal is at a high level, the corresponding device is controlled to work. Figure 5As shown, the driving timing is: in the first stage T1, the chip is enabled, EN is controlled to be high, the chip starts to work, the digital module in the chip where the communication address generation circuit is located starts to work, and the first enable signal EN_ADDR is output; in the second stage T2, the first enable signal EN_ADDR is controlled to be high, the first comparator and the second comparator are enabled to start working, and the voltage signal is compared with the first reference voltage and the second reference voltage to obtain the first logic state signal and the second logic state signal, and at the same time, the second enable signal ENZ_DFF_CLK is controlled to be high, the first D flip-flop and the second D flip-flop are enabled, and the state latching of the first logic state signal and the second logic state signal is performed; in the third stage T3, the second enable signal ENZ_DFF_CLK is controlled to be low, the first D flip-flop and the second D flip-flop will maintain the current state, and then the first enable signal EN_ADDR is controlled to be low, the entire communication address generation circuit is not enabled and stops working, but the output results of the first comparator and the second comparator (that is, the first logic state signal and the second logic state signal) can still be maintained.

[0110] An embodiment of the present application also provides a circuit system, including a microprocessor and a plurality of chips of the same specification, each chip including the above-mentioned communication address generation circuit.

[0111] Each chip is electrically connected to the microprocessor, specifically, each chip is electrically connected to the microprocessor through a first output terminal of a latch circuit and a second output terminal of the latch circuit in the chip.

[0112] In a possible embodiment, each chip may also be electrically connected to the microprocessor via a digital circuit. Each chip is used to transmit a logic state sequence consisting of a first logic state value and a second logic state value to the microprocessor via the digital circuit.

[0113] The microprocessor can obtain the communication address of the chip according to the logic state sequence, and then flexibly select the chip address from multiple chips for communication.

[0114] An embodiment of the present application also provides an electronic device, comprising the above-mentioned circuit system.

[0115] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A communication address generation circuit, applied to a target chip, for generating a communication address of the target chip; characterized in that: The communication address generation circuit comprises: a first voltage dividing circuit, a first comparison circuit, a second comparison circuit and a latch circuit; The first voltage divider circuit is used to receive an address selection signal, and output a corresponding voltage signal according to the address selection signal, and output the voltage signal to the first comparison circuit and the second comparison circuit respectively; The first comparison circuit is used to receive a first reference voltage signal and generate a first logic state signal according to the voltage signal and the first reference voltage signal; The second comparison circuit is used to receive a second reference voltage signal and generate a second logic state signal according to the voltage signal and the second reference voltage signal; The latch circuit is used to latch the first logic state signal and the second logic state signal, and output a first logic state value corresponding to the first logic state signal and a second logic state value corresponding to the second logic state signal; The first logic state value and the second logic state value are used to form a logic state sequence, and the logic state sequence is used to represent the communication address of the target chip.

2. The communication address generation circuit according to claim 1, characterized in that: The first voltage divider circuit includes: a first resistor, a second resistor, a first signal terminal and a second signal terminal; The first end of the first resistor is used to receive a supply voltage; the second end of the first resistor is electrically connected to the first end of the second resistor, and the second end of the second resistor is grounded; The input end of the first signal terminal is the input end of the first voltage divider circuit, which is used to receive the address selection signal; the output end of the first signal terminal is electrically connected to the second end of the first resistor; the input end of the second signal terminal is electrically connected to the second end of the first resistor, and the output end of the second signal terminal is the output end of the first voltage divider circuit, which is used to output the voltage signal.

3. The communication address generation circuit according to claim 1 or 2, characterized in that: The address selection signal includes a first address selection signal; The first voltage divider circuit is used to receive the first address selection signal, output a first voltage signal according to the first address selection signal, and output the first voltage signal to the first comparison circuit and the second comparison circuit respectively; The first comparison circuit is used to receive a first reference voltage signal and generate a first level signal according to the first voltage signal and the first reference voltage signal; The second comparison circuit is used to receive a second reference voltage signal and generate a second level signal according to the first voltage signal and the second reference voltage signal.

4. The communication address generating circuit according to claim 1 or 2, characterized in that: The address selection signal includes a second address selection signal; The first voltage divider circuit is used to receive the second address selection signal, output a second voltage signal according to the second address selection signal, and output the second voltage signal to the first comparison circuit and the second comparison circuit respectively; The first comparison circuit is used to receive a first reference voltage signal and generate a third level signal according to the second voltage signal and the first reference voltage signal; The second comparison circuit is used to receive a second reference voltage signal and generate a fourth level signal according to the second voltage signal and the second reference voltage signal.

5. The communication address generating circuit according to claim 1 or 2, characterized in that: The address selection signal includes a third address selection signal; The first voltage divider circuit is used to receive the third address selection signal, output a third voltage signal according to the third address selection signal, and output the third voltage signal to the first comparison circuit and the second comparison circuit respectively; The first comparison circuit is used to receive a first reference voltage signal and generate a fifth level signal according to the third voltage signal and the first reference voltage signal; The second comparison circuit is used to receive a second reference voltage signal and generate a sixth level signal according to the third voltage signal and the second reference voltage signal.

6. The communication address generating circuit according to claim 1, characterized in that: The communication address generation circuit further includes: a reference voltage generation circuit; The reference voltage generating circuit is used to generate the first reference voltage signal and the second reference voltage signal.

7. The communication address generating circuit according to claim 1, characterized in that: The first comparison circuit includes a first comparator, and the second comparison circuit includes a second comparator; The non-inverting input terminal of the first comparator is used to receive the first reference voltage signal, the inverting input terminal of the first comparator is electrically connected to the output terminal of the first voltage divider circuit, the output terminal of the first comparator is electrically connected to the first input terminal of the latch circuit, and the enable terminal of the first comparator is used to receive a first enable signal; The non-inverting input terminal of the second comparator is used to receive the second reference voltage signal, the inverting input terminal of the second comparator is electrically connected to the output terminal of the first voltage divider circuit, the output terminal of the second comparator is electrically connected to the second input terminal of the latch circuit, and the enable terminal of the second comparator is used to receive the first enable signal.

8. The communication address generating circuit according to claim 1, characterized in that: The latch circuit comprises: a first D flip-flop and a second D flip-flop; The input end of the first D flip-flop is electrically connected to the output end of the first comparison circuit, the output end of the first D flip-flop is the first output end of the latch circuit, and the enable end of the first D flip-flop is used to receive a second enable signal; The input end of the second D flip-flop is electrically connected to the output end of the second comparison circuit, the output end of the second D flip-flop is the second output end of the latch circuit, and the enable end of the second D flip-flop is used to receive the second enable signal; The first output end of the latch circuit is used to output the first logic state value; the second output end of the latch circuit is used to output the second logic state value.

9. A circuit system, characterized in that: The circuit system comprises: a microprocessor and a plurality of chips with the same specifications, each of the chips comprising the communication address generation circuit according to any one of claims 1 to 8; The first output terminal of the latch circuit and the second output terminal of the latch circuit are both electrically connected to the microprocessor; Each of the chips is used to transmit a logic state sequence consisting of the first logic state value and the second logic state value to the microprocessor; The microprocessor is used to obtain the communication address of the chip according to the logic state sequence.

10. An electronic device, characterized in that: include: The circuit system as claimed in claim 9.

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