Circuit characterization method and device, computer equipment, storage medium and computer program product

Abstract

The invention relates to a circuit characterization method and device, computer equipment, a storage medium and a computer program product. The method comprises the following steps: performing mask processing on a sample netlist diagram of a sample circuit to obtain a mask netlist diagram of the sample netlist diagram; obtaining a first sample embedding vector corresponding to the sample netlist diagram and a second sample embedding vector corresponding to the mask netlist diagram through a to-be-trained encoder model; obtaining a target loss value according to the first sample embedding vector and the second sample embedding vector; performing iterative training on the to-be-trained encoder model according to the target loss value to obtain a trained encoder model; and obtaining a to-be-analyzed netlist diagram of a to-be-analyzed circuit, inputting the to-be-analyzed netlist diagram into the trained encoder model to obtain a prediction embedding vector corresponding to the to-be-analyzed netlist diagram, and taking the prediction embedding vector as a circuit characterization result corresponding to the to-be-analyzed circuit. By adopting the method, the accuracy of circuit characterization can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a circuit characterization method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Art

[0002] At present, in the process of circuit design, in order to ensure the stability of circuit performance, how to accurately characterize the circuit is crucial.

[0003] In traditional technology, manual judgment is generally used in the process of circuit characterization; however, this manual judgment method has subjective factors and is prone to errors, resulting in low accuracy of circuit characterization. Summary of the invention

[0004] Based on this, it is necessary to provide a circuit characterization method, apparatus, computer device, computer-readable storage medium and computer program product that can improve the accuracy of circuit characterization in order to address the above technical problems.

[0005] In a first aspect, the present application provides a circuit characterization method, comprising:

[0006] Obtain a sample netlist diagram of a sample circuit;

[0007] Performing mask processing on the sample netlist diagram to obtain a masked netlist diagram of the sample netlist diagram;

[0008] Obtaining, by means of the encoder model to be trained, a first sample embedding vector corresponding to the sample netlist diagram and a second sample embedding vector corresponding to the mask netlist diagram;

[0009] According to the second sample embedding vector, a reconstructed netlist graph corresponding to the mask netlist graph is obtained, a reconstruction loss value is obtained according to a difference between the sample netlist graph and the reconstructed netlist graph, and a difference loss value is obtained according to the first sample embedding vector and the second sample embedding vector;

[0010] Performing weighted sum processing on the reconstruction loss value and the difference loss value to obtain a target loss value;

[0011] Iteratively training the encoder model to be trained according to the target loss value to obtain a trained encoder model;

[0012] A netlist diagram to be analyzed of the circuit to be analyzed is obtained, and the netlist diagram to be analyzed is input into the trained encoder model to obtain a predicted embedding vector corresponding to the netlist diagram to be analyzed as a circuit characterization result corresponding to the circuit to be analyzed.

[0013] In one embodiment, obtaining a sample netlist diagram of a sample circuit includes:

[0014] Constructing an original netlist diagram of the sample circuit;

[0015] Converting the original netlist to obtain a related netlist of the sample circuit;

[0016] The original netlist diagram and the associated netlist diagram are both used as the sample netlist diagram.

[0017] In one embodiment, constructing the original netlist diagram of the sample circuit includes:

[0018] Obtaining a circuit design file associated with the sample circuit;

[0019] Extracting connection information from the circuit design file;

[0020] The original netlist diagram is constructed according to the connection information.

[0021] In one embodiment, obtaining a difference loss value according to the first sample embedding vector and the second sample embedding vector includes:

[0022] Performing pooling processing on the first sample embedding vector and the second sample embedding vector respectively to obtain a first sample pooling vector corresponding to the sample netlist graph and a second sample pooling vector corresponding to the mask netlist graph;

[0023] Classify the first sample pooling vector and the second sample pooling vector respectively to obtain a first classification result corresponding to the sample netlist graph and a second classification result corresponding to the mask netlist graph;

[0024] The difference loss value is obtained according to the difference between the first classification result and the second classification result; the difference includes intra-class difference and category difference.

[0025] In one embodiment, obtaining a netlist diagram of the circuit to be analyzed includes:

[0026] Acquire a downstream task to be processed associated with the circuit to be analyzed; the downstream task to be processed is used to represent a downstream task for adjusting the trained encoder model;

[0027] Parsing the downstream task to be processed to obtain parsing information of the downstream task to be processed;

[0028] Extracting circuit identification information of the circuit to be analyzed from the parsed information;

[0029] A netlist diagram to be analyzed of the circuit to be analyzed is determined according to the circuit identification information.

[0030] In one embodiment, after obtaining a netlist diagram to be analyzed of a circuit to be analyzed, inputting the netlist diagram to be analyzed into the trained encoder model, and obtaining a predicted embedding vector corresponding to the netlist diagram to be analyzed as a circuit characterization result corresponding to the circuit to be analyzed, the method further includes:

[0031] Inputting the predicted embedding vector into the trained circuit detection model to obtain the predicted probability of the circuit to be analyzed under each preset circuit detection result;

[0032] From the preset circuit detection results, select the preset circuit detection result with the largest prediction probability as the target circuit detection result corresponding to the circuit to be analyzed;

[0033] If the target circuit detection result indicates that the circuit to be analyzed is an abnormal circuit, generating a repair instruction corresponding to the circuit to be analyzed;

[0034] The repair instruction is sent to a target terminal associated with the circuit to be analyzed, so that the target terminal performs corresponding repair processing on the circuit to be analyzed according to the repair instruction.

[0035] In a second aspect, the present application further provides a circuit characterization device, comprising:

[0036] A netlist acquisition module, used to acquire a sample netlist of a sample circuit;

[0037] A netlist processing module, used for performing mask processing on the sample netlist to obtain a mask netlist of the sample netlist;

[0038] A vector extraction module, used for obtaining a first sample embedding vector corresponding to the sample netlist diagram and a second sample embedding vector corresponding to the mask netlist diagram through an encoder model to be trained;

[0039] a loss value determination module, configured to obtain a reconstructed netlist graph corresponding to the mask netlist graph according to the second sample embedding vector, obtain a reconstruction loss value according to a difference between the sample netlist graph and the reconstructed netlist graph, and obtain a difference loss value according to the first sample embedding vector and the second sample embedding vector;

[0040] A loss value processing module, used for performing weighted sum processing on the reconstruction loss value and the difference loss value to obtain a target loss value;

[0041] A model training module, used for iteratively training the encoder model to be trained according to the target loss value to obtain a trained encoder model;

[0042] The result determination module is used to obtain the netlist diagram to be analyzed of the circuit to be analyzed, input the netlist diagram to be analyzed into the trained encoder model, and obtain the predicted embedding vector corresponding to the netlist diagram to be analyzed as the circuit characterization result corresponding to the circuit to be analyzed.

[0043] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0044] Obtain a sample netlist diagram of a sample circuit;

[0045] Performing mask processing on the sample netlist diagram to obtain a masked netlist diagram of the sample netlist diagram;

[0046] Obtaining, by means of the encoder model to be trained, a first sample embedding vector corresponding to the sample netlist diagram and a second sample embedding vector corresponding to the mask netlist diagram;

[0047] According to the second sample embedding vector, a reconstructed netlist graph corresponding to the mask netlist graph is obtained, a reconstruction loss value is obtained according to a difference between the sample netlist graph and the reconstructed netlist graph, and a difference loss value is obtained according to the first sample embedding vector and the second sample embedding vector;

[0048] Performing weighted sum processing on the reconstruction loss value and the difference loss value to obtain a target loss value;

[0049] Iteratively training the encoder model to be trained according to the target loss value to obtain a trained encoder model;

[0050] A netlist diagram to be analyzed of the circuit to be analyzed is obtained, and the netlist diagram to be analyzed is input into the trained encoder model to obtain a predicted embedding vector corresponding to the netlist diagram to be analyzed as a circuit characterization result corresponding to the circuit to be analyzed.

[0051] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0052] Obtain a sample netlist diagram of a sample circuit;

[0053] Performing mask processing on the sample netlist diagram to obtain a masked netlist diagram of the sample netlist diagram;

[0054] Obtaining, by means of the encoder model to be trained, a first sample embedding vector corresponding to the sample netlist diagram and a second sample embedding vector corresponding to the mask netlist diagram;

[0055] According to the second sample embedding vector, a reconstructed netlist graph corresponding to the mask netlist graph is obtained, a reconstruction loss value is obtained according to a difference between the sample netlist graph and the reconstructed netlist graph, and a difference loss value is obtained according to the first sample embedding vector and the second sample embedding vector;

[0056] Performing weighted sum processing on the reconstruction loss value and the difference loss value to obtain a target loss value;

[0057] Iteratively training the encoder model to be trained according to the target loss value to obtain a trained encoder model;

[0058] A netlist diagram to be analyzed of the circuit to be analyzed is obtained, and the netlist diagram to be analyzed is input into the trained encoder model to obtain a predicted embedding vector corresponding to the netlist diagram to be analyzed as a circuit characterization result corresponding to the circuit to be analyzed.

[0059] In a fifth aspect, the present application further provides a computer program product, including a computer program, which implements the following steps when executed by a processor:

[0060] Obtain a sample netlist diagram of a sample circuit;

[0061] Performing mask processing on the sample netlist diagram to obtain a masked netlist diagram of the sample netlist diagram;

[0062] Obtaining, by means of the encoder model to be trained, a first sample embedding vector corresponding to the sample netlist graph and a second sample embedding vector corresponding to the mask netlist graph;

[0063] According to the second sample embedding vector, a reconstructed netlist graph corresponding to the mask netlist graph is obtained, a reconstruction loss value is obtained according to a difference between the sample netlist graph and the reconstructed netlist graph, and a difference loss value is obtained according to the first sample embedding vector and the second sample embedding vector;

[0064] Performing weighted sum processing on the reconstruction loss value and the difference loss value to obtain a target loss value;

[0065] Iteratively training the encoder model to be trained according to the target loss value to obtain a trained encoder model;

[0066] A netlist diagram to be analyzed of the circuit to be analyzed is obtained, and the netlist diagram to be analyzed is input into the trained encoder model to obtain a predicted embedding vector corresponding to the netlist diagram to be analyzed as a circuit characterization result corresponding to the circuit to be analyzed.

[0067] The above-mentioned circuit characterization method, device, computer equipment, storage medium and computer program product first obtain a sample netlist diagram of a sample circuit, and mask the sample netlist diagram to obtain a masked netlist diagram of the sample netlist diagram, and obtain a first sample embedding vector corresponding to the sample netlist diagram and a second sample embedding vector corresponding to the masked netlist diagram through the encoder model to be trained, and then obtain a reconstructed netlist diagram corresponding to the masked netlist diagram according to the second sample embedding vector, and obtain a reconstruction loss value according to the difference between the sample netlist diagram and the reconstructed netlist diagram, and obtain a difference loss value according to the first sample embedding vector and the second sample embedding vector, then perform weighted sum processing on the reconstruction loss value and the difference loss value to obtain a target loss value, and then, according to the target loss value, iteratively train the encoder model to be trained to obtain a trained encoder model, and finally, obtain the netlist diagram to be analyzed of the circuit to be analyzed, input the netlist diagram to be analyzed into the trained encoder model, and obtain the predicted embedding vector corresponding to the netlist diagram to be analyzed as the circuit characterization result corresponding to the circuit to be analyzed. In this way, in the process of circuit characterization, the encoder model is pre-trained by using the sample netlist diagram of the sample circuit, so that in practical applications, after obtaining the netlist diagram to be analyzed of the circuit to be analyzed, the predicted embedding vector corresponding to the netlist diagram to be analyzed can be accurately predicted, thereby improving the determination accuracy of the predicted embedding vector corresponding to the netlist diagram to be analyzed, and then improving the determination accuracy of the circuit characterization result corresponding to the circuit to be analyzed, which is beneficial to improving the accuracy of circuit characterization; moreover, the entire process does not require human intervention, avoiding the subjective factors of manual judgment, which is prone to errors and leads to the defect of low accuracy of circuit characterization, thereby improving the accuracy of circuit characterization. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0069] Figure 1 is a schematic flow chart of a circuit characterization method in one embodiment;

[0070] Figure 2 is a flow chart of a circuit characterization method in another embodiment;

[0071] Figure 3 It is a structural schematic diagram of a unified circuit physical design phase characterization method based on different granularities in one embodiment;

[0072] Figure 4A schematic diagram of a metal segment-based graph and a netlist-level graph in one embodiment;

[0073] Figure 5 A schematic diagram of determining an embedding vector of a graph at a netlist level in one embodiment;

[0074] Figure 6 A schematic diagram of determining an embedding vector of a graph at a path level in one embodiment;

[0075] Figure 7 A schematic diagram of an embodiment of an embedded vector being applied to a downstream task;

[0076] Figure 8 is a structural block diagram of a circuit characterization device in one embodiment;

[0077] Fig. 9 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0078] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0079] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0080] In an exemplary embodiment, Figure 1 As shown, a circuit characterization method is provided. This embodiment uses the method applied to a server as an example for illustration. It is understandable that the method can also be applied to a terminal, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. The terminal can be, but is not limited to, various personal computers, laptops, smart phones, and tablet computers; the server can be implemented as an independent server or a server cluster consisting of multiple servers. In this embodiment, the method includes the following steps:

[0081] Step S101, obtaining a sample netlist diagram of a sample circuit.

[0082] The sample circuit refers to a circuit for training the encoder model to be trained.

[0083] The sample netlist diagram refers to a netlist diagram of a sample circuit.

[0084] Exemplarily, the server responds to a model training instruction for the encoder model to be trained, and determines a circuit to be trained for the encoder model to be trained as a sample circuit; then, the server obtains circuit identification information of the sample circuit, and based on the circuit identification information of the sample circuit, determines a netlist diagram corresponding to the circuit identification information of the sample circuit as a sample netlist diagram of the sample circuit.

[0085] Step S102, performing mask processing on the sample netlist to obtain a masked netlist of the sample netlist.

[0086] The masked netlist diagram refers to the sample netlist diagram after mask processing.

[0087] Exemplarily, the server performs mask processing on the sample netlist graph through a mask rate of a certain ratio to obtain a masked netlist graph of the sample netlist graph; for example, the server performs mask processing on the node features, edges and nodes of the sample netlist graph respectively to obtain a masked feature graph, a masked edge graph and a masked node graph corresponding to the sample netlist graph, and uses the masked feature graph, the masked edge graph and the masked node graph corresponding to the sample netlist graph as the masked netlist graph of the sample netlist graph.

[0088] Step S103, obtaining a first sample embedding vector corresponding to the sample netlist graph and a second sample embedding vector corresponding to the mask netlist graph through the encoder model to be trained.

[0089] The first sample embedding vector refers to the embedding vector corresponding to the sample netlist graph.

[0090] The second sample embedding vector refers to the embedding vector corresponding to the mask netlist graph.

[0091] Exemplarily, the server inputs the sample netlist diagram into the encoder model to be trained, and obtains the embedding vector corresponding to the sample netlist diagram through the encoder model to be trained as the first sample embedding vector; then, the server inputs the mask netlist diagram into the encoder model to be trained, and obtains the embedding vector corresponding to the mask netlist diagram through the encoder model to be trained as the second sample embedding vector.

[0092] Step S104, obtaining a reconstructed netlist diagram corresponding to the mask netlist diagram according to the second sample embedding vector, obtaining a reconstruction loss value according to the difference between the sample netlist diagram and the reconstructed netlist diagram, and obtaining a difference loss value according to the first sample embedding vector and the second sample embedding vector.

[0093] The reconstructed netlist diagram refers to a netlist diagram obtained by performing circuit reconstruction processing on the mask netlist diagram.

[0094] The reconstruction loss value refers to the loss value obtained based on the difference between the sample netlist and the reconstructed netlist.

[0095] The difference loss value refers to the loss value obtained according to the first sample embedding vector and the second sample embedding vector.

[0096] Exemplarily, the server inputs the second sample embedding vector into the graph neural network decoder, and determines the netlist diagram corresponding to the second sample embedding vector through the graph neural network decoder as the reconstructed netlist diagram corresponding to the mask netlist diagram; then, the server obtains the reconstruction loss value based on the difference between the sample netlist diagram and the reconstructed netlist diagram; then, the server obtains the difference loss value based on the first sample embedding vector and the second sample embedding vector.

[0097] Step S105, performing weighted sum processing on the reconstruction loss value and the difference loss value to obtain a target loss value.

[0098] Among them, the target loss value refers to the loss value obtained by weighted summing the reconstruction loss value and the difference loss value.

[0099] Exemplarily, the server determines a first weight corresponding to the reconstruction loss value and a second weight corresponding to the difference loss value; then, the server performs weighted summation processing on the reconstruction loss value and the difference loss value according to the first weight and the second weight to obtain a target loss value.

[0100] Step S106, iteratively training the encoder model to be trained according to the target loss value to obtain a trained encoder model.

[0101] Exemplarily, the server adjusts the model parameters of the encoder model to be trained according to the target loss value; then, the server re-trains the encoder model after the model parameters are adjusted until the target loss value obtained by the trained encoder model is greater than the loss value threshold, then stops training, and uses the trained encoder model as the trained encoder model.

[0102] Step S107, obtaining a netlist diagram to be analyzed of the circuit to be analyzed, inputting the netlist diagram to be analyzed into the trained encoder model, and obtaining a predicted embedding vector corresponding to the netlist diagram to be analyzed as a circuit characterization result corresponding to the circuit to be analyzed.

[0103] The circuit to be analyzed refers to a circuit that needs to be analyzed.

[0104] The netlist diagram to be analyzed refers to the netlist diagram of the circuit to be analyzed.

[0105] The predicted embedding vector refers to the embedding vector corresponding to the netlist graph to be analyzed.

[0106] The circuit characterization result is used to indicate the circuit characterization situation corresponding to the circuit to be analyzed.

[0107] Exemplarily, the server obtains a downstream task to be processed that is associated with the circuit to be analyzed; then, the server determines the netlist diagram to be analyzed of the circuit to be analyzed based on the downstream task to be processed; then, the server inputs the netlist diagram to be analyzed into the trained encoder model, and obtains an embedding vector corresponding to the netlist diagram to be analyzed as a predicted embedding vector; then, the server obtains circuit function information corresponding to the circuit to be analyzed (such as amplification function, filtering function, etc.), and uses the circuit function information and the predicted embedding vector as the circuit characterization result corresponding to the circuit to be analyzed.

[0108] In the above circuit characterization method, a sample netlist diagram of a sample circuit is first obtained, and the sample netlist diagram is masked to obtain a masked netlist diagram of the sample netlist diagram. Through the encoder model to be trained, a first sample embedding vector corresponding to the sample netlist diagram and a second sample embedding vector corresponding to the masked netlist diagram are obtained. Then, based on the second sample embedding vector, a reconstructed netlist diagram corresponding to the masked netlist diagram is obtained. A reconstruction loss value is obtained based on the difference between the sample netlist diagram and the reconstructed netlist diagram, and a difference loss value is obtained based on the first sample embedding vector and the second sample embedding vector. Then, a weighted summation process is performed on the reconstruction loss value and the difference loss value to obtain a target loss value. Then, based on the target loss value, the encoder model to be trained is iteratively trained to obtain a trained encoder model. Finally, the netlist diagram to be analyzed of the circuit to be analyzed is obtained, and the netlist diagram to be analyzed is input into the trained encoder model to obtain a predicted embedding vector corresponding to the netlist diagram to be analyzed as a circuit characterization result corresponding to the circuit to be analyzed. In this way, in the process of circuit characterization, the encoder model is pre-trained by using the sample netlist diagram of the sample circuit, so that in practical applications, after obtaining the netlist diagram to be analyzed of the circuit to be analyzed, the predicted embedding vector corresponding to the netlist diagram to be analyzed can be accurately predicted, thereby improving the determination accuracy of the predicted embedding vector corresponding to the netlist diagram to be analyzed, and then improving the determination accuracy of the circuit characterization result corresponding to the circuit to be analyzed, which is beneficial to improving the accuracy of circuit characterization; moreover, the entire process does not require human intervention, avoiding the subjective factors of manual judgment, which is prone to errors and leads to the defect of low accuracy of circuit characterization, thereby improving the accuracy of circuit characterization.

[0109] In an exemplary embodiment, the above step S101, obtaining a sample netlist diagram of the sample circuit, specifically includes the following contents: constructing an original netlist diagram of the sample circuit; converting the original netlist diagram to obtain an associated netlist diagram of the sample circuit; and using both the original netlist diagram and the associated netlist diagram as sample netlist diagrams.

[0110] The original netlist diagram refers to a diagram based on metal segments.

[0111] The associated netlist graph refers to a netlist-level graph and a path-level graph.

[0112] Exemplarily, the server obtains a circuit design file associated with the sample circuit, and constructs an original netlist diagram of the sample circuit based on the circuit design file; then, the server obtains component information, node information and connection relationship information of the original netlist diagram, and converts the original netlist diagram based on the component information, node information and connection relationship information of the original netlist diagram to obtain a netlist-level diagram corresponding to the sample circuit; then, the server obtains the starting point and end point of the current path in the original netlist diagram, and converts the original netlist diagram based on the starting point and end point of the current path in the original netlist diagram to obtain a path-level diagram corresponding to the sample circuit; then, the server uses the netlist-level diagram and the path-level diagram corresponding to the sample circuit as the associated netlist diagram of the sample circuit; then, the server uses the original netlist diagram and the associated netlist diagram as the sample netlist diagram.

[0113] In this embodiment, by using both the original netlist diagram and the associated netlist diagram as the sample netlist diagram of the sample circuit, the circuit characteristics of the sample circuit can be presented in multiple dimensions, which is beneficial to improving the accuracy of determining the sample netlist diagram of the sample circuit, avoiding the one-sided analysis caused by understanding the sample circuit from only a single perspective, and providing a data basis for subsequent analysis.

[0114] In an exemplary embodiment, constructing an original netlist diagram of a sample circuit specifically includes the following contents: acquiring a circuit design file associated with the sample circuit; extracting connection information in the circuit design file; and constructing an original netlist diagram according to the connection information.

[0115] The circuit design file is used to represent the design file of the sample circuit in the physical design stage.

[0116] The connection information is used to indicate the electrical connection relationship between various electronic components in the sample circuit.

[0117] The importance is used to indicate the influence of the connection information on the circuit.

[0118] The preset importance refers to a preset importance threshold. It should be noted that the preset importance depends on the situation.

[0119] The key connection information is used to indicate connection information whose importance is greater than a preset importance.

[0120] Exemplarily, the server obtains keywords of the sample circuit (such as the name of the circuit, the name of the project to which it belongs, a description of its main functions, and other information), and based on the keywords of the sample circuit, obtains the circuit design file corresponding to the keywords of the sample circuit from the database as the circuit design file associated with the sample circuit; then, the server parses the circuit design file to obtain parsing information corresponding to the circuit design file, and extracts connection information in the circuit design file from the parsing information corresponding to the circuit design file; then, the server generates a netlist construction instruction, and based on the netlist construction instruction, constructs a netlist corresponding to the connection information as the original netlist.

[0121] In this embodiment, the original netlist diagram is constructed based on the connection information extracted from the circuit design file, thereby accelerating the conversion process from the circuit design file to the original netlist diagram, which is beneficial to improving the construction efficiency of the original netlist diagram.

[0122] In an exemplary embodiment, the above step S104, obtaining a difference loss value based on the first sample embedding vector and the second sample embedding vector, specifically includes the following contents: performing pooling processing on the first sample embedding vector and the second sample embedding vector respectively to obtain a first sample pooling vector corresponding to the sample netlist diagram, and a second sample pooling vector corresponding to the mask netlist diagram; performing classification processing on the first sample pooling vector and the second sample pooling vector respectively to obtain a first classification result corresponding to the sample netlist diagram, and a second classification result corresponding to the mask netlist diagram; obtaining a difference loss value based on the difference between the first classification result and the second classification result; the difference includes intra-class difference and category difference.

[0123] The first sample pooling vector refers to the first sample embedding vector after pooling processing.

[0124] The second sample pooling vector refers to the second sample embedding vector after pooling processing.

[0125] The first classification result refers to the classification result corresponding to the sample netlist diagram (such as circuit function information, circuit structure information, etc.).

[0126] The second classification result refers to the classification result corresponding to the mask netlist diagram.

[0127] Among them, intra-class differences are used to indicate the degree of discreteness in the feature space distribution between similar samples, such as the differences between different modules of the same chip.

[0128] Among them, category difference is used to represent the distinction between samples of different categories in the feature space, such as different modules of different chips.

[0129] Exemplarily, the server performs average pooling processing on the first sample embedding vector through the pooling layer to obtain a pooling vector corresponding to the first sample embedding vector, as the first sample pooling vector corresponding to the sample netlist diagram; then, the server performs average pooling processing on the second sample embedding vector through the pooling layer to obtain a pooling vector corresponding to the second sample embedding vector, as the second sample pooling vector corresponding to the mask netlist diagram; then, the server performs classification processing on the first sample pooling vector through the fully connected layer to obtain a classification result corresponding to the first sample pooling vector, as the first classification result corresponding to the sample netlist diagram; then, the server performs classification processing on the second sample pooling vector through the fully connected layer to obtain a classification result corresponding to the second sample pooling vector, as the second classification result corresponding to the mask netlist diagram; then, the server determines the intra-class difference and category difference between the first classification result and the second classification result as the difference between the first classification result and the second classification result, and obtains the difference loss value according to the difference between the first classification result and the second classification result.

[0130] In this embodiment, by performing pooling processing and classification processing on the first sample embedding vector and the second sample embedding vector respectively, the first classification result and the second classification result can be accurately obtained, and then the difference loss value can be accurately obtained, so that the subsequent model training can be optimized in the direction of increasing the difference loss value, which is beneficial to improving the training effect of the model.

[0131] In an exemplary embodiment, the above-mentioned step S107, obtaining the netlist diagram to be analyzed of the circuit to be analyzed, specifically includes the following contents: obtaining the downstream tasks to be processed associated with the circuit to be analyzed; the downstream tasks to be processed are used to represent the downstream tasks for adjusting the trained encoder model; the downstream tasks to be processed are parsed to obtain the parsing information of the downstream tasks to be processed; from the parsing information, the circuit identification information of the circuit to be analyzed is extracted; according to the circuit identification information, the netlist diagram to be analyzed of the circuit to be analyzed is determined.

[0132] The pending downstream tasks refer to downstream tasks used to adjust the trained encoder model. It should be noted that this solution has a module for fine-tuning the encoder, which will gradually improve the encoder model and perform incremental learning as the downstream tasks continue to remind it.

[0133] The parsed information refers to the information obtained by parsing the downstream tasks to be processed.

[0134] The circuit identification information refers to information that uniquely distinguishes a circuit, such as a circuit number.

[0135] Exemplarily, the server obtains a downstream task for adjusting a trained encoder model as a downstream task to be processed; then, the server parses the downstream task to be processed to obtain parsing information of the downstream task to be processed; then, the server preprocesses the parsing information to obtain preprocessed parsing information; then, the server extracts the circuit identification information of the circuit to be analyzed from the preprocessed parsing information; then, the server determines the netlist diagram corresponding to the circuit identification information based on the circuit identification information as the netlist diagram to be analyzed of the circuit to be analyzed.

[0136] In this embodiment, by determining the netlist diagram based on the circuit identification information extracted from the downstream task to be processed, the netlist diagram to be analyzed of the circuit to be analyzed can be quickly determined, thereby avoiding the manual search of the netlist diagram that results in a large amount of time consumption, and is beneficial to improving the efficiency of determining the netlist diagram to be analyzed of the circuit to be analyzed.

[0137] In an exemplary embodiment, the above-mentioned step S107, after obtaining the netlist diagram to be analyzed of the circuit to be analyzed, inputting the netlist diagram to be analyzed into a trained encoder model, and obtaining a predicted embedding vector corresponding to the netlist diagram to be analyzed as a circuit characterization result corresponding to the circuit to be analyzed, specifically includes the following contents: inputting the predicted embedding vector into a trained circuit detection model to obtain a predicted probability of the circuit to be analyzed under each preset circuit detection result; from each preset circuit detection result, screening out the preset circuit detection result with the largest predicted probability as the target circuit detection result corresponding to the circuit to be analyzed; when the target circuit detection result indicates that the circuit to be analyzed is an abnormal circuit, generating a repair instruction corresponding to the circuit to be analyzed; and sending the repair instruction to a target terminal associated with the circuit to be analyzed, so that the target terminal performs corresponding repair processing on the circuit to be analyzed according to the repair instruction.

[0138] Among them, the circuit detection model refers to a network model that can use the predicted embedding vector corresponding to the netlist diagram to be analyzed to obtain the target circuit detection result corresponding to the circuit to be analyzed, such as a convolutional neural network model and a recurrent neural network model.

[0139] The preset circuit detection result refers to a preset circuit detection result, such as a normal circuit or an abnormal circuit. It should be noted that the preset circuit detection result depends on the situation.

[0140] The prediction probability refers to the possibility that the circuit detection model determines that the preset circuit detection result is correct.

[0141] The target circuit detection result is used to represent the preset circuit detection result with the highest prediction probability.

[0142] The repair instruction refers to instruction information corresponding to the repair process of the circuit to be analyzed.

[0143] The target terminal refers to the terminal associated with the circuit to be analyzed.

[0144] Exemplarily, the server inputs the predicted embedding vector into a trained circuit detection model, and obtains the predicted probability of the circuit to be analyzed under each preset circuit detection result through the trained circuit detection model; then, the server screens out the preset circuit detection result with the largest predicted probability from each preset circuit detection result, and uses the preset circuit detection result as the target circuit detection result corresponding to the circuit to be analyzed; then, the server judges the target circuit detection result: when the target circuit detection result indicates that the circuit to be analyzed is an abnormal circuit, the server generates a repair instruction corresponding to the circuit to be analyzed based on the circuit identification information corresponding to the circuit to be analyzed; then, the server establishes a network path with the target terminal, and sends the repair instruction to the target terminal associated with the circuit to be analyzed through the network path; the target terminal performs corresponding repair processing on the circuit to be analyzed according to the repair instruction.

[0145] In this embodiment, when a circuit abnormality is detected, a corresponding repair instruction is automatically generated and sent to the associated target terminal, so that the relevant personnel corresponding to the target terminal can respond immediately and process quickly according to the instruction, which is conducive to improving the timeliness of circuit repair and thus ensuring the normal operation of the circuit.

[0146] In an exemplary embodiment, Figure 2 As shown, another circuit characterization method is provided, which is described by taking the application of the method to the server as an example, and includes the following steps:

[0147] Step S201, obtaining a circuit design file associated with a sample circuit; extracting connection information in the circuit design file.

[0148] Step S202, constructing an original netlist diagram according to the connection information.

[0149] Step S203, converting the original netlist diagram to obtain a related netlist diagram of the sample circuit; and using the original netlist diagram and the related netlist diagram as sample netlist diagrams.

[0150] Step S204, performing mask processing on the sample netlist to obtain a masked netlist of the sample netlist.

[0151] Step S205, obtaining a first sample embedding vector corresponding to the sample netlist graph and a second sample embedding vector corresponding to the mask netlist graph through the encoder model to be trained.

[0152] Step S206, obtaining a reconstructed netlist graph corresponding to the mask netlist graph according to the second sample embedding vector, and obtaining a reconstruction loss value according to the difference between the sample netlist graph and the reconstructed netlist graph.

[0153] Step S207, performing pooling processing on the first sample embedding vector and the second sample embedding vector respectively, to obtain a first sample pooling vector corresponding to the sample netlist graph and a second sample pooling vector corresponding to the mask netlist graph.

[0154] Step S208, classify the first sample pooling vector and the second sample pooling vector respectively to obtain a first classification result corresponding to the sample netlist diagram and a second classification result corresponding to the mask netlist diagram; obtain a difference loss value based on the difference between the first classification result and the second classification result; the difference includes intra-class difference and category difference.

[0155] Step S209, performing weighted sum processing on the reconstruction loss value and the difference loss value to obtain a target loss value.

[0156] Step S210, iteratively training the encoder model to be trained according to the target loss value to obtain a trained encoder model.

[0157] Step S211, obtaining the downstream tasks to be processed associated with the circuit to be analyzed; parsing the downstream tasks to be processed to obtain parsing information of the downstream tasks to be processed; the downstream tasks to be processed are used to represent downstream tasks for adjusting the trained encoder model.

[0158] Step S212, extracting circuit identification information of the circuit to be analyzed from the parsed information; and determining a netlist diagram to be analyzed of the circuit to be analyzed according to the circuit identification information.

[0159] Step S213, inputting the netlist diagram to be analyzed into the trained encoder model to obtain a predicted embedding vector corresponding to the netlist diagram to be analyzed as a circuit characterization result corresponding to the circuit to be analyzed.

[0160] In the above-mentioned circuit characterization method, during the process of circuit characterization, the encoder model is pre-trained by using the sample netlist diagram of the sample circuit, so that in practical applications, after obtaining the netlist diagram to be analyzed of the circuit to be analyzed, the predicted embedding vector corresponding to the netlist diagram to be analyzed can be accurately predicted, thereby improving the determination accuracy of the predicted embedding vector corresponding to the netlist diagram to be analyzed, and then improving the determination accuracy of the circuit characterization result corresponding to the circuit to be analyzed, which is beneficial to improving the accuracy of circuit characterization; moreover, the whole process does not require human intervention, avoiding the subjective factors in the manual judgment method, which is prone to errors and leads to the defect of low accuracy of circuit characterization, thereby improving the accuracy of circuit characterization.

[0161] In an exemplary embodiment, in order to more clearly illustrate the circuit characterization method provided in the embodiment of the present application, the circuit characterization method is specifically described below with a specific embodiment. In one embodiment, Figure 3 As shown, the present application also provides a unified circuit physical design stage characterization method based on different granularities. In the process of circuit characterization, a sample netlist diagram of a sample circuit is first obtained, and the sample netlist diagram is masked to obtain a mask netlist diagram of the sample netlist diagram. Through the encoder model to be trained, a first sample embedding vector corresponding to the sample netlist diagram and a second sample embedding vector corresponding to the mask netlist diagram are obtained. Then, according to the second sample embedding vector, a reconstructed netlist diagram corresponding to the mask netlist diagram is obtained. According to the difference between the sample netlist diagram and the reconstructed netlist diagram, a reconstruction loss value is obtained, and according to the first sample embedding vector and the second sample embedding vector, a difference loss value is obtained. Then, the reconstruction loss value and the difference loss value are weighted and summed to obtain a target loss value. Then, according to the target loss value, the encoder model to be trained is iteratively trained to obtain a trained encoder model. Finally, the netlist diagram to be analyzed of the circuit to be analyzed is obtained, and the netlist diagram to be analyzed is input into the trained encoder model to obtain the predicted embedding vector corresponding to the netlist diagram to be analyzed as the circuit characterization result corresponding to the circuit to be analyzed. Specifically include the following contents:

[0162] In the first step, the design file in the physical stage is analyzed, the metal segment-based connection information is read therefrom, and a metal segment-based diagram is constructed.

[0163] In the second step, for the graph based on metal segments, the features, edges and nodes in the current graph based on metal segments are respectively masked by a certain masking rate, thereby generating several newly constructed subgraphs.

[0164] The third step is to train the machine learning model. The main module of this machine learning model is a shared graph neural network encoder, which can freely choose neural network models such as GIN (Graph Isomorphism Network), GraphSage (Graph Sample and Aggregate), GAT (Graph Attention Network) or Graph Transformer; the encoder is divided into two branches. The first branch is the branch for reconstructing nodes, edges and features, which aims to restore the nodes, edges and features of the graph. This branch contains a graph neural network decoder to reconstruct nodes, edges and features, and calculates a loss function L rec; The second branch is the contrastive learning branch, which aims to distinguish different nodes, edges and features. The output of this branch will pass through an average pooling layer, a fully connected layer, and then calculate the difference loss function L con ; Finally, the entire model considers the loss function L of the two branches rec +λL con (where λ is the preset weight, which is a positive value). The input of the second step is used as data to train this model. When the model training is completed, a trained encoder model is obtained, and the corresponding nodes, edges and feature embedding vectors are output, such as Figure 3 It should be noted that the loss function L rec The larger the value, the closer the reconstruction is to the structure before reconstruction; the difference loss function L con The larger the value, the better it is at distinguishing differences; therefore, the loss function L rec +λL con The larger the corresponding value, the better the effect.

[0165] Step 4: The main purpose of this step is to construct an embedding vector based on the netlist level. Here is an explanation. The netlist level graph is as follows. It is a coarser-grained graph modeling than the metal segment-based graph modeling. Figure 4 The edge in the right picture is a normal edge at the netlist level, but if it is subdivided into metal segments, it becomes Figure 4 The two edges and nodes in the left figure; so building a graph based on the netlist level is to convert the corresponding subgraph in the graph based on the metal segment (below Figure 4 The two edges and nodes in the left figure are converted into one edge. Average pooling is used here for conversion, and then the edges, nodes and features not involved are kept as they are. Finally, the netlist-level embedding representation is obtained, such as Figure 5 shown.

[0166] The fifth step is to construct a path-level embedding vector. The entire path can be represented as an embedding vector through average pooling, and the path can be represented as a sequence of embedding vectors based on multiple metal segments through serialization, such as Figure 6 shown.

[0167] The sixth step is to continue to incrementally learn the model obtained in the third step according to different downstream tasks, such as Figure 7 As shown, incremental learning can be performed, and the corresponding representation embedding can be applied to different downstream tasks.

[0168] The seventh step is to embed the representations trained by the model for different downstream tasks. Figure 7As shown, for metal segment-based graphs (i.e., metal connection level), downstream tasks such as feature prediction, link prediction, involved classification, graph classification, average pooling, unit classification, node classification, and data labeling can be performed; for netlist-level graphs (i.e., netlist level), downstream tasks such as metal connection type matching, Motifs processing, definition of different metal connection types, design classification, average pooling, unit classification, and data labeling can be performed; for path-level graphs (i.e., path level), downstream tasks such as path similarity, node classification, path generation, LSTM (Long Short-Term Memory) processing, and Graph Transformer processing can be performed.

[0169] In the above-mentioned embodiment, during the process of circuit characterization, the encoder model is pre-trained by using the sample netlist diagram of the sample circuit, so that in actual application, after obtaining the netlist diagram to be analyzed of the circuit to be analyzed, the predicted embedding vector corresponding to the netlist diagram to be analyzed can be accurately predicted, thereby improving the accuracy of determining the predicted embedding vector corresponding to the netlist diagram to be analyzed, and further improving the accuracy of determining the circuit characterization result corresponding to the circuit to be analyzed, which is beneficial to improving the accuracy of circuit characterization; moreover, the entire process does not require human intervention, avoiding the defect of low accuracy of circuit characterization caused by subjective factors and prone to errors in the method of manual judgment, thereby improving the accuracy of circuit characterization. At the same time, a unified circuit physical representation design scheme is proposed for the physical design stage, which is applied to various downstream tasks like word embedding. An incremental and iterative pre-trained model is proposed, which can be trained incrementally while continuously improving the accuracy and efficiency of downstream tasks. Technologies from different fields are combined into the EDA (Electronic Design Automation) field, and a more scientific and reasonable representation method is sought by crossing technologies from multiple fields. Node features are reconstructed during reconstruction, and edges and nodes are reconstructed at the same time. In the differentiation stage, circuit characteristics are considered, such as considering that the difference between nodes in high congestion and low congestion areas needs to be large.

[0170] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0171] Based on the same inventive concept, the embodiment of the present application also provides a circuit characterization device for implementing the circuit characterization method involved above. The implementation solution provided by the device to solve the problem is similar to the implementation solution recorded in the above method, so the specific limitations in one or more circuit characterization device embodiments provided below can refer to the limitations of the circuit characterization method above, and will not be repeated here.

[0172] In an exemplary embodiment, Figure 8 As shown, a circuit characterization device is provided, including: a netlist acquisition module 801, a netlist processing module 802, a vector extraction module 803, a loss value determination module 804, a loss value processing module 805, a model training module 806 and a result determination module 807, wherein:

[0173] The netlist acquisition module 801 is used to acquire a sample netlist of a sample circuit.

[0174] The netlist processing module 802 is used to perform mask processing on the sample netlist to obtain a masked netlist of the sample netlist.

[0175] The vector extraction module 803 is used to obtain a first sample embedding vector corresponding to the sample netlist diagram and a second sample embedding vector corresponding to the mask netlist diagram through the encoder model to be trained.

[0176] The loss value determination module 804 is used to obtain a reconstructed netlist diagram corresponding to the mask netlist diagram based on the second sample embedding vector, obtain a reconstruction loss value based on the difference between the sample netlist diagram and the reconstructed netlist diagram, and obtain a difference loss value based on the first sample embedding vector and the second sample embedding vector.

[0177] The loss value processing module 805 is used to perform weighted sum processing on the reconstruction loss value and the difference loss value to obtain a target loss value.

[0178] The model training module 806 is used to iteratively train the encoder model to be trained according to the target loss value to obtain a trained encoder model.

[0179] The result determination module 807 is used to obtain the netlist diagram to be analyzed of the circuit to be analyzed, input the netlist diagram to be analyzed into the trained encoder model, and obtain the predicted embedding vector corresponding to the netlist diagram to be analyzed as the circuit characterization result corresponding to the circuit to be analyzed.

[0180] In an exemplary embodiment, the netlist acquisition module 801 is also used to construct an original netlist of the sample circuit; convert the original netlist to obtain a derived netlist of the sample circuit; and use both the original netlist and the derived netlist as sample netlists.

[0181] In an exemplary embodiment, the netlist acquisition module 801 is also used to obtain a circuit design file associated with a sample circuit; extract connection information in the circuit design file, and determine the importance of each connection information; filter out connection information with an importance greater than a preset importance from each connection information as key connection information; and construct an original netlist diagram based on the key connection information.

[0182] In an exemplary embodiment, the loss value determination module 804 is also used to perform pooling processing on the first sample embedding vector and the second sample embedding vector, respectively, to obtain a first sample pooling vector corresponding to the sample netlist diagram, and a second sample pooling vector corresponding to the mask netlist diagram; perform classification processing on the first sample pooling vector and the second sample pooling vector, respectively, to obtain a first classification result corresponding to the sample netlist diagram, and a second classification result corresponding to the mask netlist diagram; and obtain a difference loss value based on the difference between the first classification result and the second classification result.

[0183] In an exemplary embodiment, the result determination module 807 is also used to obtain the downstream tasks to be processed associated with the circuit to be analyzed; parse the downstream tasks to be processed to obtain parsing information of the downstream tasks to be processed; extract the circuit identification information of the circuit to be analyzed from the parsing information; and determine the netlist diagram to be analyzed of the circuit to be analyzed based on the circuit identification information.

[0184] In an exemplary embodiment, the circuit characterization device also includes an instruction sending module, which is used to input the predicted embedding vector into a trained circuit detection model to obtain the predicted probability of the circuit to be analyzed under each preset circuit detection result; from each preset circuit detection result, the preset circuit detection result with the largest predicted probability is screened out as the target circuit detection result corresponding to the circuit to be analyzed; when the target circuit detection result indicates that the circuit to be analyzed is an abnormal circuit, a repair instruction corresponding to the circuit to be analyzed is generated; and the repair instruction is sent to a target terminal associated with the circuit to be analyzed, so that the target terminal performs corresponding repair processing on the circuit to be analyzed according to the repair instruction.

[0185] Each module in the above circuit characterization device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0186] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Fig. 9 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data such as a first sample embedding vector and a second sample embedding vector. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a circuit characterization method is implemented.

[0187] Those skilled in the art will understand that Fig. 9 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0188] In an exemplary embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0189] In an exemplary embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0190] In an exemplary embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0191] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0192] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0193] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A circuit characterization method, characterized in that: The method comprises: Obtain a sample netlist diagram of a sample circuit; Performing mask processing on the sample netlist diagram to obtain a masked netlist diagram of the sample netlist diagram; Obtaining, by means of the encoder model to be trained, a first sample embedding vector corresponding to the sample netlist diagram and a second sample embedding vector corresponding to the mask netlist diagram; According to the second sample embedding vector, a reconstructed netlist graph corresponding to the mask netlist graph is obtained, a reconstruction loss value is obtained according to a difference between the sample netlist graph and the reconstructed netlist graph, and a difference loss value is obtained according to the first sample embedding vector and the second sample embedding vector; Performing weighted sum processing on the reconstruction loss value and the difference loss value to obtain a target loss value; Iteratively training the encoder model to be trained according to the target loss value to obtain a trained encoder model; A netlist diagram to be analyzed of the circuit to be analyzed is obtained, and the netlist diagram to be analyzed is input into the trained encoder model to obtain a predicted embedding vector corresponding to the netlist diagram to be analyzed as a circuit characterization result corresponding to the circuit to be analyzed.

2. The method according to claim 1, characterized in that The step of obtaining a sample netlist diagram of a sample circuit includes: Constructing an original netlist diagram of the sample circuit; Converting the original netlist to obtain a related netlist of the sample circuit; The original netlist diagram and the associated netlist diagram are both used as the sample netlist diagram.

3. The method according to claim 2, characterized in that The constructing of the original netlist diagram of the sample circuit comprises: Obtaining a circuit design file associated with the sample circuit; Extracting connection information from the circuit design file; The original netlist diagram is constructed according to the connection information.

4. The method according to claim 1, characterized in that: The obtaining a difference loss value according to the first sample embedding vector and the second sample embedding vector includes: Performing pooling processing on the first sample embedding vector and the second sample embedding vector respectively to obtain a first sample pooling vector corresponding to the sample netlist graph and a second sample pooling vector corresponding to the mask netlist graph; Classify the first sample pooling vector and the second sample pooling vector respectively to obtain a first classification result corresponding to the sample netlist graph and a second classification result corresponding to the mask netlist graph; The difference loss value is obtained according to the difference between the first classification result and the second classification result; the difference includes intra-class difference and category difference.

5. The method according to claim 1, characterized in that The step of obtaining a netlist diagram of the circuit to be analyzed includes: Acquire a downstream task to be processed associated with the circuit to be analyzed; the downstream task to be processed is used to represent a downstream task for adjusting the trained encoder model; Parsing the downstream task to be processed to obtain parsing information of the downstream task to be processed; Extracting circuit identification information of the circuit to be analyzed from the parsed information; A netlist diagram to be analyzed of the circuit to be analyzed is determined according to the circuit identification information.

6. The method according to any one of claims 1 to 5, characterized in that: After obtaining a netlist diagram to be analyzed of the circuit to be analyzed, inputting the netlist diagram to be analyzed into the trained encoder model, and obtaining a predicted embedding vector corresponding to the netlist diagram to be analyzed as a circuit characterization result corresponding to the circuit to be analyzed, the method further includes: Inputting the predicted embedding vector into the trained circuit detection model to obtain the predicted probability of the circuit to be analyzed under each preset circuit detection result; From the preset circuit detection results, select the preset circuit detection result with the largest prediction probability as the target circuit detection result corresponding to the circuit to be analyzed; If the target circuit detection result indicates that the circuit to be analyzed is an abnormal circuit, generating a repair instruction corresponding to the circuit to be analyzed; The repair instruction is sent to a target terminal associated with the circuit to be analyzed, so that the target terminal performs corresponding repair processing on the circuit to be analyzed according to the repair instruction.

7. A circuit characterization device, characterized in that: The device comprises: A netlist acquisition module, used to acquire a sample netlist of a sample circuit; A netlist processing module, used for performing mask processing on the sample netlist to obtain a mask netlist of the sample netlist; A vector extraction module, used for obtaining a first sample embedding vector corresponding to the sample netlist diagram and a second sample embedding vector corresponding to the mask netlist diagram through an encoder model to be trained; a loss value determination module, configured to obtain a reconstructed netlist graph corresponding to the mask netlist graph according to the second sample embedding vector, obtain a reconstruction loss value according to a difference between the sample netlist graph and the reconstructed netlist graph, and obtain a difference loss value according to the first sample embedding vector and the second sample embedding vector; A loss value processing module, used for performing weighted sum processing on the reconstruction loss value and the difference loss value to obtain a target loss value; A model training module, used for iteratively training the encoder model to be trained according to the target loss value to obtain a trained encoder model; The result determination module is used to obtain the netlist diagram to be analyzed of the circuit to be analyzed, input the netlist diagram to be analyzed into the trained encoder model, and obtain the predicted embedding vector corresponding to the netlist diagram to be analyzed as the circuit characterization result corresponding to the circuit to be analyzed.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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