Method for rapidly solving plane segmentation via hole in multilayer integrated circuit board

Abstract

The invention provides a method for rapidly solving a plane segmentation via hole in a multilayer integrated circuit board. The method comprises the following steps: calculating a connection relation of all elements in the multilayer integrated circuit board, determining a vertical position of each via hole, identifying a plane layer intersected with the via hole, recording connection information, allocating a priority value to each plane layer, sorting according to the priority values, and creating a data structure QMaplt; a QPair is used as a QPair; int, int, and intgt; , QSett, QSett; a Viagt; gt; the data structure is converted into QMaplt; via, QSetlt, Via, QSetlt; a QPair is used as a QPair; int, int, and intgt; gt; gt; and on the basis of the obtained relation that each via hole is cut by the plane, cutting holes segmented by the plane. According to the method, through an automatic data processing and optimization algorithm, the accuracy and efficiency of via hole segmentation are improved, the design and manufacturing cost is reduced, the production cycle is shortened, and powerful technical support is provided for design and manufacturing of a multilayer integrated circuit board.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit boards, and more specifically, to a method for quickly solving plane segmentation vias in a multi-layer integrated circuit board. Background Art

[0002] Traditional via segmentation methods rely on complex meshing and iterative geometric modeling techniques. These methods often require a lot of computing resources and time when dealing with multi-layer PCB structures, especially when facing high-density circuit designs. Their efficiency and accuracy are difficult to meet the needs of industrial-grade applications. In addition, existing technologies often use approximate calculations when dealing with the interaction between electromagnetic fields and vias, which may lead to large errors in high-frequency applications, affecting the performance and reliability of the circuit.

[0003] As electronic devices develop towards higher performance and more complex functions, higher requirements are placed on the design of multi-layer PCBs. In high-frequency, high-speed, and high-power application scenarios, the electromagnetic properties of vias have an increasingly significant impact on signal integrity and power integrity. Therefore, how to quickly and accurately segment vias in multi-layer PCBs has become a technical problem that needs to be solved in the field of circuit design and manufacturing. Existing grid-based segmentation methods and geometric modeling techniques have low computational efficiency when dealing with large-scale problems and are difficult to adapt to changing design requirements.

[0004] In order to solve the above problems, researchers have proposed some improved via segmentation techniques, such as feature recognition-based segmentation methods and multi-layer modeling and mapping techniques. These methods have improved the efficiency and accuracy of segmentation to a certain extent, but there are still some limitations. For example, the feature recognition-based method has high requirements on the recognition ability of features, while the multi-layer modeling and mapping technology is still relatively complex in the organization and processing of data structures when dealing with complex multi-layer structures. Summary of the invention

[0005] In a first aspect of the present invention, a method for quickly solving plane segmentation vias in a multi-layer integrated circuit board is provided, comprising the following steps:

[0006] Calculate the connection relationship of all elements in a multi-layer integrated circuit board;

[0007] For each hole, find the plane that connects to it from top to bottom or from bottom to top;

[0008] Sort the layers of the connected planes;

[0009] Combine the holes split by two planes into a QMap data structure <QPair<int,int> ,QSet <via>>

[0010] Convert data structure to QMap <Via,QSet<QPair<int,int> >>, you can get the relationship between each Via being cut by the plane;

[0011] Based on the relationship between each via being cut by a plane, holes divided by the plane are cut out.

[0012] As a further improvement of the present application, calculating the connection relationship of all elements in the multi-layer integrated circuit board includes the following steps:

[0013] Use graph theory algorithms to build the connection diagram of the circuit board;

[0014] Through the connection diagram of the circuit board, identify and record the connection relationship between each via and the plane layer.

[0015] As a further improvement of the present application, for each hole, from top to bottom or from bottom to top, finding the plane connected thereto includes:

[0016] Determine the vertical position of each via;

[0017] Based on the vertical position of the via, identify the plane layer that intersects with it;

[0018] Record the connection information between each via and the intersecting plane layer.

[0019] As a further improvement of the present application, sorting the layers of the connected planes includes:

[0020] Assign a priority value to each plane layer based on its physical location or electrical characteristics;

[0021] Sort the plane layers by priority value.

[0022] As a further improvement of the present application, the data structure QMap of the holes divided by the two planes is combined <QPair<int,int> ,QSet <via>> Includes:

[0023] For each pair of intersecting planes, create a QPair<int,int> Instance, represents this pair of plane layers;

[0024] For each QPair<int,int> Example, create a QSet <via>An instance for storing vias intersecting the pair of plane layers;

[0025] Add each via to the QSet corresponding to the plane layer it intersects <via>middle.

[0026] As a further improvement of this application, the data structure is converted to QMap <Via,QSet<QPair<int,int> >> Includes:

[0027] For each via, create a QSet <QPair<int,int> >Instance, used to store the plane layer pair intersected by the via;

[0028] Traversing the original data structure QMap <QPair<int,int> ,QSet <via>>, for each QPair<int,int> and the corresponding QSet <via>, add each via to the QSet corresponding to the plane layer pair it intersects <QPair<int,int> >Medium;

[0029] Construct a new data structure QMap <Via,QSet<QPair<int,int> >>.

[0030] As a further improvement of the present application, based on the relationship that each Via is cut by a plane, cutting out holes divided by a plane includes:

[0031] Traversing the QMap data structure <Via,QSet<QPair<int,int> >> For each via, get the intersecting plane layer pair;

[0032] Determine the splitting position of the via according to the intersecting plane layer pairs;

[0033] The holes divided by the plane are cut out based on the determined division positions of the via holes.

[0034] In a second aspect of the present invention, a via segmentation system for a multilayer integrated circuit board is provided, the system comprising:

[0035] A calculation module, used to calculate the connection relationship of all elements in the multi-layer integrated circuit board;

[0036] A connecting plane module is used to find the plane connected to each hole from top to bottom or from bottom to top;

[0037] A sorting module, used to sort the layers of the connected planes;

[0038] Combination module, used to combine the hole data structure QMap of two plane partitions <QPair<int,int> ,QSet <via>>

[0039] Conversion module, used to convert data structures to QMap <Via,QSet<QPair<int,int> >>, you can get the relationship between each Via being cut by the plane;

[0040] The cutting module is used to cut out holes divided by planes based on the relationship between each Via being cut by the plane.

[0041] In a third aspect of the present invention, there is provided an electronic device, comprising:

[0042] at least one processor; and

[0043] A memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor so that the at least one processor can execute a method for quickly solving plane segmentation vias in a multi-layer integrated circuit board as described in any one of the first aspects of the present invention.

[0044] In a fourth aspect of the present invention, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute a method for quickly solving plane segmentation vias in a multi-layer integrated circuit board as described in any one of the first aspects of the present invention.

[0045] According to the above-mentioned embodiments of the present invention, at least the following beneficial effects are achieved: According to the embodiments of the present invention, the method for quickly solving the plane segmentation vias in the multi-layer integrated circuit board has significant beneficial effects: by accurately calculating the connection relationship of all elements in the circuit board and innovatively using the QMap data structure to organize the relationship between the vias and the plane layer, the present invention greatly improves the efficiency and accuracy of via segmentation. This method not only reduces the number of iterations in the design stage, but also reduces the error rate in the manufacturing process, thereby shortening the overall production cycle and reducing costs. In addition, the automated data processing process reduces manual intervention, further improves the reliability of the design, and provides strong technical support for the design and manufacture of multi-layer integrated circuit boards. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, in which:

[0047] Figure 1 A schematic flow chart of a method for quickly solving planar segmented vias in a multi-layer integrated circuit board provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The principles and spirit of the present invention will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are provided only to enable those skilled in the art to better understand and implement the present invention, and are not intended to limit the scope of the present invention in any way. On the contrary, these embodiments are provided to make the present invention more thorough and complete, and to fully convey the scope of the present invention to those skilled in the art.

[0049] Those skilled in the art know that the embodiments of the present invention can be implemented as a system, device, apparatus, method or computer program product. Therefore, the present invention can be specifically implemented in the following forms, namely: complete hardware, complete software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0050] It should be noted that any number of elements in the drawings is for illustration rather than limitation, and any naming is only for distinction and does not have any limiting meaning.

[0051] Reference below Figure 1 A method for quickly solving plane split vias in a multi-layer integrated circuit board comprises the following steps:

[0052] Calculate the connection relationship of all elements in a multi-layer integrated circuit board;

[0053] It should be noted that a multi-layer integrated circuit board refers to a complex circuit structure composed of multiple conductive layers and insulating material layers, which is widely used in modern electronic devices. The connection relationship of all elements covers the interconnection details between vias, conductive layers, insulating layers and other circuit components on the circuit board.

[0054] Specifically, this can be achieved by applying algorithms from graph theory to construct a connection diagram of a circuit board, which details the connection paths between all components on the circuit board. In this process, the connection relationship between each via and the plane layer is recorded in detail so that these connections can be accurately identified and processed in subsequent steps.

[0055] Preferably, the process of calculating the connection relationship can use the depth-first search (DFS) or breadth-first search (BFS) in the graph theory algorithm to traverse the connection diagram of the circuit board to ensure that the connection path of each component is detected; for each via, record its connection status with the adjacent plane layer, including the type of connection (such as direct connection or connection through a conductive path) and the strength of the connection; integrate this information into a database or data structure for easy access and processing in subsequent steps.

[0056] For each hole, find the plane that connects to it from top to bottom or from bottom to top;

[0057] It should be noted that each via on the circuit board is analyzed to determine which plane layers it is connected to. Vias are guide holes that pass through the circuit board. They are used to connect different conductive layers to achieve electrical connections. Planes refer to the conductive layers on the circuit board. They can be single-layer or multi-layer and are used to form the transmission path of the circuit.

[0058] Specifically, this step can be achieved by determining the vertical position of each via, that is, their exact position in the board stack. Then, based on this position information, identify the plane layers that intersect with it. In this process, a coordinate system can be used to accurately locate the position of each via, and determine which plane layers they intersect with based on these coordinates. For example, by introducing automated image recognition technology to automatically identify and record the location of vias and the connected plane layers. In addition, machine learning algorithms can be used to predict and verify the connection relationship between vias and plane layers, thereby improving the accuracy and efficiency of this step.

[0059] Sort the layers of the connected planes;

[0060] It should be noted that the identified plane layers connected to the vias are sorted for subsequent analysis and processing. Sorting refers to rearranging the plane layers according to certain standards or rules to ensure that they are processed in a specific order.

[0061] Specifically, this can be achieved by assigning a priority value to each plane layer, which can be based on the physical location, electrical characteristics, or other relevant factors of the plane layer. For example, the priority value can be assigned based on the connection strength between the plane layer and the via, the conductive performance of the plane layer, or the functional role of the plane layer in the circuit board.

[0062] Preferably, the sorting process can adopt multiple algorithms, such as quick sort, merge sort or heap sort, to ensure the efficiency and accuracy of the sorting process. In addition, a weighted sorting mechanism can be introduced, that is, multiple factors are considered in the sorting process, such as the electrical characteristics and physical position of the plane layer, to achieve more refined sorting control.

[0063] Combine the holes split by two planes into a QMap data structure <QPair<int,int> ,QSet <via>>

[0064] It should be noted that QMap is a key-value pair mapping data structure, which is often used to store and manage ordered key-value pair data.<int,int> Represents a pair of two integers, used to represent the numbers or identities of two plane layers. <via>It represents a collection of via identifiers, which is used to store vias that intersect a specific pair of plane layers.

[0065] Specifically, you can create a QPair<int,int> instances, each representing a pair of intersecting planes. Then, for each pair of planes, create a QSet <via>Instance, used to store all vias that intersect this pair of plane layers. In this way, each via is recorded in the QSet corresponding to the plane layer pair it intersects.

[0066] Preferably, this step can be further optimized, for example, by introducing a hash table to improve the access and retrieval speed of data. In addition, more complex data structures such as graph databases or network analysis tools can also be used to support larger and more complex circuit board designs.

[0067] Convert data structure to QMap <Via,QSet<QPair<int,int> >>, you can get the relationship between each Via being cut by the plane;

[0068] It should be noted that the purpose of converting the data structure is to obtain the relationship between each via and the plane, so as to provide accurate data support for the segmentation of the via.

[0069] Specifically, you can traverse the original QMap <QPair<int,int> ,QSet <via>>Data structure to implement, for each QPair<int,int> and the corresponding QSet <via>, add each via to the QSet corresponding to the plane layer pair it intersects <QPair<int,int> > In this way, each via has a direct connection to the plane layer pair it intersects.

[0070] Preferably, multiple algorithms can be used to implement it, such as hash table conversion algorithm, shortest path algorithm in graph theory, etc., to ensure the efficiency and accuracy of the conversion process. In addition, parallel computing technology, such as GPU acceleration or distributed computing, can also be introduced to handle large-scale data structure conversion tasks.

[0071] Based on the relationship between each via being cut by a plane, holes divided by the plane are cut out.

[0072] It should be noted that cutting refers to the precise physical division of vias according to design requirements during the manufacturing process of the circuit board to achieve hierarchical connection of the circuit.

[0073] Specifically, you can traverse the converted data structure QMap <Via,QSet<QPair<int,int> >>To achieve this, for each via, obtain its intersecting plane layer pair, then determine the via segmentation position based on this information and perform the cutting operation.

[0074] Preferably, a variety of cutting techniques can be used, such as laser cutting, plasma cutting or mechanical drilling, to ensure the accuracy and quality of cutting. In addition, an automated cutting control system can be introduced to improve the automation and repeatability of the cutting process.

[0075] In some embodiments, calculating the connection relationship of all elements in a multi-layer integrated circuit board includes the following steps:

[0076] Use graph theory algorithms to build the connection diagram of the circuit board;

[0077] Through the connection diagram of the circuit board, identify and record the connection relationship between each via and the plane layer.

[0078] First, define each element on the circuit board (e.g., vias, pads, conductive layers, etc.) as a node in the graph. Then, define the edges in the graph based on the physical or electrical connections between these elements. For example, if two vias are connected by a conductive layer, draw an edge between the corresponding nodes. In this way, the connection relationship of the entire circuit board can be abstracted as a graph structure.

[0079] Preferably, the process of constructing the connection graph can use a variety of graph theory algorithms, such as depth-first search (DFS) or breadth-first search (BFS) to traverse the elements of the circuit board and determine the connection relationship between them. In addition, an existing graph database or graph processing software can be used to assist in the construction and storage of this connection graph for subsequent processing and analysis. For example, a graph database such as Neo4j can be used to store the connection graph, and the graph algorithm provided by it can be used for efficient query and analysis.

[0080] More specifically, the process of constructing a connection graph may include: first, numbering or labeling all elements on the circuit board for easy identification in the graph. Then, based on the design file or manufacturing data of the circuit board, determine the connection relationship between these elements and add corresponding edges to the graph. In addition, weights or labels can be added to the edges in the graph to indicate the strength, type, or other properties of the connection. For example, weights can be added to edges representing conductive connections to indicate the conductivity or signal transmission characteristics of the connection. In this way, the connection graph can not only represent the topology of the circuit board, but also provide detailed information about the connection characteristics.

[0081] In some embodiments, for each hole, from top to bottom or from bottom to top, finding a plane connected thereto comprises:

[0082] Determine the vertical position of each via;

[0083] Based on the vertical position of the via, identify the plane layer that intersects with it;

[0084] Record the connection information between each via and the intersecting plane layer.

[0085] Accurately determine the vertical position of each via, which is a key step in identifying the connection relationship between the via and the plane layer. The vertical position refers to the relative position of the via in the PCB stackup structure.

[0086] Specifically, determining the vertical position of the via can be achieved through a variety of technologies, such as using X-ray imaging technology or mechanical probe scanning technology to measure the specific position of the via in the PCB. In addition, the position of the via can also be predetermined by computer-aided design (CAD) data in the design stage. Once the vertical position of the via is determined, the plane layer that intersects with it can be identified based on this position information. This step is completed by analyzing the laminated structure of the PCB, which involves an understanding of the physical and electrical properties of each layer in the PCB.

[0087] Preferably, an automated optical inspection device can be used to identify and verify the vertical position of the via. Such equipment can provide high-precision measurements and can quickly process large amounts of data. In addition, a machine learning algorithm can be used to analyze the connection relationship between the via and the plane layer to improve the accuracy and efficiency of the identification process. For example, a machine learning model can be trained to identify the connection pattern between the via and the plane layer, thereby reducing manual intervention and improving production efficiency.

[0088] When recording the connection information of each via and the intersecting plane layer, barcode or QR code labels can be used to mark the vias, and the connection information can be automatically recorded by scanning these labels. Such an automated recording system can not only reduce human errors, but also improve the speed and accuracy of data recording. In addition, this data can be integrated into the PCB manufacturing execution system (MES) to facilitate tracking and analysis of the entire production process.

[0089] In some embodiments, ordering the layers of the connected planes includes:

[0090] Assign a priority value to each plane layer based on its physical location or electrical characteristics;

[0091] Sort the plane layers by priority value.

[0092] Sorting the connected plane layers ensures that each plane layer can be processed according to a specific priority during the subsequent via segmentation process. Plane layers usually refer to the various layers used to arrange circuits in a printed circuit board (PCB), and these layers are arranged in order according to certain rules or standards.

[0093] Specifically, it can be done by analyzing the physical position or electrical characteristics of each plane layer. For example, a priority value can be assigned to each plane layer based on factors such as the proximity of the plane layer to the via, the current capacity requirement, and the signal integrity requirement. In practice, the power layer and the ground layer usually need to be tightly coupled to increase the capacitance between the power layer and the ground layer, thereby increasing the resonant frequency. In addition, the high-speed signal transmission layer should be a signal intermediate layer and sandwiched between two inner electrical layers to provide electromagnetic shielding and limit signal radiation.

[0094] Preferably, the sorting process can also take into account the symmetry of the stacked structure to reduce crosstalk between signal layers. For example, avoiding two signal layers directly adjacent to each other and adding a ground plane between them can effectively avoid crosstalk. At the same time, automated algorithms, such as the Kruskal algorithm or topological sorting, can also be used to handle the sorting problem to ensure that each signal layer is adjacent to a suitable reference layer. In this way, the performance of the circuit board can be optimized, and the signal integrity and power supply stability can be improved.

[0095] In some embodiments, the data structure QMap of the holes that combine two plane partitions <QPair<int,int> ,QSet <via>> Includes:

[0096] For each pair of intersecting planes, create a QPair<int,int> Instance, represents this pair of plane layers;

[0097] For each QPair<int,int> Example, create a QSet <via>An instance for storing vias intersecting the pair of plane layers;

[0098] Add each via to the QSet corresponding to the plane layer it intersects <via>middle.

[0099] It should be noted that the data structure QMap <QPair<int,int> ,QSet <via>> is used to store and organize the relationship between vias and intersecting plane layers. QMap is an associative container based on key-value pairs, which allows you to map vias based on a key (in this case, QPair<int,int> ) to quickly look up a value (in this case a QSet <via>). QPair<int,int> QSet is a template class used to store a pair of values, which is used here to represent the numbers of two plane layers. <via>Is an unordered collection used to store unique via identifiers (Via).

[0100] First, traverse all possible plane layer pairs in the multi-layer integrated circuit board, and for each pair of intersecting plane layers, create a QPair<int,int> Then, for each QPair<int,int> Example, create a QSet <via>Instance to store the vias that intersect this pair of plane layers. In this process, QSet <via>By utilizing the unordered collection feature, the stored via identifiers are ensured to be unique and duplication is avoided.

[0101] Preferably, when creating a QPair<int,int> When you create an instance, you can also overload the global hash function (qHash()) for it to ensure that QMap can efficiently handle the hash value of the key. In addition, you can <via>You can use custom comparison functions to further optimize the storage and retrieval efficiency of vias. For example, you can define a structure or class for Via and overload comparison operators (such as <) in it so that QSet can sort or retrieve vias according to specific criteria.

[0102] In some embodiments, the conversion data structure is a QMap <Via,QSet<QPair<int,int> >> Includes:

[0103] For each via, create a QSet <QPair<int,int> >Instance, used to store the plane layer pair intersected by the via;

[0104] Traversing the original data structure QMap <QPair<int,int> ,QSet <via>>, for each QPair<int,int> and the corresponding QSet <via>, add each via to the QSet corresponding to the plane layer pair it intersects <QPair<int,int> >Medium;

[0105] Construct a new data structure QMap <Via,QSet<QPair<int,int> >>.

[0106] In order to reorganize the information in the original data structure, detailed information of the plane layer pairs intersecting with each via is provided. This conversion makes the data more directly reflect the relationship between the via and the plane layer, which is convenient for subsequent analysis and processing.

[0107] Specifically, this step can be achieved in the following way: First, create a QSet for each via <QPair<int,int> >Instance, this collection will be used to store the plane layer pairs that intersect with the via. Then, traverse the original data structure QMap <QPair<int,int> ,QSet <via>>For each entry in QPair<int,int> ) and its corresponding via set (QSet <via>), add these vias to the QSet corresponding to the plane layer pairs they intersect <QPair<int,int> > in.

[0108] In some embodiments, iterators can be used during the traversal process to avoid unnecessary data copying, or a range-based for loop of C++11 can be used to simplify the code. In addition, an exception handling mechanism can be introduced to handle any errors that may occur during the traversal or insertion process to ensure the robustness of the data structure conversion.

[0109] In some embodiments, based on the relationship that each Via is cut by a plane, cutting out holes divided by the plane includes:

[0110] Traversing the QMap data structure <Via,QSet<QPair<int,int> >> For each via, get the intersecting plane layer pair;

[0111] Determine the splitting position of the via according to the intersecting plane layer pairs;

[0112] The holes divided by the plane are cut out based on the determined division positions of the via holes.

[0113] Based on the obtained relationship between each via and the plane layer, the via is accurately segmented. This step is the key link of the whole method, which ensures that the via can be correctly segmented according to the specific design requirements of the multi-layer integrated circuit board.

[0114] First, traverse the data structure QMap <Via,QSet<QPair<int,int> >> For each entry in the data structure, get all the intersecting plane layer pairs corresponding to each via. In this process, the QMap key (via identifier) ​​and value (the set of plane layer pairs intersecting with the via) will be used to determine the exact location of each via and the plane layer that needs to be split.

[0115] This can be assisted by automated software tools. For example, an algorithm can be developed that can read the data in QMap and calculate the via segmentation position based on the intersection relationship between the via and the plane layer. This algorithm can be integrated into the PCB design software to perform via segmentation in an automated manner.

[0116] When determining the segmentation position of the via, advanced computational geometry algorithms, such as line segment intersection algorithms or polygon clipping algorithms, can be used to ensure the accuracy of the segmentation position. In addition, machine learning techniques can be introduced to predict and optimize the cutting path of the via to further improve the efficiency and accuracy of the cutting process. For example, machine learning models can be used to analyze historical cutting data, learn the best cutting strategies for different types of vias, and apply these strategies to guide the actual cutting process.

[0117] The above embodiments of the present invention have the following beneficial effects:

[0118] The above-mentioned embodiment of the present invention significantly improves the accuracy and efficiency of via segmentation by accurately calculating the connection relationship between vias and plane layers in a multi-layer integrated circuit board and using an efficient data structure to organize and process this information. This method not only reduces the number of iterations in the design stage, but also reduces the error rate in the manufacturing process, thereby shortening the overall production cycle and reducing costs. In addition, the automated data processing process reduces manual intervention, further improves the reliability of the design, and provides strong technical support for the design and manufacture of multi-layer integrated circuit boards.

[0119] Some embodiments provide a via segmentation system for a multi-layer integrated circuit board, the system comprising:

[0120] A calculation module, used to calculate the connection relationship of all elements in the multi-layer integrated circuit board;

[0121] A connecting plane module is used to find the plane connected to each hole from top to bottom or from bottom to top;

[0122] A sorting module, used to sort the layers of the connected planes;

[0123] Combination module, used to combine the hole data structure QMap of two plane partitions <QPair<int,int> ,QSet <via>>

[0124] Conversion module, used to convert data structures to QMap <Via,QSet<QPair<int,int> >>, you can get the relationship between each Via being cut by the plane;

[0125] The cutting module is used to cut out holes divided by planes based on the relationship between each Via being cut by the plane.

[0126] It is understood that the modules described in the via segmentation system of the multilayer integrated circuit board are similar to those described in the reference Figure 1 The steps in the method of the via segmentation system of the multi-layer integrated circuit board described above correspond to each other. Therefore, the operations, features and beneficial effects described above for the via segmentation system of the multi-layer integrated circuit board are also applicable to the via segmentation system of the multi-layer integrated circuit board and the modules contained therein, and will not be repeated here.

[0127] The electronic devices in some embodiments of the present invention may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc.

[0128] Electronic devices may include processing devices (e.g., central processing units, graphics processing units, etc.), which may perform various appropriate actions and processes according to programs stored in a read-only memory (ROM) or programs loaded from a storage device into a random access memory (RAM). In RAM, various programs and data required for the operation of the electronic device are also stored. The processing device, ROM, and RAM are connected to each other via a bus. An input / output (I / O) interface is also connected to the bus.

[0129] Typically, the following devices can be connected to the I / O interface: input devices including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices including, for example, a magnetic tape, a hard disk, etc.; and communication devices. The communication device can allow the electronic device to communicate with other devices wirelessly or by wire to exchange data. It should be understood that it is not required to implement or have all the devices shown. More or fewer devices may be implemented or have alternatively. Each box shown may represent one device, or may represent multiple devices as needed.

[0130] Furthermore, the storage medium of the embodiment of the present application stores program instructions that can implement all the above methods, wherein the program instructions can be stored in the above storage medium in the form of a software product, including several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, or terminal devices such as a computer, a server, a mobile phone, and a tablet.

[0131] The above descriptions are only some preferred embodiments of the present invention and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present invention is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the embodiments of the present invention to form a technical solution.< / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via>

Claims

1. A method for quickly solving plane segmentation vias in a multi-layer integrated circuit board, characterized in that: The steps include: Calculate the connection relationship of all elements in a multi-layer integrated circuit board; For each hole, find the plane that connects to it from top to bottom or from bottom to top; Sort the layers of the connected planes; Combine the holes split by two planes into a QMap data structure <QPair<int,int> ,QSet <via> >；< / via> Convert data structure to QMap <Via,QSet<QPair<int,int> >>, you can get the relationship between each Via being cut by the plane; Based on the relationship between each via being cut by a plane, holes divided by the plane are cut out.

2. The method according to claim 1, characterized in that Calculating the connection relationship of all elements in a multilayer integrated circuit board includes the following steps: Use graph theory algorithms to build the connection diagram of the circuit board; Through the connection diagram of the circuit board, identify and record the connection relationship between each via and the plane layer.

3. The method according to claim 1 or 2, characterized in that: For each hole, from top to bottom or bottom to top, find the planes that connect it: Determine the vertical position of each via; Based on the vertical position of the via, identify the plane layer that intersects with it; Record the connection information between each via and the intersecting plane layer.

4. The method according to claim 1 or 3, characterized in that: Sorting the layers of a connected plane involves: Assign a priority value to each plane layer based on its physical location or electrical characteristics; Sort the plane layers by priority value.

5. The method according to claim 1 or 4, characterized in that: Combine the holes split by two planes into a QMap data structure <QPair<int,int> ,QSet <via> > Includes:< / via> For each pair of intersecting planes, create a QPair<int,int> Instance, represents this pair of plane layers; For each QPair<int,int> Example, create a QSet <via> An instance for storing vias intersecting the pair of plane layers;< / via> Add each via to the QSet corresponding to the plane layer it intersects <via> middle.< / via> 6. The method according to claim 1 or 5, characterized in that: Convert data structure to QMap <Via,QSet<QPair<int,int> >> Includes: For each via, create a QSet <QPair<int,int> >Instance, used to store the plane layer pair intersected by the via; Traversing the original data structure QMap <QPair<int,int> ,QSet <via>>, for each QPair<int,int> and the corresponding QSet <via> , add each via to the QSet corresponding to the plane layer pair it intersects <QPair<int,int> >Medium;< / via> < / via> Construct a new data structure QMap <Via,QSet<QPair<int,int> >>.

7. The method according to claim 1 or 6, characterized in that: Based on the relationship between each Via being cut by a plane, the holes cut out by the plane include: Traversing the QMap data structure <Via,QSet<QPair<int,int> >> For each via, get the intersecting plane layer pair; Determine the splitting position of the via according to the intersecting plane layer pairs; The holes divided by the plane are cut out based on the determined division positions of the via holes.

8. A via segmentation system for a multi-layer integrated circuit board, characterized in that: The system includes: A calculation module, used to calculate the connection relationship of all elements in the multi-layer integrated circuit board; A connecting plane module is used to find the plane connected to each hole from top to bottom or from bottom to top; A sorting module, used to sort the layers of the connected planes; Combination module, used to combine the hole data structure QMap of two plane partitions <QPair<int,int> ,QSet <via> >；< / via> Conversion module, used to convert data structures to QMap <Via,QSet<QPair<int,int> >>, you can get the relationship between each Via being cut by the plane; The cutting module is used to cut out holes divided by planes based on the relationship between each Via being cut by the plane.

9. An electronic device, comprising: at least one processor; as well as A memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor so that the at least one processor can execute a method for quickly solving plane segmentation vias in a multi-layer integrated circuit board as described in any one of claims 1-7.

10. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to enable the computer to execute a method for quickly solving plane segmentation vias in a multi-layer integrated circuit board according to any one of claims 1-7.

Images