Matrix transposition method and device based on hardware, storage medium and chip
By configuring a buffer for the matrix and switching the read and write directions during the transposition operation, the problem of configuring two buffers in the prior art resulting in large chip area is solved, and efficient matrix transposition and area reduction are achieved.
Patent Information
- Application Number
- CN202411600339.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-11
- Publication Date
- 2025-02-28
AI Technical Summary
In the prior art, two buffers are configured to perform ping-pong operations on the matrix, resulting in a large chip area.
By configuring a buffer for the matrix to be transposed, during the transpose operation, data is cached into the buffer according to the first write direction, and after full writing, the destination address is read out and written, and then the new data is cached to the free area according to the second write direction until the matrix transposition is completed.
The ping-pong operation of the matrix is achieved through a buffer, which improves the efficiency of matrix transposition, reduces the area of the chip, and reduces the impact of bandwidth instability on chip performance.
Smart Images
Figure CN119538999A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chips, and in particular to a hardware-based matrix transposition method, device, storage medium and chip. Background Art
[0002] When a neural network processing unit (NPU) is used to transpose a matrix, two buffers are usually configured, and a ping-pong operation is performed on the matrix through the two buffers during the transposition process.
[0003] Specifically, the matrix to be transposed is determined according to the source address, and data is read from the matrix row by row and written into the first buffer; data is read from the first buffer column by column and written into the destination address, and at the same time, data is read from the matrix row by row and written into the second buffer; data is read from the second buffer column by column and written into the destination address, and at the same time, data is read from the matrix row by row and written into the first buffer; and so on, until all data in the matrix is written into the destination address and then stops.
[0004] Since two buffers need to be configured to read and write matrix data, the chip area is larger. Summary of the invention
[0005] The present application provides a hardware-based matrix transposition method, device, storage medium and chip, which are used to solve the problem that configuring two buffers to perform ping-pong operations on the matrix results in a large chip area. The technical solution is as follows:
[0006] According to a first aspect of the present application, a hardware-based matrix transposition method is provided, the method comprising:
[0007] Configure a buffer for the matrix to be transposed;
[0008] When performing a transposition operation on the matrix, caching data read from the matrix into the buffer in a first writing direction;
[0009] After the buffer is filled, the data in the buffer are sequentially read out and written into the destination address according to a first reading direction, the first reading direction is perpendicular to the first writing direction, and at the same time, the data newly read from the matrix is cached into an idle area according to a second writing direction, the idle area is an area released after the data is read out, and the second writing direction is the same as the first reading direction;
[0010] After all the data in the buffer are refreshed, the data in the buffer are sequentially read out and written into the destination address according to a second read direction, the second read direction is the same as the first write direction, and at the same time, the data newly read from the matrix is cached into the free area according to the first write direction;
[0011] The transposition operation is stopped until all the data in the matrix are written into the destination address.
[0012] In a possible implementation manner, the first writing direction and the second reading direction are row directions, and the first reading direction and the second writing direction are column directions.
[0013] In a possible implementation, the step of sequentially reading the data in the buffer and writing the data in the destination address in the first reading direction includes: sequentially reading the i-th column of data in the buffer and writing the data in the destination address, where i is a positive integer;
[0014] The caching of the data newly read from the matrix into the free area according to the second write direction includes: releasing the free area of the i-th column after the data of the i-th column is read out, and caching a row of data newly read from the matrix into the free area of the i-th column.
[0015] In a possible implementation, sequentially reading the data in the buffer and writing them to the destination address according to the second reading direction includes: sequentially reading the j-th row of data in the buffer and writing them to the destination address, where j is a positive integer;
[0016] The caching of the data newly read from the matrix into the free area according to the first write direction includes: releasing the j-th row of free area after the j-th row of data is read out, and caching a row of data newly read from the matrix into the j-th row of free area.
[0017] In a possible implementation manner, the first writing direction and the second reading direction are column directions, and the first reading direction and the second writing direction are row directions.
[0018] In a possible implementation, sequentially reading the data in the buffer and writing them to the destination address according to the first reading direction includes: sequentially reading the i-th row of data in the buffer and writing them to the destination address, where i is a positive integer;
[0019] The method of caching the data newly read from the matrix into the free area according to the second write direction includes: releasing the free area of the i-th row after the i-th row of data is read out, and caching a column of data newly read from the matrix into the free area of the i-th row.
[0020] In a possible implementation, sequentially reading the data in the buffer and writing them to the destination address according to the second read direction includes: sequentially reading the j-th column of data in the buffer and writing them to the destination address, where j is a positive integer;
[0021] The caching of the data newly read from the matrix into the free area according to the first write direction includes: releasing the jth column free area after the jth column data is read out, and caching a column of data newly read from the matrix into the jth column free area.
[0022] According to a second aspect of the present application, a hardware-based matrix transposition device is provided, the device comprising:
[0023] A configuration module is used to configure a buffer for the matrix to be transposed;
[0024] a transposition module, configured to cache data read from the matrix into the buffer in a first writing direction when performing a transposition operation on the matrix;
[0025] The transposition module is further used to read the data in the buffer in sequence and write them into the destination address according to a first reading direction after the buffer is filled, wherein the first reading direction is perpendicular to the first writing direction, and at the same time, cache the newly read data from the matrix into an idle area according to a second writing direction, wherein the idle area is an area released after the data is read out, and the second writing direction is the same as the first reading direction;
[0026] The transposition module is further configured to read out the data in the buffer in sequence and write them into the destination address according to a second reading direction after all the data in the buffer are refreshed, wherein the second reading direction is the same as the first writing direction, and at the same time, cache the data newly read from the matrix into the free area according to the first writing direction;
[0027] The transposition module is further configured to stop the transposition operation until all the data in the matrix are written into the destination address.
[0028] According to a third aspect of the present application, a computer-readable storage medium is provided, wherein at least one instruction is stored in the storage medium, and the at least one instruction is loaded and executed by a processor to implement the hardware-based matrix transposition method as described above.
[0029] According to a fourth aspect of the present application, a chip is provided, wherein the chip includes the above-mentioned hardware-based matrix transposition device.
[0030] The beneficial effects of the technical solution provided by this application include at least:
[0031] After a row of data in the buffer is read out, a row of free areas is released, and new data in the matrix is written into this row of free areas; then, after a column of data in the buffer is read out, a column of free areas is released, and new data in the matrix is written into this column of free areas. In this way, by switching the reading and writing direction of the data in the buffer, it is possible to fully utilize the released cache space to write new data while reading data, thereby realizing ping-pong operation through a buffer, which not only improves the transposition efficiency of the matrix, but also reduces the area of the chip and reduces the impact of bandwidth instability on chip performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0033] Figure 1 is a flowchart of a hardware-based matrix transposition method provided by an embodiment of the present application;
[0034] Figure 2 is a flowchart of a hardware-based matrix transposition method provided by an embodiment of the present application;
[0035] Figure 3 is a schematic diagram of the reading and writing direction of data in a buffer zone shown in one embodiment of the present application;
[0036] Figure 4 is a flowchart of a hardware-based matrix transposition method provided by an embodiment of the present application;
[0037] Figure 5 It is a structural block diagram of a hardware-based matrix transposition device provided by an embodiment of the present application. DETAILED DESCRIPTION
[0038] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.
[0039] like Figure 1 As shown, it shows a method flow chart of a hardware-based matrix transposition method provided by an embodiment of the present application, and the hardware-based matrix transposition method can be applied to a chip. The hardware-based matrix transposition method may include:
[0040] Step 101, configure a buffer for the matrix to be transposed.
[0041] When using the NPU hardening solution to perform a transposition operation on a matrix, a buffer needs to be configured for the matrix. The storage space of the buffer is smaller than the storage space of all the data in the matrix, that is, the data in the matrix needs to be written into the buffer in batches for the transposition operation.
[0042] Step 102 : When performing a transposition operation on a matrix, cache the data read from the matrix into a buffer according to a first writing direction.
[0043] The first writing direction is the same as the reading direction of the data in the matrix. Specifically, when the reading direction of the data in the matrix is the row direction, the first writing direction is the row direction, that is, a row of data is read from the matrix and the row of data is written into a row area of the buffer. When the reading direction of the data in the matrix is the column direction, the first writing direction is the column direction, that is, a column of data is read from the matrix and the column of data is written into a column area of the buffer.
[0044] Step 103, after the buffer is filled, the data in the buffer is read out and written into the destination address in sequence according to the first reading direction, the first reading direction and the first writing direction are perpendicular to each other, and at the same time, the data newly read from the matrix is cached into the free area according to the second writing direction, the free area is the area released after the data is read out, and the second writing direction is the same as the first reading direction.
[0045] The destination address is the storage address of the transposed matrix of the matrix.
[0046] When the first writing direction is the row direction, the first reading direction is the column direction, and the second writing direction is also the column direction; when the first writing direction is the column direction, the first reading direction is the row direction, and the second writing direction is also the row direction, so as to realize data transposition.
[0047] When the first reading direction is the row direction, each time a row of data is read from the buffer, a row of free areas is released in the buffer. At this time, new data can be read from the remaining data in the matrix and cached in this row of free areas.
[0048] When the first reading direction is the column direction, each time a column of data is read from the buffer, a column of free area is released in the buffer. At this time, new data can be read from the remaining data in the matrix and cached in this column of free area.
[0049] In this way, while the cached data is read out from the buffer, new data in the matrix can be written into the free area that has been released in the buffer, thereby realizing a data ping-pong operation through a buffer.
[0050] Step 104, after all the data in the buffer are refreshed, the data in the buffer are read out and written to the destination address in sequence according to the second read direction, the second read direction is the same as the first write direction, and at the same time, the data newly read from the matrix is cached into the free area according to the first write direction.
[0051] The data in the buffer is completely refreshed, which means that all the data in the buffer is read out, and all the free areas are filled with data again. Assuming that the storage space of the buffer is 5×5, and the first reading direction is the column direction, the data in the buffer is completely refreshed, which means that 5 columns of data are read out, and 5 columns of new data are written again.
[0052] When the first writing direction is a row direction, the second reading direction is a row direction; when the first writing direction is a column direction, the second reading direction is a column direction.
[0053] When the second reading direction is the row direction, each time a row of data is read from the buffer, a row of free areas is released in the buffer. At this time, new data can be read from the remaining data in the matrix and cached in this row of free areas.
[0054] When the second reading direction is the column direction, each time a column of data is read from the buffer, a column of free area is released in the buffer. At this time, new data can be read from the remaining data in the matrix and cached in this column of free area.
[0055] In this way, while the cached data is read out from the buffer, new data in the matrix can be written into the free area that has been released in the buffer, thereby realizing a data ping-pong operation through a buffer.
[0056] Step 105, the transposition operation is stopped until all the data in the matrix are written into the destination address.
[0057] In this embodiment, steps 103 and 104 may be executed cyclically until all the data in the matrix are written into the destination address, thereby completing the transposition of the matrix.
[0058] In summary, the hardware-based matrix transposition method provided by the embodiment of the present application releases a row of free areas after a row of data in the buffer is read out, and writes new data in the matrix into the row of free areas; then, after a column of data in the buffer is read out, releases a column of free areas, and writes new data in the matrix into the column of free areas. In this way, by switching the reading and writing direction of the data in the buffer, it is possible to fully utilize the released cache space to write new data while reading data, thereby realizing ping-pong operation through a buffer, which not only improves the transposition efficiency of the matrix, but also reduces the area of the chip, and can also reduce the impact of bandwidth instability on chip performance.
[0059] In this embodiment, the first writing direction and the second reading direction are row directions, and the first reading direction and the second writing direction are column directions. Figure 2 As shown, it shows a flowchart of a hardware-based matrix transposition method provided by an embodiment of the present application, and the hardware-based matrix transposition method can be applied to a chip. The hardware-based matrix transposition method may include:
[0060] Step 201: configure a buffer for the matrix to be transposed.
[0061] When using the NPU hardening solution to perform a transposition operation on a matrix, a buffer needs to be configured for the matrix. The storage space of the buffer is smaller than the storage space of all the data in the matrix, that is, the data in the matrix needs to be written into the buffer in batches for the transposition operation.
[0062] Step 202: When performing a transposition operation on a matrix, data read from the matrix is cached in a buffer in a row direction.
[0063] Specifically, data is read from the matrix row by row, and each row of data is cached in a corresponding row area in the buffer.
[0064] like Figure 3 As shown, the data in the matrix is cached into the buffer according to the write direction 1.
[0065] Step 203, after the buffer is filled, the i-th column data in the buffer is read out in sequence and written into the destination address. At the same time, after the i-th column data is read out, the i-th column free area is released, and a row of data newly read from the matrix is cached in the i-th column free area.
[0066] Wherein, i is a positive integer.
[0067] The destination address is the storage address of the transposed matrix of the matrix.
[0068] Each time a column of data is read from the buffer, a column of free area is released in the buffer. At this time, new data can be read from the remaining data in the matrix and cached in this column of free area.
[0069] like Figure 3 As shown, data is read from the buffer according to the read direction 1, and data in the matrix is cached in the buffer according to the write direction 2.
[0070] In this way, while the cached data is read out from the buffer, new data in the matrix can be written into the free area that has been released in the buffer, thereby realizing a data ping-pong operation through a buffer.
[0071] Step 204, after all the data in the buffer are refreshed, the j-th row of data in the buffer is read out and written to the destination address in sequence. At the same time, after the j-th row of data is read out, the j-th row of free area is released, and a row of data newly read from the matrix is cached in the j-th row of free area.
[0072] Wherein, j is a positive integer.
[0073] Each time a row of data is read from the buffer, a row of free area is released in the buffer. At this time, new data can be read from the remaining data in the matrix and cached in this row of free area.
[0074] like Figure 3 As shown, data is read from the buffer according to the read direction 2, and data in the matrix is cached in the buffer according to the write direction 1.
[0075] In this way, while the cached data is read out from the buffer, new data in the matrix can be written into the free area that has been released in the buffer, thereby realizing a data ping-pong operation through a buffer.
[0076] Step 205, the transposition operation is stopped until all the data in the matrix are written into the destination address.
[0077] In this embodiment, steps 203 and 204 may be executed cyclically until all the data in the matrix are written into the destination address, thereby completing the transposition of the matrix.
[0078] In summary, the hardware-based matrix transposition method provided by the embodiment of the present application releases a row of free areas after a row of data in the buffer is read out, and writes new data in the matrix into the row of free areas; then, after a column of data in the buffer is read out, releases a column of free areas, and writes new data in the matrix into the column of free areas. In this way, by switching the reading and writing direction of the data in the buffer, it is possible to fully utilize the released cache space to write new data while reading data, thereby realizing ping-pong operation through a buffer, which not only improves the transposition efficiency of the matrix, but also reduces the area of the chip, and can also reduce the impact of bandwidth instability on chip performance.
[0079] In this embodiment, the first writing direction and the second reading direction are column directions, and the first reading direction and the second writing direction are row directions. Figure 4 As shown, it shows a flowchart of a hardware-based matrix transposition method provided by an embodiment of the present application, and the hardware-based matrix transposition method can be applied to a chip. The hardware-based matrix transposition method may include:
[0080] Step 401: configure a buffer for the matrix to be transposed.
[0081] When using the NPU hardening solution to perform a transposition operation on a matrix, a buffer needs to be configured for the matrix. The storage space of the buffer is smaller than the storage space of all the data in the matrix, that is, the data in the matrix needs to be written into the buffer in batches for the transposition operation.
[0082] Step 402: When performing a transposition operation on the matrix, data read from the matrix is cached in a buffer in a column direction.
[0083] Specifically, data is read from the matrix column by column, and each column of data is cached in a corresponding column area in the buffer.
[0084] Step 403, after the buffer is filled, the i-th row data in the buffer is read out in sequence and written into the destination address. At the same time, after the i-th row data is read out, the i-th row free area is released, and a column of data newly read from the matrix is cached into the i-th row free area.
[0085] Wherein, i is a positive integer.
[0086] The destination address is the storage address of the transposed matrix of the matrix.
[0087] Each time a row of data is read from the buffer, a row of free area is released in the buffer. At this time, new data can be read from the remaining data in the matrix and cached in this row of free area.
[0088] In this way, while the cached data is read out from the buffer, new data in the matrix can be written into the free area that has been released in the buffer, thereby realizing a data ping-pong operation through a buffer.
[0089] Step 404, after all the data in the buffer are refreshed, the j-th column data in the buffer is read out and written to the destination address in sequence. At the same time, after the j-th column data is read out, the j-th column free area is released, and a column of data newly read from the matrix is cached in the j-th column free area.
[0090] Wherein, j is a positive integer.
[0091] Each time a column of data is read from the buffer, a column of free area is released in the buffer. At this time, new data can be read from the remaining data in the matrix and cached in this column of free area.
[0092] In this way, while the cached data is read out from the buffer, new data in the matrix can be written into the free area that has been released in the buffer, thereby realizing a data ping-pong operation through a buffer.
[0093] Step 405, the transposition operation is stopped until all the data in the matrix are written into the destination address.
[0094] In this embodiment, steps 403 and 404 may be executed cyclically until all the data in the matrix are written into the destination address, thereby completing the transposition of the matrix.
[0095] In summary, the hardware-based matrix transposition method provided by the embodiment of the present application releases a row of free areas after a row of data in the buffer is read out, and writes new data in the matrix into the row of free areas; then, after a column of data in the buffer is read out, releases a column of free areas, and writes new data in the matrix into the column of free areas. In this way, by switching the reading and writing direction of the data in the buffer, it is possible to fully utilize the released cache space to write new data while reading data, thereby realizing ping-pong operation through a buffer, which not only improves the transposition efficiency of the matrix, but also reduces the area of the chip, and can also reduce the impact of bandwidth instability on chip performance.
[0096] like Figure 5 As shown, it shows a structural block diagram of a hardware-based matrix transposition device provided by an embodiment of the present application, and the hardware-based matrix transposition device can be applied to a chip. The hardware-based matrix transposition device may include:
[0097] A configuration module 510, configured to configure a buffer for the matrix to be transposed;
[0098] A transposition module 520, configured to cache data read from the matrix into a buffer in a first writing direction when performing a transposition operation on the matrix;
[0099] The transposition module 520 is further used to read the data in the buffer in sequence and write them into the destination address according to a first reading direction after the buffer is filled, wherein the first reading direction is perpendicular to the first writing direction, and at the same time, cache the newly read data from the matrix into the free area according to the second writing direction, wherein the free area is an area released after the data is read out, and the second writing direction is the same as the first reading direction;
[0100] The transposition module 520 is further used to read the data in the buffer in sequence and write them into the destination address according to a second reading direction after all the data in the buffer is refreshed, wherein the second reading direction is the same as the first writing direction, and at the same time, cache the data newly read from the matrix into the free area according to the first writing direction;
[0101] The transposition module 520 is further configured to stop the transposition operation until all the data in the matrix is written into the destination address.
[0102] In an optional embodiment, the first writing direction and the second reading direction are row directions, and the first reading direction and the second writing direction are column directions.
[0103] In an optional embodiment, the transposition module 520 is further used to: sequentially read out the i-th column data in the buffer and write them into the destination address, where i is a positive integer;
[0104] The transposition module 520 is further used to release the free area of the i-th column after the i-th column data is read out, and cache a row of data newly read from the matrix into the free area of the i-th column.
[0105] In an optional embodiment, the transposition module 520 is further used to: sequentially read out the j-th row of data in the buffer and write it into the destination address, where j is a positive integer;
[0106] The transposition module 520 is further used to release the j-th row free area after the j-th row of data is read out, and cache a row of data newly read from the matrix into the j-th row free area.
[0107] In an optional embodiment, the first writing direction and the second reading direction are column directions, and the first reading direction and the second writing direction are row directions.
[0108] In an optional embodiment, the transposition module 520 is further used to: sequentially read out the i-th row of data in the buffer and write it into the destination address, where i is a positive integer;
[0109] The transposition module 520 is further used to release the free area of the i-th row after the i-th row of data is read out, and cache a column of data newly read from the matrix into the free area of the i-th row.
[0110] In an optional embodiment, the transposition module 520 is further used to: sequentially read out the j-th column of data in the buffer and write it into the destination address, where j is a positive integer;
[0111] The transposition module 520 is further used to release the jth column free area after the jth column data is read out, and cache a column of data newly read from the matrix into the jth column free area.
[0112] In summary, the hardware-based matrix transposition device provided in the embodiment of the present application releases a row of free areas after a row of data in the buffer is read out, and writes new data in the matrix into the row of free areas; then, after a column of data in the buffer is read out, a column of free areas is released, and the new data in the matrix is written into the column of free areas. In this way, by switching the reading and writing direction of the data in the buffer, it is possible to fully utilize the released cache space to write new data while reading the data, thereby realizing a ping-pong operation through a buffer, which not only improves the transposition efficiency of the matrix, but also reduces the area of the chip, and can also reduce the impact of bandwidth instability on chip performance.
[0113] An embodiment of the present application provides a computer-readable storage medium, wherein the storage medium stores at least one instruction, and the at least one instruction is loaded and executed by a processor to implement the hardware-based matrix transposition method as described above.
[0114] An embodiment of the present application provides a chip, wherein the chip includes any of the above-mentioned hardware-based matrix transposition devices.
[0115] It should be noted that: the hardware-based matrix transposition device provided in the above embodiment only uses the division of the above functional modules as an example when performing hardware-based matrix transposition. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the hardware-based matrix transposition device is divided into different functional modules to complete all or part of the functions described above. In addition, the hardware-based matrix transposition device provided in the above embodiment and the hardware-based matrix transposition method embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.
[0116] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.
[0117] The above description is not intended to limit the embodiments of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the protection scope of the embodiments of the present application.
Claims
1. A hardware-based matrix transposition method, characterized in that: The method comprises: Configure a buffer for the matrix to be transposed; When performing a transposition operation on the matrix, caching data read from the matrix into the buffer in a first writing direction; After the buffer is filled, the data in the buffer are sequentially read out and written into the destination address according to a first reading direction, the first reading direction is perpendicular to the first writing direction, and at the same time, the data newly read from the matrix is cached into an idle area according to a second writing direction, the idle area is an area released after the data is read out, and the second writing direction is the same as the first reading direction; After all the data in the buffer are refreshed, the data in the buffer are sequentially read out and written into the destination address according to a second read direction, the second read direction is the same as the first write direction, and at the same time, the data newly read from the matrix is cached into the free area according to the first write direction; The transposition operation is stopped until all the data in the matrix are written into the destination address.
2. The hardware-based matrix transposition method according to claim 1, characterized in that: The first writing direction and the second reading direction are row directions, and the first reading direction and the second writing direction are column directions.
3. The hardware-based matrix transposition method according to claim 2, characterized in that: The step of sequentially reading the data in the buffer and writing the data in the destination address according to the first reading direction includes: sequentially reading the i-th column of data in the buffer and writing the data in the destination address, where i is a positive integer; The caching of the data newly read from the matrix into the free area according to the second write direction includes: releasing the free area of the i-th column after the data of the i-th column is read out, and caching a row of data newly read from the matrix into the free area of the i-th column.
4. The hardware-based matrix transposition method according to claim 2, characterized in that: The step of sequentially reading the data in the buffer and writing the data in the destination address according to the second reading direction includes: sequentially reading the j-th row of data in the buffer and writing the data in the destination address, where j is a positive integer; The caching of the data newly read from the matrix into the free area according to the first write direction includes: releasing the j-th row of free area after the j-th row of data is read out, and caching a row of data newly read from the matrix into the j-th row of free area.
5. The hardware-based matrix transposition method according to claim 1, characterized in that: The first writing direction and the second reading direction are column directions, and the first reading direction and the second writing direction are row directions.
6. The hardware-based matrix transposition method according to claim 5, characterized in that: The step of sequentially reading the data in the buffer and writing the data in the destination address according to the first reading direction includes: sequentially reading the i-th row of data in the buffer and writing the data in the destination address, where i is a positive integer; The caching of the data newly read from the matrix into the free area according to the second write direction includes: releasing the free area of the i-th row after the i-th row of data is read out, and caching a column of data newly read from the matrix into the free area of the i-th row.
7. The hardware-based matrix transposition method according to claim 5, characterized in that: The step of sequentially reading the data in the buffer and writing the data in the destination address according to the second reading direction includes: sequentially reading the data in the jth column in the buffer and writing the data in the destination address, where j is a positive integer; The caching of the data newly read from the matrix into the free area according to the first write direction includes: releasing the jth column free area after the jth column data is read out, and caching a column of data newly read from the matrix into the jth column free area.
8. A hardware-based matrix transposition device, characterized in that: The device comprises: A configuration module is used to configure a buffer for the matrix to be transposed; a transposition module, configured to cache data read from the matrix into the buffer in a first writing direction when performing a transposition operation on the matrix; The transposition module is further used to read the data in the buffer in sequence and write them into the destination address according to a first reading direction after the buffer is filled, wherein the first reading direction is perpendicular to the first writing direction, and at the same time, cache the newly read data from the matrix into an idle area according to a second writing direction, wherein the idle area is an area released after the data is read out, and the second writing direction is the same as the first reading direction; The transposition module is further configured to read out the data in the buffer in sequence and write them into the destination address according to a second reading direction after all the data in the buffer are refreshed, wherein the second reading direction is the same as the first writing direction, and at the same time, cache the data newly read from the matrix into the free area according to the first writing direction; The transposition module is further configured to stop the transposition operation until all the data in the matrix are written into the destination address.
9. A computer-readable storage medium, characterized in that: The storage medium stores at least one instruction, and the at least one instruction is loaded and executed by the processor to implement the hardware-based matrix transposition method according to any one of claims 1 to 7.
10. A chip, characterized in that: Chips include: The hardware-based matrix transposition device as described in claim 8.