Method for improving silicon deposition

Abstract

The techniques of the present disclosure generally relate to the field of semiconductor devices. More specifically, semiconductor structures, systems, and methods of making the same include a surface-modified silicon layer formed by reacting a deposited silicon layer with a halide reactant. The system includes one or more reaction chambers constructed and arranged to hold a substrate; a silicon precursor container constructed and arranged to contain and evaporate a silicon precursor; a halide reactant container constructed and arranged to contain and vaporize a halide reactant; an exhaust gas source; and a controller; wherein a controller is configured to control the flow of the silicon precursor and the halide reactant into the reaction chamber, thereby forming a surface-modified silicon layer on the substrate.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor devices, manufacturing processes and systems. More specifically, systems and methods suitable for forming semiconductor structures including surface-modified silicon layers are disclosed. Background Art

[0002] The modern semiconductor industry faces several processing challenges in order to increase functionality while reducing device size. Semiconductor manufacturing involves a series of complex processes such as deposition, etching, lithography, and doping. Even small variations in these processes can lead to non-uniform material properties or device characteristics across the wafer. Process variations can be caused by factors such as equipment calibration, temperature fluctuations, or inconsistent chemical composition. For example, when thin silicon films are deposited onto a wafer to form various device layers, non-uniform deposition rates or film thicknesses can lead to variations in electrical properties, structural integrity, and semiconductor performance. A particular problem is the so-called "edge effect," which occurs when excess silicon material is deposited to the edge of the wafer surface. In conventional semiconductor manufacturing, excess silicon is typically polished or etched after deposition to smooth the surface and obtain a certain layer thickness and surface roughness. However, non-uniform or non-selective etching can lead to non-uniform feature depths, which can affect the electronic properties of semiconductor devices. Therefore, there is a need to remedy the above limitations of existing semiconductor manufacturing technology by providing a method for improving silicon deposition with increased uniformity and high yield. Summary of the invention

[0003] This summary is provided to introduce some concepts in a simplified form. These concepts are further described in detail in the detailed description of the example embodiments disclosed below. This summary is not intended to identify the key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0004] One aspect of the present disclosure relates to a system, comprising:

[0005] - one or more reaction chambers constructed and arranged to hold a substrate;

[0006] - a silicon precursor container constructed and arranged to contain and evaporate a silicon precursor;

[0007] - a halide reactant vessel constructed and arranged to contain and vaporize a halide reactant;

[0008] - Exhaust source; and

[0009] - Controller;

[0010] The controller is configured to control the silicon precursor and the halide reactant to flow into the reaction chamber, thereby forming a surface-modified silicon layer on the substrate.

[0011] In a specific embodiment, the system disclosed herein provides that the system also includes an oxygen reactant container, which is constructed and arranged to contain and evaporate an oxygen reactant; and wherein the controller is configured to control the flow of the oxygen reactant into the reaction chamber to form a surface-modified silicon oxide layer on the substrate.

[0012] In a specific embodiment, the system disclosed herein provides that the system also includes a nitrogen reactant container, which is constructed and arranged to contain and evaporate a nitrogen reactant; and wherein a controller is configured to control the flow of the nitrogen reactant into the reaction chamber to form a surface-modified silicon nitride layer on the substrate.

[0013] In another aspect, the present disclosure provides a method for precursor deposition in a semiconductor manufacturing process, the method comprising the steps of:

[0014] a) providing a substrate to a reaction chamber;

[0015] b) executing one or more loops, the loops comprising:

[0016] i. contacting the silicon precursor with at least a portion of the substrate by introducing a silicon precursor into the reaction chamber;

[0017] ii. contacting the halide reactant with at least a portion of the substrate by introducing a halide reactant into the reaction chamber,

[0018] Thereby, a surface modified silicon layer is formed on at least a portion of the substrate.

[0019] In certain embodiments, the methods disclosed herein provide a cycle of step b) further comprising contacting the oxygen reactant with at least a portion of the substrate by introducing the oxygen reactant into the reaction chamber; thereby forming a surface-modified silicon oxide layer on at least a portion of the substrate.

[0020] In certain embodiments, the methods disclosed herein provide a cycle of step b) further comprising contacting the nitrogen reactant with at least a portion of the substrate by introducing the nitrogen reactant into the reaction chamber; thereby forming a surface-modified silicon nitride layer on at least a portion of the substrate.

[0021] In certain embodiments, the methods disclosed herein provide for introducing the silicon precursor and the halide reactant into the reaction chamber simultaneously. In certain embodiments, the methods disclosed herein provide for introducing the silicon precursor into the reaction chamber prior to the halide reactant.

[0022] In certain embodiments, the methods disclosed herein provide for introducing the silicon precursor and the halide reactant into the reaction chamber at a silicon precursor / halide reactant volume flow ratio of at least 1.1 to at most 100.0.

[0023] In certain embodiments, the methods disclosed herein provide that the silicon precursor is selected from the group consisting of Si n H 2n+2 、Si n H 2n and Si(OR 1 )4; wherein n is an integer from 1 to 20, m is an integer from 3 to 20; and wherein each R 1 Independently selected from C 1-8 alkyl.

[0024] In certain embodiments, the methods disclosed herein provide a silicon precursor selected from silane (SiH4), disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H 10 ), isotetrasilane, pentasilane (Si5H 12 ), isopentasilane, neopentasilane, hexasilane (Si6H 14 ), cyclotrisilane (Si3H6), cyclotetrasilane (Si4H8), cyclopentasilane (Si5H 10 ), cyclohexasilane (Si6H 12 ), tetramethyl orthosilicate (Si(OCH3)4) and tetraethyl orthosilicate (Si(OC2H5)4).

[0025] In certain embodiments, the methods disclosed herein provide that the halide reactant is selected from elemental halogens and halogen compounds; and wherein the halogen compound comprises an element selected from H, B, Al, Si, P, O, N and S and one or more halogens.

[0026] In certain embodiments, the methods disclosed herein provide that the halide reactant can be selected from fluorine (F2), chlorine (Cl2), bromine (Br2), iodine (I2), hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), hydrogen iodide (HI), phosphorus trifluoride (PF3), phosphorus pentafluoride (PF5), phosphorus trichloride (PCl3), phosphorus pentachloride (PCl5), thionyl chloride (SOCl2), phosphorus tribromide (PBr3), phosphorus pentabromide (PBr5), sulfur bromide (SOBr2), tetrafluorosilane (SiF4), tetrachlorosilane (SiCl4), tetrabromosilane (SiBr4), trifluorosilane (SiHF3), trichlorosilane (SiHCl3), tribromosilane (SiHBr3), ), difluorosilane (SiH2F2), dichlorosilane (SiH2Cl2), dibromosilane (SiH2Br2), fluorosilane (SiH3F), chlorosilane (SiH3Cl), bromosilane (SiH3Br), hexafluorodisilane (Si2F6), hexachlorodisilane (Si2Cl6), hexabromodisilane (Si2Br6), octafluorotrisilane (Si3F8), octachlorotrisilane (Si3Cl8), octabromotrisilane (Si3Br8), boron trifluoride (BF3), boron trichloride (BCl3), boron tribromide (BBr3), boron triiodide (BI3), aluminum trifluoride (AlF3), aluminum trichloride (AlCl3), aluminum tribromide (AlBr3) and aluminum triiodide (AlI3).

[0027] In certain embodiments, the methods disclosed herein provide that the substrate may be made of silicon oxide, silicon germanium, gallium arsenide, indium gallium arsenide, gallium nitride, and / or silicon nitride.

[0028] In certain embodiments, the methods disclosed herein provide for the formation of a surface modified silicon layer having an average growth rate of at least 0.05 nm / min.

[0029] In certain embodiments, the methods disclosed herein provide for the formation of a surface modified silicon layer having an average growth rate of at least 0.10 nm / min.

[0030] In certain embodiments, the methods disclosed herein provide that the substrate may be heated to a temperature of at least 200°C and at most 1000°C, preferably at least 350°C and at most 650°C.

[0031] In certain embodiments, the methods disclosed herein provide for a reaction chamber to have a pressure of at least 0.1 Torr and at most 50.0 Torr, preferably at least 0.5 Torr and at most 10 Torr.

[0032] In certain embodiments, the methods disclosed herein provide a surface modified silicon layer having an average surface roughness deviation of less than 10.0%.

[0033] In certain embodiments, the methods disclosed herein provide a surface modified silicon layer having an average surface roughness deviation of less than 3.0%.

[0034] In certain embodiments, the methods disclosed herein provide a surface modified silicon layer having an average thickness of 1 nm or less.

[0035] In certain embodiments, the methods disclosed herein provide that the steps of depositing a silicon precursor and reacting the deposited silicon layer with a halide reactant are repeated two or more times to obtain a target average thickness.

[0036] In a specific embodiment, further comprising a step c) of doping the formed surface modified silicon layer with a dopant, wherein the dopant comprises an element from the group comprising at least one of P, As, Sb, B, Al and In.

[0037] In certain embodiments, the methods disclosed herein also provide that the dopant can be selected from PH3, PF5, PCl5, PBr5, AsF5, AsCl5, AsBr5, AsH3, SbF3, SbCl3, SbBr3, BF3, BCl3, BBr3, B2H6, AlF3, AlCl3, AlBr3, InF3, InCl3 and InBr3.

[0038] Another aspect of the present disclosure relates to a layered structure comprising:

[0039] substrate, and

[0040] one or more surface modified silicon layers deposited on at least a portion of the substrate;

[0041] Characterized in that the surface-modified silicon layer or layers has an average surface roughness deviation of less than 10.0%.

[0042] In certain embodiments, the layered structures disclosed herein provide one or more surface modified silicon layers with an average surface roughness deviation of less than 3.0%.

[0043] In certain embodiments, the layered structures disclosed herein provide one or more surface-modified silicon layers obtained according to the methods disclosed herein.

[0044] In certain embodiments, the layered structures disclosed herein provide that each of the one or more surface-modified silicon layers has an average thickness of 1 nm or less.

[0045] In a specific embodiment, the layered structure further comprises a dopant, and wherein the dopant comprises an element from the group consisting of at least one of P, As, Sb, B, Al, and In.

[0046] Another aspect of the present disclosure relates to the use of a halide reactant for reducing within-wafer non-uniformity (WIWNU) of a surface modified silicon layer.

[0047] In certain embodiments, the uses disclosed herein provide that the surface modified silicon layer has an average surface roughness deviation of less than 10.0%.

[0048] In certain embodiments, the uses disclosed herein provide that the surface modified silicon layer has an average surface roughness deviation of less than 3.0%.

[0049] In certain embodiments, the uses disclosed herein provide that the halide reactant can be selected from fluorine (F2), chlorine (Cl2), bromine (Br2), iodine (I2), hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), hydrogen iodide (HI), phosphorus trifluoride (PF3), phosphorus pentafluoride (PF5), phosphorus trichloride (PCl3), phosphorus pentachloride (PCl5), thionyl chloride (SOCl2), phosphorus tribromide (PBr3), phosphorus pentabromide (PBr5), sulfur bromide (SOBr2), tetrafluorosilane (SiF4), tetrachlorosilane (SiCl4), tetrabromosilane (SiBr 4 ), trifluorosilane (SiHF3), trichlorosilane (SiHCl3), tribromosilane (SiHBr3), difluorosilane (SiH2F2), dichlorosilane (SiH2Cl2), dibromosilane (SiH2Br2), fluorosilane (SiH3F), chlorosilane (SiH3Cl), bromosilane (SiH3Br), hexafluorodisilane (Si2F6), hexachlorodisilane (Si2Cl6), hexabromodisilane (Si2Br6), octafluorotrisilane (Si3F8), octachlorotrisilane (Si3Cl8), octabromotrisilane (Si3Br8), boron trifluoride (BF3), boron trichloride (BCl3), boron tribromide (BBr3), boron triiodide (BI3), aluminum trifluoride (AlF3), aluminum trichloride (AlCl3), aluminum tribromide (AlBr3) and aluminum triiodide (AlI3). BRIEF DESCRIPTION OF THE DRAWINGS

[0050] It should be understood that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the size of some elements in the drawings may be exaggerated relative to other elements to help improve the understanding of the illustrated embodiments of the present disclosure.

[0051] Figure 1An exemplary embodiment of a precursor deposition method in a semiconductor manufacturing process of the present disclosure is described. The method begins 111 after a substrate has been provided to a reaction chamber. The cyclic deposition process includes contacting a silicon precursor with at least a portion of a substrate surface with a silicon precursor pulse 112. Optionally, after the silicon precursor pulse 112, the reaction chamber is purged 113. Then, a halide reactant compound is provided to the reaction chamber with a halide reactant pulse 114. Optionally, after the halide reactant pulse, the reaction chamber can be purged 115. The silicon precursor pulse 112, the halide reactant pulse 114, and the optional purges 113, 115 can be repeated 116 any number of times to obtain a surface-modified silicon layer or film having a desired thickness. When a surface-modified silicon layer having a desired thickness has been deposited, the method ends 117. Once the method ends, the substrate can, for example, be subjected to additional processes to form a device structure and / or device.

[0052] Figure 2 An exemplary embodiment of a precursor deposition method in a semiconductor manufacturing process of the present disclosure is described. The method begins 211 after a substrate has been provided to a reaction chamber. The cyclic deposition process includes providing a halide reactant to the reaction chamber with a halide reactant pulse 212. Optionally, after the halide reactant pulse 212, the reaction chamber is purged 213. Then, the silicon precursor is contacted with at least a portion of the substrate with a silicon precursor pulse 214. Optionally, after the silicon precursor pulse, the reaction chamber can be purged 215. The halide reactant pulse 212, the silicon precursor pulse 214 and the optional purges 213, 215 can be repeated 216 any number of times to obtain a surface-modified silicon layer having a desired thickness. When a surface-modified silicon layer having a desired thickness has been deposited, the method ends 217. Once the method ends, the substrate can, for example, be subjected to additional processes to form a device structure and / or device.

[0053] Figure 3 An exemplary embodiment of a precursor deposition method in a semiconductor manufacturing process of the present disclosure is described. The method begins 311 after a substrate has been provided to a reaction chamber. The cyclic deposition process includes contacting a silane precursor with at least a portion of the substrate surface and reacting the deposited silicon layer with a halide reactant with a combined silicon precursor and halide reactant pulse 312. Optionally, after the combined silicon precursor and halide reactant pulse 312, the reaction chamber is purged 313. The combined silicon precursor and halide reactant pulse 312 and the optional purge 313 can be repeated 314 any number of times to obtain a surface-modified silicon layer or film having a desired thickness. When a surface-modified silicon layer having a desired thickness has been deposited, the method ends 315. Once the method ends, the substrate can, for example, be subjected to additional processes to form a device structure and / or device.

[0054] Figure 4A system 400 according to a further exemplary embodiment of the present disclosure is shown. The system 400 can be used to perform the methods described herein and / or form part of the structures or devices described herein.

[0055] In the illustrated example, the system 400 includes one or more reaction chambers 402, a silicon precursor container 404, a halide reactant container 406, a purge gas source 408, an exhaust 410, and a controller 412. The reaction chamber 402 can include any suitable reaction chamber, such as an ALD or CVD reaction chamber. Optionally, the system 400 includes additional reactant containers, such as oxygen reactant and / or nitrogen reactant containers 405.

[0056] Silicon precursor container 404 may include a container and one or more silicon precursors described herein - alone or mixed with one or more carrier gases (e.g., inert gases). Halide reactant container 406 may include a container and a halide reactant described herein - alone or mixed with one or more carrier gases. As described herein, purge gas source 408 may include one or more inert gases, such as N2 or a rare gas. System 400 may include any suitable number of gas sources. Gas sources 404-408 may be coupled to reaction chamber 402 via pipelines 414-418, and pipelines 414-418 may each include a flow controller, a valve, a heater, etc. Exhaust device 410 may include one or more vacuum pumps.

[0057] Controller 412 includes electronic circuits and software to selectively operate valves, manifolds, heaters, pumps and other components included in system 400. Such circuits and components are used to introduce precursors, reactants and purge gases from corresponding sources 404-408. Controller 412 can control the timing of gas pulse sequences, the temperature of substrates and / or reaction chambers, the pressure in the reaction chamber and various other operations to provide the correct operation of system 400. Controller 412 may include control software to control the inflow and outflow of precursors, reactants and purge gases into and out of reaction chamber 402 by electrically or pneumatically controlling valves. Controller 412 may include modules that perform certain tasks, such as software or hardware components, such as FPGA or ASIC. Modules may advantageously be configured to reside on an addressable storage medium of a control system and configured to perform one or more processes. Other configurations of system 400 are possible, including precursor and reactant sources and purge gas sources of different numbers and types. In addition, it should be understood that there are many arrangements of valves, conduits, precursor sources and purge gas sources that can be used to achieve the goal of selectively supplying gas to reaction chamber 402. Additionally, as a schematic representation of the system, many components have been omitted to simplify the illustration, and these components may include, for example, various valves, manifolds, purifiers, heaters, containers, vents, and / or bypasses.

[0058] During operation of reactor system 400, a substrate, such as a semiconductor wafer (not shown), is transferred from, for example, a substrate handling system to reaction chamber 402. Once the substrate is transferred to reaction chamber 402, one or more gases, such as precursors, reactants, carrier gases, and / or purge gases, are introduced into reaction chamber 402 from gas sources 404-408.

[0059] Figure 5 A graphical representation of the layer thickness deviation of a deposited silicon layer without addition of a halide reactant (Comparative Example 1) and with addition of a halide reactant (Example 1) is shown. DETAILED DESCRIPTION

[0060] Although certain embodiments and examples are disclosed below, those skilled in the art will appreciate that the invention extends beyond the specifically disclosed embodiments and / or uses of the invention and obvious modifications and equivalents thereof. Therefore, it is intended that the scope of the disclosed invention should not be limited by the specifically disclosed embodiments described below.

[0061] In the following detailed description, the underlying technology of the present disclosure will be described through different aspects of the present disclosure. It will be readily understood that the various aspects of the present disclosure, as generally described herein and shown in the accompanying drawings, may be arranged, replaced, combined and designed in a variety of different configurations, all of which are expressly intended and form part of the present disclosure. This description is intended to help the reader more easily understand the technical concepts, but is not meant to limit the scope of the present disclosure, which is limited only by the claims.

[0062] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places in this specification do not necessarily all refer to the same embodiment.

[0063] As used herein, the term "includes" and its variations are synonymous with "comprises" and its variations or "contains" and its variations, and are inclusive or open-ended and do not exclude additional, unlisted components, elements, or method steps. The term "includes" and its variations, when referring to the components, elements, or method steps, also include embodiments consisting of the components, elements, or method steps. The singular forms "a", "an", and "the" include singular and plural referents unless the context clearly dictates otherwise.

[0064] The objects described herein as "connected" or "coupled" reflect a functional relationship between the objects being described, that is, the term indicates that the objects being described must be connected in a manner to perform the specified function, which may be direct or indirect connection, in an electrical or non-electrical (i.e., physical) manner, as appropriate to the context in which the term is used.

[0065] As used herein, the term "substantially" refers to the complete or nearly complete extent or degree of an action, characteristic, property, state, structure, item, or result. For example, a "substantially" closed object means that the object is completely closed or nearly completely closed. In some cases, the exact degree of deviation from absolute completeness that is permitted may depend on the circumstances. Generally speaking, however, near completion will have the same overall result as if absolute and complete completion were obtained. When used in a negative sense, the use of "substantially" also applies to referring to the complete or nearly complete absence of an action, characteristic, property, state, structure, item, or result.

[0066] As used herein, the term "about" is used to provide flexibility to a numerical value or a range endpoint, and a given value can be "slightly above" or "slightly below" the value or endpoint, depending on the specific circumstances. Unless otherwise specified, the term "about" used in accordance with a specific numerical value or numerical range should also be understood to support such numerical terms or ranges without the term "about". For example, the expression "about 30" should be interpreted as supporting not only values ​​slightly above and slightly below 30, but also the actual numerical value of 30.

[0067] Numerical ranges listed by endpoints include all integers, and where appropriate, include fractions within the range (e.g., 1 to 5 may include 1, 2, 3, 4 when involving, for example, multiple elements, and may also include 1.5, 2, 2.75, and 3.80 when involving, for example, measured values). The description of endpoints also includes the endpoint values ​​themselves (e.g., 1.0 to 5.0 includes 1.0 and 5.0). Any numerical range listed herein is intended to include all subranges contained therein. In addition, the terms first, second, third, etc. in the specification and claims are used to distinguish similar elements, and are not necessarily used to describe continuous or chronological order, unless otherwise specified. It should be understood that the terms used in this manner are interchangeable where appropriate, and the embodiments of the present disclosure described herein can operate in other sequences different from those described or shown herein.

[0068] In this specification, reference may be made to devices, structures, systems, or methods that provide "improved" performance (e.g., increased or decreased results, as the case may be). It should be understood that, unless otherwise stated, such "improvement" is a measure of the benefit obtained based on a comparison with a device, structure, system, or method in the prior art. In addition, it should be understood that the degree of improved performance may vary between the disclosed embodiments, and equality or consistency in the amount, degree, or implementation of improved performance should not be assumed to be universally applicable.

[0069] In addition, embodiments of the present disclosure may include hardware, software, and electronic components or modules, which, for purposes of discussion, may be illustrated and described as if most of the components were implemented only in hardware. However, those skilled in the art will recognize, based on a reading of this detailed description, that in at least one embodiment, the electronic-based aspects of the present invention may be implemented in software (e.g., instructions stored on a non-transitory computer-readable medium) that may be executed by one or more processing units (e.g., microprocessors and / or application-specific integrated circuits). Therefore, it should be noted that the technology of the present disclosure may be implemented using multiple hardware- and software-based devices and multiple different structural components. For example, the "server" and "computing device" described in the specification may include one or more processing units, one or more computer-readable media modules, one or more input / output interfaces, and various connections of connecting components.

[0070] The term "alkyl" as a group or part of a group refers to a group of formula C n H 2n+1 wherein n is a number greater than or equal to 1. The alkyl group may be straight or branched and may be substituted as indicated herein. Typically, the alkyl groups disclosed herein contain 1 to 8 carbon atoms, preferably 1 to 6 carbon atoms, and more preferably 1 to 4 carbon atoms. When a subscript is used after a carbon atom, the subscript refers to the number of carbon atoms that the named group may contain. For example, the term "C 1-8 "Alkyl" as a group or part of a group refers to a group of the formula -C n H 2n+1 wherein n is a number from 1 to 8. Thus, for example, "C 1-8 "Alkyl" includes all straight or branched chain alkyl groups having between 1 and 8 carbon atoms, thus including methyl, ethyl, n-propyl, isopropyl, butyl and isomers thereof (e.g., n-butyl, isobutyl and tert-butyl); pentyl and isomers thereof, hexyl and isomers thereof, etc. "Substituted alkyl" refers to an alkyl group substituted at any available attachment point with one or more substituents (e.g., 1 to 3 substituents, such as 1, 2 or 3 substituents). The term "halo" or "halogen" as a group or part of a group may be a general term for fluorine (F), chlorine (Cl), bromine (Br), iodine (I).

[0071] In the present disclosure, "gas" may include materials that may be gaseous at normal temperature and pressure (NTP), evaporated solids and / or evaporated liquids, and may be composed of a single gas or a gas mixture depending on the circumstances. Gases other than process gases, i.e., gases that are not introduced through gas distribution components, other gas distribution devices, etc., may be used, for example, to seal reaction spaces, and may include sealing gases, such as rare gases. In some cases, the term "precursor" may refer to a compound that participates in a chemical reaction that produces another compound, particularly a compound that constitutes a membrane matrix or a main skeleton of a membrane; the term "reactant" may be used interchangeably with the term precursor.

[0072] As used herein, the term "substrate" may refer to any one or more underlying materials that may be used to form or on which a device, circuit, or film may be formed. A "substrate" may be continuous or non-continuous; rigid or flexible; solid or porous; and combinations thereof. A substrate may be in any form, such as a powder, a plate, or a workpiece. Plate-like substrates may include wafers of various shapes and sizes. A substrate may include a bulk material, such as silicon (e.g., single crystal silicon), other Group IV materials, such as germanium, or other semiconductor materials, such as Group II-VI or Group III-V semiconductor materials, and may include one or more layers covering or underlying the bulk material. In addition, the substrate may include various features, such as depressions, protrusions, etc., formed in or on at least a portion of a substrate layer. For example, a substrate may include a bulk semiconductor material and an insulating or (high-k) dielectric material layer covering at least a portion of the bulk semiconductor material.

[0073] As used herein, the terms "film" and / or "layer" may refer to any continuous or discontinuous structure and material, such as materials deposited by the methods disclosed herein. For example, the film and / or layer may include a two-dimensional material, a three-dimensional material, nanoparticles, or even a partial or complete molecular layer or a partial or complete atomic layer or atom and / or molecular clusters, or a layer composed of isolated atoms and / or molecules. The film or layer may include a material or layer having pinholes, which may be continuous or discontinuous.

[0074] In general, the technology disclosed herein relates to the field of semiconductor devices, more specifically, to a semiconductor manufacturing system for producing several electronic components such as microprocessors, integrated circuit chips and memory chips. The important step of semiconductor formation mentioned here is the reaction between the deposited silicon compound (e.g., silicon, silicon oxide and / or silicon nitride) and / or any intermediate and the halide reactant (e.g., elemental halogen and / or other halogenating agent, compound or reagent). Advantageously, it has been found that the system disclosed herein allows the epitaxial growth rate (i.e., crystal growth rate) of the silicon monolayer to be controlled to reduce the intra-wafer non-uniformity (WIWNU), thereby producing a uniform layer with controlled thickness and surface roughness. In general, the system disclosed herein includes a reaction chamber, a plurality of containers or gas sources, and a controller for controlling the flow from the plurality of containers or gas sources to the reaction chamber. The controlled co-flow or sequential flow of precursors and reactants from the plurality of containers or gas sources to the reaction chamber of the system disclosed herein allows the precise proportion of each component to be adjusted, even for materials with complex stoichiometry. Furthermore, compared to prior art deposition systems and methods, the present disclosure allows for area-selective deposition without the need for additional etchants or specific capping tools.

[0075] As described in more detail below, various embodiments of the present disclosure are directed to a system comprising:

[0076] - one or more reaction chambers constructed and arranged to hold a substrate;

[0077] - a silicon precursor container constructed and arranged to contain and evaporate a silicon precursor;

[0078] - a halide reactant vessel constructed and arranged to contain and vaporize a halide reactant;

[0079] - Exhaust source; and

[0080] - Controller;

[0081] The controller is configured to control the silicon precursor and the halide reactant to flow into the reaction chamber, thereby forming a surface-modified silicon layer on the substrate.

[0082] In a specific embodiment, the system disclosed herein provides that the system also includes an oxygen reactant container, which is constructed and arranged to contain and evaporate an oxygen reactant; and wherein the controller is configured to control the flow of the oxygen reactant into the reaction chamber to form a surface-modified silicon oxide layer on the substrate.

[0083] In a specific embodiment, the system disclosed herein provides that the system also includes a nitrogen reactant container, which is constructed and arranged to contain and evaporate a nitrogen reactant; and wherein a controller is configured to control the flow of the nitrogen reactant into the reaction chamber to form a surface-modified silicon nitride layer on the substrate.

[0084] Another aspect of the present disclosure relates to a method for precursor deposition in a semiconductor manufacturing process, the method comprising the steps of:

[0085] a) providing a substrate to a reaction chamber;

[0086] b) executing one or more loops, the loops comprising:

[0087] i. contacting the silicon precursor with at least a portion of the substrate by introducing a silicon precursor into the reaction chamber;

[0088] ii. contacting the halide reactant with at least a portion of the substrate by introducing a halide reactant into the reaction chamber,

[0089] Thereby, a surface-modified silicon layer is formed on at least a portion of the substrate.

[0090] Advantageously, the inventors have found that the methods disclosed herein allow for control of the epitaxial growth rate (i.e., crystal growth rate) of a silicon monolayer to reduce within-wafer non-uniformity (WIWNU), thereby producing a uniform layer with controlled thickness and surface roughness. Without wishing to be bound by theory, the inventors have found that during deposition or conversion of a silane precursor to a silicon layer, the observed edge effects are substantially controlled by the formation of polysilicon hydride intermediates. The formation of the unstable polysilicon hydride intermediates may produce differences in silicon growth rates on the substrate surface, resulting in non-uniform monolayers. Compared to the prior art, the present invention allows for control of the silicon growth rate on the substrate surface during material deposition without the need for additional polishing or etching.

[0091] As used herein, the term "semiconductor structure" or "semiconductor device" refers to an electronic component that relies on the electronic properties of semiconductor materials to achieve its function. The electrical conductivity of semiconductors is between that of conductors (e.g., copper) and insulators (e.g., soda-lime-silicon glass). The methods disclosed herein can be used, for example, to form a complementary metal oxide semiconductor (CMOS) device or a portion of such a device. However, unless otherwise specified, the present disclosure is not necessarily limited to these examples.

[0092] Specifically, forming a film (e.g., a surface-modified silicon film) or layer comprising silicon on a substrate as described herein involves a cyclic deposition process, such as an atomic layer deposition process or a cyclic chemical vapor deposition process. In some embodiments, the cyclic deposition process includes one or more cycles. In a specific embodiment, the method disclosed herein includes at least 1 cycle, at least 2 cycles, at least 5 cycles, at least 10 cycles, at least 20 cycles, at least 40 cycles, at least 100 cycles, at least 200 cycles, at least 400 cycles, at least 600 cycles, at least 1000 cycles. In some embodiments, these steps may be repeated from at least 1 cycle to at most 1000 cycles, or from at least 2 cycles to at most 100 cycles, or from at least 5 cycles to at most 50 cycles. It should be understood that different silicon precursors and / or halide reactants can be used during each cycle.

[0093] It should also be understood that other reactants may be introduced during the deposition of the silicon precursor to obtain different silicon-containing layers. In certain embodiments, the methods disclosed herein provide that the cycle of step b) further comprises contacting the oxygen reactant with at least a portion of the substrate by introducing an oxygen reactant into the reaction chamber; thereby forming a surface-modified silicon oxide (SiO2) layer on at least a portion of the substrate. Suitable oxygen reactants include H2O, H2O2, O3, O2, oxygen-containing plasmas, N2O, NO, N2O5, and oxygen radicals.

[0094] In certain embodiments, the methods disclosed herein provide a cycle of step b) further comprising contacting the nitrogen reactant with at least a portion of the substrate by introducing the nitrogen reactant into the reaction chamber; thereby forming a surface-modified silicon nitride (SiN) layer on at least a portion of the substrate. Suitable nitrogen reactants include NH3, diazene (N2H2), hydrazine (N2H4), methylhydrazine (N2MeH3), ethylhydrazine (N2EtH3), propylhydrazine (N2nPrH3), butylhydrazine (N2nBuH3), tert-butylhydrazine (N2tBuH3), 1,1 dimethylhydrazine (N2Me2H2), 1,1-diethylhydrazine (N2Et2H2), 1,1-dipropylhydrazine (N2nPr2H2), 1,1-dibutylhydrazine (N2nBu2H2), trimethylsilylhydrazine (N2[Si(Me)3]H2) and tris(trimethylsilyl)silylhydrazine (N2[Si(Si(Me)3)3]H2). Therefore, the method disclosed herein is not limited to silicon deposition, but can be used to deposit other silicon-containing materials with high area selection accuracy, low surface roughness and a low number of surface defects.

[0095] In certain embodiments, the method disclosed herein provides a cycle including one or more silicon precursor pulses and one or more halide reactant pulses. In some preferred embodiments, each pulse can be followed by a purge of an inert gas selected from at least one of N2 and a rare gas.

[0096] The cycle includes one or more pulses. In some embodiments, at least one pulse involves a self-limiting surface reaction. In some embodiments, all pulses involve a self-limiting surface reaction. In some embodiments, the cycle includes a silicon precursor pulse and a halide reactant pulse. In the silicon precursor pulse, the silicon precursor may be provided to the reaction chamber. With the halide reactant pulse, the halide reactant may be provided to the reaction chamber. In some embodiments, the cycle includes a silicon precursor pulse, an oxygen reactant pulse, and a halide reactant pulse. With the oxygen reactant pulse, the oxygen reactant may be provided to the reaction chamber. In some embodiments, the cycle includes a silicon precursor pulse, a nitrogen reactant pulse, and a halide reactant pulse. With the nitrogen reactant pulse, the nitrogen reactant may be provided to the reaction chamber. It should be understood that the system disclosed herein is configured to control the aforementioned silicon precursor pulse, the halide reactant pulse, and the optional oxygen reactant pulse and / or nitrogen reactant pulse of the method disclosed herein. Therefore, by exposing the substrate surface to different chemicals, reactants, or precursors one at a time, a thin film can be gradually deposited by repeatedly exposing to (non-overlapping) pulses.

[0097] As used herein, the term "silicon layer" may be used to refer to such a thin film when a silicon precursor is deposited on at least a portion of a substrate. Subsequently, when the silicon layer is reacted with a halide reactant, the thin film may be referred to as a "surface-modified silicon layer". It should be understood that the surface-modified silicon layer disclosed herein may include silicon (Si) and / or silicon oxide (SiO2), depending on the silicon precursor and possible contaminants of the substrate and / or reaction chamber. Preferably, the surface-modified silicon layer may be deposited by uniform epitaxial growth, thereby producing a single-crystalline silicon layer with a controlled thickness.

[0098] As used herein, the term "silicon oxide layer" may be used to refer to a thin film when a silicon precursor is deposited on at least a portion of a substrate and the deposited silicon is reacted with an oxygen reactant. Subsequently, when the silicon layer is reacted with a halide reactant, the thin film may be referred to as a "surface-modified silicon oxide layer". It should be understood that the surface-modified silicon oxide layer disclosed herein comprises silicon oxide (SiO2) and optionally silicon (Si). The ratio of silicon oxide to silicon in the surface-modified silicon oxide layer depends on the nature and amount of the silicon precursor, the oxygen reactant, and the halide reactant.

[0099] As used herein, the term "silicon nitride layer" may be used to refer to a thin film when a silicon precursor is deposited on at least a portion of a substrate and the deposited silicon is reacted with a nitrogen reactant. Subsequently, when the silicon layer is reacted with a halide reactant, the thin film may be referred to as a "surface-modified silicon nitride layer". It should be understood that the surface-modified silicon nitride layer disclosed herein includes silicon nitride (SiN) and optionally silicon (Si). The ratio of silicon nitride to silicon in the surface-modified silicon nitride layer depends on the nature and amount of the silicon precursor, the nitrogen reactant, and the halide reactant.

[0100] As used herein, the term "epitaxial growth" refers to a crystal growth or material deposition, wherein a new layer is formed with respect to a substrate in one or more well-defined orientations. The deposited crystalline thin film may also be referred to as an "epitaxial film" or "epitaxial layer". For example, an "epitaxial wafer" or "epi wafer" may be a semiconductor structure made by epitaxial growth, wherein the growth layer may be the same material as the substrate (e.g., single crystal silicon) or a different material. Typically, the precursor deposition in the semiconductor manufacturing process involves a reversible reaction under chemical equilibrium, wherein the growth rate depends on the ratio of each precursor source and / or reactant source, typically expressed as a volume flow rate. In gas phase reactions, such as chemical or physical vapor deposition, different side reactions may compete with the silicon deposition reaction, resulting in surface defects and uneven deposition (e.g., edge effects). Typically, in order to eliminate edge effects, additional steps such as etching or polishing and / or equipment such as a retainer boat or a ring boat are required to control excess deposition. However, the additional steps and / or equipment bring several disadvantages to semiconductor manufacturing. For example, uneven etching may adversely affect the (electro)chemical stability of the formed semiconductor. Additionally, non-selective etching or masking may result in variations in material properties, feature depths, and impurities.

[0101] Advantageously, the inventors have found that the combination of silicon precursors and halide reactants in the same and / or different pulses or depositions results in balanced epitaxial growth and improved film formation. In addition, compared to prior art methods for eliminating edge effects in semiconductor manufacturing, the methods disclosed herein significantly reduce the number of reagents or precursors and purification steps required to form a silicon layer with high uniformity. As used herein, the term "surface-modified silicon layer" may be used to refer to such an improved silicon film having a uniform thickness and a smooth surface (i.e., low surface roughness) without the need for additional etching or polishing.

[0102] In some specific embodiments, the methods disclosed herein provide for the simultaneous introduction of a silicon precursor and a halide reactant into a reaction chamber. Thus, a pulse of a silicon precursor and a pulse of a halide reactant can be combined to co-flow or simultaneously introduce a silicon precursor (gas) and a halide reactant (gas) into a reaction chamber. Without wishing to be bound by theory, it has been found that the difference in the reactivity of the silicon precursor and the halide reactant relative to the substrate surface can allow for selective epitaxial growth and controlled material deposition.

[0103] In some specific embodiments, the methods disclosed herein provide that the silicon precursor may be introduced into the reaction chamber prior to the halide reactant. However, in other embodiments, the pulse of the halide reactant compound may precede the pulse of the silicon precursor.

[0104] It should be understood that any two steps and / or pulses can be separated by a purge. Thus, in some embodiments, the step of contacting the silicon precursor and the step of reacting the halide reactant are separated by a purge. In some embodiments, subsequent cycles are separated by a purge.

[0105] In some embodiments, the substrate can be made of semiconductor materials, including, for example, silicon, silicon germanium, silicon oxide, gallium arsenide, gallium nitride, and silicon carbide. In some preferred embodiments, the substrate can be made of silicon oxide, silicon germanium, gallium arsenide, indium gallium arsenide, gallium nitride, and / or silicon nitride.

[0106] The continuous substrate may extend beyond the boundaries of the processing / reaction chamber where the deposition process occurs. In some processes, the continuous substrate may be moved through the processing chamber so that the process continues until the end of the substrate is reached. The continuous substrate may be provided from a continuous substrate feed system to allow the continuous substrate to be manufactured and output in any suitable form. Non-limiting examples of continuous substrates may include thin sheets or flexible materials. The continuous substrate may also include a carrier or sheet on which a non-continuous substrate is mounted.

[0107] It has been found that the ratio of silicon precursor and halide reactant can be varied to accelerate or decelerate epitaxial growth on the substrate surface, more specifically, at the edge of the substrate surface, to produce a surface modified silicon layer with improved thickness uniformity and a smooth surface. In a specific embodiment, the method disclosed herein provides for introducing the silicon precursor and the halide reactant into the reaction chamber at the following volume flow ratio of silicon precursor / halide reactant: at least 1.1 and at most 1000.0, or at least 1.1 and at most 900.0, or at least 1.1 and at most 800.0, or at least 1.1 and at most 700.0, or at least 1.1 and at most 600.0, or at least 1.1 and at most 500.0, or at least 1.1 and at most 400.0, or at least 1.1 and at most 300.0, or at least 1.1 and at most 200.0, or at least 1.1 and at most 100.0, or at least 1.5 and at most 100. 0, or at least 2 and at most 100.0, or at least 2.5 and at most 100.0, or at least 3.0 and at most 100.0, or at least 3.5 and at least 100.0, or at least 4.0 and at most 100.0, or at least 4.5 and at most 100.0, or at least 5.0 and at most 100.0, or at least 5.0 and at most 90.0, or at least 5.0 and at most 80.0, or at least 5.0 and at most 70.0, or at least 5.0 and at most 60.0, or at least 5.0 and at most 50.0, or at least 5.0 and at most 40.0, or at least 5.0 and at most 30.0, or at least 5.0 and at most 20.0. An advantage of the silicon precursor / halide reactant volume flow ratios disclosed herein is the flexibility to adjust the volume flow ratio of the halide reactant to the volume ratio of the silane precursor based on the intrinsic reactivity to the substrate surface and / or the formation of polysilicon hydride intermediates.

[0108] In certain embodiments, the methods disclosed herein provide that the silicon precursor may be selected from the group consisting of Si n H 2n+2 、Si n H 2n and Si(OR 1 )4; wherein n is an integer from 1 to 20, m is an integer from 3 to 20; and wherein each R 1 Independently selected from C 1-8 In the present disclosure, n is an integer from 1 to 20, or from 1 to 15, preferably from 1 to 10, or from 1 to 8, more preferably from 1 to 6, and most preferably from 1 to 4. In the present disclosure, m is an integer from 3 to 20, or from 3 to 12, preferably from 3 to 10, or from 3 to 8, more preferably from 3 to 6, and most preferably from 3 to 5. In a specific embodiment, the method disclosed herein provides that the silicon precursor can be selected from silane (SiH4), disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H 10 ), isotetrasilane, pentasilane (Si5H 12), isopentasilane, neopentasilane, hexasilane (Si6H 14 ), cyclotrisilane (Si3H6), cyclotetrasilane (Si4H8), cyclopentasilane (Si5H 10 ), cyclohexasilane (Si6H 12 ), tetramethyl orthosilicate (Si(OCH3)4) and tetraethyl orthosilicate (Si(OC2H5)4). It will be appreciated that in principle any silicon compound consisting of one or more Si-H bonds may be included in the silicon precursor. Higher order silanes, such as trisilane, are generally more thermally unstable and may increase the growth rate of the silicon layer.

[0109] Generally, the halide reactants disclosed herein can be considered to consist of at least one halogen functional group (-X, where X = F, Cl, Br or I). In certain embodiments, the halide reactant can be selected from elemental halogens and halogen compounds; and wherein the halogen compound comprises an element selected from H, B, Al, Si, P, O, N and S and one or more halogens.

[0110] In certain embodiments, the methods disclosed herein provide that the halide reactant can be selected from fluorine (F2), chlorine (Cl2), bromine (Br2), iodine (I2), hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), hydrogen iodide (HI), phosphorus trifluoride (PF3), phosphorus pentafluoride (PF5), phosphorus trichloride (PCl3), phosphorus pentachloride (PCl5), thionyl chloride (SOCl2), phosphorus tribromide (PBr3), phosphorus pentabromide (PBr5), sulfur bromide (SOBr2), tetrafluorosilane (SiF4), tetrachlorosilane (SiCl4), tetrabromosilane (SiBr 4), trifluorosilane (SiHF3), trichlorosilane (SiHCl3), tribromosilane (SiHBr3), difluorosilane (SiH2F2), dichlorosilane (SiH2Cl2), dibromosilane (SiH2Br2), fluorosilane (SiH3F), chlorosilane (SiH3Cl), bromosilane (SiH3Br), hexafluorodisilane (Si2F6), hexachlorodisilane (Si2Cl6), hexabromodisilane (Si2Br6), octafluorotrisilane (Si3F8), octachlorotrisilane (Si3Cl8), octabromotrisilane (Si3Br8), boron trifluoride (BF3), boron trichloride (BCl3), boron tribromide (BBr3), boron triiodide (BI3), aluminum trifluoride (AlF3), aluminum trichloride (AlCl3), aluminum tribromide (AlBr3) and aluminum triiodide (AlI3). Advantageously, reacting the halide reactant with the deposited silicon material allows obtaining a surface modified silicon layer having a uniform layer thickness and surface roughness by controlling the silicon growth rate. In some embodiments, the methods disclosed herein provide a surface modified silicon layer having an average surface roughness deviation of less than 10.0%, or less than 9.0%, or less than 8.0%, or less than 7.0%, or less than 6.0%, or less than 5.0%, preferably less than 3.0%.

[0111] In other embodiments, the methods disclosed herein provide a surface-modified silicon layer having an average surface roughness deviation of less than 2.0%, or less than 1.0%, or less than 0.5%. Technicians know how to measure the surface roughness deviation of a deposited surface-modified silicon layer. For example, an atomic force microscope operated in tapping mode is a common analytical tool for determining the average surface roughness deviation. In some embodiments, the methods disclosed herein provide a surface-modified silicon layer having an average thickness of 3nm or less, or 2.5nm or less, or 2nm or less, or 1.5nm or less, or 1nm or less, or 0.5nm or less, or 0.25nm or less, or 0.10nm or less.

[0112] In some embodiments, the methods disclosed herein provide a surface-modified silicon layer formed having an average growth rate of at least 0.05 nm / min, preferably at least 0.10 nm / min, or at least 0.15 nm / min, or at least 0.20 nm / min, or at least 0.25 nm / min, or at least 0.30 nm / min, or at least 0.35 nm / min, or at least 0.40 nm / min, or at least 0.50 nm / min. The average growth rate values ​​listed (each alternating pulse of precursor / reactant gas and purge gas (e.g., inert carrier gas)) are advantageous for semiconductor manufacturing. In particular, the methods disclosed herein provide a controlled growth rate, which may be desired to avoid side reactions and / or morphological changes in the deposited silicon-containing film.

[0113] As used herein, the term "deposition" or "cyclic deposition" or "cyclic deposition process" or "cyclic deposition process" refers to the sequential introduction of silane precursors (and / or reactants) into a reaction chamber to deposit a layer or film on a substrate, and includes processing techniques such as atomic layer deposition (ALD), cyclic chemical vapor deposition (cyclic CVD), and mixed cyclic deposition processes including an ALD component and a cyclic CVD component. In a preferred embodiment, the deposition process disclosed herein refers to an atomic layer deposition process. Typically, one deposition cycle can form a film or layer of about 0.10 nm. However, the experimental thickness can vary depending on the amount and type of cycles and the available reaction sites on the substrate. In some preferred embodiments, the methods disclosed herein provide a surface-modified silicon layer having an average thickness of 3 nm or less, or 2.5 nm or less, or 2 nm or less, or 1.5 nm or less, or 1 nm or less, or 0.5 nm or less, or 0.25 nm or less, or 0.10 nm or less. For many electronic applications, including work function and / or threshold voltage adjustment in transistors, a lower thickness layer may be ideal.

[0114] The term "atomic layer deposition" (ALD) refers to a vapor deposition process in which a deposition cycle (typically a plurality of consecutive deposition cycles) is performed in a processing chamber. The term atomic layer deposition as used herein is also meant to include processes designated by related terms, such as chemical vapor atomic layer deposition, atomic layer epitaxy (ALE), molecular beam epitaxy (MBE), gas source MBE, organometallic MBE, and chemical beam epitaxy when performed with alternating pulses of precursor / reactive gas and purge gas (e.g., inert carrier gas). Typically, for an ALD process, during each cycle, a (silicon) precursor may be introduced into a reaction chamber and may be chemically adsorbed to a deposition surface (e.g., a substrate surface that may include previously deposited material or other material from a previous ALD cycle) and form a material, such as approximately a monolayer or sub-monolayer of material, or several monolayers of material, or multiple monolayers of material, which is not susceptible to reaction with additional precursors (i.e., a self-limiting reaction). Thereafter, in some cases, a (halide, oxygen, and / or nitrogen) reactant (e.g., another precursor or reactive gas) may be subsequently introduced into the processing chamber for converting the chemically adsorbed precursor to the desired material on the deposition surface. The reactants are able to further react with the precursors. During one or more repetitions, for example during each deposition step, a purge step may be utilized to remove any excess precursor from the process chamber and / or to remove any excess reactants and / or reaction byproducts from the reaction chamber. Note that, as used herein, an ALD process does not necessarily include a series of self-limiting surface reactions. Advantageously, the methods of the present disclosure allow for the deposition of a uniform surface-modified silicon layer with few or no surface defects.

[0115] As used herein, the term "deposition" refers to the sequential introduction of precursors (and / or reactants) into a reaction chamber to deposit a layer or film on a substrate, and includes processing techniques such as atomic layer deposition (ALD), cyclic chemical vapor deposition (cyclic CVD), and hybrid cyclic deposition processes including an ALD component and a cyclic CVD component. In a preferred embodiment, the deposition process disclosed herein refers to an atomic layer deposition process. Examples of reaction chambers or process chambers include a cross-flow reactor, a showerhead reactor, or a hot wall reactor.

[0116] The term "atomic layer deposition" (ALD) refers to a vapor deposition process in which material deposition (usually multiple continuous material depositions) is performed in a processing chamber. The term atomic layer deposition as used herein is also meant to include processes designated by related terms, such as chemical vapor atomic layer deposition, atomic layer epitaxy (ALE), molecular beam epitaxy (MBE), gas source MBE, organometallic MBE, and chemical beam epitaxy when performed with alternating pulses of precursor / reactive gas and purge gas (e.g., inert carrier gas). Typically, for an ALD process, during each continuous deposition, a (metal) precursor may be introduced into a reaction chamber and may be chemically adsorbed onto a deposition surface (e.g., a substrate surface that may include previously deposited material or other material from a previous ALD cycle) and form a material, such as approximately a monolayer or sub-monolayer of material, or several monolayers of material, or multiple monolayers of material, which is not easily reactive with additional precursors (i.e., a self-limiting reaction). Thereafter, in some cases, a reactant (e.g., another precursor or reactive gas) may be subsequently introduced into the processing chamber for converting the chemically adsorbed precursor into the desired material on the deposition surface. The reactant is capable of further reacting with the precursor. During one or more repetitions, for example during each deposition step, a purge step may be utilized to remove any excess precursor from the process chamber and / or to remove any excess reactant and / or reaction byproducts from the reaction chamber. Note that, as used herein, an ALD process does not necessarily include a series of self-limiting surface reactions. Advantageously, the method of the present invention allows for the formation of a surface-modified silicon layer in a single ALD process. Thus, faster deposition is allowed with greater error tolerance than disclosed in the prior art.

[0117] In some embodiments, the plurality of deposition cycles may include a plurality of main cycles. The main cycle may include a halide reactant pulse and one or more sub-cycles. The sub-cycle may include a silicon precursor pulse. The sub-cycle may include a silicon precursor pulse followed by an oxygen reactant pulse. The sub-cycle may include a silicon precursor pulse followed by a nitrogen reactant pulse. Thus, in some embodiments, the plurality of deposition cycles may be represented by formula i):

[0118] [(silicon precursor) x sub-cycle + halide reactant] x main cycle i)

[0119] Additionally or alternatively, in some embodiments, the plurality of deposition cycles may be represented by equation ii:

[0120] [(silicon precursor + oxygen reactant) x sub-cycle + halide reactant] x main cycle ii)

[0121] Additionally or alternatively, in some embodiments, the plurality of deposition cycles may be represented by equation iii:

[0122] [(silicon precursor + nitrogen reactant) x sub-cycle + halide reactant] x main cycle iii)

[0123] Wherein, "Silicon Precursor" represents a silicon precursor pulse, "Oxygen Reactant" represents an oxygen reactant pulse, "Nitrogen Reactant" represents a nitrogen reactant pulse, "x Sub-Cycles" represents the number of sub-cycles per main cycle, "Halide Reactant" represents a halide reactant pulse, "x Main Cycles" represents the number of main cycles, and "+" represents one pulse after another. In such an embodiment, the halide reactant is introduced only during the halide reactant pulse, so that edge defects are minimized.

[0124] In some embodiments, the method comprises from at least 2 sub-cycles to at most 5 sub-cycles, or from at least 5 sub-cycles to at most 10 sub-cycles, or from at least 10 sub-cycles to at most 20 sub-cycles, or from at least 20 sub-cycles to at most 50 sub-cycles, or from at least 50 sub-cycles to at most 100 sub-cycles, or from at least 100 sub-cycles to at most 200 sub-cycles, or from at least 200 sub-cycles to at most 500 sub-cycles, or from at least 500 sub-cycles to at most 1000 sub-cycles, or from at least 1000 sub-cycles to at most 2000 sub-cycles.

[0125] In some embodiments, the silicon precursor pulse lasts at least 0.01 second to at most 120 seconds, or at least 0.01 second to at most 0.1 second, or at least 0.01 second to at most 0.02 seconds, or at least 0.02 seconds to at most 0.05 seconds, or at least 0.05 seconds to at most 0.1 second, or at least 0.1 second to at most 20 seconds, or at least 0.1 second to at most 0.2 seconds, or at least 0.2 seconds to at most 0.5 seconds, or at least 0.5 seconds to at most 1.0 second, or at least 1.0 second to at most 2.0 seconds, or at least 2.0 seconds to at most 5.0 seconds, or at least 5.0 seconds to at most 10.0 seconds, or at least 10.0 seconds to at most 20.0 seconds. In some embodiments, the halide reactant pulse and / or the oxygen reactant pulse and / or the nitrogen reactant pulse lasts at least 0.1 second to at most 20 seconds, or at least 0.1 second to at most 0.2 seconds, or at least 0.2 seconds to at most 0.5 seconds, or at least 0.5 seconds to at most 1.0 seconds, or at least 1.0 seconds to at most 2.0 seconds, or at least 2.0 seconds to at most 5.0 seconds, or at least 5.0 seconds to at most 10.0 seconds, or at least 10.0 seconds to at most 20.0 seconds, or at least 20.0 seconds to at most 120.0 seconds, or at least 20.0 seconds to at most 50.0 seconds, or at least 50.0 seconds to at most 80.0 seconds, or at least 80.0 seconds to at most 120.0 seconds.

[0126] The methods disclosed herein can be performed at different temperatures and / or pressures. In some embodiments, the substrate may be heated to a temperature of at least 200°C and at most 1000°C, or at least 200°C and at most 800°C, or at least 200°C and at most 750°C, or at least 200°C and at most 700°C, or at least 300°C and at most 750°C, or at least 300°C and at most 700°C, or at least 300°C and at most 650°C, preferably at least 350°C and at most 650°C. The listed temperatures can reduce the time required for material deposition, although lower or higher temperatures are also contemplated. In some embodiments, the pressure of the reaction chamber is at least 0.1 Torr and at most 50.0 Torr, or at least 0.1 Torr and at most 40.0 Torr, or at least 0.1 Torr and at most 30.0 Torr, or at least 0.1 Torr and at most 20.0 Torr, or at least 0.5 Torr and at most 20.0 Torr, preferably at least 0.5 Torr and at most 10 Torr. The pressures listed may reduce the time required for material deposition, although lower or higher pressures are contemplated.

[0127] The surface modified silicon layer can be deposited in any suitable reactor. Thus, in some embodiments, the surface modified silicon layer can be deposited in a cross-flow reactor. In some embodiments, the surface modified silicon layer can be deposited in a showerhead reactor. In some embodiments, the surface modified silicon layer can be deposited in a hot wall reactor. Doing so can advantageously improve the uniformity and / or repeatability of the surface modified silicon layer deposition process.

[0128] In some embodiments, after the cyclic deposition process, the substrate may be subjected to an annealing step in an environment containing hydrogen and nitrogen. Suitably, the annealing step may be performed at a temperature of at least 300° C. to at most 600° C. Alternatively, the annealing step may be performed at a temperature of at least 300° C. to at most 1000° C.

[0129] In some embodiments, the silicon precursor can be provided to the reaction chamber from a temperature controlled precursor container. In some embodiments, the temperature controlled precursor container can be configured to cool the precursor. In some embodiments, the temperature controlled precursor container can be configured to heat the precursor. In some embodiments, the temperature controlled precursor container can be maintained at a temperature of at least -50°C to at most 20°C, or at a temperature of at least 20°C to at most 250°C, or at least 100°C to at most 200°C.

[0130] In some embodiments, the silicon precursor can be provided to the reaction chamber by a carrier gas. Exemplary carrier gases include nitrogen (N2) and noble gases such as He, Ne, Ar, Xe or Kr.

[0131] Suitable surface-modified silicon layers disclosed herein may include doped or undoped silicon. Undoped silicon may be referred to as intrinsic silicon. Doped silicon may include n-type dopants, which include pentavalent elements phosphorus (P), arsenic (As) and / or antimony (Sb). Additionally or alternatively, doped silicon may include p-type dopants, which include trivalent elements boron (B), aluminum (Al) or indium (In). The term "dopant" used herein refers to a compound, chemical reagent or impurity added to a semiconductor to increase conductivity. As disclosed herein, in order to introduce dopants into a surface-modified silicon layer, a variety of vapor deposition techniques may be used, which typically include at least two steps. First, the dopant may be deposited on the surface of a uniform silicon film, and then the deposited dopant layer may be incorporated or driven into the body of the surface-modified silicon layer.

[0132] In a specific embodiment, the method disclosed herein further comprises a step c) of doping the formed surface-modified silicon layer with a dopant, wherein the dopant comprises an element from the group comprising at least one of P, As, Sb, B, Al and In. In some preferred embodiments, the dopant may be selected from PH3, PF5, PCl5, PBr5, AsF5, AsCl5, AsBr5, AsH3, SbF3, SbCl3, SbBr3, BF3, BCl3, BBr3, B2H6, AlF3, AlCl3, AlBr3, InF3, InCl3 and InBr3. The listed dopants facilitate the deposition of precursors in semiconductor manufacturing processes with improved surface properties and fewer defects (e.g., edge effects).

[0133] In another aspect of the present invention, the present disclosure relates to a layered structure comprising:

[0134] substrate, and

[0135] one or more surface-modified silicon layers deposited on at least a portion of the substrate;

[0136] Characterized in that one or more surface modified silicon layers have an average surface roughness deviation of less than 10.0%, or less than 9.0%, or less than 8.0%, or less than 7.0%, or less than 6.0%, or less than 5.0%, preferably less than 3.0%. In some embodiments, the semiconductor comprises a layered structure disclosed herein. In a specific embodiment, the layered structure disclosed herein provides that one or more surface modified silicon layers have an average thickness of 3nm or less, or 2nm or less, or 1nm or less, or 0.5nm or less.

[0137] In certain embodiments, the layered structures disclosed herein provide one or more surface-modified silicon layers obtained according to the methods disclosed herein. Advantageously, when compared to silicon layers reported in the prior art, the one or more surface-modified silicon layers disclosed herein are characterized by a lower number of deposition defects, a controlled layer thickness, and a smooth surface, thereby resulting in improved electrical properties of the resulting semiconductor.

[0138] In some embodiments, the layered structure further comprises a dopant, and wherein the dopant comprises an element from the group comprising at least one of P, As, Sb, B, Al, and In. In particular, the dopant may be contained in at least one of the one or more surface-modified silicon layers, resulting in a layered structure having improved conductive properties.

[0139] In another aspect of the invention, the present disclosure relates to the use of halide reactants for reducing the wafer-wide non-uniformity (WIWNU) of a surface-modified silicon layer. As disclosed herein, when silicon is deposited on the surface, the halide reactant can accelerate and / or decelerate the growth rate of the silicon layer at the edge of the surface. In addition, the silicon growth rate can be independently adjusted by controlling the silicon precursor pulse (growth pulse) and the halide reactant pulse (etching pulse). In specific embodiments, the use of the halide reactants disclosed herein provides a surface-modified silicon layer with an average surface roughness deviation of less than 10.0%, or less than 9.0%, or less than 8.0%, or less than 7.0%, or less than 6.0%, or less than 5.0%, preferably less than 3.0%. In certain embodiments, the halide reactant can be selected from fluorine (F2), chlorine (Cl2), bromine (Br2), iodine (I2), hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), hydrogen iodide (HI), phosphorus trifluoride (PF3), phosphorus pentafluoride (PF5), phosphorus trichloride (PCl3), phosphorus pentachloride (PCl5), thionyl chloride (SOCl2), phosphorus tribromide (PBr3), phosphorus pentabromide (PBr5), sulfur bromide (SOBr2), tetrafluorosilane (SiF4), tetrachlorosilane (SiCl4), tetrabromosilane (SiBr 4 ), trifluorosilane (SiHF3), trichlorosilane (SiHCl3), tribromosilane (SiHBr3), difluorosilane (SiH2F2), dichlorosilane (SiH2Cl2), dibromosilane (SiH2Br2), fluorosilane (SiH3F), chlorosilane (SiH3Cl), bromosilane (SiH3Br), hexafluorodisilane (Si2F6), hexachlorodisilane (Si2Cl6), hexabromodisilane (Si2Br6), octafluorotrisilane (Si3F8), octachlorotrisilane (Si3Cl8), octabromotrisilane (Si3Br8), boron trifluoride (BF3), boron trichloride (BCl3), boron tribromide (BBr3), boron triiodide (BI3), aluminum trifluoride (AlF3), aluminum trichloride (AlCl3), aluminum tribromide (AlBr3) and aluminum triiodide (AlI3).

[0140] The illustrations presented herein are not meant to be actual views of any particular material, structure, or device but are merely idealized representations used to describe embodiments of the present disclosure.

[0141] The specific embodiments shown and described are illustrative of the present invention and its best mode and are not intended to limit the scope of these aspects and embodiments in any way. In fact, for the sake of brevity, the traditional manufacturing, connection, preparation and other functional aspects of the system may not be described in detail. In addition, the connecting lines shown in the various figures are intended to represent exemplary functional relationships and / or physical connections between various elements. In actual systems, there may be many alternative or additional functional relationships or physical connections, and / or may not exist in some embodiments.

[0142] It should be understood that the configuration and / or method described herein are exemplary in nature, and these specific embodiments or examples should not be considered restrictive, because many variations are possible. The specific routine or method described herein can represent one or more of any number of processing strategies. Therefore, the various actions shown can be performed in the order shown, in other orders, or omitted in some cases.

[0143] The subject matter of the present disclosure includes all novel and nonobvious combinations and subcombinations of the various processes, systems and configurations, and other features, functions, acts and / or properties disclosed herein, and any and all equivalents thereof.

[0144] Example

[0145] The following is an example of a technology according to the present disclosure. The examples are provided to help readers understand the technical concept more easily, but are not intended to identify the most important or essential features, nor to limit the scope of the present disclosure.

[0146] Example 1 - Uniform surface modified silicon layer

[0147] To demonstrate the improved reduction in within-wafer non-uniformity (WIWNU) of the surface modified silicon layer obtained by the methods disclosed herein, a layered structure was formed by exposing a silicon substrate to:

[0148] - Silicon precursor pulse (Si3H8) to obtain Comparative Example 1;

[0149] - Co-flow of silicon precursor pulse (Si3H8) and halide reactant pulse (BCl3) to obtain Example 1;

[0150] A chemical vapor deposition (CVD) process is used.

[0151] The following parameters were used for the CVD process of Comparative Example 1:

[0152] -Substrate temperature: 400℃

[0153] -Pressure in reaction chamber: 0.2 Torr

[0154] -Trisilane (Si3H8) exposure: 3000 seconds

[0155] The following parameters were used for the CVD process of Example 1:

[0156] -Substrate temperature: 400℃

[0157] -Pressure in reaction chamber: 0.2 Torr

[0158] -Trisilane (Si3H8) and boron trichloride (BCl3) exposure: 3000 seconds

[0159] As in Example 1 Figure 5 As shown, the addition of the halide reactant reduces the WIWNU by a factor of about 23. In particular, at the edge of the silicon wafer, an increase in silicon deposition can be seen for Comparative Example 1.

[0160] Example 2

[0161] The following parameters were used for the CVD process of Comparative Example 2:

[0162] -Substrate temperature: 400℃

[0163] -Pressure in reaction chamber: 0.2 Torr

[0164] -Trisilane (Si3H8) pulse: 300 seconds

[0165] - Purge time after trisilane (Si3H8) pulse: 5 seconds

[0166] - Number of pulse sequence repetitions: 10

[0167] The following parameters were used for the CVD process of Example 2:

[0168] -Substrate temperature: 400℃

[0169] -Pressure in reaction chamber: 0.2 Torr

[0170] -Trisilane (Si3H8) pulse: 300 seconds

[0171] - Purge time after trisilane (Si3H8) pulse: 5 seconds

[0172] - Boron trichloride (BCl3) pulse: 5 seconds

[0173] - Purge time after BCl3 pulse: 5 seconds

[0174] - Number of pulse sequence repetitions: 10

Claims

1. A method for depositing a precursor in a semiconductor manufacturing process, the method comprising the following steps: a) providing a substrate to a reaction chamber; b) executing one or more loops, the loops comprising: i. contacting the silicon precursor with at least a portion of the substrate by introducing a silicon precursor into the reaction chamber; ii. contacting the halide reactant with at least a portion of the substrate by introducing a halide reactant into the reaction chamber, Thereby, a surface-modified silicon layer is formed on at least a portion of the substrate.

2. The method according to claim 1, wherein: The cycle of step b) further comprises contacting the oxygen reactant with at least a portion of the substrate by introducing the oxygen reactant into the reaction chamber; thereby forming a surface-modified silicon oxide layer on at least a portion of the substrate.

3. The method according to claim 1, wherein: The cycle of step b) further comprises contacting the nitrogen reactant with at least a portion of the substrate by introducing the nitrogen reactant into the reaction chamber; thereby forming a surface-modified silicon nitride layer on at least a portion of the substrate.

4. The method according to claim 1, wherein: The silicon precursor and the halide reactant are introduced into the reaction chamber at a volume flow ratio of silicon precursor / halide reactant of at least 1.1 to at most 100.

0.

5. The method according to claim 1, wherein: The silicon precursor is selected from the group consisting of Si n H 2n+2 、Si n H 2n and Si(OR 1 )4; wherein n is an integer from 1 to 20, m is an integer from 3 to 20; and wherein each R 1 Independently selected from C 1-8 alkyl.

6. The method according to claim 1, wherein: The silicon precursor is selected from silane (SiH4), disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H 10 ), isotetrasilane, pentasilane (Si5H 12 ), isopentasilane, neopentasilane, hexasilane (Si6H 14 ), cyclotrisilane (Si3H6), cyclotetrasilane (Si4H8), cyclopentasilane (Si5H 10 ), cyclohexasilane (Si6H 12 ), tetramethyl orthosilicate (Si(OCH3)4) and tetraethyl orthosilicate (Si(OC2H5)4).

7. The method according to claim 1, wherein: The halide reactant is selected from elemental halogens and halogen compounds; and wherein the halogen compound comprises an element selected from H, B, Al, Si, P, O, N and S and one or more halogens.

8. The method according to claim 1, wherein: The halide reactant is selected from fluorine (F2), chlorine (Cl2), bromine (Br2), iodine (I2), hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), hydrogen iodide (HI), phosphorus trifluoride (PF3), phosphorus pentafluoride (PF5), phosphorus trichloride (PCl3), phosphorus pentachloride (PCl5), thionyl chloride (SOCl2), phosphorus tribromide (PBr3), phosphorus pentabromide (PBr5), sulfur bromide (SOBr2), tetrafluorosilane (SiF4), tetrachlorosilane (SiCl4), tetrabromosilane (SiBr4), trifluorosilane (SiHF3), trichlorosilane (SiHCl3), tribromosilane (SiHBr3), difluorosilane (SiH 2F2), dichlorosilane (SiH2Cl2), dibromosilane (SiH2Br2), fluorosilane (SiH3F), chlorosilane (SiH3Cl), bromosilane (SiH3Br), hexafluorodisilane (Si2F6), hexachlorodisilane (Si2Cl6), hexabromodisilane (Si2Br6), octafluorotrisilane (Si3F8), octachlorotrisilane (Si3Cl8), octabromotrisilane (Si3Br8), boron trifluoride (BF3), boron trichloride (BCl3), boron tribromide (BBr3), boron triiodide (BI3), aluminum trifluoride (AlF3), aluminum trichloride (AlCl3), aluminum tribromide (AlBr3) and aluminum triiodide (AlI3).

9. The method according to claim 1, wherein: The formed surface modified silicon layer has an average growth rate of at least 0.10 nm / min.

10. The method according to claim 1, wherein: The substrate is heated to a temperature of at least 200°C and at most 1000°C.

11. The method according to claim 1, wherein: The reaction chamber has a pressure of at least 0.1 Torr and at most 50.0 Torr.

12. The method according to claim 1, wherein: The surface modified silicon layer has an average surface roughness deviation of less than 3.0%.

13. The method according to claim 1, wherein: The surface-modified silicon layer has an average thickness of 1 nm or less.

14. The method according to claim 1, further comprising the step c) of doping the formed surface-modified silicon layer with a dopant, wherein the dopant comprises an element from the group consisting of at least one of P, As, Sb, B, Al, and In.

15. A system comprising: - one or more reaction chambers constructed and arranged to hold a substrate; - a silicon precursor container constructed and arranged to contain and evaporate a silicon precursor; - a halide reactant vessel constructed and arranged to contain and vaporize a halide reactant; - Exhaust source; as well as - Controller; The controller is configured to control the silicon precursor and the halide reactant to flow into the reaction chamber, thereby forming a surface-modified silicon layer on the substrate.

16. A layered structure comprising: substrate, and one or more surface modified silicon layers deposited on at least a portion of the substrate; Characterized in that the surface-modified silicon layer or layers has an average surface roughness deviation of less than 10.0%.

17. The layered structure according to claim 16, wherein The one or more surface modified silicon layers have an average surface roughness deviation of less than 3.0%.

18. The layered structure according to claim 16, wherein Each of the one or more surface-modified silicon layers has an average thickness of 1 nm or less.

19. The layered structure according to claim 16, wherein: The layered structure further includes a dopant, and wherein the dopant includes an element from the group consisting of at least one of P, As, Sb, B, Al, and In.

20. Use of a halide reactant for reducing the wafer within wafer non-uniformity (WIWNU) of a surface modified silicon-containing layer.

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