Active absorption circuit

Abstract

The invention provides an active absorption circuit which is used for absorbing voltage stress generated when a switching tube in a DC-DC conversion circuit is turned off, and the DC-DC conversion circuit comprises a power supply part, a load part, a first rectifier diode D1, a transformer TX1 and a first field effect transistor Q1. The active absorption circuit comprises a reference voltage setting circuit, a first absorption circuit, a comparison circuit, a second absorption circuit and an anti-logic circuit, the reference voltage setting circuit is connected with the load part in parallel, the first absorption circuit is connected with the first field effect transistor Q1 and the comparison circuit, and the comparison circuit is further connected with the reference voltage setting circuit; the second absorption circuit is connected with the first field effect transistor Q1. The anti-logic circuit is connected with the comparison circuit and the second absorption circuit. When the voltage stress is smaller than the reference voltage value, stress absorption is carried out through the second absorption circuit; and when the voltage stress is greater than the reference voltage value, the comparison circuit is started to perform stress release, so that the technical effect of accurately controlling the voltage stress of the switching tube is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to an active absorption circuit. Background Art

[0002] In the design of DC-DC conversion circuits, due to the existence of stray inductance in actual circuits or devices, when the switch tube turns off the current, the current energy in the stray inductance needs to continue to be discharged, but the switch tube is already in the off state, and the current in the stray inductance cannot flow through the channel of the switch tube, but can only flow through the parasitic capacitance at both ends of the switch tube. Therefore, LC resonance occurs between the stray inductance and parasitic capacitance in the circuit. When the leakage inductance is larger or the turn-off current is larger, the voltage amplitude generated by the resonance is higher. This voltage amplitude is superimposed on the turn-off voltage platform of the switch tube, forming the switch stress in the operation of the DC-DC conversion circuit.

[0003] Switching stress will increase the difficulty of DC-DC conversion circuit design. When designing products, the voltage resistance of the switching tube must be greater than the maximum stress that may occur in various working conditions of the DC-DC conversion circuit. At the same time, in order to ensure the reliability of the product after mass production, it is also necessary to consider the discreteness of the leakage inductance of the transformer after mass production. The selection of the switching tube must leave a large enough margin. This will lead to an increase in the cost of selecting too large a margin for the switching device, or cause the switching device to be risky due to high stress conditions after working for a long time.

[0004] That is, how to provide a new type of active absorption circuit to achieve the technical effect of accurately controlling the voltage stress of the switch tube and reducing the circuit cost is a technical problem that urgently needs to be solved in this field. Summary of the invention

[0005] In view of the above-mentioned problems, the present invention aims to provide an active absorption circuit to solve at least one of the above-mentioned technical problems.

[0006] In order to at least solve the above technical problems, the present invention provides an active absorption circuit, which is used to absorb the voltage stress generated when the first field effect tube Q1 in the DC-DC conversion circuit is turned off. The DC-DC conversion circuit includes a power supply part, a load part, a first rectifier diode D1, a transformer TX1 and a first field effect tube Q1. The positive electrode of the power supply part is connected to the same-name terminal on the input side of the transformer TX1, the opposite-name terminal on the input side of the transformer TX1 is connected to the drain of the first field effect tube Q1, the positive electrode of the first rectifier diode D1 is connected to the opposite-name terminal on the output side of the transformer TX1, the negative electrode of the first rectifier diode D1 is connected to one end of the load part, the negative electrode of the power supply part, the source of the first field effect tube Q1, the other end of the load part and the same-name terminal on the output side of the transformer TX1 are all grounded, and the active absorption circuit includes:

[0007] A reference voltage setting circuit, the reference voltage setting circuit is connected in parallel to both ends of the load part;

[0008] A first absorption circuit, wherein a first end and a second end of the first absorption circuit are respectively connected to two ends of the first field effect transistor Q1;

[0009] a comparison circuit, wherein a first end of the comparison circuit is connected to a third end of the first absorption circuit, a second end of the comparison circuit is connected to a voltage setting end of the reference voltage setting circuit, and a third end of the comparison circuit is connected to a fourth end of the first absorption circuit;

[0010] a second absorption circuit, wherein a first end of the second absorption circuit is connected to a drain of the first field effect transistor Q1;

[0011] An inverting logic circuit, wherein a first end of the inverting logic circuit is connected to the fourth end of the comparison circuit, and a second end of the inverting logic circuit is connected to the second end of the second absorption circuit.

[0012] Preferably, the power supply part comprises:

[0013] A DC power supply V1, wherein the positive electrode of the DC power supply V1 is connected to the same-name terminal of the input side of the transformer TX1, and the negative electrode of the DC power supply V1 is grounded;

[0014] A first capacitor C1 is connected in parallel to two ends of the DC power source V1.

[0015] Preferably, the load part comprises:

[0016] A first resistor R1, one end of the first resistor R1 is connected to the cathode of the first rectifier diode D1, and the other end of the first resistor R1 is grounded;

[0017] a second capacitor C2, wherein the second capacitor C2 is connected in parallel to two ends of the first resistor R1;

[0018] The reference voltage setting circuit is connected in parallel to two ends of the first resistor R1.

[0019] Preferably, the first absorption circuit comprises:

[0020] A second rectifier diode D2, wherein the anode of the second rectifier diode D2 is connected to the first end of the first absorption circuit and the drain of the first field effect transistor Q1;

[0021] a third capacitor C3, one end of the third capacitor C3 is connected to the cathode of the second rectifier diode D2, and the other end of the third capacitor C3 is connected to the source of the first field effect transistor Q1 as the second end of the first absorption circuit;

[0022] a second resistor R2, one end of the second resistor R2 being connected to one end of the third capacitor C3;

[0023] a third resistor R3, one end of the third resistor R3 is connected to the other end of the second resistor R2, and the other end of the third resistor R3 is grounded;

[0024] a fourth capacitor C4, wherein the fourth capacitor C4 is connected in parallel to two ends of the third resistor R3;

[0025] Among them, one end of the third resistor R3 is connected to the third end of the first absorption circuit and the first end of the comparison circuit, and the cathode of the second rectifier diode D2 is connected to the fourth end of the first absorption circuit and the third end of the comparison circuit.

[0026] Preferably, the reference voltage setting circuit comprises:

[0027] a fourth resistor R4, one end of the fourth resistor R4 is connected to one end of the first resistor R1;

[0028] a voltage zener diode D3, wherein a cathode of the voltage zener diode D3 is connected to the other end of the fourth resistor R4, and an anode of the voltage zener diode D3 is grounded;

[0029] The cathode of the voltage stabilizing diode D3 is connected to the voltage setting end of the reference voltage setting circuit and the second end of the comparison circuit.

[0030] Preferably, the comparison circuit comprises:

[0031] A comparator X1, wherein the non-inverting input terminal of the comparator X1 is the first terminal of the comparison circuit connected to one end of the third resistor R3, the inverting input terminal of the comparator X1 is the second terminal of the comparison circuit connected to the cathode of the voltage stabilizing diode D3, the positive power supply terminal of the comparator X1 is connected to the cathode of the first rectifier diode D1, and the negative power supply terminal of the comparator X1 is grounded;

[0032] a second field effect transistor Q2, wherein the gate of the second field effect transistor Q2 is connected to the output end of the comparator X1, the output end of the comparator X1 is connected to the fourth end of the comparison circuit and the first end of the inversion logic circuit, and the drain of the second field effect transistor Q2 is connected to the third end of the comparison circuit and the cathode of the second rectifier diode D2;

[0033] A transistor Q3, wherein the base of the transistor Q3 is connected to the source of the second field effect transistor Q2, the emitter of the transistor Q3 is grounded, and the collector of the transistor Q3 is connected to the output end of the comparator X1;

[0034] a fifth resistor R5, one end of which is connected to the collector of the transistor Q3 and the output end of the comparator X1 respectively, and the other end of which is connected to the positive power supply end of the comparator X1;

[0035] A sixth resistor R6, one end of the sixth resistor R6 is connected to the source of the second field effect transistor Q2 and the base of the transistor Q3 respectively, and the other end of the sixth resistor R6 is connected to the emitter of the transistor Q3.

[0036] Preferably, the second absorption circuit comprises:

[0037] a seventh resistor R7, one end of the seventh resistor R7 being connected to the first end of the second absorption circuit and the drain of the first field effect transistor Q1;

[0038] a fifth capacitor C5, one end of the fifth capacitor C5 being connected to the other end of the seventh resistor R7;

[0039] A fourth field effect transistor Q4, wherein the drain of the fourth field effect transistor Q4 is connected to the other end of the fifth capacitor C5, the source of the fourth field effect transistor Q4 is grounded, and the gate of the fourth field effect transistor Q4 is connected to the second end of the second absorption circuit and the second end of the inversion logic circuit.

[0040] Preferably, the inversion logic circuit comprises:

[0041] a fifth field effect transistor Q5, wherein the gate of the fifth field effect transistor Q5 is connected to the first end of the inverting logic circuit and the output end of the comparator X1, the source of the fifth field effect transistor Q5 is grounded, and the drain of the fifth field effect transistor Q5 is connected to the second end of the inverting logic circuit and the gate of the fourth field effect transistor Q4;

[0042] An eighth resistor R8, one end of the eighth resistor R8 is connected to the drain of the fifth field effect transistor Q5, and the other end of the eighth resistor R8 is connected to the cathode of the first rectifier diode D1.

[0043] Preferably, the comparison circuit further includes:

[0044] The ninth resistor R9 is connected between the non-inverting input terminal and the output terminal of the comparator X1.

[0045] Preferably, the first field effect transistor Q1, the second field effect transistor Q2, the fourth field effect transistor Q4, and the fifth field effect transistor Q5 are all NMOS transistors, and the transistor Q3 is an NPN transistor.

[0046] Beneficial effects:

[0047] The present invention provides an active absorption circuit for absorbing voltage stress generated when a switch tube in a DC-DC conversion circuit is turned off, wherein the DC-DC conversion circuit comprises a power supply part, a load part, a first rectifier diode D1, a transformer TX1 and a first field effect tube Q1, the power supply part and the first field effect tube Q1 are connected to the input side of the transformer TX1, the output side of the transformer TX1 is connected to the load through the first rectifier diode D1 to form a DC-DC voltage conversion circuit, the active absorption circuit comprises a reference voltage setting circuit, a first absorption circuit, a comparison circuit, a second absorption circuit and an inverting logic circuit, the reference voltage setting circuit is connected in parallel to the two ends of the load part; the first end and the second end of the first absorption circuit are respectively connected to the two ends of the first field effect tube Q1; the first end of the comparison circuit is connected to the third end of the first absorption circuit, the second end of the comparison circuit is connected to the voltage setting end of the reference voltage setting circuit, and the third end of the comparison circuit is connected to the fourth end of the first absorption circuit; the first end of the second absorption circuit is connected to the first field effect tube Q1; ... first field effect tube Q1; the second end of the comparison circuit is connected to the first field effect tube Q1; the second end of the comparison circuit is connected to the first field effect tube Q1; the second end of the comparison circuit is connected to the first field effect tube Q1; the second end of the comparison circuit is connected to the first field effect tube Q1; the second end of the comparison circuit is connected to the first field effect tube Q1 The first end of the inverting logic circuit is connected to the drain of the first field effect tube Q1; the first end of the inverting logic circuit is connected to the fourth end of the comparison circuit, and the second end of the inverting logic circuit is connected to the second end of the second absorption circuit, so as to generate a reference voltage value through the reference voltage setting circuit and connect it to the comparison circuit, and by connecting the comparison circuit to the first absorption circuit, the voltage stress of the first field effect tube Q1 is compared with the reference voltage value through the comparison circuit, thereby realizing the monitoring of the voltage stress, so that when the voltage stress is greater than the reference voltage value, the comparison circuit is started to release the stress; by setting an inverting logic circuit between the comparison circuit and the second absorption circuit, the inverting logic control between the comparison circuit and the second absorption circuit is realized, and when the second absorption circuit is turned on, the comparison circuit is not started, so that when the voltage stress is less than the reference voltage value, the voltage stress is absorbed by the second absorption circuit, thereby realizing the precise control of the stress voltage of the first field effect tube Q1, and when Q1 is selected, it is not necessary to reserve a large voltage resistance margin, further reducing the circuit cost while ensuring the reliability of the circuit.

[0048] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0050] Figure 1 A schematic diagram of a circuit structure in which the active absorption circuit provided in the first embodiment is applied to a DC-DC conversion circuit;

[0051] Figure 2 A partial structural diagram of the active absorption circuit provided in Example 1.

[0052] Reference numerals:

[0053] 1. Reference voltage setting circuit;

[0054] 2. The first absorption circuit;

[0055] 3. Comparison circuit;

[0056] 4. The second absorption circuit;

[0057] 5. Inverse logic circuit. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of this specification to clearly and completely describe the technical solutions in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention; the "and / or" keyword involved in this implementation represents both and, or. In other words, A and / or B mentioned in the embodiments of this specification represent both A and B, and A or B, and describe the three states of A and B. For example, A and / or B means: only A is included but not B; only B is included but not A; A and B are included.

[0059] Meanwhile, in the embodiments of this specification, when a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a central component at the same time. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time.

[0060] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0061] Embodiment 1

[0062] See also Figure 1-2The first embodiment of the present invention provides an active absorption circuit for absorbing the voltage stress generated when the first field effect tube Q1 in the DC-DC conversion circuit is turned off. The DC-DC conversion circuit includes a power supply part, a load part, a first rectifier diode D1, a transformer TX1 and a first field effect tube Q1. The positive electrode of the power supply part is connected to the same-name terminal on the input side of the transformer TX1, the opposite-name terminal on the input side of the transformer TX1 is connected to the drain of the first field effect tube Q1, the positive electrode of the first rectifier diode D1 is connected to the opposite-name terminal on the output side of the transformer TX1, the negative electrode of the first rectifier diode D1 is connected to one end of the load part, and the negative electrode of the power supply part, the source of the first field effect tube Q1, the other end of the load part and the same-name terminal on the output side of the transformer TX1 are all grounded. The active absorption circuit includes a reference voltage setting circuit 1, a first absorption circuit 2, a comparison circuit 3, a second absorption circuit 4 and an inverting logic circuit 5. The reference voltage setting circuit 1 is connected in parallel to the two ends of the load part; the first end and the second end of the first absorption circuit 2 are respectively connected to the two ends of the first field effect tube Q1; the first end of the comparison circuit 3 is connected to the third end of the first absorption circuit 2, the second end of the comparison circuit 3 is connected to the voltage setting end of the reference voltage setting circuit 1, and the third end of the comparison circuit 3 is connected to the fourth end of the first absorption circuit 2; the first end of the second absorption circuit 4 is connected to the drain of the first field effect tube Q1; the first end of the inverting logic circuit 5 is connected to the fourth end of the comparison circuit 3, and the second end of the inverting logic circuit 5 is connected to the second end of the second absorption circuit 4.

[0063] The present invention provides an active absorption circuit for absorbing voltage stress generated when a switch tube in a DC-DC conversion circuit is turned off, wherein the DC-DC conversion circuit comprises a power supply part, a load part, a first rectifier diode D1, a transformer TX1 and a first field effect tube Q1, the power supply part and the first field effect tube Q1 are connected to the input side of the transformer TX1, the output side of the transformer TX1 is connected to the load through the first rectifier diode D1 to form a DC-DC voltage conversion circuit, the active absorption circuit comprises a reference voltage setting circuit 1, a first absorption circuit 2, a comparison circuit 3, a second absorption circuit 4 and an inverting logic circuit 5, the reference voltage setting circuit 1 is connected in parallel to the two ends of the load part; the first end and the second end of the first absorption circuit 2 are respectively connected to the two ends of the first field effect tube Q1; the first end of the comparison circuit 3 is connected to the third end of the first absorption circuit 2, the second end of the comparison circuit 3 is connected to the voltage setting end of the reference voltage setting circuit 1, and the third end of the comparison circuit 3 is connected to the fourth end of the first absorption circuit 2; the first end of the second absorption circuit 4 is connected to the first field effect tube The drain of Q1 is connected; the first end of the inverting logic circuit 5 is connected to the fourth end of the comparison circuit 3, and the second end of the inverting logic circuit 5 is connected to the second end of the second absorption circuit 4, so as to generate a reference voltage value through the reference voltage setting circuit 1 and connect it to the comparison circuit 3. By connecting the comparison circuit 3 with the first absorption circuit 2, the voltage stress of the first field effect tube Q1 is compared with the reference voltage value through the comparison circuit 3, thereby realizing the monitoring of the voltage stress, so that when the voltage stress is greater than the reference voltage value, the comparison circuit 3 is started to release the stress; by setting an inverting logic circuit 5 between the comparison circuit 3 and the second absorption circuit 4, the inverting logic control between the comparison circuit 3 and the second absorption circuit 4 is realized, and when the second absorption circuit 4 is turned on, the comparison circuit 3 is not started, so that when the voltage stress is less than the reference voltage value, the voltage stress is absorbed by the second absorption circuit 4, thereby realizing the precise control of the stress voltage of the first field effect tube Q1, and when Q1 is selected, it is not necessary to reserve a large voltage resistance margin, further reducing the circuit cost while ensuring the reliability of the circuit.

[0064] The cathode of the first rectifier diode D1 is also connected to the power supply terminals of the comparison circuit 3 and the inversion logic circuit 5 respectively, so as to provide voltage to the comparison circuit 3 and the inversion logic circuit 5 .

[0065] In a possible implementation, the power supply part includes a DC power supply V1 and a first capacitor C1, the positive electrode of the DC power supply V1 is connected to the same-name terminal on the input side of the transformer TX1, and the negative electrode of the DC power supply V1 is grounded; the first capacitor C1 is connected in parallel to both ends of the DC power supply V1.

[0066] Furthermore, the load part includes a first resistor R1 and a second capacitor C2, one end of the first resistor R1 is connected to the cathode of the first rectifier diode D1, and the other end of the first resistor R1 is grounded; the second capacitor C2 is connected in parallel to both ends of the first resistor R1; wherein, the reference voltage setting circuit 1 is connected in parallel to both ends of the first resistor R1.

[0067] Specifically, the active absorption circuit provided in the present application is used to absorb the voltage stress generated when the first field effect transistor Q1 in the DC-DC conversion circuit is turned off. The DC-DC conversion circuit is a flyback topology structure, wherein the DC power supply V1 is the input voltage, the first capacitor C1 is the DC-DC input filter capacitor, the first field effect transistor Q1 is the flyback switch tube, the first rectifier diode D1 is the flyback output rectifier diode, the second capacitor C2 is the flyback output filter capacitor, and the first resistor R1 is the flyback output load resistor. The basic working principle of the DC-DC conversion circuit is to use the transformer to store and release energy when the switch tube is turned on and off to realize the conversion of electric energy, that is, when the first field effect tube Q1 is turned on, the input voltage V1 passes through the primary winding P1 of the transformer. At this time, due to the relationship between the same-name terminals, the voltage of the secondary winding S1 is reversed, the first rectifier diode D1 is cut off, the transformer does not supply power to the load part, and the primary winding P1 of the transformer begins to store energy; when the first field effect tube Q1 is turned off, the current of the primary winding P1 is suddenly interrupted, according to Lenz's law, the secondary winding S1 induces a forward voltage, the first rectifier diode D1 is turned on, and the energy stored in the transformer is released to the load part and the output filter capacitor C2 through the secondary winding S1. The gate of the first field effect tube Q1 is connected to the control chip of the external power circuit, and the PWM wave emitted by the control chip periodically controls the on and off of the first field effect tube Q1.

[0068] In a possible embodiment, the first absorption circuit 2 includes a second rectifier diode D2, a third capacitor C3, a second resistor R2, a third resistor R3 and a fourth capacitor C4, the positive electrode of the second rectifier diode D2 is connected to the first end of the first absorption circuit 2 and the drain of the first field effect transistor Q1; one end of the third capacitor C3 is connected to the negative electrode of the second rectifier diode D2, and the other end of the third capacitor C3 is connected to the second end of the first absorption circuit 2 and the source of the first field effect transistor Q1; one end of the second resistor R2 is connected to one end of the third capacitor C3; one end of the third resistor R3 is connected to the other end of the second resistor R2, and the other end of the third resistor R3 is grounded; the fourth capacitor C4 is connected in parallel to both ends of the third resistor R3; wherein, one end of the third resistor R3 is connected to the third end of the first absorption circuit 2 and the first end of the comparison circuit 3, and the negative electrode of the second rectifier diode D2 is connected to the fourth end of the first absorption circuit 2 and the third end of the comparison circuit 3.

[0069] Specifically, the second rectifier diode D2 and the third capacitor C3 are connected to the two ends of the first field effect tube Q1, which is the absorption circuit of Q1. When Q1 is turned off and stress is generated, the voltage stress is stored in the third capacitor C3 through the unidirectional conduction of D2. The resistors R2 and R3 are connected to the third capacitor C3, and the voltage of C3 is monitored through voltage division sampling. When the voltage on R3 exceeds the set threshold value Vref, the comparator X1 will output a high level and turn on the second field effect tube Q2. It can be seen that the voltage on the third capacitor C3 can be accurately controlled through the voltage division setting of R2 and R3, and the voltage on the third capacitor C3 is the stress voltage of the first field effect tube Q1.

[0070] In a possible implementation, the reference voltage setting circuit 1 includes a fourth resistor R4 and a Zener diode D3, one end of the fourth resistor R4 is connected to one end of the first resistor R1; the cathode of the Zener diode D3 is connected to the other end of the fourth resistor R4, and the anode of the Zener diode D3 is grounded; wherein the cathode of the Zener diode D3 is connected to the voltage setting end of the reference voltage setting circuit 1 and the second end of the comparison circuit 3.

[0071] Specifically, the voltage zener diode D3 is a voltage reference source, the fourth resistor R4 is a current limiting resistor, and a reference voltage value Vref is generated by R4 and D3. Vref is connected to the reverse input terminal of the comparator X1 to monitor the voltage stress of Q1 based on the reference voltage value Vref.

[0072] In a possible implementation, the comparison circuit 3 includes a comparator X1, a second field effect transistor Q2, a triode Q3, a fifth resistor R5 and a sixth resistor R6, the non-inverting input terminal of the comparator X1 is the first end of the comparison circuit 3 connected to one end of the third resistor R3, the inverting input terminal of the comparator X1 is the second end of the comparison circuit 3 connected to the negative electrode of the voltage-stabilizing diode D3, the positive power supply terminal of the comparator X1 is the power supply terminal of the comparison circuit 3 connected to the negative electrode of the first rectifier diode D1, and the negative power supply terminal of the comparator X1 is grounded; the gate of the second field effect transistor Q2 is connected to the output terminal of the comparator X1, the output terminal of the comparator X1 is the fourth end of the comparison circuit 3 connected to the first end of the inverting logic circuit 5, The drain of the second field effect transistor Q2 is connected to the third end of the comparison circuit 3 and the cathode of the second rectifier diode D2; the base of the triode Q3 is connected to the source of the second field effect transistor Q2, the emitter of the triode Q3 is grounded, and the collector of the triode Q3 is connected to the output end of the comparator X1; one end of the fifth resistor R5 is connected to the collector of the triode Q3 and the output end of the comparator X1 respectively, and the other end of the fifth resistor R5 is connected to the positive power supply end of the comparator X1, which is equivalent to being connected to the cathode of the second rectifier diode D2; one end of the sixth resistor R6 is connected to the source of the second field effect transistor Q2 and the base of the triode Q3 respectively, and the other end of the sixth resistor R6 is connected to the emitter of the triode Q3.

[0073] Specifically, the upper end of the second field effect tube Q2 is connected to the third capacitor C3, and the lower end is grounded through R6. When the second field effect tube Q2 is turned on, the energy stored in the capacitor C3 is discharged through Q2 and R6. Then when the first field effect tube Q1 is turned off again to generate stress, the leakage inductance energy is stored on C3 through D2. The circuit can discharge the leakage inductance energy one by one to ensure that the voltage stress of the first field effect tube Q1 is within a reasonable safety range. The transistor Q3 and the sixth resistor R6 together form an overcurrent protection circuit. If an abnormal current appears in the Q2 and D2 paths, and the abnormal current exceeds the set value, Q2 can be turned off.

[0074] Among them, the PVDD terminal provides an initial level for Q2 through the fifth resistor R5, that is, when working, if the peak voltage is less than the reference voltage value, the comparator outputs a low level; when the peak voltage exceeds the set value, the comparator flips, and PVDD gives Q2 a high level through R5 to turn on Q2 for protection.

[0075] In a possible embodiment, the second absorption circuit 4 includes a seventh resistor R7, a fifth capacitor C5 and a fourth field effect transistor Q4, one end of the seventh resistor R7 is connected to the first end of the second absorption circuit 4 and the drain of the first field effect transistor Q1; one end of the fifth capacitor C5 is connected to the other end of the seventh resistor R7; the drain of the fourth field effect transistor Q4 is connected to the other end of the fifth capacitor C5, the source of the fourth field effect transistor Q4 is grounded, and the gate of the fourth field effect transistor Q4 is connected to the second end of the second absorption circuit 4 and the second end of the anti-logic circuit 5.

[0076] Specifically, the on-off of the seventh resistor R7 and the fifth capacitor C5 path is controlled by the on-off of the fourth field effect transistor Q4, wherein the switching logic of the fourth field effect transistor Q4 is opposite to that of the second field effect transistor Q2, that is, when the comparison circuit 3 is started and the comparator X1 outputs a high level, the second field effect transistor Q2 and the fifth field effect transistor Q5 are turned on, at this time the fourth field effect transistor Q4 is turned off, and the R7 and C5 paths are disconnected; when the comparator X1 outputs a low level, the second field effect transistor Q2 and the fifth field effect transistor Q5 are turned off, at this time the fourth field effect transistor Q4 is turned on, and the R7 and C5 paths are connected.

[0077] In a possible implementation, the inverting logic circuit 5 includes a fifth field effect transistor Q5 and an eighth resistor R8, the gate of the fifth field effect transistor Q5 is the first end of the inverting logic circuit 5 connected to the output end of the comparator X1, the source of the fifth field effect transistor Q5 is grounded, and the drain of the fifth field effect transistor Q5 is the second end of the inverting logic circuit 5 connected to the gate of the fourth field effect transistor Q4; one end of the eighth resistor R8 is connected to the drain of the fifth field effect transistor Q5, and the other end of the eighth resistor R8 is the power supply end of the inverting logic circuit 5 connected to the negative electrode of the first rectifier diode D1.

[0078] Specifically, the inverting logic circuit 5 formed by the fifth field effect transistor Q5 and the eighth resistor R8 includes a method that makes the switching logic of Q4 opposite to that of Q2, that is, when Q2 is turned on, Q4 is turned off; when Q2 is turned off, Q4 is turned on.

[0079] In a possible implementation, the comparison circuit 3 also includes a ninth resistor R9, which is connected between the in-phase input terminal and the output terminal of the comparator X1, and is used to form a hysteresis network in the comparison circuit 3 to implement the hysteresis function of the comparator threshold, thereby ensuring that the auxiliary switch is not frequently turned on and off.

[0080] In a possible implementation manner, the first field effect transistor Q1 , the second field effect transistor Q2 , the fourth field effect transistor Q4 , and the fifth field effect transistor Q5 are all NMOS transistors, and the transistor Q3 is an NPN transistor.

[0081] This application provides two stress absorption paths, namely the R7, C5 absorption branch and the D2, Q2 absorption branch, and only one of the two branches will be turned on. R7, C5 can only absorb the stress of Q1 under normal working conditions. Under normal working conditions, the voltage stress generated by Q1 is less than the set reference voltage value Vref. When overcurrent, hardware overvoltage, and large load jump occur, due to the large amount of energy stored in the transformer leakage inductance, R7, C5 are not enough to release the large leakage inductance energy, and it is necessary to switch to the Q2, D2 absorption branch to forcibly release the leakage inductance energy.

[0082] That is, the circuit principle of this application is:

[0083] Under normal working conditions, that is, when the stress voltage of Q1 is less than the set reference voltage value Vref, Q2 and Q5 are disconnected, and Q4 is turned on. At this time, the absorption branches of D2 and Q2 do not work, and the absorption branches of R7 and C5 are turned on to absorb the voltage stress.

[0084] However, when the outgoing line is under abnormally large load transient condition, the R7 and C5 absorption branches can no longer protect Q1. At this time, the stress voltage of Q1 is greater than the set reference voltage value Vref, Q2 and Q5 are turned on, and Q4 is turned off. At this time, the R7 and C5 absorption branches are disconnected, while the D2 and Q2 absorption branches are turned on to discharge the leakage inductance energy.

[0085] The active absorption circuit provided in the present application is suitable for use in medium and low voltage circuits, such as circuits with a voltage below 800V-900V. The active absorption circuit provided in the present application has the following advantages:

[0086] 1. Since the voltage stress of the first field effect tube Q1 is monitored and compared through the hardware circuit, the stress optimization of Q1 under various working conditions can be accurately controlled without considering the discreteness of other transformer components, which greatly improves the life and reliability of the power supply in the DC-DC conversion circuit.

[0087] 2. The active absorption circuit can reduce the loss of the passive circuit in the circuit and improve the efficiency of the whole circuit;

[0088] 3. Since the stress voltage of the first field effect tube Q1 can be accurately controlled, it is not necessary to reserve a large voltage tolerance when selecting the main switch tube Q1, thereby further reducing the circuit cost while ensuring the circuit reliability.

[0089] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0090] The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. An active absorption circuit, characterized in that: The active absorption circuit is used to absorb the voltage stress generated in the DC-DC conversion circuit. The DC-DC conversion circuit includes a power supply part, a load part, a first rectifier diode D1, a transformer TX1 and a first field effect transistor Q1. The positive electrode of the power supply part is connected to the same-name terminal on the input side of the transformer TX1, the opposite-name terminal on the input side of the transformer TX1 is connected to the drain of the first field effect transistor Q1, the positive electrode of the first rectifier diode D1 is connected to the opposite-name terminal on the output side of the transformer TX1, the negative electrode of the first rectifier diode D1 is connected to one end of the load part, the negative electrode of the power supply part, the source of the first field effect transistor Q1, the other end of the load part and the same-name terminal on the output side of the transformer TX1 are all grounded. The active absorption circuit includes: A reference voltage setting circuit, the reference voltage setting circuit is connected in parallel to both ends of the load part; a first absorption circuit, wherein a first end of the first absorption circuit is connected to the drain of the first field effect transistor Q1, and a second end of the first absorption circuit is connected to the source of the first field effect transistor Q1; a comparison circuit, wherein a first end of the comparison circuit is connected to a third end of the first absorption circuit, a second end of the comparison circuit is connected to a voltage setting end of the reference voltage setting circuit, and a third end of the comparison circuit is connected to a fourth end of the first absorption circuit; a second absorption circuit, wherein a first end of the second absorption circuit is connected to a drain of the first field effect transistor Q1; An inverting logic circuit, wherein a first end of the inverting logic circuit is connected to the fourth end of the comparison circuit, and a second end of the inverting logic circuit is connected to the second end of the second absorption circuit.

2. The active absorption circuit according to claim 1, characterized in that: The power supply part includes: A DC power supply V1, wherein the positive electrode of the DC power supply V1 is connected to the same-name terminal of the input side of the transformer TX1, and the negative electrode of the DC power supply V1 is grounded; A first capacitor C1 is connected in parallel to two ends of the DC power source V1.

3. The active absorption circuit according to claim 2, characterized in that: The load part includes: A first resistor R1, one end of the first resistor R1 is connected to the cathode of the first rectifier diode D1, and the other end of the first resistor R1 is grounded; a second capacitor C2, wherein the second capacitor C2 is connected in parallel to two ends of the first resistor R1; The reference voltage setting circuit is connected in parallel to two ends of the first resistor R1.

4. The active absorption circuit according to claim 3, characterized in that: The first absorption circuit comprises: A second rectifier diode D2, wherein the anode of the second rectifier diode D2 is the first end of the first absorption circuit; a third capacitor C3, one end of the third capacitor C3 is connected to the cathode of the second rectifier diode D2, and the other end of the third capacitor C3 is the second end of the first absorption circuit; a second resistor R2, one end of the second resistor R2 being connected to one end of the third capacitor C3; a third resistor R3, one end of the third resistor R3 is connected to the other end of the second resistor R2, and the other end of the third resistor R3 is grounded; a fourth capacitor C4, wherein the fourth capacitor C4 is connected in parallel to two ends of the third resistor R3; One end of the third resistor R3 is the third end of the first absorption circuit, and the cathode of the second rectifier diode D2 is the fourth end of the first absorption circuit.

5. The active absorption circuit according to claim 4, characterized in that: The reference voltage setting circuit comprises: a fourth resistor R4, one end of the fourth resistor R4 is connected to one end of the first resistor R1; a voltage zener diode D3, wherein a cathode of the voltage zener diode D3 is connected to the other end of the fourth resistor R4, and an anode of the voltage zener diode D3 is grounded; Wherein, the cathode of the voltage stabilizing diode D3 is the voltage setting terminal of the reference voltage setting circuit.

6. The active absorption circuit according to claim 5, characterized in that: The comparison circuit comprises: A comparator X1, wherein the non-inverting input terminal of the comparator X1 is the first terminal of the comparison circuit, the inverting input terminal of the comparator X1 is the second terminal of the comparison circuit, the positive power supply terminal of the comparator X1 is connected to the cathode of the first rectifier diode D1, and the negative power supply terminal of the comparator X1 is grounded; a second field effect transistor Q2, wherein the gate of the second field effect transistor Q2 is connected to the output end of the comparator X1, the output end of the comparator X1 is the fourth end of the comparison circuit, and the drain of the second field effect transistor Q2 is the third end of the comparison circuit; A transistor Q3, wherein the base of the transistor Q3 is connected to the source of the second field effect transistor Q2, the emitter of the transistor Q3 is grounded, and the collector of the transistor Q3 is connected to the output end of the comparator X1; a fifth resistor R5, one end of which is connected to the collector of the transistor Q3 and the output end of the comparator X1 respectively, and the other end of which is connected to the positive power supply end of the comparator X1; A sixth resistor R6, one end of the sixth resistor R6 is connected to the source of the second field effect transistor Q2 and the base of the transistor Q3 respectively, and the other end of the sixth resistor R6 is connected to the emitter of the transistor Q3.

7. The active absorption circuit according to claim 6, characterized in that: The second absorption circuit comprises: a seventh resistor R7, one end of the seventh resistor R7 being the first end of the second absorption circuit; a fifth capacitor C5, one end of the fifth capacitor C5 being connected to the other end of the seventh resistor R7; A fourth field effect transistor Q4, wherein the drain of the fourth field effect transistor Q4 is connected to the other end of the fifth capacitor C5, the source of the fourth field effect transistor Q4 is grounded, and the gate of the fourth field effect transistor Q4 is the second end of the second absorption circuit.

8. The active absorption circuit according to claim 7, characterized in that: The inversion logic circuit comprises: a fifth field effect transistor Q5, wherein the gate of the fifth field effect transistor Q5 is the first end of the inverting logic circuit, the source of the fifth field effect transistor Q5 is grounded, and the drain of the fifth field effect transistor Q5 is the second end of the inverting logic circuit; An eighth resistor R8, one end of the eighth resistor R8 is connected to the drain of the fifth field effect transistor Q5, and the other end of the eighth resistor R8 is connected to the cathode of the first rectifier diode D1.

9. The active absorption circuit according to claim 8, characterized in that: The comparison circuit further comprises: The ninth resistor R9 is connected between the non-inverting input terminal and the output terminal of the comparator X1.

10. The active absorption circuit according to claim 9, characterized in that: The first field effect transistor Q1 , the second field effect transistor Q2 , the fourth field effect transistor Q4 , and the fifth field effect transistor Q5 are all NMOS transistors, and the transistor Q3 is an NPN transistor.

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