High-dynamic-response high-frequency square-wave pulse current source and control method thereof

Abstract

The invention relates to the technical field of power electronics, and particularly discloses a high-dynamic-response high-frequency square-wave pulse current source and a control method thereof.The high-dynamic-response high-frequency square-wave pulse current source is provided with a DC-DC conversion circuit, a voltage loop control circuit, a PWM signal circuit, a current loop control circuit and the like, and the DC-DC conversion circuit, the current loop control circuit and the PWM signal circuit form a current loop; loop control is carried out on the output current of the DC-DC conversion circuit, so that the frequency and the pulse width of the output current of the high-frequency square-wave pulse current source meet requirements; and the DC-DC conversion circuit, the filter circuit, the protection circuit, the voltage loop control circuit and the PWM signal circuit form a voltage loop, so that the output voltage of the high-frequency square-wave pulse current source meets the safety requirement. According to the invention, voltage and current double-loop control is adopted, the output response speed is high, the output frequency and the pulse width are adjustable, the structure is simple, the cost is low, and the circuit is suitable for a plurality of fields such as laser and CLASS-D power amplifiers.

Description

Technical Field

[0001] The invention relates to the technical field of power electronics, and in particular to a high-frequency square wave pulse current source with high dynamic response and a control method thereof. Background Art

[0002] In the field of laser lighting, pulse drive technology is widely used in semiconductor lasers because it can effectively reduce structural heating and provide greater output power, thereby generating stronger light pulses. Traditional current sources often face efficiency and stability issues. High-frequency square wave pulse current sources have become an important solution for laser driving due to their fast response and precise control characteristics. By adjusting the frequency and amplitude of the pulse, this current source can effectively improve the output power and spot quality of the laser. In addition, the use of square wave waveforms reduces harmonic distortion and improves the overall performance of the system.

[0003] With the advancement of laser technology, the market demand for high-efficiency and high-quality current sources continues to increase. The operation of semiconductor lasers depends on the control of the excitation current, and the fluctuation of the excitation current may affect the stability of the laser. Therefore, optimizing the quality of the current pulse output by the driving power supply is the key to improving the performance of the laser. However, the current high-frequency square wave pulse current source has a slow response speed and cannot accurately control the frequency and amplitude of the output current. Summary of the invention

[0004] The present invention provides a high-frequency square wave pulse current source with high dynamic response and a control method thereof, and solves the technical problem of how to improve the response speed of the high-frequency square wave pulse current source and how to accurately control the frequency and amplitude of the output current.

[0005] In order to solve the above technical problems, the present invention provides a high-frequency square wave pulse current source with high dynamic response, including a DC-DC conversion circuit, a filter circuit, a protection circuit, a voltage sampling circuit, a voltage loop control circuit, a PWM signal circuit, a current loop control circuit and a reference signal modulation circuit, wherein the voltage sampling circuit is used to collect the output voltage of the protection circuit and convert it into a sampling voltage and send it to the voltage loop control circuit; the voltage loop control circuit generates a voltage control signal according to the sampling voltage and sends it to the PWM signal circuit; the current loop control circuit is used to collect the current of the sampling resistor R1 in the DC-DC conversion circuit and generates a current control signal according to the output current and sends it to the PWM signal circuit; the PWM signal circuit is used to generate a PWM signal according to the voltage control signal and the current control signal to act on the DC-DC conversion circuit; the DC-DC conversion circuit outputs a waveform following the reference signal waveform under the control of the PWM signal; the filter circuit is used to filter the output waveform of the DC-DC conversion circuit; the protection circuit is used to perform overvoltage protection; the reference signal modulation circuit is used to provide a reference current to the current loop control circuit.

[0006] Preferably, the DC-DC conversion circuit rectifies the DC power supply through a synchronous rectification BUCK converter, and the PWM signal circuit controls the on and off of two switching tubes of the synchronous rectification BUCK converter by sending a PWM signal to achieve conversion from the DC power supply to a square wave pulse.

[0007] Preferably, the DC-DC conversion circuit includes a DC power supply E dc , NMOS transistors Q1 and Q2 that form the synchronous rectification BUCK converter, inductor L1, sampling resistor R1 and capacitors C1, C2, C3, C4, DC power supply E dc The positive terminal and negative terminal are connected to the drain of transistor Q1 and the source of transistor Q2 respectively, the source of transistor Q1 is connected to the drain of transistor Q2 and one end of inductor L1, the source of transistor Q2 is also grounded and connected to one end of sampling resistor R1, capacitors C1, C2, C3, and C4 are connected in parallel to the other end of inductor L1 and the other end of sampling resistor R1 in sequence, and the gate of transistor Q1 and the gate of transistor Q2 are connected to the PWM signal circuit.

[0008] Preferably, the voltage loop control circuit uses an analog circuit for PID control, and obtains a voltage error signal by subtracting a reference voltage VREF from a sampled voltage V_sample collected in real time, and inputs the signal into a PID controller. The PID controller calculates a corresponding voltage control signal V_control and gives it to a PWM signal circuit.

[0009] Preferably, V_control is equal to Where etv = VREF-V_sample represents the error between V_sample and VREF, K pv , T iv and T dv They represent voltage proportion, integration, and differential coefficients respectively, T1 represents the voltage integration period, represents the integral of etv, Represents the differentiation of etv.

[0010] Preferably, the voltage loop control circuit includes resistors R5, R6, R7, a sliding rheostat R8, capacitors C8, C9, C10, diodes D1, D2, and an operational amplifier U2; the output end of V_sample is connected to the resistor R7 and then connected to the negative input end of the operational amplifier U2, the series resistor R5 and capacitor C8 are connected in parallel to the resistor R7, the series resistor R6 and capacitor C9 are sequentially connected between the negative input end and the output end of the operational amplifier U2, the diode D1 is forwardly connected between the common end of the resistor R6 and the capacitor C9 and the output end of the operational amplifier U2, the two constant ends of the sliding rheostat R8 are connected to the 3.3V bias voltage and the ground, the sliding end of the sliding rheostat R8 is connected to the positive input end of the operational amplifier U2 as the output end of the reference voltage VREF, the capacitor C10 is connected between the positive input end of the operational amplifier U2 and the ground, the positive end of the diode D2 is connected to the output end of the operational amplifier U2, and the negative end of the diode D2 outputs the voltage control signal V_control to the PWM signal circuit; under this circuit structure, KpvTdv=R6*C9.

[0011] Preferably, the current loop control circuit adopts PI control, and a current error signal is obtained by subtracting a reference current IREF from a sampled current I_sample collected in real time, and the current error signal is input into a PI controller. The PI controller calculates a corresponding current control signal I_control and gives it to a PWM signal circuit.

[0012] Preferably, I_control is equal to eti=IREF-I_sample represents the error between the reference current IREF and the sampled current I_sample, K pi , T ii They represent the current proportion and integration coefficient respectively, and T2 represents the current integration period.

[0013] Preferably, the current loop control circuit includes resistors R15, R16, R17, R18, R19, R20, R21, R22, R23, a sliding rheostat R14, capacitors C12, C13, a diode D3, and operational amplifiers U4, U5, and U6; the output end of the current sampling signal I_sample is connected to the resistors R18 and R20 connected in series in sequence and then to ground, the two constant ends of the sliding rheostat R14 are connected to the 3.3V bias voltage and ground, the sliding end of the sliding rheostat R14 is connected to the resistor R15 and then to the positive input end of the operational amplifier U4, the capacitor C12 is connected between the common end of the sliding rheostat R14 and the resistor R15 and the ground, the output end of the operational amplifier U4 is connected to the resistor R19 and then to the positive input end of the operational amplifier U5, and the positive The input end is also connected to the common end of resistors R18 and R20, resistors R17 and R16 are connected in series between the output end of the operational amplifier U5 and the ground, the common end of resistors R17 and R16 is also connected to the negative input end of the operational amplifier U5, the output end of the operational amplifier U5 is also connected to the negative input end of the operational amplifier U6 through resistor R21, the reference current IREF is connected to the positive input end of the operational amplifier U6 through resistor R22, resistor R23 and capacitor C13 are connected in series between the negative input end and the output end of the operational amplifier U6, the diode D3 is forwardly connected between the common end of resistor R23 and capacitor C13 and the output end of the operational amplifier U6, and the output end of the operational amplifier U6 outputs the current control signal I_control to the PWM signal circuit; under this circuit structure,

[0014] The present invention also provides a control method for a high-frequency square wave pulse current source with high dynamic response, which is applied to the high-frequency square wave pulse current source with high dynamic response. The key point is that the control method comprises the steps of:

[0015] Real-time acquisition of the current I_sample of the sampling resistor R1 and the output voltage V_sample of the protection circuit;

[0016] Subtract the reference current IREF from the current I_sample of the resistor R1 collected in real time to obtain a current error signal, which is input into the current loop control circuit. The current loop control circuit calculates and obtains a corresponding current control signal I_control to the PWM signal circuit;

[0017] Subtract the reference voltage VREF from the sampled voltage V_sample collected in real time to obtain a voltage error signal, which is input into the voltage loop control circuit. The voltage loop control circuit calculates and obtains a corresponding voltage control signal V_control to the PWM signal circuit;

[0018] The PWM signal circuit generates a PWM signal according to the voltage control signal and the current control signal to act on the DC-DC conversion circuit;

[0019] Return to step one.

[0020] The present invention provides a high-frequency square wave pulse current source with high dynamic response and a control method thereof, wherein the high-frequency square wave pulse current source is provided with a DC-DC conversion circuit, a filter circuit, a protection circuit, a voltage sampling circuit, a voltage loop control circuit, a PWM signal circuit, a current loop control circuit and a reference signal modulation circuit, wherein the DC-DC conversion circuit, the filter circuit and the protection circuit constitute the current source main circuit, and the voltage sampling circuit, the voltage loop control circuit, the PWM signal circuit, the current loop control circuit and the reference signal modulation circuit constitute the main circuit control circuit to control the output voltage and current of the main circuit to meet the requirements. The present invention adopts a DC-DC conversion circuit, a current loop control circuit and a PWM signal circuit to form a current loop to perform loop control on the output current of the DC-DC conversion circuit so that the frequency and pulse width of the output current of the high-frequency square wave pulse current source meet the requirements; it adopts a DC-DC conversion circuit, a filter circuit, a protection circuit, a voltage loop control circuit and a PWM signal circuit to form a voltage loop so that the output voltage of the high-frequency square wave pulse current source meets the safety requirements. The invention adopts voltage and current dual-loop control, has fast output response speed, and adjustable output frequency and pulse width. The invention has simple structure and low cost, and is suitable for multiple fields such as laser and CLASS-D power amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a circuit structure diagram of a high-frequency square wave pulse current source with high dynamic response provided by an embodiment of the present invention;

[0022] Figure 2 is a circuit diagram of a DC-DC conversion circuit, a filter circuit, and a protection circuit provided by an embodiment of the present invention;

[0023] Figure 3 is a structural diagram of a power supply circuit provided by an embodiment of the present invention;

[0024] Figure 4 is a circuit diagram of a reference signal modulation circuit provided by an embodiment of the present invention;

[0025] Figure 5 is a circuit diagram of a voltage sampling circuit provided by an embodiment of the present invention;

[0026] Figure 6 is a control principle diagram of a voltage loop and a current loop control circuit provided by an embodiment of the present invention;

[0027] Figure 7is a circuit diagram of a voltage loop control circuit provided by an embodiment of the present invention;

[0028] Figure 8 is a circuit diagram of a current loop control circuit provided by an embodiment of the present invention;

[0029] Fig. 9 is a circuit diagram of a PWM signal circuit provided by an embodiment of the present invention;

[0030] Fig.10 The embodiment of the present invention provides Figure 1 Specific circuit diagram;

[0031] Fig.11 is a waveform diagram of the output of the PWM signal circuit provided by an embodiment of the present invention;

[0032] Fig.12 1 is a diagram of the voltage (3 channels) and the driving signal waveform (2 channels) of the transistor Q1 provided in an embodiment of the present invention;

[0033] Fig.13 1 is a diagram of the voltage (3 channels) and the driving signal waveform (2 channels) of the transistor Q2 provided in an embodiment of the present invention;

[0034] Fig.14 The output current waveform (3 channels) of the protection circuit provided in the embodiment of the present invention, the reference signal input waveform (1 channel) and the driving waveforms (2 channels and 4 channels) of the NMOS transistor switch elements Q1 and Q2. DETAILED DESCRIPTION

[0035] The following specifically illustrates the implementation mode of the present invention in conjunction with the accompanying drawings. The embodiments are provided for illustrative purposes only and cannot be understood as limiting the present invention. The accompanying drawings are provided for reference and illustration only and do not constitute a limitation on the scope of patent protection of the present invention, because many changes can be made to the present invention without departing from the spirit and scope of the present invention.

[0036] The embodiment of the present invention provides a high-frequency square wave pulse current source with high dynamic response, such as Figure 1As shown, it includes a DC-DC conversion circuit, a filter circuit, a protection circuit, a voltage sampling circuit, a voltage loop control circuit, a PWM signal circuit, a current loop control circuit and a reference signal modulation circuit. The voltage sampling circuit is used to collect the output voltage (VOUT) of the protection circuit and convert it into a sampling voltage (V_sample) and send it to the voltage loop control circuit. The voltage loop control circuit generates a voltage control signal (V_control) according to the sampling voltage (V_sample) and sends it to the PWM signal circuit. The current loop control circuit is used to collect the current (I_sample) of the sampling resistor R1 in the DC-DC conversion circuit and generate a current control signal (I_control) according to the current (I_sample) and send it to the PWM signal circuit. The PWM signal circuit is used to generate a PWM signal according to the voltage control signal (V_control) and the current control signal (I_control) to act on the DC-DC conversion circuit. The DC-DC conversion circuit outputs a waveform following the reference signal waveform under the control of the PWM signal; the filter circuit is used to filter the output waveform of the DC-DC conversion circuit; and the reference signal modulation circuit is used to provide a reference current (IREF) to the current loop control circuit.

[0037] The present invention provides a high-frequency square wave pulse current source with high dynamic response, which is provided with a DC-DC conversion circuit, a filter circuit, a protection circuit, a voltage sampling circuit, a voltage loop control circuit, a PWM signal circuit, a current loop control circuit and a reference signal modulation circuit, wherein the DC-DC conversion circuit, the filter circuit, and the protection circuit constitute the current source main circuit, and the voltage sampling circuit, the voltage loop control circuit, the PWM signal circuit, the current loop control circuit and the reference signal modulation circuit constitute the main circuit control circuit to control the output voltage and current of the main circuit to meet the requirements. The present invention adopts a DC-DC conversion circuit, a current loop control circuit, and a PWM signal circuit to form a current loop to perform loop control on the output current of the DC-DC conversion circuit, so that the frequency and pulse width of the output current of the high-frequency square wave pulse current source meet the requirements; it adopts a DC-DC conversion circuit, a filter circuit, a protection circuit, a voltage loop control circuit, and a PWM signal circuit to form a voltage loop, so that the output voltage of the high-frequency square wave pulse current source meets the safety requirements. The invention adopts voltage and current dual-loop control, has fast output response speed, and adjustable output frequency and pulse width. The invention has simple structure and low cost, and is suitable for multiple fields such as laser and CLASS-D power amplifier.

[0038] In this embodiment, the DC-DC conversion circuit needs to generate square wave pulses. A relatively simple method is to invert the DC power supply through a synchronous rectification BUCK converter. The PWM signal circuit controls the on and off of the two switching tubes of the half-bridge inverter by sending a PWM signal, thereby realizing the conversion from DC power supply to square wave pulses.

[0039] As a more preferred embodiment, Figure 2 As shown, the DC-DC conversion circuit includes a DC power supply E dc , (NMOS) transistors Q1 and Q2 that form the synchronous rectifier BUCK converter, and also include inductor L1, sampling resistor R1 and capacitors C1, C2, C3, C4, among which the DC power supply E dc The positive terminal and negative terminal of the power inductor L1 are connected to the drain of transistor Q1 and the source of transistor Q2 respectively, the source of transistor Q1 is connected to the drain of transistor Q2 and one end of inductor L1, the source of transistor Q2 is also grounded and connected to one end of sampling resistor R1, capacitors C1, C2, C3, and C4 are connected in parallel to the other end of inductor L1 and the other end of sampling resistor R1 in turn, and the gate of transistor Q1 and the gate of transistor Q2 are connected to the PWM signal circuit (respectively connected to the PWMH output end and the PWML output end of the PWM signal circuit). Here, the role of power inductor L1 is to resonate with the parasitic capacitance of NMOS tube, completely release the charge in the parasitic capacitance of NMOS tube, and finally realize ZVS, and the current of inductor L1 is used as a state variable to participate in current loop control. The role of capacitors C1, C2, C3, and C4 is filtering. The two NMOS transistors of the DC-DC conversion circuit of this embodiment realize soft switching, and the loss of its operation is very small.

[0040] In this embodiment, the filter circuit is used to provide multi-stage filtering to eliminate voltage and current pulsation and switching noise. A relatively simple method is to use inductors and capacitors to form an LC filter network. As a relatively preferred implementation, the filter circuit of this example is as follows Figure 2 As shown, it includes an inductor L2, an inductor L3, a capacitor C5 and a capacitor C6, wherein the inductor L2 and the inductor L3 are connected in series, the capacitors C5 and C6 are connected between the inductor L2 and the inductor L3 to form a T-type structure, and the filter circuit is connected in parallel to the capacitors C1, C2, C3, and C4 of the DC-DC conversion circuit.

[0041] In this embodiment, the protection circuit is used to protect the circuit from overvoltage. As a preferred implementation, Figure 2 As shown, in this example, the varistor R2 is used as a protection circuit. When the voltage exceeds the clamping voltage, the varistor will quickly reduce its resistance and guide the excess voltage to the ground, thereby protecting subsequent components from damage.

[0042] In addition, in order to power the corresponding chips in the sampling circuit, the reference signal modulation circuit, the voltage loop control circuit, the current loop control circuit, and the PWM signal circuit, this embodiment also provides a power supply circuit, the circuit structure of which is as follows: Figure 3 As shown, it includes a first-stage power supply circuit and a second-stage power supply circuit, respectively as shown Figure 3As shown in (a) and (b). Figure 3 As shown, the first-stage power supply circuit and the second-stage power supply circuit use the SSP9481 chip and the ME3121 chip respectively. The SSP9481 chip converts the input voltage VIN into VOU1 to power the driver chip (in the reference signal modulation circuit and the PWM signal circuit) and serves as the input of the ME3121. The ME3121 chip converts VOUT1 into VOU2 to power the chips in the voltage loop control circuit and the current loop control circuit and serves as the bias voltage of the reference signal modulation circuit, the voltage loop control circuit, and the current loop control circuit.

[0043] More specifically, Figure 3 As shown in (a), the first-stage signal circuit includes resistors R31, R32, R33, and R34, an inductor L4, capacitors C16, C17, C18, and C19, and a diode D6. The input voltage VIN is connected to the VIN terminal (voltage input terminal) of the SSP9481 chip, and the GND terminal (reference ground terminal) of the SSP9481 chip is grounded. The resistors R31 and R32 are connected in series between the input voltage VIN and the ground. The common terminal of the resistors R31 and R32 is connected to the EN terminal (enable control terminal) of the SSP9481 chip. The capacitor C16 is connected to the input voltage VIN. The voltage VIN is connected to the ground, the BST end (analog ground end) of the SSP9481 chip is connected to the capacitor C17 and then reversely connected to the diode D6 and then grounded, the SW end (switch end) of the SSP9481 chip is connected to one end of the inductor L4, and the other end of the inductor L4 outputs the voltage VOUT1 and is connected to the capacitor C18 and then grounded; the FB end (feedback end) of the SSP9481 chip is connected to one end of the resistor R33 and one end of the resistor R34, the other end of the resistor R33 is grounded, the other end of the resistor R34 is connected to the other end of the inductor L4, and the capacitor C19 is connected in parallel with the resistor R33.

[0044] The EN pin voltage of the SPP9481 chip should satisfy Venr = 1.4V. According to the circuit structure, there are:

[0045]

[0046] The voltage VFB of the FB pin of the SPP9481 chip is 0.812V. According to the required value of VOUT1, the specific values ​​of the resistors R31, R32, R33 and R34 can be calculated.

[0047] Based on:

[0048]

[0049] The specific value of L4 can be calculated, △I represents the inductor ripple current, and fosc represents the switching frequency.

[0050] More specifically, Figure 3 As shown in (b), the second-stage signal circuit includes resistors R35, R36, R37, R38, inductor L5, capacitors C20, C21, C22, C23, C24, diode D6, VOUT1 connects one end of capacitor C20, one end of capacitor C21, one end of resistor R35 and IN end (input voltage end) of chip ME3121, the other end of capacitor C20 is grounded, the other end of capacitor C21 is connected to the other end of resistor R35, one end of resistor R36 is connected to EN end (enable control end) of chip ME3121, the other end of resistor R36 is grounded, and the BOOT end (bootstrap end, used to connect bootstrap capacitor, is The high-side switch driving circuit inside the chip provides the necessary voltage) connects capacitor C22 and then connects the LX terminal of chip ME3121 (the switching terminal, which is the output terminal of the power switch inside the chip and is used to connect the external inductor and output capacitor) and one end of the inductor L5. The other end of the inductor L5 outputs VOUT2. Resistors R37 and R38 are connected in series between the other end of the inductor L5 and the ground. Capacitor C23 is connected between the other end of the inductor L5 and the FB terminal of chip ME3121 (the feedback terminal, which is used to connect the external feedback resistor network to set and adjust the output voltage). Capacitor C24 is connected between the other end of the inductor L5 and the ground. The GND terminal of chip ME3121 is grounded.

[0051] according to Figure 3 For the circuit structure shown in (b), the output voltage of the ME3121 chip should satisfy the following formula:

[0052]

[0053] Then, the inductor L5 should satisfy:

[0054]

[0055] Among them, Ipeak represents the peak current, and its value needs to ensure that when the output current is maximum, Ipeak is less than the chip peak current limit value 1.9A and the saturation current of the inductor, T represents the inverse of the switching frequency, and Iout represents the output current. Thus, the value of L5 can be obtained.

[0056] The reference signal modulation circuit is used to provide a reference current signal (IREF) for the current loop control circuit. Specifically, it converts the reference signal into a reference current signal (IREF), and is mainly constructed using resistors, capacitors, and comparators. As a relatively simple implementation, the reference signal modulation circuit of this example adopts Figure 4The circuit structure shown specifically includes a reference signal generating circuit (for providing an input reference signal), resistors R9, R10, R11, R12, R13, capacitors C11, C12 and an operational amplifier U3, the IN0 output terminal of the reference signal is connected to resistors R9 and R10 connected in series in sequence and then connected to the output terminal of the operational amplifier U3, the output terminal of the operational amplifier U3 outputs a reference current signal (IREF), the capacitor C11 is connected between the negative input terminal and the output terminal of the operational amplifier U3, the common terminal of the resistors R9 and R10 is connected to the negative input terminal of the operational amplifier U3, the IN1 output terminal of the reference signal is connected to resistor R12 and then connected to the positive input terminal of the operational amplifier U3, the resistors R11 and R12 are connected in series in sequence between a 3.3V voltage and ground, the common terminal of the resistors R11 and R12 is connected to the positive input terminal of the operational amplifier U3, and the bypass capacitor C12 is connected between the positive input terminal of the operational amplifier U3 and ground. The IN+ terminal of the reference signal conditioning circuit is connected to the reference voltage 3.3V through the voltage divider resistors R11, R12, and R13 to form a bias network, and the IN- terminal is connected to the resistors R9 and R10. These two resistors form the negative feedback network of the operational amplifier. The output terminal of the operational amplifier U3 is IREF, which is controlled by the negative feedback network (R9 and R10). The IREF current is the output signal of the circuit and depends on the input differential voltage and the ratio of the feedback resistors.

[0057] according to Figure 4 The circuit structure shown in the figure can obtain the reference current signal (IREF) as:

[0058]

[0059] The output voltage sampling circuit is used to sample and transform the output voltage VOUT of the protection circuit, and is mainly constructed by resistors, capacitors and comparators. As a relatively simple implementation method, the output voltage sampling circuit of this example adopts the following Figure 5 The circuit structure shown includes resistors R3 and R4 (forming a resistor voltage divider network), capacitor C7, and operational amplifier U1, wherein resistors R3 and R4 are sequentially connected in series between VOUT and ground, capacitor C7 is connected between the common end of resistors R3 and R4 and ground, the common end of resistors R3 and R4 is also connected to the positive input end of operational amplifier U1, the negative input end of operational amplifier U1 is connected to its output end, and the output end of operational amplifier U1 outputs a sample voltage (V_sample). V_sample and VOUT satisfy the relationship:

[0060]

[0061] The voltage loop control circuit and the current loop control circuit provided by the present invention have the following control principles: Figure 6As shown, PID control is adopted for voltage (a voltage error signal is obtained by subtracting a reference voltage VREF from a sampled voltage V_sample collected in real time, and the voltage error signal is input into a PID controller. The PID controller calculates a corresponding voltage control signal V_control and gives it to a PWM signal circuit), and PI control is adopted for current (a current error signal is obtained by subtracting a reference current IREF from a sampled current I_sample collected in real time, and the voltage error signal is input into a PI controller. The PI controller calculates a corresponding current control signal I_control and gives it to a PWM signal circuit).

[0062] Specifically, the process of PID controller obtaining V_control can be formulated as:

[0063]

[0064] Where, etv = VREF-V_sample represents the error between V_sample and VREF, K pv , T iv and T dv They represent voltage proportion, integration, and differential coefficients respectively, T1 represents the voltage integration period, represents the integral of etv, Represents the differentiation of etv.

[0065] The voltage loop control circuit is mainly constructed by using resistors, sliding resistors, capacitors, comparators and diodes. As a preferred implementation, Figure 7 The structure diagram of the voltage loop control circuit provided in this embodiment is shown, which includes resistors R5, R6, R7, sliding rheostat R8, capacitors C8, C9, C10, diodes D1, D2, and operational amplifier U2. The output end of V_sample is connected to the resistor R7 and then connected to the negative input end of the operational amplifier U2, the series resistor R5 and capacitor C8 are connected in parallel to the resistor R7, the series resistor R6 and capacitor C9 are sequentially connected between the negative input end and the output end of the operational amplifier U2, the diode D1 is forwardly connected between the common end of the resistor R6 and the capacitor C9 and the output end of the operational amplifier U2, the two fixed ends of the sliding rheostat R8 are connected to the 3.3V bias voltage and the ground, the sliding end of the sliding rheostat R8 is connected to the positive input end of the operational amplifier U2 as the output end of the reference voltage VREF, the capacitor C10 is connected between the positive input end of the operational amplifier U2 and the ground (for filtering), the positive end of the diode D2 is connected to the output end of the operational amplifier U2, and the negative end of the diode D2 outputs the voltage control signal V_control to the PWM signal circuit.

[0066] based on Figure 7 The circuit structure shown can be obtained:

[0067]

[0068] The voltage control signal V_control (the voltage thereof) can be obtained according to formula (9).

[0069] Specifically, the process of obtaining I_control by the PI controller can be formulated as:

[0070]

[0071] Here, eti=IREF-I_sample represents the error between the reference current IREF and the sampled current I_sample, K pi , T ii They represent the current proportion and integration coefficient respectively, and T2 represents the current integration period.

[0072] The current loop control circuit is mainly constructed by using resistors, sliding resistors, capacitors, comparators and diodes. As a preferred implementation, Figure 8 The structure diagram of the current loop control circuit provided in this embodiment is shown, which includes resistors R15, R16, R17, R18, R19, R20, R21, R22, R23, a sliding rheostat R14, capacitors C12, C13, a diode D3, and operational amplifiers U4, U5, and U6. The output end of the current sampling signal I_sample is connected to the resistors R18 and R20 connected in series in sequence and then to ground, the two fixed ends of the sliding rheostat R14 are connected to the 3.3V bias voltage and ground, the sliding end of the sliding rheostat R14 is connected to the positive input end of the operational amplifier U4 after the resistor R15, the capacitor C12 is connected between the common end of the sliding rheostat R14 and the resistor R15 and the ground, the output end of the operational amplifier U4 is connected to the resistor R19 and then to the positive input end of the operational amplifier U5, the positive input end of the operational amplifier U5 is also connected to the common end of the resistors R18 and R20, and the resistors R17 and R16 are connected in series in sequence to the operational amplifier U5. The common end of resistors R17 and R16 is also connected to the negative input end of operational amplifier U5, and the output end of operational amplifier U5 is also connected to the negative input end of operational amplifier U6 through resistor R21. Reference current IREF is connected to the positive input end of operational amplifier U6 through resistor R22. Resistor R23 and capacitor C13 are sequentially connected in series between the negative input end and the output end of operational amplifier U6. Diode D3 is forwardly connected between the common end of resistor R23 and capacitor C13 and the output end of operational amplifier U6. The output end of operational amplifier U6 outputs current control signal I_control to the PWM signal circuit. The voltage I_sample of sampling resistor R1 is superimposed on bias current IP through resistor R18, R19, and R20 voltage divider circuit, and then amplified and output I1 through operational amplifier U5, wherein bias current IP can be adjusted by sliding rheostat R14.

[0073] against Figure 8 The current loop control circuit shown has:

[0074]

[0075] The PWM signal circuit is mainly constructed using resistors, capacitors, comparators, inverters and diodes. As a preferred implementation, Fig. 9 The structure diagram of the PWM signal circuit provided in this embodiment is shown, which includes resistors R24, R25, R26, R27, R28, R29, R30, capacitors C14, C15, C16, diodes D4, D5, comparator U7, and inverter U8. The signal output end of V_control is connected to the positive input end of the comparator U7 through resistors R24 and R25 connected in series in sequence, the signal output end of I_control is grounded through a resistor R28 and a capacitor C16 connected in series in sequence, the common end of the resistor R28 and the capacitor C16 is also connected to the common end of the resistors R24 and R25, the output end of the operational amplifier U5 is connected to the negative input end of the comparator U7 through a resistor R29, the resistor R26 is connected between the positive input end and the output end of the comparator U7, the output end of the comparator U7 also outputs the PWM control signal PWMH of the NMOS transistor Q1 through a parallel resistor R27 and a reverse diode D4, and the output end of PWML is also grounded through the capacitor C14; the output end of the comparator U7 is connected to the parallel resistor R30 and the reverse diode D5 through the inverter U8, and then outputs the PWM control signal PWML of the NMOS transistor Q2, and the output end of PWML is also grounded through the capacitor C15. Capacitor C14, resistor R27, and diode D4 form a delay circuit, and capacitor C15, resistor R30, and diode D5 form a delay circuit. I_control signal and V_control signal serve as the positive input terminal of comparator U7 and I1 signal serves as the negative input terminal of comparator U7. When the positive input terminal signal is less than the negative input terminal, the comparator outputs a high level to control the NMOS transistor Q1 to turn on, otherwise, it outputs a low level to turn off the NMOS transistor Q1. When the positive input terminal signal is less than the negative input terminal, the comparator outputs a high level, the inverter outputs a low level, and controls the NMOS transistor Q2 to turn off, otherwise, the inverter outputs a high level to control the NMOS transistor Q2 to turn on.

[0076] The current loop and voltage loop control circuit of this embodiment is a pure analog circuit design with fast response speed, and the output pulse wave frequency and pulse width are adjustable. The frequency and pulse width of the output pulse current can be adjusted by adjusting the frequency and duty cycle of the input reference signal.

[0077] Fig. 9The working principle of the PWM signal circuit shown is that the I / V_control signal is compared with the I1 signal through the comparator U7, the output result is delayed by the RC circuit to generate a dead time, and finally the PWM control signal PWMH of the NMOS transistor Q1 is output, the output of the comparator U7 is inverted by the inverter U8, the output signal is delayed by the RC to generate a dead time, and finally the PWM control signal PWML of the NMOS transistor Q2 is output.

[0078] joint Figures 2 to 9 ,available Figure 1 The specific circuit diagram is as follows Fig.10 shown.

[0079] Experimental settings: input DC voltage 48V, maximum input current 10A, output current peak 2A, output current rise and fall edge: less than 10μs. The output current frequency and pulse width are controlled by inputting 0~5V analog signal.

[0080] Fig.11 The PWM signal circuit output waveform is shown. Fig.11 It can be seen that the principle of generating the control signal is that when the current of L1 is less than the current of the positive input terminal of the comparator, the comparator outputs the PWMH signal to control the switch tube Q1 to turn on.

[0081] Fig.12 Shown Figure 1 The voltage of the NMOS transistor switch element Q1 (channel 3) and the PWMH signal waveform (channel 2). Fig.12 It can be seen that Q1 achieves zero voltage turn-on.

[0082] like Fig.13 Shown Figure 1 The voltage of the NMOS transistor switch element Q2 (channel 3) and the PWML signal waveform (channel 2). Fig.13 It can be seen that Q2 achieves zero voltage turn-on.

[0083] like Fig.14 The waveform of the output current of the protection circuit and the driving waveform of the NMOS transistor switch elements Q1 and Q2 are shown. Channel 3 is the output current waveform of the protection circuit, channel 1 is the reference signal input waveform, and channels 2 and 4 are the driving waveforms of the NMOS transistor switch elements Q1 and Q2 respectively. Fig.14 It can be seen that the reference signal input is 200Hz, the pulse width is 100us, and the amplitude is 5V; the frequency of the output current of the protection circuit is 200Hz, the pulse width is 100us, the amplitude is 2A, the rise time is 1.58us, and the fall time is 1.52us. The frequency of the driving waveform of the driving signal NMOS transistor switch elements Q1 and Q2 reaches megahertz.

[0084] The above experimental results show that the pulse current output by the high-frequency square wave current source has a fast response speed, the time for the output current to rise from 0 to 2A is less than 10μs, the frequency of the driving waveform of the NMOS transistor switch elements Q1 and Q2 reaches megahertz, and Q1 and Q2 achieve soft switching. And the output pulse current can follow the frequency and pulse width of the input reference signal.

[0085] With respect to a high-frequency square wave pulse current source with high dynamic response provided by the present invention, an embodiment of the present invention further provides a control method of a high-frequency square wave pulse current source with high dynamic response, which comprises the steps of:

[0086] Real-time acquisition of the current I_sample of the sampling resistor R1 and the output voltage V_sample of the protection circuit;

[0087] Subtract the reference current IREF from the current I_sample of the resistor R1 collected in real time to obtain a current error signal, which is input into the current loop control circuit. The current loop control circuit calculates and obtains a corresponding current control signal I_control to the PWM signal circuit;

[0088] Subtract the reference voltage VREF from the sampled voltage V_sample collected in real time to obtain a voltage error signal, which is input into the voltage loop control circuit. The voltage loop control circuit calculates and obtains a corresponding voltage control signal V_control to the PWM signal circuit;

[0089] The PWM signal circuit generates a PWM signal according to the voltage control signal and the current control signal to act on the DC-DC conversion circuit;

[0090] Return to step one.

[0091] The more specific control process of this control method has been explained in the above-mentioned high-frequency square wave pulse current source and will not be repeated here.

[0092] The present invention provides a high-frequency square wave pulse current source with high dynamic response and a control method thereof, wherein the high-frequency square wave pulse current source is provided with a DC-DC conversion circuit, a filter circuit, a protection circuit, a voltage sampling circuit, a voltage loop control circuit, a PWM signal circuit, a current loop control circuit and a reference signal modulation circuit, wherein the DC-DC conversion circuit, the filter circuit and the protection circuit constitute the current source main circuit, and the voltage sampling circuit, the voltage loop control circuit, the PWM signal circuit, the current loop control circuit and the reference signal modulation circuit constitute the main circuit control circuit to control the output voltage and current of the main circuit to meet the requirements. The present invention adopts a DC-DC conversion circuit, a current loop control circuit and a PWM signal circuit to form a current loop to perform loop control on the output current of the DC-DC conversion circuit so that the frequency and pulse width of the output current of the high-frequency square wave pulse current source meet the requirements; it adopts a DC-DC conversion circuit, a filter circuit, a protection circuit, a voltage loop control circuit and a PWM signal circuit to form a voltage loop so that the output voltage of the high-frequency square wave pulse current source meets the safety requirements. The invention adopts voltage and current dual-loop control, has fast output response speed, and adjustable output frequency and pulse width. The invention has simple structure and low cost, and is suitable for multiple fields such as laser and CLASS-D power amplifier.

[0093] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. A high-frequency square wave pulse current source with high dynamic response, characterized in that: The invention comprises a DC-DC conversion circuit, a filter circuit, a protection circuit, a voltage sampling circuit, a voltage loop control circuit, a PWM signal circuit, a current loop control circuit and a reference signal modulation circuit. The voltage sampling circuit is used to collect the output voltage of the protection circuit and convert it into a sampling voltage and send it to the voltage loop control circuit. The voltage loop control circuit generates a voltage control signal according to the sampling voltage and sends it to the PWM signal circuit. The current loop control circuit is used to collect the current of the sampling resistor R1 in the DC-DC conversion circuit and generates a current control signal according to the current and sends it to the PWM signal circuit. The PWM signal circuit is used to generate a PWM signal according to the voltage control signal and the current control signal to act on the DC-DC conversion circuit. The DC-DC conversion circuit outputs a waveform following the reference signal waveform under the control of the PWM signal. The filter circuit is used to filter the output waveform of the DC-DC conversion circuit. The protection circuit is used to perform overvoltage protection. The reference signal modulation circuit is used to provide a reference current to the current loop control circuit.

2. A high-frequency square wave pulse current source with high dynamic response according to claim 1, characterized in that: The DC-DC conversion circuit rectifies the DC power supply through a synchronous rectification BUCK converter, and the PWM signal circuit controls the on and off of two switching tubes of the synchronous rectification BUCK converter by sending a PWM signal to achieve the conversion from the DC power supply to the square wave pulse.

3. A high-frequency square wave pulse current source with high dynamic response according to claim 2, characterized in that: The DC-DC conversion circuit includes a DC power supply E dc , NMOS transistors Q1 and Q2 that form the synchronous rectification BUCK converter, inductor L1, sampling resistor R1 and capacitors C1, C2, C3, C4, DC power supply E dc The positive terminal and negative terminal are connected to the drain of transistor Q1 and the source of transistor Q2 respectively, the source of transistor Q1 is connected to the drain of transistor Q2 and one end of inductor L1, the source of transistor Q2 is also grounded and connected to one end of sampling resistor R1, capacitors C1, C2, C3, and C4 are connected in parallel to the other end of inductor L1 and the other end of sampling resistor R1 in sequence, and the gate of transistor Q1 and the gate of transistor Q2 are connected to the PWM signal circuit.

4. The high-frequency square wave pulse current source with high dynamic response according to claim 1, characterized in that: The voltage loop control circuit uses an analog circuit to perform PID control. By subtracting the reference voltage VREF from the sampled voltage V_sample collected in real time, a voltage error signal is obtained and input into the PID controller. The PID controller calculates the corresponding voltage control signal V_control and gives it to the PWM signal circuit.

5. A high-frequency square wave pulse current source with high dynamic response according to claim 4, characterized in that: V_control is equal to where e tv = VREF-V_sample represents the error between V_sample and VREF, K pv , T iv and T dv They represent voltage proportion, integration, and differential coefficients respectively, T1 represents the voltage integration period, Indicates e tv The integral of Indicates e tv The differential of .

6. A high-frequency square wave pulse current source with high dynamic response according to claim 5, characterized in that: The voltage loop control circuit includes resistors R5, R6, R7, a sliding rheostat R8, capacitors C8, C9, C10, diodes D1, D2, and an operational amplifier U2; the output end of V_sample is connected to the resistor R7 and then connected to the negative input end of the operational amplifier U2, the series resistor R5 and capacitor C8 are connected in parallel to the resistor R7, the series resistor R6 and capacitor C9 are sequentially connected between the negative input end and the output end of the operational amplifier U2, the diode D1 is forwardly connected between the common end of the resistor R6 and the capacitor C9 and the output end of the operational amplifier U2, the two fixed ends of the sliding rheostat R8 are connected to the 3.3V bias voltage and the ground, the sliding end of the sliding rheostat R8 is connected to the positive input end of the operational amplifier U2 as the output end of the reference voltage VREF, the capacitor C10 is connected between the positive input end of the operational amplifier U2 and the ground, the positive end of the diode D2 is connected to the output end of the operational amplifier U2, and the negative end of the diode D2 outputs the voltage control signal V_control to the PWM signal circuit; under this circuit structure, K pv T dv =R6*C9.

7. The high-frequency square wave pulse current source with high dynamic response according to claim 1, characterized in that: The current loop control circuit uses an analog circuit to perform PI control. By subtracting the reference current IREF from the sampled current I_sample collected in real time, a current error signal is obtained and input into the PI controller. The PI controller calculates the corresponding current control signal I_control and gives it to the PWM signal circuit.

8. A high-frequency square wave pulse current source with high dynamic response according to claim 7, characterized in that: e ti =IREF-I_sample represents the error between the reference current IREF and the sampled current I_sample, K pi , T ii They represent the current proportion and integration coefficient respectively, and T2 represents the current integration period.

9. A high-frequency square wave pulse current source with high dynamic response according to claim 8, characterized in that: The current loop control circuit includes resistors R15, R16, R17, R18, R19, R20, R21, R22, and R23, a sliding rheostat R14, capacitors C12 and C13, a diode D3, and operational amplifiers U4, U5, and U6; the output end of the current sampling signal I_sample is connected to the resistors R18 and R20 connected in series in sequence and then to ground, the two fixed ends of the sliding rheostat R14 are connected to the 3.3V bias voltage and the ground, the sliding end of the sliding rheostat R14 is connected to the resistor R15 and then to the positive input end of the operational amplifier U4, the capacitor C12 is connected between the common end of the sliding rheostat R14 and the resistor R15 and the ground, the output end of the operational amplifier U4 is connected to the resistor R19 and then to the positive input end of the operational amplifier U5, and the positive input end of the operational amplifier U5 is connected to the resistor R19. The end is also connected to the common end of resistors R18 and R20, resistors R17 and R16 are connected in series between the output end of the operational amplifier U5 and the ground, the common end of resistors R17 and R16 is also connected to the negative input end of the operational amplifier U5, the output end of the operational amplifier U5 is also connected to the negative input end of the operational amplifier U6 through resistor R21, the reference current IREF is connected to the positive input end of the operational amplifier U6 through resistor R22, resistor R23 and capacitor C13 are connected in series between the negative input end and the output end of the operational amplifier U6, the diode D3 is forwardly connected between the common end of resistor R23 and capacitor C13 and the output end of the operational amplifier U6, and the output end of the operational amplifier U6 outputs the current control signal I_control to the PWM signal circuit; under this circuit structure, 10. A control method for a high-frequency square wave pulse current source with high dynamic response, applied to a high-frequency square wave pulse current source with high dynamic response as claimed in any one of claims 1 to 9, characterized in that: Includes steps: Real-time acquisition of the current I_sample of the sampling resistor R1 and the output voltage V_sample of the protection circuit; Subtract the reference current IREF from the current I_sample of the resistor R1 collected in real time to obtain a current error signal, which is input into the current loop control circuit. The current loop control circuit calculates and obtains a corresponding current control signal I_control to the PWM signal circuit; Subtract the reference voltage VREF from the sampled voltage V_sample collected in real time to obtain a voltage error signal, which is input into the voltage loop control circuit. The voltage loop control circuit calculates and obtains a corresponding voltage control signal V_control to the PWM signal circuit; The PWM signal circuit generates a PWM signal according to the voltage control signal and the current control signal to act on the DC-DC conversion circuit; Return to step one.

Images