High-voltage driving circuit and system for subscriber line interface circuit

Abstract

The invention provides a high-voltage driving circuit and system for a subscriber line interface circuit. The high-voltage driving circuit comprises an upper driving circuit I11 and a lower driving circuit I22, and the upper driving circuit I11 and the lower driving circuit I22 form a push-pull output structure. A differential pair amplification scheme is used, a CASCODE (sleeve) structure is adopted in an adjusting tube, and the CASCODE structure is composed of a low-voltage MOS (metal oxide semiconductor) tube and two high-voltage tubes with withstand voltage lower than 90V. According to the invention, the requirement of high voltage resistance of the circuit is met, and the process realization difficulty is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of user line interface circuits, and in particular to a high voltage driving circuit and system for a user line interface circuit. Background Art

[0002] SLIC chips are widely used in switching systems and access network systems; they provide a communication interface between digital switching networks and analog subscriber lines, which are connected to user equipment through central switches. For example, in the field of telephone communications, the connection between telephones and telephone switches is through SLIC chips. SLIC chips convert analog signals through telephone lines into digital PCM signals, and also control the ringing of telephones, generate prompt tones, and display caller ID.

[0003] Analog subscriber lines and subscriber equipment form a subscriber loop. Subscriber equipment interface facilities require SLIC to provide relatively high voltage and current to subscriber equipment on the subscriber loop for signal control (line feeding). Voice communication is a low-voltage analog signal on the subscriber loop, so SLIC must also use low-voltage analog signals for detection and communication. SLIC must convert low-voltage analog signals into digital signals and send them to the digital network, and also convert digital signals received from the digital network into low-voltage analog signals and transmit them to subscriber equipment on the subscriber loop.

[0004] Usually low voltage integrated circuits are used in combination with high voltage integrated circuits to provide the required signal processing capabilities while providing driving capabilities for larger line loads at voltages up to 100V or more. In a design, the current source provided by the low voltage integrated circuit is mirrored and amplified by the high voltage integrated circuit to provide a larger current to the load, thereby enabling the high voltage integrated circuit to control the user line according to the control signal.

[0005] In order to save power and reduce the burden on low-voltage integrated circuits, the current provided by low-voltage integrated circuits is much smaller than the current provided by high-voltage integrated circuits to the load. The high-voltage integrated circuit amplifies the current provided by the low-voltage circuit to the required level. Usually, the current amplification of high-voltage line-fed drivers is achieved through current mirrors.

[0006] Reference Figure 1 As shown, a current mirror is disclosed in the prior art, and its implementation relies on high-voltage NMOS and PMOS devices. In modern high-voltage CMOS processes, to obtain the same electrical characteristics (such as Ron), PMOS devices are much larger than NMOS devices because the gate capacitance of PMOS devices is larger than the gate capacitance of corresponding NMOS devices, resulting in a potential lower bandwidth of the PMOS current source.

[0007] Using current mirror amplification is an effective line drive method. However, in addition to certain requirements on output current accuracy, noise, offset, and peak-to-peak value of output voltage under high current, the system loop also requires the system to be stable and have a large bandwidth.

[0008] The disadvantages of this solution include: 1) In modern high-voltage CMOS processes, to obtain the same electrical characteristics (such as Ron), PMOS devices are much larger than NMOS devices because the gate capacitance of PMOS devices is larger than the gate capacitance of corresponding NMOS devices, resulting in a potentially lower bandwidth of the PMOS current source. 2) In modern high-voltage CMOS processes, due to the existence of channel modulation effects, NMOS and PMOS currents increase with increasing VDS, making it difficult to accurately control the current accuracy.

[0009] Reference Figure 2 As shown, in another prior art, a differential pair of operational amplifiers and adjustment tubes are used. The current at the input terminal I1 of the line-fed driver generates a1*I1 current at the output terminal through the upper drive amplifier and the feedback resistor; at the same time, the current at the input terminal I2 generates a2*I2 current at the output terminal through the lower drive amplifier and the feedback resistor. During normal operation, I1=I2, a2=a1+1, making the push-pull output currents equal.

[0010] The disadvantages of this solution are as follows: 1) In this solution, the adjustment tube (NM8, NM16) is a High-Side-NMOS. As the voltage resistance requirement increases, the difficulty of the manufacturing process increases significantly, and the cost also increases significantly. In modern high-voltage CMOS processes, the operating voltage of High-Side-NMOS can usually only meet the use below 90V and cannot meet the application requirements above 100V. 2) In modern high-voltage CMOS processes, the turn-on voltage VTH of the high-voltage MOS tube is usually much higher than that of the low-voltage MOS tube, making it difficult to control the high-voltage adjustment tube through the differential amplifier circuit. Summary of the invention

[0011] In view of the defects in the prior art, an object of the present invention is to provide a high-voltage driving circuit and system for a subscriber line interface circuit.

[0012] A high voltage driving circuit for a subscriber line interface circuit according to the present invention comprises: an upper driving circuit I11 and a lower driving circuit I22;

[0013] The upper driving circuit I11 and the lower driving circuit I22 form a push-pull output structure.

[0014] Preferably, the upper driving circuit I11 includes: a high-voltage PMOS tube PM1, a high-voltage PMOS tube PM2, a high-voltage PMOS tube PM3, a high-voltage PMOS tube PM11, a high-voltage PMOS tube PM12, and a high-voltage PMOS tube PM14; a low-voltage PMOS tube PM4, and a low-voltage PMOS tube PM5; a high-voltage NMOS tube NM9, and a high-voltage NMOS tube NM10; a low-voltage NMOS tube NM6, a low-voltage NMOS tube NM7, a low-voltage NMOS tube NM8, and a low-voltage NMOS tube NM13; a transistor NPN1, and a transistor NPN2; a diode DZ1, a diode DZ2, a diode DZ3, and a diode DZ4; a resistor R1, a resistor R2, and a resistor R3;

[0015] The gates of the high-voltage PMOS tubes PM1, PM2, PM3, PM11, and PM12 and the drain of the high-voltage NMOS tube NM10 are all grounded; the source of the high-voltage PMOS tube PM1 is connected to the input I1 terminal, the drain of the high-voltage PMOS tube PM1 is connected to the emitter of the transistor NPN1, and one end of the resistor R2; the source of the high-voltage PMOS tube PM2 is connected to the input I3 terminal, the drain of the high-voltage PMOS tube PM2 is connected to the source of the low-voltage PMOS tube PM4; the source of the high-voltage PMOS tube PM3 is connected to the input I4 terminal, and the high-voltage The drain of the high-voltage PMOS tube PM3 is connected to the source of the low-voltage PMOS tube PM5; the source of the high-voltage PMOS tube PM11 is connected to the input I7 terminal, the drain of the high-voltage PMOS tube PM11 is connected to the gate of the high-voltage NMOS tube NM10, the cathode of the diode DZ3, and the cathode of the diode DZ1; the source of the high-voltage PMOS tube PM12 is connected to the input I8 terminal, the drain of the high-voltage PMOS tube PM12 is connected to the anode of the diode DZ1, the gate of the high-voltage NMOS tube NM9, the cathode of the diode DZ4, the drain of the low-voltage NMOS tube NM13, and the cathode of the diode DZ2; the The gate is connected to the gate of the low-voltage PMOS tube PM5, the drain of the low-voltage PMOS tube PM5, the gate of the low-voltage NMOS tube NM7, the drain of the low-voltage NMOS tube NM7, and the gate of the low-voltage NMOS tube NM6; the source of the high-voltage NMOS tube NM10 is connected to the anode of the diode DZ3 and the drain of the high-voltage NMOS tube NM9; the drain of the low-voltage PMOS tube PM4 is connected to the drain of the low-voltage NMOS tube NM6 and the gate of the low-voltage NMOS tube NM8; the drain of the low-voltage NMOS tube NM8 is connected to the gate of the low-voltage NMOS tube NM13, the anode of the diode DZ4, and the source of the high-voltage NMOS tube NM9. The source of the low-voltage NMOS tube NM13 is connected to the anode of the diode DZ2 and the source of the high-voltage PMOS tube PM14; the source of the low-voltage NMOS tube NM6 is connected to the collector of the transistor NPN1; the source of the low-voltage NMOS tube NM7 is connected to the base of the transistor NPN2, the collector of the transistor NPN2, and the base of the transistor NPN1; the emitter of the transistor NPN2 is connected to one end of the resistor R3; one end of the resistor R2 and one end of the resistor R1, and the gate of the high-voltage PMOS tube PM14 are connected to the TIP_RING end; the drain end of the high-voltage PMOS tube PM14 is connected to the VBAT end.

[0016] Preferably, the lower driving circuit I22 includes: a high-voltage PMOS tube PM15, a high-voltage PMOS tube PM16, a high-voltage PMOS tube PM17, a high-voltage PMOS tube PM18, a high-voltage PMOS tube PM19, a high-voltage PMOS tube PM20, a high-voltage PMOS tube PM21, and a high-voltage PMOS tube PM27; a high-voltage NMOS tube NM25, a high-voltage NMOS tube NM26; a low-voltage NMOS tube NM22, a low-voltage NMOS tube NM23, a low-voltage NMOS tube NM24, and a low-voltage NMOS tube NM28; a transistor NPN3, a transistor NPN4; a diode DZ5, a diode DZ6, a diode DZ7, and a diode DZ8; a resistor R4, a resistor R5, and a resistor R6;

[0017] The gates of the high-voltage PMOS tube PM15, the high-voltage PMOS tube PM16, the high-voltage PMOS tube PM17, the high-voltage PMOS tube PM18, and the high-voltage PMOS tube PM19 are all grounded; the drain of the high-voltage NMOS tube NM26 is connected to the TIP_RING terminal; the source of the high-voltage PMOS tube PM15 is connected to the input I2 terminal, the drain of the high-voltage PMOS tube PM15 is connected to the emitter of the transistor NPN3, and one end of the resistor R5; the source of the high-voltage PMOS tube PM16 is connected to the input I5 terminal, the drain of the high-voltage PMOS tube PM16 is connected to the source of the high-voltage PMOS tube PM20; The source of high-voltage PMOS tube PM7 is connected to the input I6 terminal, the drain of high-voltage PMOS tube PM17 is connected to the source of high-voltage PMOS tube PM21; the source of high-voltage PMOS tube PM18 is connected to the input I9 terminal, the drain of high-voltage PMOS tube PM18 is connected to the gate of high-voltage NMOS tube NM26, the cathode of diode DZ5, and the cathode of diode DZ7; the source of high-voltage PMOS tube PM19 is connected to the input I10 terminal, the drain of high-voltage PMOS tube PM19 is connected to the anode of diode DZ5, the gate of high-voltage NMOS tube NM25, the cathode of diode DZ6, the drain of low-voltage NMOS tube NM28, and the cathode of diode DZ8; The gate of the high-voltage PMOS tube PM20 is connected to the gate of the high-voltage PMOS tube PM21, the drain of the high-voltage PMOS tube PM21, the gate of the low-voltage NMOS tube NM23, the drain of the low-voltage NMOS tube NM23, and the gate of the low-voltage NMOS tube NM22; the source of the high-voltage NMOS tube NM26 is connected to the anode of the diode DZ7 and the drain of the high-voltage NMOS tube NM25; the drain of the high-voltage PMOS tube PM20 is connected to the drain of the low-voltage NMOS tube NM22 and the gate of the low-voltage NMOS tube NM24; the drain of the low-voltage NMOS tube NM24 is connected to the gate of the low-voltage NMOS tube NM28, the anode of the diode DZ8 The anode of the low-voltage NMOS tube NM28 is connected to the anode of the diode DZ6 and the source of the high-voltage PMOS tube PM27; the source of the low-voltage NMOS tube NM22 is connected to the collector of the transistor NPN3; the source of the low-voltage NMOS tube NM23 is connected to the base of the transistor NPN4, the collector of the transistor NPN4, and the base of the transistor NPN3; the emitter of the transistor NPN3 is connected to one end of the resistor R5; one end of the resistor R5 and one end of the resistor R4, the gate of the high-voltage PMOS tube PM27, and the drain of the high-voltage PMOS tube PM27 are connected to the VBAT terminal.

[0018] Preferably, the amplifier in the upper driving circuit I11 is formed by connecting transistor NPN1, transistor NPN2, NMOS tube low voltage NMOS tube NM6, low voltage NMOS tube NM7 into a sleeve input structure, and connecting high voltage PMOS tube PM2, high voltage PMOS tube PM3, low voltage PMOS tube PM4, low voltage PMOS tube PM5 into a sleeve load; bias current is provided by input terminals I3 and I4. The output of the amplifier controls the gate of the low voltage NMOS tube NM8 of the adjustment tube and forms a negative feedback structure through resistors R1, R2, and R3; the differential pair input introduces a resistor network composed of resistors R1, R2, and R3, which forms a linear transconductance loop with the differential pair transistors NPN1 and NPN2.

[0019] Preferably, in the upper driving circuit I11, the current provided by the input terminal I1 is applied to the connection between the emitter of the transistor NPN1 and the resistor R2 through the high-voltage PMOS transistor PM1, and the CASCODE combination composed of the adjustment tube low-voltage NMOS tube NM8, high-voltage NMOS tube NM9, and high-voltage NMOS tube NM10 controlled by the output of the differential amplifier is output to the connection between the resistor R1 and the resistor R3, and its output current Iout1 is:

[0020] Iout1=[(I1+I3)*R2-I4*(R1+R3)] / R1 (1)

[0021] Among them, I3 = I4, and its value is much smaller than I1;

[0022] Let R2 = a*R1; R3 = (a-1)*R1;

[0023] Simplifying formula (1) we get:

[0024] Iout1={(I1+I3)*a*R1-I4*[(a-1)*R1+R1]} / R1=a*I1 (2)

[0025] Ignoring I3 and I4, the current output from the upper drive circuit to TIP_RING is:

[0026] TIP_RING1=(1+a)*I1 (3).

[0027] Preferably, in the lower driving circuit I22, the input terminal I2 provides a current which is applied to the connection between the emitter of NPN3 and the resistor R5 through the high-voltage PMOS tube PM15, and the CASCODE combination composed of the adjustment tubes NM24, NM25, and NM26 controlled by the differential amplifier output is output to the connection between the resistor R6 and the resistor R4, and the output current Iout2 is:

[0028] Iout2=[(I2+I5)*R5-I6*(R6+ R4)] / R4 (4)

[0029] Among them, I5=I6, and its value is much smaller than I2;

[0030] Let R5 = b*R4; R6 = (b-1)*R4;

[0031] Simplifying formula (4) yields:

[0032] Iout2={(I2+I5)*b*R4-I6*[(b-1)*R4+R4]} / R4=b*I2 (5)

[0033] The current output from the lower drive circuit to TIP_RING is:

[0034] TIP_RING2=b*I2 (6).

[0035] Preferably, I1=I2, b=a+1, and the push-pull output current from the upper driving circuit I11 to TIP_RING is equal to the push-pull output current from the lower driving circuit I22 to TIP_RING.

[0036] A high-voltage driving system for a user line interface circuit provided according to the present invention comprises two groups of high-voltage driving circuits for the user line interface circuit, the two groups of high-voltage driving circuits for the user line interface circuit form a bridge drive, and the push and pull circuits in the high-voltage driving circuit of the user line interface circuit adopt time-sharing operation.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] The present invention uses a differential pair amplification scheme, and the adjustment tube adopts a CASCODE (sleeve) structure, which is composed of a low-voltage MOS tube and two high-voltage tubes with a withstand voltage lower than 90 V. The present invention meets the high withstand voltage requirements of the circuit and reduces the difficulty of process implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0040] Figure 1 It is a circuit structure diagram of the prior art 1;

[0041] Figure 2 It is a circuit structure diagram of the second prior art;

[0042] Figure 3 This is a structural diagram of the high-voltage drive circuit in the present invention. DETAILED DESCRIPTION

[0043] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0044] The present invention discloses a high voltage driving circuit. Figure 3 As shown, it includes: an upper driving circuit I11 and a lower driving circuit I22 forming a push-pull output structure.

[0045] The upper driving circuit I11 includes high-voltage PMOS tube PM1, high-voltage PMOS tube PM2, high-voltage PMOS tube PM3, high-voltage PMOS tube PM11, high-voltage PMOS tube PM12, and high-voltage PMOS tube PM14; low-voltage PMOS tube PM4 and low-voltage PMOS tube PM5; high-voltage NMOS tube NM9 and high-voltage NMOS tube NM10; low-voltage NMOS tube NM6, low-voltage NMOS tube NM7, low-voltage NMOS tube NM8 and low-voltage NMOS tube NM13; transistor NPN1 and transistor NPN2; diode DZ1, diode DZ2, diode DZ3, and diode DZ4; resistor R1, resistor R2, and resistor R3.

[0046] The circuit structure of the upper driving circuit I11 includes: the gates of the high-voltage PMOS tube PM1, the high-voltage PMOS tube PM2, the high-voltage PMOS tube PM3, the high-voltage PMOS tube PM11, and the high-voltage PMOS tube PM12 are grounded with the drain of the high-voltage NMOS tube NM10; the source of the high-voltage PMOS tube PM1 is connected to the input I1 terminal, the drain of the high-voltage PMOS tube PM1 is connected to the emitter of the transistor NPN1, and one end of the resistor R2. The source of the high-voltage PMOS tube PM2 is connected to the input I3 terminal, and the drain of the high-voltage PMOS tube PM2 is connected to the source of the low-voltage PMOS tube PM4; the source of the high-voltage PMOS tube PM3 is connected to the input I4 terminal, and the drain of the high-voltage PMOS tube PM3 is connected to the source of the low-voltage PMOS tube PM5; the source of the high-voltage PMOS tube PM11 is connected to the input I7 terminal, and the drain of the high-voltage PMOS tube PM11 is connected to the gate of the high-voltage NMOS tube NM10, the cathode of the diode DZ3, and the cathode of the diode DZ1; the high The source of the high-voltage PMOS tube PM12 is connected to the input I8 terminal, the drain of the high-voltage PMOS tube PM12 is connected to the anode of the diode DZ1, the gate of the high-voltage NMOS tube NM9, the cathode of the diode DZ4, the drain of the low-voltage NMOS tube NM13, and the cathode of the diode DZ2; the gate of the low-voltage PMOS tube PM4 is connected to the gate of the low-voltage PMOS tube PM5, the drain of the low-voltage PMOS tube PM5, the gate of the low-voltage NMOS tube NM7, the drain of the low-voltage NMOS tube NM7, and the low-voltage NMOS tube NM6 The gate of the high-voltage NMOS tube NM10 is connected; the source of the high-voltage NMOS tube NM10 is connected to the anode of the diode DZ3, and the drain of the high-voltage NMOS tube NM9 is connected; the drain of the low-voltage PMOS tube PM4 is connected to the drain of the low-voltage NMOS tube NM6, and the gate of the low-voltage NMOS tube NM8; the drain of the low-voltage NMOS tube NM8 is connected to the gate of the low-voltage NMOS tube NM13, the anode of the diode DZ4, and the source of the high-voltage NMOS tube NM9; the source of the low-voltage NMOS tube NM13 is connected to the anode of the diode DZ2, the high-voltage PMO The source of the S tube PM14 is connected; the source of the low-voltage NMOS tube NM6 is connected to the collector of the transistor NPN1; the source of the low-voltage NMOS tube NM7 is connected to the base of the transistor NPN2, the collector of the transistor NPN2, and the base of the transistor NPN1; the emitter of the transistor NPN2 is connected to one end of the resistor R3; one end of the resistor R2 and one end of the resistor R1, and the gate of the high-voltage PMOS tube PM14 are connected to the TIP_RING end; the drain end of the high-voltage PMOS tube PM14 is connected to the VBAT end.

[0047] The lower driving circuit I22 includes a high-voltage PMOS tube PM15, a high-voltage PMOS tube PM16, a high-voltage PMOS tube PM17, a high-voltage PMOS tube PM18, a high-voltage PMOS tube PM19, a high-voltage PMOS tube PM20, a high-voltage PMOS tube PM21, and a high-voltage PMOS tube PM27; a high-voltage NMOS tube NM25, a high-voltage NMOS tube NM26; a low-voltage NMOS tube NM22, a low-voltage NMOS tube NM23, a low-voltage NMOS tube NM24, and a low-voltage NMOS tube NM28; a transistor NPN3, a transistor NPN4; a diode DZ5, a diode DZ6, a diode DZ7, and a diode DZ8; a resistor R4, a resistor R5, and a resistor R6.

[0048] The circuit structure of the lower driving circuit I22 includes: the gates of the high-voltage PMOS tube PM15, the high-voltage PMOS tube PM16, the high-voltage PMOS tube PM17, the high-voltage PMOS tube PM18, and the high-voltage PMOS tube PM19 are connected to the ground; the drain of the high-voltage NMOS tube NM26 is connected to the TIP_RING end; the source of the high-voltage PMOS tube PM15 is connected to the input I2 end, the drain of the high-voltage PMOS tube PM15 is connected to the emitter of the transistor NPN3, and one end of the resistor R5; the source of the high-voltage PMOS tube PM16 is connected to the input I5 end, and the drain of the high-voltage PMOS tube PM16 is connected to the source of the high-voltage PMOS tube PM20; The source of the high-voltage PMOS tube PM17 is connected to the input I6 terminal, and the drain of the high-voltage PMOS tube PM17 is connected to the source of the high-voltage PMOS tube PM21; the source of the high-voltage PMOS tube PM18 is connected to the input I9 terminal, and the drain of the high-voltage PMOS tube PM18 is connected to the gate of the high-voltage NMOS tube NM26, the cathode of the diode DZ5, and the cathode of the diode DZ7; the source of the high-voltage PMOS tube PM19 is connected to the input I10 terminal, and the drain of the high-voltage PMOS tube PM19 is connected to the anode of the diode DZ5, the gate of the high-voltage NMOS tube NM25, the cathode of the diode DZ6, the drain of the low-voltage NMOS tube NM28, and the diode DZ8 The cathode of the high-voltage PMOS tube PM20 is connected; the gate of the high-voltage PMOS tube PM21, the drain of the high-voltage PMOS tube PM21, the gate of the low-voltage NMOS tube NM23, the drain of the low-voltage NMOS tube NM23, and the gate of the low-voltage NMOS tube NM22 are connected; the source of the high-voltage NMOS tube NM26 is connected to the anode of the diode DZ7, and the drain of the high-voltage NMOS tube NM25; the drain of the high-voltage PMOS tube PM20 is connected to the drain of the low-voltage NMOS tube NM22, and the gate of the low-voltage NMOS tube NM24; the drain of the low-voltage NMOS tube NM24 is connected to the gate of the low-voltage NMOS tube NM28, the diode D The anode of Z8 is connected to the source of the high-voltage NMOS tube NM25; the source of the low-voltage NMOS tube NM28 is connected to the anode of the diode DZ6 and the source of the high-voltage PMOS tube PM27; the source of the low-voltage NMOS tube NM22 is connected to the collector of the transistor NPN3; the source of the low-voltage NMOS tube NM23 is connected to the base of the transistor NPN4, the collector of the transistor NPN4, and the base of the transistor NPN3; the emitter of the transistor NPN3 is connected to one end of the resistor R5; one end of the resistor R5 and one end of the resistor R4, the gate of the high-voltage PMOS tube PM27, and the drain of the high-voltage PMOS tube PM27 are connected to the VBAT terminal.

[0049] The working principle of the high voltage driving circuit disclosed in the present invention is as follows:

[0050] The structures of the upper and lower driving circuits are basically the same, except that the upper driving circuit I11 is a source output, and is a CASCODE structure (common source and common gate structure) output composed of a low-voltage NMOS tube NM8 and two high-voltage NMOS tubes NM9 and a high-voltage NMOS tube NM10, while the lower driving circuit I22 is a drain output, and is a CASCODE structure composed of a low-voltage NMOS tube NM24 and two high-voltage NMOS tubes NM25 and NM26.

[0051] The amplifier in the upper driving circuit is formed by connecting transistor NPN1, transistor NPN2, low voltage NMOS tube NM6, low voltage NMOS tube NM7 into a sleeve input structure (CASCODE), and connecting high voltage PMOS tube PM2, high voltage PMOS tube PM3, low voltage PMOS tube PM4, low voltage PMOS tube PM5 into a sleeve load. The bias current is provided by input terminals I3 and I4. The output of the amplifier controls the gate of the low voltage NMOS tube NM8 of the adjustment tube and forms a negative feedback structure through resistors R1, R2, and R3. The differential pair input introduces a resistor network composed of resistors R1, R2, and R3, which forms a linear transconductance loop with the differential pair transistors NPN1 and NPN2. The CASCODE architecture determines that the low-frequency gain of the amplifier circuit is large enough, and the high loop gain effectively reduces the error of the current mirror.

[0052] The output of the amplifier circuit is connected to the gate of the low-voltage NMOS tube NM8, and the low-voltage NMOS tube NM8 is well matched with the low-voltage NMOS tube NM6 and the low-voltage NMOS tube NM7; and the high-voltage NMOS tube NM9 and the high-voltage NMOS tube NM10 are combined to withstand the voltage of more than 100V required by the system. The input terminals I7 and I8 provide the current required for biasing the gates of the high-voltage NMOS tubes NM9 and NM10, and the breakdown voltage of the Zener diode DZ1 can be adjusted to 60V-80V; the breakdown voltage of the diode DZ2 is 5.5V, which determines the appropriate maximum drain-source operating voltage for the low-voltage NMOS tubes NM8, NM9 and NM10; the breakdown voltage of the diodes DZ3 and DZ4 is 5.5V, which provides gate-source protection for the high-voltage NMOS tubes NM9 and NM10. The main purpose of introducing the low-voltage NMOS tube NM13 is to prevent the low-voltage NMOS tube NM8 from being subjected to excessively high voltage in the cut-off state and causing leakage. Excessive leakage will have an adverse effect on system matching.

[0053] The current provided by the input terminal I1 is applied to the connection between the emitter of the transistor NPN1 and the resistor R2 through the high-voltage PMOS tube PM1. The CASCODE combination composed of the adjustment tube low-voltage NMOS tube NM8, high-voltage NMOS tube NM9, and high-voltage NMOS tube NM10 controlled by the output of the differential amplifier is output to the connection between the resistor R1 and the resistor R3. Its output current Iout1 is:

[0054] Iout1=[(I1+I3)*R2-I4*(R1+R3)] / R1 (1)

[0055] Among them, I3=I4, which is guaranteed by design, and its value is much smaller than I1.

[0056] Resistance R2 = a*R1; R3 = (a-1)*R1.

[0057] Therefore, simplifying formula (1) yields:

[0058] Iout={(I1+I3)*a*R1-I4*[(a-1)*R1+R1]} / R1=a*I1 (2)

[0059] Ignoring I3 and I4, the current output from the upper drive circuit to TIP_RING is:

[0060] TIP_RING1=(1+a)*I1 (3)

[0061] For the lower drive circuit, the above analysis and description are also applicable. The input terminal I2 provides current through the high-voltage PMOS tube PM15 and is applied to the junction of the emitter of NPN3 and the resistor R5. The CASCODE combination composed of the adjustment tubes NM24, NM25, and NM26 controlled by the differential amplifier output is output to the junction of the resistor R6 and the resistor R4. The output current Iout2 is:

[0062] Iout2=[(I2+I5)*R5-I6*(R6+R4)] / R4 (4)

[0063] Among them, I5=I6, which is guaranteed by design and its value is much smaller than I2;

[0064] R5 = b*R4; R6 = (b-1)*R4;

[0065] Therefore, simplifying formula (4) yields:

[0066] Iout2={(I2+I5)*b*R4-I6*[(b-1)*R4+R4]} / R4=b*I2 (5)

[0067] The current output from the lower drive circuit to TIP_RING is:

[0068] TIP_RING2=b*I2 (6)

[0069] In the design, it is ensured that I1=I2, b=a+1, so the push-pull output current of the upper drive circuit and the lower drive circuit to TIP_RING is equal.

[0070] In practical applications, the system consists of two Figure 3 The circuit shown constitutes a bridge driver. Figure 3 The so-called push and pull circuits in the circuit work in time-sharing mode.

[0071] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A high voltage driving circuit for a subscriber line interface circuit, characterized in that: include: An upper driving circuit I11 and a lower driving circuit I22; The upper driving circuit I11 and the lower driving circuit I22 form a push-pull output structure.

2. The high voltage driving circuit for a subscriber line interface circuit according to claim 1, characterized in that: The upper driving circuit I11 includes: a high-voltage PMOS tube PM1, a high-voltage PMOS tube PM2, a high-voltage PMOS tube PM3, a high-voltage PMOS tube PM11, a high-voltage PMOS tube PM12, and a high-voltage PMOS tube PM14; a low-voltage PMOS tube PM4 and a low-voltage PMOS tube PM5; a high-voltage NMOS tube NM9 and a high-voltage NMOS tube NM10; a low-voltage NMOS tube NM6, a low-voltage NMOS tube NM7, a low-voltage NMOS tube NM8, and a low-voltage NMOS tube NM13; a transistor NPN1 and a transistor NPN2; a diode DZ1, a diode DZ2, a diode DZ3, and a diode DZ4; a resistor R1, a resistor R2, and a resistor R3; The gates of the high-voltage PMOS tubes PM1, PM2, PM3, PM11, and PM12 and the drain of the high-voltage NMOS tube NM10 are all grounded; the source of the high-voltage PMOS tube PM1 is connected to the input I1 terminal, the drain of the high-voltage PMOS tube PM1 is connected to the emitter of the transistor NPN1, and one end of the resistor R2; the source of the high-voltage PMOS tube PM2 is connected to the input I3 terminal, the drain of the high-voltage PMOS tube PM2 is connected to the source of the low-voltage PMOS tube PM4; the source of the high-voltage PMOS tube PM3 is connected to the input I4 terminal, and the high-voltage The drain of the high-voltage PMOS tube PM3 is connected to the source of the low-voltage PMOS tube PM5; the source of the high-voltage PMOS tube PM11 is connected to the input I7 terminal, the drain of the high-voltage PMOS tube PM11 is connected to the gate of the high-voltage NMOS tube NM10, the cathode of the diode DZ3, and the cathode of the diode DZ1; the source of the high-voltage PMOS tube PM12 is connected to the input I8 terminal, the drain of the high-voltage PMOS tube PM12 is connected to the anode of the diode DZ1, the gate of the high-voltage NMOS tube NM9, the cathode of the diode DZ4, the drain of the low-voltage NMOS tube NM13, and the cathode of the diode DZ2; the The gate is connected to the gate of the low-voltage PMOS tube PM5, the drain of the low-voltage PMOS tube PM5, the gate of the low-voltage NMOS tube NM7, the drain of the low-voltage NMOS tube NM7, and the gate of the low-voltage NMOS tube NM6; the source of the high-voltage NMOS tube NM10 is connected to the anode of the diode DZ3 and the drain of the high-voltage NMOS tube NM9; the drain of the low-voltage PMOS tube PM4 is connected to the drain of the low-voltage NMOS tube NM6 and the gate of the low-voltage NMOS tube NM8; the drain of the low-voltage NMOS tube NM8 is connected to the gate of the low-voltage NMOS tube NM13, the anode of the diode DZ4, and the source of the high-voltage NMOS tube NM9. The source of the low-voltage NMOS tube NM13 is connected to the anode of the diode DZ2 and the source of the high-voltage PMOS tube PM14; the source of the low-voltage NMOS tube NM6 is connected to the collector of the transistor NPN1; the source of the low-voltage NMOS tube NM7 is connected to the base of the transistor NPN2, the collector of the transistor NPN2, and the base of the transistor NPN1; the emitter of the transistor NPN2 is connected to one end of the resistor R3; one end of the resistor R2 and one end of the resistor R1, and the gate of the high-voltage PMOS tube PM14 are connected to the TIP_RING end; the drain end of the high-voltage PMOS tube PM14 is connected to the VBAT end.

3. The high voltage driving circuit for a subscriber line interface circuit according to claim 1, characterized in that: The lower driving circuit I22 includes: a high-voltage PMOS tube PM15, a high-voltage PMOS tube PM16, a high-voltage PMOS tube PM17, a high-voltage PMOS tube PM18, a high-voltage PMOS tube PM19, a high-voltage PMOS tube PM20, a high-voltage PMOS tube PM21, and a high-voltage PMOS tube PM27; a high-voltage NMOS tube NM25, a high-voltage NMOS tube NM26; a low-voltage NMOS tube NM22, a low-voltage NMOS tube NM23, a low-voltage NMOS tube NM24, and a low-voltage NMOS tube NM28; a transistor NPN3, a transistor NPN4; a diode DZ5, a diode DZ6, a diode DZ7, and a diode DZ8; a resistor R4, a resistor R5, and a resistor R6; The gates of the high-voltage PMOS tube PM15, the high-voltage PMOS tube PM16, the high-voltage PMOS tube PM17, the high-voltage PMOS tube PM18, and the high-voltage PMOS tube PM19 are all grounded; the drain of the high-voltage NMOS tube NM26 is connected to the TIP_RING terminal; the source of the high-voltage PMOS tube PM15 is connected to the input I2 terminal, the drain of the high-voltage PMOS tube PM15 is connected to the emitter of the transistor NPN3, and one end of the resistor R5; the source of the high-voltage PMOS tube PM16 is connected to the input I5 terminal, the drain of the high-voltage PMOS tube PM16 is connected to the source of the high-voltage PMOS tube PM20; The source of high-voltage PMOS tube PM7 is connected to the input I6 terminal, the drain of high-voltage PMOS tube PM17 is connected to the source of high-voltage PMOS tube PM21; the source of high-voltage PMOS tube PM18 is connected to the input I9 terminal, the drain of high-voltage PMOS tube PM18 is connected to the gate of high-voltage NMOS tube NM26, the cathode of diode DZ5, and the cathode of diode DZ7; the source of high-voltage PMOS tube PM19 is connected to the input I10 terminal, the drain of high-voltage PMOS tube PM19 is connected to the anode of diode DZ5, the gate of high-voltage NMOS tube NM25, the cathode of diode DZ6, the drain of low-voltage NMOS tube NM28, and the cathode of diode DZ8; The gate of the high-voltage PMOS tube PM20 is connected to the gate of the high-voltage PMOS tube PM21, the drain of the high-voltage PMOS tube PM21, the gate of the low-voltage NMOS tube NM23, the drain of the low-voltage NMOS tube NM23, and the gate of the low-voltage NMOS tube NM22; the source of the high-voltage NMOS tube NM26 is connected to the anode of the diode DZ7 and the drain of the high-voltage NMOS tube NM25; the drain of the high-voltage PMOS tube PM20 is connected to the drain of the low-voltage NMOS tube NM22 and the gate of the low-voltage NMOS tube NM24; the drain of the low-voltage NMOS tube NM24 is connected to the gate of the low-voltage NMOS tube NM28, the anode of the diode DZ8 The anode of the low-voltage NMOS tube NM28 is connected to the anode of the diode DZ6 and the source of the high-voltage PMOS tube PM27; the source of the low-voltage NMOS tube NM22 is connected to the collector of the transistor NPN3; the source of the low-voltage NMOS tube NM23 is connected to the base of the transistor NPN4, the collector of the transistor NPN4, and the base of the transistor NPN3; the emitter of the transistor NPN3 is connected to one end of the resistor R5; one end of the resistor R5 and one end of the resistor R4, the gate of the high-voltage PMOS tube PM27, and the drain of the high-voltage PMOS tube PM27 are connected to the VBAT terminal.

4. The high voltage driving circuit for a subscriber line interface circuit according to claim 1, characterized in that: The amplifier in the upper driving circuit I11 is formed by connecting transistor NPN1, transistor NPN2, NMOS tube low voltage NMOS tube NM6, low voltage NMOS tube NM7 into a sleeve input structure, and connecting high voltage PMOS tube PM2, high voltage PMOS tube PM3, low voltage PMOS tube PM4, low voltage PMOS tube PM5 into a sleeve load; bias current is provided by input terminals I3 and I4. The output of the amplifier controls the gate of the low voltage NMOS tube NM8 of the adjustment tube and forms a negative feedback structure through resistors R1, R2, and R3; the differential pair input introduces a resistor network composed of resistors R1, R2, and R3, which forms a linear transconductance loop with the differential pair transistors NPN1 and NPN2.

5. The high voltage driving circuit for a subscriber line interface circuit according to claim 1, characterized in that: In the upper driving circuit I11, the current provided by the input terminal I1 is applied to the connection between the emitter of the transistor NPN1 and the resistor R2 through the high-voltage PMOS tube PM1, and the CASCODE combination composed of the adjustment tube low-voltage NMOS tube NM8, high-voltage NMOS tube NM9, and high-voltage NMOS tube NM10 controlled by the output of the differential amplifier is output to the connection between the resistor R1 and the resistor R3, and its output current Iout1 is: Iout1=[(I1+I3)*R2-I4*(R1+R3)] / R1 (1) Among them, I3 = I4, and its value is much smaller than I1; Let R2 = a*R1; R3 = (a-1)*R1; Simplifying formula (1) we get: Iout1={(I1+I3)*a*R1-I4*[(a-1)*R1+R1]} / R1=a*I1 (2) Ignoring I3 and I4, the current output from the upper drive circuit to TIP_RING is: TIP_RING1=(1+a)*I1 (3).

6. The high voltage driving circuit for a subscriber line interface circuit according to claim 5, characterized in that: In the lower driving circuit I22, the input terminal I2 provides current which is applied to the connection between the emitter of NPN3 and the resistor R5 through the high-voltage PMOS tube PM15, and the CASCODE combination composed of the adjustment tubes NM24, NM25, and NM26 controlled by the differential amplifier output is output to the connection between the resistor R6 and the resistor R4, and its output current Iout2 is: Iout2=[(I2+I5)*R5-I6*(R6+R4)] / R4 (4) Among them, I5=I6, and its value is much smaller than I2; Let R5 = b*R4; R6 = (b-1)*R4; Simplifying formula (4) yields: Iout2={(I2+I5)*b*R4-I6*[(b-1)*R4+R4]} / R4=b*I2 (5) The current output from the lower drive circuit to TIP_RING is: TIP_RING2=b*I2 (6).

7. The high voltage driving circuit for a subscriber line interface circuit according to claim 6, characterized in that: I1=I2, b=a+1, the push-pull output current from the upper driving circuit I11 to TIP_RING is equal to the push-pull output current from the lower driving circuit I22 to TIP_RING.

8. A high voltage driving system for a subscriber line interface circuit, characterized in that: The invention comprises two groups of high-voltage driving circuits of the user line interface circuit as described in any one of claims 1 to 7, wherein the two groups of high-voltage driving circuits of the user line interface circuit form a bridge drive, and the push and pull circuits in the high-voltage driving circuit of the user line interface circuit adopt time-sharing operation.

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