Successive approximation register analog-to-digital converter with programmable sampling noise cancellation

Abstract

An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC), a comparator coupled to an output of the DAC, a successive approximation register (SAR) logic unit coupled to an output of the comparator, and a programmable delay unit. The comparator includes: a preamplifier having an input coupled to the output of the DAC; and a latch having an input coupled to an output of the preamplifier and an output coupled to an input of the SAR logic unit. An SAR logic unit generates a control signal, and a programmable delay unit adjusts a delay between the control signal and a delayed control signal based on at least one parameter such that a comparator receives the control signal and the delayed control signal. In some embodiments, the parameter is at least one of a frequency of a signal input to the DAC, a source impedance of a circuit driving the input signal, and a preamplifier power mode.

Description

Technical Field

[0001] The present invention relates to a successive approximation register analog-to-digital converter with programmable sampling noise cancellation. Background Art

[0002] Some successive approximation register (SAR) analog / digital converters use a fixed delay across a preamplifier included in a comparator to reduce sampling noise. During this delay, sampling noise and errors from the DAC are increased and stored at the output of the preamplifier. The residual error from the delayed sample at the preamplifier output is reduced by the preamplifier gain. However, the use of a fixed delay only reduces sampling noise in narrow use cases with a predetermined input signal frequency and preamplifier bandwidth. For example, a fixed delay is selected based on the expected input signal frequency, and sampling noise cannot be reduced for an input signal with a frequency twice the expected input signal frequency. In addition, a fixed delay cannot reduce sampling noise for an input signal with an expected input signal frequency but driven by a circuit with a higher impedance than expected. In addition, a long delay time reduces bandwidth requirements and the power of the preamplifier, but may cause the preamplifier to saturate. A short delay time reduces the possibility of saturation of the preamplifier, but increases bandwidth requirements and the power used by the preamplifier. Therefore, an improved technique for reducing sampling noise is needed. Summary of the invention

[0003] An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC), a comparator coupled to the output of the DAC, a successive approximation register (SAR) logic unit coupled to the output of the comparator, and a programmable delay unit. The comparator includes a preamplifier and a latch. The input of the preamplifier is coupled to the output of the DAC, and the input of the latch is coupled to the output of the preamplifier. The SAR logic unit is coupled to the input of the latch and is configured to generate a control signal for the comparator. The programmable delay unit is configured to delay the control signal so that the comparator receives the control signal and the delayed control signal. The programmable delay unit is configured to adjust the delay between the control signal and the delayed control signal based on at least one parameter.

[0004] In some embodiments, the ADC further comprises a first switch and a second switch. The first switch has a first end coupled to the input of the preamplifier and a second end coupled to the first common-mode voltage supply rail, and is configured to open and close based on a control signal. The second switch has a third end coupled to the input of the latch and a fourth end coupled to the second common-mode voltage supply rail, and is configured to open and close based on a delayed control signal. In some embodiments, the first common-mode voltage supply rail and the second common-mode voltage supply rail provide different common-mode voltages. In other embodiments, the first common-mode voltage supply rail and the second common-mode voltage supply rail provide the same common-mode voltage.

[0005] In some embodiments, the at least one parameter includes at least one of the following: a frequency of an input signal provided to the DAC, a source impedance of a circuit driving the input signal provided to the DAC, a power mode of a preamplifier, a clock frequency of the ADC, a sampling time of the ADC, a resolution mode of the ADC, and an oversampling ratio of the ADC. In some embodiments, the at least one parameter is input by a user.

[0006] In some embodiments, the programmable delay unit is configured to implement a first delay between the control signal and the delayed control signal for a first input signal provided to the DAC, and implement a second delay between the control signal and the delayed control signal for a second input signal. In some embodiments, the programmable delay unit includes at least one of an analog delay unit and a digital delay unit. The at least one of the analog delay unit and the digital delay unit enables a desired delay resolution of the programmable delay unit. In some embodiments, the programmable delay unit is configured to reduce the delay between the control signal and the delayed control signal in response to a source impedance of a circuit driving the input signal provided to the DAC being greater than a predetermined threshold, so that the control signal and the delayed control signal are substantially the same.

[0007] An apparatus includes a comparator and a programmable delay unit. The comparator includes a preamplifier and a latch. The input of the preamplifier is configured to receive an input signal, and the input of the latch is coupled to the output of the preamplifier. The programmable delay unit is configured to delay a control signal for the comparator so that the comparator receives the control signal and the delayed control signal. The programmable delay unit is configured to adjust the delay between the control signal and the delayed control signal based on at least one parameter.

[0008] In some embodiments, the device further comprises a first switch and a second switch. The first switch has a first end coupled to the input of the preamplifier and a second end coupled to the first common-mode voltage supply rail, and is configured to open and close based on a control signal. The second switch has a third end coupled to the input of the latch and a fourth end coupled to the second common-mode voltage supply rail, and is configured to open and close based on a delayed control signal. In some embodiments, the first common-mode voltage supply rail and the second common-mode voltage supply rail provide different common-mode voltages. In other embodiments, the first common-mode voltage supply rail and the second common-mode voltage supply rail provide the same common-mode voltage.

[0009] In some embodiments, the at least one parameter includes at least one of the following: frequency of the input signal, source impedance of the circuit driving the input signal, power mode of the preamplifier, clock frequency of the device, sampling time, resolution mode, and oversampling ratio. In some embodiments, the at least one parameter is input by a user.

[0010] In some embodiments, the programmable delay cell is configured to implement a first delay between the control signal and the delayed control signal for a first input signal, and implement a second delay between the control signal and the delayed control signal for a second input signal. In some embodiments, the programmable delay cell includes at least one of an analog delay cell and a digital delay cell. The at least one of the analog delay cell and the digital delay cell enables a desired delay resolution of the programmable delay cell. In some embodiments, the programmable delay cell is configured to reduce the delay between the control signal and the delayed control signal in response to a source impedance of a circuit driving the input signal being greater than a predetermined threshold, so that the control signal and the delayed control signal are substantially the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0012] Figure 1 An example analog-to-digital converter (ADC) system is shown in block diagram form in accordance with one embodiment.

[0013] Figure 2 An example ADC system with programmable delay to reduce sampling noise is shown in block diagram form according to one embodiment.

[0014] Figure 3 A graph showing ADC conversion error versus delay according to one embodiment is shown.

[0015] Unless otherwise indicated, the same reference numerals are used in different drawings to indicate the same items. The drawings are not necessarily drawn to scale. DETAILED DESCRIPTION

[0016] As discussed previously herein, some techniques for reducing sampling noise in SAR ADCs use a fixed delay across a preamplifier included in a comparator, and thus reduce sampling noise in certain narrow use cases with only a predetermined input signal frequency and preamplifier bandwidth. The disclosed techniques for implementing a programmable delay across the preamplifier allow the SAR ADC to reduce sampling noise while accommodating a range of input source impedances, signal frequencies, and power constraints. Furthermore, a general-purpose SAR ADC used in a variety of applications can adjust the programmable delay based on current operating parameters to reduce sampling noise across a range of use cases.

[0017] Figure 1 An example analog-to-digital converter (ADC) system 100 according to one embodiment is shown in block diagram form. The ADC system 100 includes a digital-to-analog converter (DAC) 110, a comparator 140, and a successive approximation register (SAR) logic unit 170. In some embodiments, the comparator 140 includes a preamplifier 145 and a latch 150. The ADC system 100 converts an analog input voltage Vin 105 to a corresponding binary value. In one embodiment of the present invention, the ADC system 100 is a single-ended SAR ADC. In one embodiment of the present invention, the ADC system 100 has a resolution of n bits, where 'n' is a positive integer greater than 1.

[0018] DAC 110 receives input voltage Vin 105, DAC control signal DAC_CTL 180, high reference voltage VREFH 115 and low reference voltage VREFL 120. High reference voltage VREFH 115 has a value greater than low reference voltage VREFL 120. A first output of DAC 110 is coupled to a positive input of a preamplifier 145 in comparator 140, and a second output of DAC 110 is coupled to a negative input of preamplifier 145. A positive input of preamplifier 145 is coupled to a first end of switch S130, and a negative input of preamplifier 145 is coupled to a first end of switch S135. Second ends of switches S130 and 135 are configured to receive common mode voltage VCM 125. Switches S130 and 135 are configured to be opened and closed based on sampling control signal SMP 175 provided by SAR logic unit 170.

[0019] A first output of the preamplifier 145 is coupled to a positive input of a latch 150, and a second output of the preamplifier 145 is coupled to a negative input of the latch 150. The latch 150 also receives a control signal LATCH 185 provided by the SAR logic unit 170. The output 160 of the latch 150 and the comparator 140 are provided to the SAR logic unit 170, which also receives a clock signal CLK 165. The SAR logic unit 170 generates a DAC control signal DAC_CTL 180 for the DAC 110, a sampling control signal SMP 175 for the switches S130 and 135, and a latch control signal LATCH 185 for the latch 150.

[0020] Preamplifier 145 uses techniques such as auto-zeroing, for example, to reduce non-idealities introduced by latch 150, such as offset, noise, and voltage kickback to DAC 110. Sampled kT / C noise may be reduced at least in part by introducing delay into comparator 140, as described herein with respect to Figure 2 Further description. Figure 2 An example ADC system 200 with programmable delay to reduce sampling noise according to one embodiment is shown in block diagram form. Figure 1 100, such that like numbers refer to like components. In addition, for simplicity, the SAR logic unit 170 is omitted from the diagram of the ADC system 200. The ADC system 200 includes the components of the ADC system 100, as well as a resistor R 210 representing the source impedance of the drive circuit system for the input signal Vin 105, capacitors C 230 and 235, switches S 240 and 245, and a programmable delay unit 250. The input signal Vin 105 is provided to a first end of the resistor R 210, and a second end of the resistor R 210 is coupled to the DAC 110.

[0021] A first output of the DAC 110 is represented as VP 215 and is coupled to a positive input of a preamplifier 145 in the comparator 140, and a second output of the DAC 110 is represented as VM 220 and is coupled to a negative input of the preamplifier 145. A first output of the preamplifier 145 is coupled to a first end of a capacitor C 230, and a second output of the preamplifier 145 is coupled to a first end of a capacitor C 235. A second end of the capacitor C 230 is coupled to a positive input of a latch 150, and a second end of the capacitor C 235 is coupled to a negative input of the latch 150.

[0022] The positive input of latch 150 is coupled to a first end of switch S240, and the negative input of latch 150 is coupled to a first end of switch S245. The second ends of switches S240 and 245 are configured to receive a common mode voltage VCM 125. In this example, the same common mode voltage VCM 125 is used for sampling switches S130 and 135 and latch input switches S240 and 245, but in other embodiments, different common mode voltages may be used. Switches S240 and 245 are configured to open and close based on a delayed sampling control signal SMP_DELAY 270 provided by a programmable delay unit 250. Programmable delay unit 250 generates a delayed sampling control signal SMP_DELAY 270 based on a sampling control signal SMP 175 provided by SAR logic unit 170.

[0023] The following techniques may be used to reduce the sampling noise of the ADC system 200. During the sampling phase, for example, when the sampling control signal SMP 175 is logic high, the sampling switches S130 and 135 are closed to sample the input voltage VIN105 at the input of the DAC 110. The offset voltage of the preamplifier 145 is increased by the gain A of the preamplifier 145 and stored on the capacitors C230 and 235. At the end of the sampling phase, for example, at the falling edge of the sampling control signal SMP 175, the sampling switches S130 and 135 are opened, thereby disconnecting the positive and negative inputs of the preamplifier 145 from the common mode voltage VCM 125. The sampling error Vse is introduced from kT / C noise, charge injection, and clock feedthrough as a differential voltage between Vp 215 and Vm 220. The sampled error Vse is amplified by the gain A of the preamplifier 145 and is stored on capacitors C 230 and 235 along with the preamplifier offset voltage.

[0024] At the end of the delayed sampling phase, for example, at the falling edge of the delayed sampling control signal SMP_DELAY 270, the latch input switches S240 and 245 are opened, thereby disconnecting the positive and negative inputs of the latch 150 from the common mode voltage VCM 125. The amplified sampling error AVse, the preamplifier offset voltage, and the change in the delay between Vin 105 relative to the falling edge of the sampling control signal SMP175 and the falling edge of the delayed sampling control signal SMP_DELAY 270 are stored on capacitors C 230 and 235, thereby creating a new sampling error Vse2 from the kt / C noise of C 230 and C 235 and the charge injection and clock feedthrough from switches S240 and S245. This new sampling error Vse2 attenuates the gain A of the preamplifier 145 when it is traced back to VP 215 and VM 220. After being processed by the SAR logic unit 170 and ignoring quantization errors, the ADC output code is approximately equal to the value of the input voltage signal Vin 105 at the falling edge of the delayed sampling control signal SMP_DELAY 270 plus the second sampling error Vse2 divided by the gain A of the preamplifier 145. The sampling error Vse is cancelled, and the second sampling error Vse2 is divided by the gain A of the preamplifier 145. For a gain A of five and assuming infinite preamplifier bandwidth, the second sampling error Vse2 is reduced by approximately 80%. The new sampling time for the input voltage Vin 105 is at the falling edge of the delayed sampling control signal SMP_DELAY 270, rather than the falling edge of the sampling control signal SMP 175.

[0025] The tradeoff in eliminating sampling errors using this particular technique is the delay between the falling edge of the sampling control signal SMP 175 and the falling edge of the delayed sampling control signal SMP_DELAY 270 compared to the bandwidth of the preamplifier 145. In order to completely eliminate the sampling error Vse, either a long delay time or a very high preamplifier bandwidth is required. A long delay time may result in preamplifier saturation due to the change in the value of Vin 105 during the delay period, and a high preamplifier bandwidth may result in high power consumption. The tradeoff between a fixed delay and the bandwidth of the preamplifier 145 can be optimized for a specific implementation and a known constant input frequency, but the delay time can be varied to accommodate different input frequencies and source resistance Rs 210.

[0026] For example, the programmable delay unit 250 may adjust the delay between the falling edge of the sampling control signal SMP 175 and the falling edge of the delayed sampling control signal SMP_DELAY 270 based on the control signal CTL_DELAY 260 that may be provided by the controller. The delay between the falling edge of the sampling control signal SMP 175 and the falling edge of the delayed sampling control signal SMP_DELAY 270 may be selected based on the sampling frequency, the source resistance Rs 210, the power mode of the ADC system 200, and other ADC control settings of the ADC system 200 such as the clock frequency of the clock signal CLK 165, the sampling time, the resolution mode, the oversampling ratio, etc.

[0027] For example, the delay may be selected based on the sampling frequency and the assumption that the maximum input frequency of the input signal Vin105 is approximately half the sampling frequency. As another example, the user may provide the maximum input frequency of the input signal Vin105 and / or the source resistance R210 based on the specific implementation. In response to the source resistance R210 being greater than the threshold resistance, the programmable delay unit 250 may set a longer multi-cycle delay or disable the delay entirely. The threshold resistance may be selected as a resistance that causes the settling time to be high enough that an ADC conversion error occurs.

[0028] The programmable delay cell 250 may be any suitable delay cell or combination of delay cells that achieves the desired delay resolution of a particular implementation. For example, the programmable delay cell 250 may be an analog delay cell, such as a fixed current that charges a programmable capacitor followed by a Schmitt trigger or comparator; a programmable current that charges a fixed capacitor followed by a Schmitt trigger or comparator; a programmable logic delay stage that can be calibrated with a reference clock; or a combination thereof. Alternatively, the programmable delay cell 250 may be a digital delay cell, such as a programmable number of clock cycles or half cycles. As another alternative, the programmable delay cell 250 may be a combination of analog and digital delay cells.

[0029] Figure 3A graphical representation 300 of ADC conversion error versus delay is shown according to one embodiment. The graphical representation 300 shows a number of sampling errors ranging from zero millivolts (mV) or no error to 43.9 mV, and the corresponding ADC conversion error versus delay. The graph 300 is based on a value of Rs 210 of 1 kilo-ohm (kΩ). The shape of these conversion error curves will vary for different values ​​of Rs 210 and other factors such as preamplifier bandwidth. ADC conversion errors are measured in the number of least significant bits (LSBs). An LSB is defined as the difference between the high reference voltage VREFH 115 and the low reference voltage VREFL 120 divided by 2 to the power of n, where n is the number of bits in the ADC. With sufficiently long delays and settling times, all values ​​of the sampling error approach zero conversion error. However, an erroneous delay time may introduce errors. For example, a zero mV sampling error corresponds to a conversion error of approximately 90 LSBs at a 2 nanosecond delay, rather than the expected zero conversion error. The programmable delay enabled by the programmable delay unit 250 in the ADC system 200 allows the delay to be varied for a particular implementation and Rs 210 value and reduces the likelihood of error or the likelihood of erroneously increasing error.

[0030] As described herein, the disclosed techniques for implementing programmable delays allow a SAR ADC to reduce sampling noise while accommodating a range of input source impedances, signal frequencies, and power constraints. For example, the programmable delay allows the SAR ADC to reduce sampling noise for a specific input signal frequency and source impedance of the input signal driving circuitry while also reducing the power used by the preamplifier. Furthermore, a general-purpose SAR ADC used in a variety of applications can be adjusted based on current operating parameters to reduce sampling noise across a range of use cases.

[0031] Features specifically shown or described with respect to one embodiment set forth herein may be implemented in other embodiments set forth herein.

[0032] In this specification, the term "coupling" may encompass the connection, connectivity or signal path that implements a functional relationship according to this specification, including intermediate or intervening components that do not change the functional relationship. The device "configured to" perform a task or function may be configured by programming or hard wiring, for example, when the manufacturer manufactures, and / or the device may be configured or reconfigured by the user after manufacturing. The configuration may be performed by firmware and / or software, hardware components and the construction and / or layout of the connection or any combination thereof. As used herein, "node", "pin" and "lead" are used interchangeably. A circuit or device described herein as including certain components may actually be suitable for coupling to those components to form the described circuit system or device.

[0033] While particular embodiments of the present invention have been shown and described, those skilled in the art will recognize that, based on the teachings herein, further changes and modifications may be made without departing from the present invention and its broader aspects, and therefore, the appended claims are intended to cover within their scope all such changes and modifications that are within the true spirit and scope of the present invention.

Claims

1. An analog-to-digital converter ADC, characterized in that: include: Digital / analog converter DAC; a comparator coupled to the output of the DAC, the comparator comprising a preamplifier and a latch, wherein an input of the preamplifier is coupled to the output of the DAC and an input of the latch is coupled to the output of the preamplifier; a successive approximation register (SAR) logic unit coupled to the output of the latch and configured to generate a control signal for the comparator; as well as A programmable delay unit is configured to delay the control signal so that the comparator receives the control signal and the delayed control signal, wherein the programmable delay unit is configured to adjust a delay between the control signal and the delayed control signal based on at least one parameter.

2. The ADC according to claim 1, characterized in that Also includes: a first switch having a first end coupled to the input of the preamplifier and a second end coupled to a first common-mode voltage supply rail, wherein the first switch is configured to open and close based on the control signal; as well as A second switch has a third terminal coupled to the input of the latch and a fourth terminal coupled to a second common mode voltage supply rail, wherein the second switch is configured to open and close based on the delayed control signal.

3. The ADC according to claim 1, characterized in that The at least one parameter includes at least one of: a frequency of an input signal provided to the DAC, a source impedance of a circuit driving the input signal provided to the DAC, a power mode of the preamplifier, a clock frequency of the ADC, a sampling time of the ADC, a resolution mode of the ADC, and an oversampling ratio of the ADC.

4. The ADC according to claim 1, characterized in that The programmable delay unit is configured to implement a first delay between the control signal and the delayed control signal for a first input signal provided to the DAC, and to implement a second delay between the control signal and the delayed control signal for a second input signal.

5. The ADC according to claim 1, characterized in that The programmable delay cell includes at least one of an analog delay cell and a digital delay cell, wherein the at least one of the analog delay cell and the digital delay cell enables a desired delay resolution for the programmable delay cell.

6. The ADC according to claim 1, characterized in that: The programmable delay unit is configured to reduce the delay between the control signal and the delayed control signal so that the control signal and the delayed control signal are substantially the same in response to a source impedance of a circuit driving the input signal provided to the DAC being greater than a predetermined threshold.

7. A device, characterized in that: include: a comparator comprising a preamplifier and a latch, wherein an input of the preamplifier is configured to receive an input signal and an input of the latch is coupled to an output of the preamplifier; as well as A programmable delay unit is configured to delay a control signal for the comparator so that the comparator receives the control signal and the delayed control signal, wherein the programmable delay unit is configured to adjust a delay between the control signal and the delayed control signal based on at least one parameter.

8. The device according to claim 7, characterized in that Also includes: a first switch having a first end coupled to the input of the preamplifier and a second end coupled to a first common-mode voltage supply rail, wherein the first switch is configured to open and close based on the control signal; as well as A second switch has a third terminal coupled to the input of the latch and a fourth terminal coupled to a second common mode voltage supply rail, wherein the second switch is configured to open and close based on the delayed control signal.

9. The device according to claim 7, characterized in that The programmable delay unit is configured to implement a first delay between the control signal and the delayed control signal for a first input signal and to implement a second delay between the control signal and the delayed control signal for a second input signal.

10. The device according to claim 7, characterized in that The programmable delay cell includes at least one of an analog delay cell and a digital delay cell, wherein the at least one of the analog delay cell and the digital delay cell enables a desired delay resolution for the programmable delay cell.

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