Semiconductor device
By forming the first and second regions of macroscopic sparse structure on the semiconductor substrate, and forming active trenches and control gate trenches in the trenches of the first region, the problem of failure in the prior art cannot be sufficiently reduced, and a more efficient loss reduction and on-speed are achieved.
Patent Information
- Application Number
- CN202410277944.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-23
- Filing Date
- 2024-03-12
- Publication Date
- 2025-02-28
AI Technical Summary
The existing semiconductor devices with macroscopic sparse structure cannot fully reduce losses under multi-gate drive.
By forming the first and second regions of the macroscopic sparse structure on the semiconductor substrate, active trenches and control gate trenches are formed in the trenches of the first region, and the gate electrodes of the control gate trenches are shut down early when off, so that holes are discharged through the sides of the control gate trenches.
It is possible to fully reduce losses, especially turn-off losses under multi-gate drive, while improving the on-off speed and efficiency.
Smart Images
Figure CN119545821A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device. Background Art
[0002] A semiconductor device has been proposed that reduces turn-on loss by using a macroscopic sparse structure in which a first region where three or more active trenches are arranged and a second region where a plurality of dummy trenches are arranged are alternately provided (for example, see Patent Document 1).
[0003] Patent Document 1: Patent Publication No. 6743026
[0004] Since multi-gate driving is not considered in conventional semiconductor devices with macroscopic sparse structures, there is a problem that the loss cannot be reduced sufficiently. Summary of the invention
[0005] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to obtain a semiconductor device capable of sufficiently reducing loss.
[0006] The semiconductor device disclosed herein is characterized in that it comprises: a semiconductor substrate of a first conductivity type having a first region and a second region adjacent to each other; a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; a source layer of a first conductivity type formed on the upper surface side of the base layer; a plurality of gate electrodes formed in a plurality of trenches penetrating the source layer and the base layer from the upper surface side of the semiconductor substrate via a gate insulating film; an emitter electrode formed on the upper surface of the semiconductor substrate; a collector layer of a second conductivity type formed on the lower surface side of the semiconductor substrate; and a collector electrode formed on the lower surface of the semiconductor substrate, wherein the trench in the first region comprises a first trench and two or more second trenches sandwiching the first trench from both sides, the gate electrodes formed in the two or more second trenches are connected to each other and are not connected to the gate electrode formed in the first trench, the gate electrode formed in the trench in the second region is connected to the emitter electrode, and the base layer is connected to the emitter electrode in a region sandwiched by the first region and the second region.
[0007] In the present disclosure, two or more second trenches are formed in a first region of a macroscopic sparse structure in a manner of sandwiching the first trench from both sides. The gate electrodes of the two or more second trenches are connected to each other and are not connected to the gate electrode of the first trench. In addition, the base layer is connected to the emitter electrode in the region sandwiched by the first region and the second region. For example, when shutting down, the gate electrode of the second trench is shut down earlier than the gate electrode of the first trench, so that holes flowing from the bottom of the second region to the bottom of the first region can be discharged to the emitter electrode through the side of the second trench, thereby reducing the shutdown loss. As a result, the loss can be sufficiently reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.
[0009] Figure 2 This is a diagram showing the driving of the semiconductor device according to the first embodiment.
[0010] Figure 3 This is a cross-sectional view showing Modification 1 of the semiconductor device according to the first embodiment.
[0011] Figure 4 This is a cross-sectional view showing a second modification of the semiconductor device according to the first embodiment.
[0012] Figure 5 This is a cross-sectional view showing a third modification of the semiconductor device according to the first embodiment.
[0013] Figure 6 This is a cross-sectional view showing a fourth modification of the semiconductor device according to the first embodiment.
[0014] Figure 7 It is a cross-sectional view showing a semiconductor device according to a second embodiment.
[0015] Figure 8 This is a cross-sectional view showing a modification of the semiconductor device according to the second embodiment.
[0016] Fig. 9 It is a cross-sectional view showing a semiconductor device according to a third embodiment.
[0017] Fig.10 It is a cross-sectional view showing a first modification of the semiconductor device according to the third embodiment.
[0018] Fig.11 It is a cross-sectional view showing a second modification of the semiconductor device according to the third embodiment.
[0019] Fig.12 This is a cross-sectional view showing a third modification of the semiconductor device according to the third embodiment.
[0020] Fig.13 It is a cross-sectional view showing a fourth modification of the semiconductor device according to the third embodiment.
[0021] Fig.14 It is a cross-sectional view showing a fifth modification of the semiconductor device according to the third embodiment.
[0022] Fig.15 It is a cross-sectional view showing a semiconductor device according to a fourth embodiment.
[0023] Fig.16 This is a cross-sectional view showing a modified example of the semiconductor device according to the fourth embodiment.
[0024] Fig.17 It is a cross-sectional view showing a semiconductor device according to a fifth embodiment.
[0025] Fig.18 This is a cross-sectional view showing a modified example of the semiconductor device according to the fifth embodiment.
[0026] Description of reference numerals: 1... semiconductor substrate; 1a... first region; 1b... second region; 1c... third region; 2... n-type carrier accumulation layer; 3... p-type base layer; 4... n-type carrier accumulation layer; 5... p-type base layer; 6... n-type carrier accumulation layer; 7... p-type base layer; 8... n-type carrier accumulation layer; 9... n-type carrier accumulation layer; 10... n-type carrier accumulation layer; 11... + type source layer; 5... trench; 5a... active trench; 5b... control gate trench; 6... gate insulating film; 7... gate electrode; 9... emitter electrode; 11... p-type collector layer; 12... collector; 13... control unit. DETAILED DESCRIPTION
[0027] The semiconductor device according to the embodiment will be described with reference to the drawings. The same reference numerals are given to the same or corresponding components, and duplicate description may be omitted.
[0028] In the following description, n and p represent the conductivity type of the semiconductor. The first conductivity type is described as n-type and the second conductivity type is described as p-type. However, the first conductivity type may be described as p-type and the second conductivity type may be described as n-type. － Indicates that the impurity concentration is lower than n, n + Indicates that the impurity concentration is higher than n. Similarly, p + It indicates that the impurity concentration is a higher concentration than p. In addition, the features of the semiconductor device of each embodiment may be appropriately combined to enhance the effect of the present invention.
[0029] Implementation method 1.
[0030] Figure 11 is a cross-sectional view showing a semiconductor device according to Embodiment 1. The semiconductor device is an insulated gate bipolar transistor (hereinafter referred to as IGBT).
[0031] The semiconductor substrate 1 constitutes n － The n-type impurity of the semiconductor substrate 1 is, for example, arsenic or phosphorus. The concentration of the n-type impurity of the semiconductor substrate 1 is 1.0E+12 / cm 3 ~1.0E+15 / cm 3 The semiconductor substrate 1 has a first region 1 a and a second region 1 b adjacent to each other.
[0032] The n-type carrier storage layer 2 is formed on the n-type surface of the semiconductor substrate 1. － The n-type impurity of the n-type carrier storage layer 2 is, for example, arsenic or phosphorus. The concentration of the n-type impurity of the n-type carrier storage layer 2 is 1.0E+13 / cm 3 ~1.0E+17 / cm 3 By forming the n-type carrier storage layer 2, the conduction loss when the current flows can be reduced. Alternatively, the n-type carrier storage layer 2 may not be formed, and an n-type carrier storage layer 2 may be provided in the region of the n-type carrier storage layer 2. － The structure of the n-type drift layer can also be － This type of drift layer is collectively called the drift layer.
[0033] The p-type base layer 3 is formed on the upper surface side of the n-type carrier storage layer 2. That is, the n-type carrier storage layer 2 is formed below the p-type base layer 3. The p-type impurities of the p-type base layer 3 are, for example, boron or aluminum. The impurity concentration of the p-type base layer 3 is 1.0E+12 / cm 3 ~1.0E+19 / cm 3 .n + The p-type source layer 4 is formed on the upper surface side of the p-type base layer 3. + The n-type impurity of the n-type source layer 4 is, for example, arsenic or phosphorus. + The impurity concentration of the source layer 4 is 1.0E+17 / cm 3 ~1.0E+20 / cm 3 .
[0034] A plurality of trenches 5 are formed so as to penetrate the semiconductor substrate 1 from the upper surface side thereof. + The p-type source layer 4, the p-type base layer 3 and the n-type carrier storage layer 2 reach the n-type － A gate insulating film 6 is formed along the inner wall of the trench 5. A plurality of gate electrodes 7 are formed inside the plurality of trenches 5 via the gate insulating film 6. The gate electrodes 7 are connected to the n +type source layer 4, p-type base layer 3, n-type carrier storage layer 2 and n － type drift layer opposite.
[0035] Along the extending direction of the trench 5, n + Type source layer 4 and p + Type contact layer (not shown). + Type source layer 4 and p + The p-type contact layer constitutes the upper surface of the semiconductor substrate 1. + The p-type impurity of the p-type contact layer is, for example, boron or aluminum. + The concentration of p-type impurities in the p-type contact layer is higher than that in the p-type base layer 3, which is 1.0E+15 / cm 3 ~1.0E+20 / cm 3 . When it is necessary to distinguish between + In the case of the p-type contact layer and the p-type base layer 3, they may be referred to separately, or the p + The p-type contact layer and the p-type base layer 3 are collectively referred to as a p-type base layer.
[0036] An interlayer insulating film 8 is formed on the trench 5. Although not shown, a barrier metal is formed on the region of the upper surface of the semiconductor substrate 1 where the interlayer insulating film 8 is not formed and on the interlayer insulating film 8. The barrier metal is a conductor containing titanium (Ti), such as titanium nitride or TiSi alloyed with titanium and silicon (Si). + Type source layer 4 and p + The contact layer is in ohmic contact with n + Type source layer 4 and p + type contact layer. The emitter electrode 9 is formed on the upper surface of the semiconductor substrate 1 and connected to the barrier metal. The emitter electrode 9 is, for example, an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy), or may be an electrode composed of a multilayer metal film, which is formed by chemical plating or electrolytic plating on the electrode formed of the aluminum alloy. The plating formed by chemical plating or electrolytic plating is, for example, a nickel (Ni) plating film. In the case where the fine area between the adjacent interlayer insulating films 8 cannot be well embedded in the emitter electrode 9, tungsten with better embedding properties than the emitter electrode 9 may be formed in the fine area, and the emitter electrode 9 may be formed on the tungsten. In addition, it is also possible not to form a barrier metal, but to form an emitter electrode 9 on the n + Type source layer 4 and p + The emitter electrode 9 is formed on the n-type contact layer. + A barrier metal is formed on the n-type semiconductor layer such as the n-type source layer 4. The barrier metal and the emitter electrode 9 may be collectively referred to as an emitter electrode.
[0037] The n-type buffer layer 10 is formed on the n-type surface of the semiconductor substrate 1－ The n-type impurities of the n-type buffer layer 10 are, for example, phosphorus (P) and protons (H + ) or both. The concentration of the n-type impurity in the n-type buffer layer 10 is greater than n － The drift layer height is 1.0E+12 / cm 3 ~1.0E+18 / cm 3 The n-type buffer layer 10 is provided to suppress the occurrence of punch-through of the depletion layer extending from the p-type base layer 3 to the lower surface when the semiconductor device is in the off state. Alternatively, the n-type buffer layer 10 may not be formed, and an n-type buffer layer 10 may also be provided in the region of the n-type buffer layer 10. － The n-type buffer layer 10 and the n-type drift layer 14 may also be formed. － This type of drift layer is collectively called the drift layer.
[0038] The p-type collector layer 11 is formed on the lower surface side of the n-type buffer layer 10. － A p-type collector layer 11 is formed between the p-type drift layer and the lower surface of the semiconductor substrate 1. The p-type impurities of the p-type collector layer 11 are, for example, boron or aluminum. The impurity concentration of the p-type collector layer 11 is 1.0E+16 / cm 3 ~1.0E+20 / cm 3 The semiconductor substrate 1 is formed from n + Type source layer 4 and p + The range from the p-type contact layer to the p-type collector layer 11.
[0039] The collector electrode 12 is formed on the lower surface of the semiconductor substrate 1. The collector electrode 12 is made of an aluminum alloy, or an aluminum alloy and a plated film, similarly to the emitter electrode 9. The collector electrode 12 may also have a structure different from that of the emitter electrode 9. The collector electrode 12 is in ohmic contact with the p-type collector layer 11 and is electrically connected to the p-type collector layer 11.
[0040] Three or more trenches 5 are formed in the first region 1a. In the present embodiment, the trenches 5 in the first region 1a include an active trench 5a and two or more control gate trenches 5b sandwiching the active trench 5a from both sides. The gate electrodes 7 formed in the two or more control gate trenches 5b are connected to each other and are not connected to the gate electrode 7 formed in the active trench 5a.
[0041] One or more trenches 5 are formed in the second region 1b. The trenches 5 in the second region 1b are dummy trenches 5c. The gate electrode 7 formed in the dummy trench 5c is connected to the emitter electrode 9. The p-type base layer 3 is connected to the emitter electrode 9 in the region sandwiched between the first region 1a and the second region 1b.
[0042] The gate insulating film 6 of the active trench 5a and the p-type base layer 3 and n +When a gate driving voltage is applied to the gate electrode 7 of the active trench 5a, a channel is formed in the p-type base layer 3 in contact with the gate insulating film 6 of the active trench 5a. + The type source layer 4 may be in contact with the active trench 5a or may not be in contact with the dummy trench 5c. + The type source layer 4 may not be formed in the region sandwiched by the dummy trenches 5 c.
[0043] Figure 2 1 is a diagram showing the driving of the semiconductor device according to Embodiment 1. When the IGBT is turned on, the control unit 13 turns on the gate electrode 7 of the control gate trench 5b at a time t1 later than the gate electrode 7 of the active trench 5a. When the IGBT is turned off, the control unit 13 turns off the gate electrode 7 of the control gate trench 5b at a time t2 earlier than the gate electrode 7 of the active trench 5a.
[0044] Next, a method for manufacturing the semiconductor device according to the first embodiment is described. First, a semiconductor device having an n － The semiconductor substrate 1 is a semiconductor substrate 1 having a type drift layer. For example, an FZ wafer produced by the FZ (Floating Zone) method or an MCZ wafer produced by the MCZ (Magnetic applied CZochralki) method is used as the semiconductor substrate 1. An n-type wafer containing n-type impurities may also be used as the semiconductor substrate 1. The concentration of n-type impurities contained in the semiconductor substrate 1 is appropriately selected according to the withstand voltage of the semiconductor device to be manufactured. For example, in a semiconductor device with a withstand voltage of 1200V, the concentration of n-type impurities in the semiconductor substrate 1 is adjusted so that n － The resistivity of the type drift layer is about 40 to 120 Ω·cm. In addition, in the process of preparing the semiconductor substrate 1, the entire semiconductor substrate 1 is n － After p-type or n-type impurity ions are implanted from the upper surface or lower surface of the semiconductor substrate 1, they are diffused in the semiconductor substrate 1 by heat treatment or the like, thereby forming a p-type or n-type semiconductor layer.
[0045] Next, n-type impurities such as phosphorus (P) are implanted from the upper surface side of the semiconductor substrate 1 and are placed in the n －The n-type carrier storage layer 2 is diffused into the p-type drift layer to form an n-type carrier storage layer 2. In addition, p-type impurities such as boron (B) are injected from the upper surface side of the semiconductor substrate 1 to form a p-type base layer 3. The n-type carrier storage layer 2 and the p-type base layer 3 are formed by diffusing the impurity ions by heat treatment after injecting impurity ions into the semiconductor substrate 1. The n-type impurities and the p-type impurities are ion-implanted after the upper surface of the semiconductor substrate 1 is masked, so that the n-type carrier storage layer 2 and the p-type base layer 3 are selectively formed on the upper surface side of the semiconductor substrate 1. In addition, the masking process refers to the process of applying a resist to the upper surface of the semiconductor substrate 1 and forming an opening in a specified area of the resist using a photolithography technique to form a mask. Ion implantation or etching is performed in a specified area of the semiconductor substrate 1 through the opening of the mask.
[0046] Next, n-type impurities are selectively implanted into the upper surface side of the p-type base layer 3 by masking to form an n-type base layer. + The n-type impurity injected is, for example, arsenic (As) or phosphorus (P). In addition, p-type impurities are selectively injected into the upper surface side of the p-type base layer 3 by masking to form a p-type source layer 4. + The implanted p-type impurities are, for example, boron (B) or aluminum (Al).
[0047] Next, after depositing an oxide film such as SiO2 on the upper surface of the semiconductor substrate 1, an opening is formed in the oxide film at the portion where the groove 5 is to be formed by masking. The semiconductor substrate 1 is etched using the oxide film with the opening as a mask to form the groove 5. The groove 5 penetrates the p-type base layer 3 and the n-type base layer 5 from the upper surface side of the semiconductor substrate 1. + Type source layer 4 reaches n － Type drift layer. + The sidewalls of the trench 5 of the type source layer 4 constitute n + Type source layer 4 is a part of the electrode.
[0048] Next, the semiconductor substrate 1 is heated in an atmosphere containing oxygen to form a gate insulating film 6 on the inner wall of the trench 5 and the upper surface of the semiconductor substrate 1. In the trench 5 having the gate insulating film 6 formed on the inner wall, polysilicon doped with n-type or p-type impurities is deposited by CVD (chemical vapor deposition) or the like to form a gate electrode 7.
[0049] Next, after forming an interlayer insulating film 8 on the trench 5, the gate insulating film 6 formed on the upper surface of the semiconductor substrate 1 is removed. The interlayer insulating film 8 is, for example, SiO2. + Type source layer 4 and p + A contact hole is formed in the interlayer insulating film 8 by masking above the type contact layer.
[0050] Next, a barrier metal is formed on the upper surface of the semiconductor substrate 1 and on the interlayer insulating film 8. An emitter electrode 9 is formed on the barrier metal. For example, the barrier metal is formed by forming a film of titanium nitride using PDV (physical vapor deposition) or CVD. For example, the emitter electrode 9 is formed by depositing an aluminum silicon alloy (Al-Si alloy) on the barrier metal using PVD such as sputtering or evaporation. In addition, a nickel alloy (Ni alloy) can be further formed on the formed aluminum silicon alloy by chemical plating or electrolytic plating to serve as the emitter electrode 9. Since the metal film that can be easily formed by plating serves as the emitter electrode 9, the heat capacity of the emitter electrode 9 can be increased to improve the heat resistance.
[0051] Next, the lower surface side of the semiconductor substrate 1 is ground to thin the semiconductor substrate 1 to a predetermined thickness. The thickness of the ground semiconductor substrate 1 is, for example, 80 μm to 200 μm. In addition, after the emitter electrode 9 composed of the aluminum silicon alloy is formed by PVD, in the case where a nickel alloy is further formed by plating, the plating process for forming the nickel alloy can also be performed after the processing of the lower surface side of the semiconductor substrate 1.
[0052] Next, n-type impurities are implanted from the bottom surface of the semiconductor substrate 1 to form an n-type buffer layer 10. For example, phosphorus (P) ions or protons (H + ) to form an n-type buffer layer 10. It can also be formed by injecting both protons and phosphorus. Protons can be injected from the lower surface of the semiconductor substrate 1 to a deep position with a relatively low acceleration energy. By changing the acceleration energy, the depth of the injected protons can be changed relatively easily. Therefore, when the n-type buffer layer 10 is formed by protons, if multiple injections are performed while changing the acceleration energy, an n-type buffer layer 10 with a wide width in the thickness direction of the semiconductor substrate 1 can be formed compared to formation by phosphorus. In addition, phosphorus can increase the activation rate as an n-type impurity compared to protons. Therefore, by forming the n-type buffer layer 10 with phosphorus, even after the semiconductor substrate 1 is thinned, it is possible to more reliably suppress the occurrence of punch-through in the depletion layer. In order to further thin the semiconductor substrate 1, it is preferred to inject both protons and phosphorus to form the n-type buffer layer 10. In this case, the protons are injected to a position deeper than the phosphorus from the lower surface.
[0053] Next, p-type impurities are injected from the lower surface side of the semiconductor substrate 1 to form a p-type collector layer 11. For example, boron (B) is injected to form the p-type collector layer 11. After ion implantation from the lower surface side of the semiconductor substrate 1, the lower surface is irradiated with laser for laser annealing, thereby activating the implanted boron to form the p-type collector layer 11. At this time, phosphorus used for the n-type buffer layer 10 implanted from the lower surface of the semiconductor substrate 1 to a relatively shallow position is also activated at the same time. On the other hand, since protons are activated at relatively low annealing temperatures such as 350°C to 500°C, in addition to the process for proton activation after proton implantation, it is necessary to be careful not to make the entire semiconductor substrate 1 reach a temperature higher than 350°C to 500°C. Laser annealing can make only the lower surface of the semiconductor substrate 1 reach a high temperature, so it can also be used to activate n-type impurities or p-type impurities after proton implantation.
[0054] Next, a collector electrode 12 is formed on the lower surface of the semiconductor substrate 1. The collector electrode 12 may be formed over the entire lower surface of the n-type wafer serving as the semiconductor substrate 1. The collector electrode 12 is formed by depositing aluminum silicon alloy (Ai-Si alloy) or titanium (Ti) by PVD such as sputtering or evaporation, but may also be formed by stacking a plurality of metals such as aluminum silicon alloy, titanium, nickel or gold. The collector electrode 12 may also be formed by further forming a metal film by chemical plating or electrolytic plating on the metal film formed by PVD.
[0055] The semiconductor device of this embodiment is manufactured through the above steps. A plurality of semiconductor devices are manufactured in a matrix form on one n-type wafer. Therefore, the semiconductor device is completed by cutting into individual semiconductor devices by laser dicing or blade dicing.
[0056] As described above, the semiconductor device of the present embodiment has a macroscopic sparse structure in which a first region 1a having three or more grooves 5 including an active groove 5a is formed and a second region 1b having one or more dummy grooves 5c is adjacent. In such a macroscopic sparse structure, the turn-on loss can be reduced. However, since the holes below the second region 1b where no electrons are injected flow to the bottom of the first region 1a where electrons are injected, a deviation in the hole density is generated in the lateral direction, resulting in an increase in the turn-off loss. Therefore, in the present embodiment, two or more control gate grooves 5b are formed in the first region 1a in a manner that sandwiches the active grooves 5a from both sides. In addition, the p-type base layer 3 is connected to the emitter electrode 9 in the region sandwiched by the first region 1a and the second region 1b. By turning off the gate electrode 7 of the control gate trench 5b earlier than the gate electrode 7 of the active trench 5a during turn-off, holes flowing from the lower part of the second region 1b to the lower part of the first region 1a can be discharged to the emitter electrode 9 through the side of the control gate trench 5b, thereby reducing turn-off loss. As a result, the loss can be sufficiently reduced.
[0057] In addition, when the IGBT is turned on, the control unit 13 turns on the gate electrode 7 of the control gate trench 5b at a later time than the gate electrode 7 of the active trench 5a. Therefore, since the gate electrode 7 of the active trench 5a is turned on first, the charging cycle of the gate capacity required for turning on can be shortened, and it can be turned on at a high speed. As a result, the turn-on loss can be further reduced. In addition, only one of the above-mentioned control at the time of turning off and the control at the time of turning on by the control unit 13 can be implemented.
[0058] In addition, by forming the n-type carrier accumulation layer 2 below the p-type base layer 3, the promotion of electron injection and the hole accumulation effect can be increased and the on-voltage can be reduced. However, the deviation of the hole density of the macroscopic sparse structure is further increased, which will increase the increase of the turn-off loss. In contrast, in this embodiment, since the holes flowing from the bottom of the second region 1b to the bottom of the first region 1a can be discharged to the emitter electrode 9 through the side of the control gate trench 5b, the turn-off loss can be reduced. Therefore, the turn-off loss can be reduced while reducing the on-voltage.
[0059] Figure 3 This is a cross-sectional view showing Modification 1 of the semiconductor device of Embodiment 1. The number of dummy trenches 5c included in the second region 1b is one, which is less than the number of trenches 5 included in the first region 1a, which is three. Figure 42 is a cross-sectional view showing a variation 2 of the semiconductor device of the first embodiment. The second region 1b includes four trenches 5, which is more than the three trenches 5 included in the first region 1a. In this way, it is preferred that the number of dummy trenches 5c included in the second region 1b is greater than the number of trenches 5 included in the first region 1a. Thus, the effect of reducing the gate-emitter capacitance, which is a characteristic of the macroscopic sparse structure, is improved, and the turn-on loss can be reduced. In addition, the amount of holes flowing from the bottom of the second region 1b to the bottom of the first region 1a increases, and the increased amount of holes is discharged to the emitter electrode 9, thereby further reducing the turn-on loss.
[0060] Figure 5 1 is a cross-sectional view showing a modification 3 of the semiconductor device of the first embodiment. The interlayer insulating film 8 is formed over the second region 1b. Therefore, the p-type base layer 3 sandwiched by the dummy trench 5c of the second region 1b is not connected to the emitter electrode 9. As a result, the amount of holes flowing from the lower part of the second region 1b to the lower part of the first region 1a increases, and the increased amount of holes is discharged to the emitter electrode 9, thereby further reducing the turn-on loss.
[0061] Figure 6 1 is a cross-sectional view showing a variation 4 of the semiconductor device of Embodiment 1. In the first region 1a, the number of control gate trenches 5b is three times or more the number of active trenches 5a. Thus, the hole discharge effect from the control gate trenches 5b is further improved, and thus the turn-off loss can be further reduced.
[0062] Implementation method 2.
[0063] Figure 7 2 is a cross-sectional view showing a semiconductor device according to Embodiment 2. In this embodiment, the trench 5 in the first region 1 a includes a control gate trench 5 b and two or more active trenches 5 a sandwiching the control gate trench 5 b from both sides.
[0064] When the control unit 13 is turned off, the gate electrode 7 of the active trench 5a is turned off later than the gate electrode 7 of the control gate trench 5b. Therefore, when the control gate trench 5b is turned off, there is no electron injection and the conduction loss (on-voltage) increases. The on-voltage at this transition is called the transition on-voltage.
[0065] In the first region 1a, the active trench 5a sandwiches the control gate trench 5b from both sides. As a result, electrons are injected from the active trenches 5a on both sides to the bottom of the control gate trench 5b that is turned off at an early time and has no electron injection, thereby reducing the conduction loss (over-conduction voltage). As a result, the loss can be sufficiently reduced.
[0066] Figure 82 is a cross-sectional view showing a variation of the semiconductor device of Embodiment 2. In the first region 1a, the number of active trenches 5a is three times or more the number of control gate trenches 5b. As a result, the amount of electron injection from the active trenches 5a increases, thereby further reducing conduction loss (transient conduction voltage).
[0067] Implementation method 3.
[0068] Fig. 9 1 is a cross-sectional view showing a semiconductor device according to Embodiment 3. The semiconductor substrate 1 further includes a third region 1c. A second region 1b is disposed between the first region 1a and the third region 1c. In the first region 1a, an active trench 5a and two or more control gate trenches 5b sandwiching the active trench 5a from both sides are formed, similarly to Embodiment 1. On the other hand, a control gate trench 5b and two or more active trenches 5a sandwiching the control gate trench 5b from both sides are formed in the third region 1c.
[0069] The conduction loss (excessive conduction voltage) that can be reduced when the carrier density is high and the turn-off loss that can be reduced when the carrier density is low are in a trade-off relationship, and the loss ratio varies depending on the driving frequency used, etc. For example, in high-speed applications where the switching loss ratio is large, the turn-off loss is emphasized, and in low-speed applications where the conduction loss ratio is large, the excessive conduction voltage is emphasized. Therefore, a structure that can flexibly adjust the loss ratio of the excessive conduction voltage and the turn-off loss according to the application is preferred. In contrast, in the present embodiment, by adjusting the ratio of the number of first regions 1a to the number of third regions 1c, it is possible to adjust the electron injection amount and the hole discharge amount, and adjust the loss ratio of the excessive conduction voltage and the turn-off loss. In addition, since in Fig. 9 In the embodiment, the ratio of the number of the first regions 1 a to the number of the third regions 1 c is set to 1:1, so that the transition ON voltage becomes lower than the case where only the first regions 1 a are provided.
[0070] Fig.10 1 is a cross-sectional view showing a variation 1 of the semiconductor device of the third embodiment. The ratio of the number of first regions 1a to the number of third regions 1c is set to 2:1 to adjust in the direction of reducing the turn-off loss. In addition, the ratio can also be set to 1:2 to adjust in the direction of reducing the excessive conduction voltage. Although the range of the ratio is described as 1:2 to 2:1, it is not limited to this. For example, when it is expanded to 1:5 to 5:1, the adjustment range can be further expanded.
[0071] Fig.112 is a cross-sectional view showing a variation 2 of the semiconductor device of the third embodiment. Three or more trenches 5 are formed in the third region 1c, and the three or more trenches 5 include one or more active trenches 5a and zero or one or more control gate trenches 5b. The proportion of the active trenches 5a formed in the third region 1c is greater than the proportion of the active trenches 5a formed in the first region 1a. Thus, the amount of electron injection during the period after the gate electrode 7 of the control gate trench 5b is turned off can be increased, so the loss ratio of the over-conduction voltage and the turn-off loss can be adjusted to the side with a lower over-conduction voltage.
[0072] Fig.12 2 is a cross-sectional view showing a third variation of the semiconductor device according to the third embodiment. Fig.11 In the embodiment, the ratio of the number of the first regions 1a to the number of the third regions 1c is set to 1:1, but it may also be as follows: Fig.12 Thus, the ratio is set to 1:2 to adjust in the direction of further reducing the over-conduction voltage. The ratio is not limited to these, and the reduction rate of the over-conduction voltage can be adjusted by appropriately adjusting.
[0073] Fig.13 1 is a cross-sectional view showing a modification 4 of the semiconductor device of Embodiment 3. In the third region 1c, only one or more control gate trenches 5b are formed as trenches 5. Thus, the hole ejection effect can be improved, and the loss ratio of the transient on-voltage and the turn-off loss can be adjusted to the side with lower turn-off loss.
[0074] Fig.14 2 is a cross-sectional view showing a fifth variation of the semiconductor device according to the third embodiment. Fig.13 The ratio of the number of the first regions 1a to the number of the third regions 1c is set to 1:1, but it may also be as follows Fig.14 In this way, the ratio is set to 1:2 to adjust in the direction of further reducing the turn-off loss. The ratio is not limited to these, and the reduction rate of the turn-off loss can be adjusted by appropriately adjusting.
[0075] Implementation method 4.
[0076] Fig.15 1 is a cross-sectional view of a semiconductor device according to Embodiment 4. In this embodiment, the impurity concentration of the n-type carrier storage layer 2a in the first region 1a where the channel is formed is higher than the impurity concentration of the n-type carrier storage layer 2b in the second region 1b where the channel is not formed. The amount of electron injection from the active trench 5a and the control gate trench 5b can be increased, and the amount of hole discharge from the second region 1b can be increased, so the trade-off between the on-voltage and the off-loss can be improved. The other structures and effects are the same as those of Embodiment 1, etc.
[0077] Fig.162 is a cross-sectional view showing a variation of the semiconductor device of Embodiment 4. When the amount of electron injection is large at the time of switching on, the temporal variation of the current becomes large, causing electromagnetic radiation noise. Therefore, the impurity concentration of the n-type carrier accumulation layer 2c in contact with the control gate trench 5b switched on at a late moment can be made higher than the impurity concentration of the n-type carrier accumulation layer 2a in contact with the active trench 5a switched on at an early moment and affecting the temporal variation of the current. Thus, the on-voltage can be reduced without increasing the temporal variation of the current. Therefore, the trade-off between electromagnetic radiation noise and the on-voltage can be improved.
[0078] Implementation method 5.
[0079] Fig.17 1 is a cross-sectional view showing a semiconductor device of Embodiment 5. Although the semiconductor devices of Embodiments 1 to 4 are IGBTs, the semiconductor device of this embodiment is an RC-IGBT. An n-type cathode layer 14 is formed on the lower surface side of the semiconductor substrate 1. By turning on the gate electrode 7 of the active trench 5a or the control gate trench 5b before the recovery action of the diode to inject electrons, the hole density can be reduced, thereby reducing the recovery loss. The other structures and effects are the same as those of Embodiment 1, etc.
[0080] Fig.18 2 is a cross-sectional view showing a modified example of the semiconductor device of the fifth embodiment. Fig.17 In the embodiment, an n-type cathode layer 14 is formed in the second region 1b, but it may also be Fig.18 As shown, an n-type cathode layer 14 is formed in the second region 1 b and the third region 1 c.
[0081] In addition, the semiconductor substrate 1 is not limited to being formed of silicon, and can also be formed of a wide bandgap semiconductor having a larger bandgap than silicon. Examples of wide bandgap semiconductors are silicon carbide, gallium nitride-based materials, Ga2O3, or diamond. Such a semiconductor device formed of a wide bandgap semiconductor has high voltage resistance and allowable current density, and can therefore be miniaturized. By using this miniaturized semiconductor device, a semiconductor module incorporating the semiconductor device can also be miniaturized and highly integrated. In addition, since the semiconductor device has high heat resistance, the heat sink of the radiator can be miniaturized, and the water cooling part can be air-cooled, so the semiconductor module can be further miniaturized. In addition, since the semiconductor device has low power loss and high efficiency, the semiconductor module can be made more efficient.
[0082] The preferred embodiments are described in detail above, but the present invention is not limited to the above embodiments, and various modifications and substitutions can be made to the above embodiments without departing from the scope of the claims.
[0083] (Note 1)
[0084] A semiconductor device, characterized in that it comprises:
[0085] A semiconductor substrate of a first conductivity type having a first region and a second region adjacent to each other;
[0086] A base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate;
[0087] A source layer of a first conductivity type formed on an upper surface side of the base layer;
[0088] a plurality of gate electrodes formed through a gate insulating film in the interior of a plurality of trenches penetrating the source layer and the base layer from the upper surface side of the semiconductor substrate;
[0089] an emitter electrode formed on the upper surface of the semiconductor substrate;
[0090] a collector layer of a second conductivity type formed on the lower surface side of the semiconductor substrate; and
[0091] a collector electrode formed on the lower surface of the semiconductor substrate,
[0092] The grooves in the first region include: a first groove and two or more second grooves sandwiching the first groove from both sides,
[0093] The gate electrodes formed in the two or more second trenches are connected to each other and are not connected to the gate electrode formed in the first trench.
[0094] The gate electrode of the trench formed in the second region is connected to the emitter electrode,
[0095] The base layer is connected to the emitter electrode in a region sandwiched by the first region and the second region.
[0096] (Note 2)
[0097] The semiconductor device according to Supplementary Note 1 is characterized in that
[0098] A control unit is further provided which turns off the gate electrode of the control gate trench earlier than the gate electrode of the active trench when the gate electrode is turned off.
[0099] The first trench is the active trench,
[0100] The second trench is the control gate trench.
[0101] (Note 3)
[0102] The semiconductor device according to Supplementary Note 2 is characterized in that
[0103] In the first region, the number of the control gate trenches is more than three times the number of the active trenches.
[0104] (Note 4)
[0105] The semiconductor device according to Supplementary Note 1 is characterized in that
[0106] A control unit is further provided which turns on the gate electrode of the control gate trench at a timing later than the gate electrode of the active trench when the gate electrode is turned on.
[0107] The first trench is the active trench,
[0108] The second trench is the control gate trench.
[0109] (Note 5)
[0110] The semiconductor device according to Supplementary Note 1 is characterized in that
[0111] A control unit is further provided which turns off the gate electrode of the control gate trench earlier than the gate electrode of the active trench when the gate electrode is turned off.
[0112] The first trench is the control gate trench,
[0113] The second trench is the active trench.
[0114] (Note 6)
[0115] The semiconductor device according to Supplementary Note 5 is characterized in that
[0116] In the first region, the number of the active trenches is more than three times the number of the control gate trenches.
[0117] (Note 7)
[0118] The semiconductor device according to any one of Supplementary Notes 2 to 4, characterized in that:
[0119] The semiconductor substrate has a third region,
[0120] The second area is arranged between the first area and the third area,
[0121] The control gate trench and two or more active trenches sandwiching the control gate trench from both sides are formed in the third region.
[0122] (Note 8)
[0123] The semiconductor device according to any one of Supplementary Notes 2 to 6, characterized in that:
[0124] The semiconductor substrate has a third region,
[0125] The second area is arranged between the first area and the third area,
[0126] A proportion of the active trenches formed in the third region is greater than a proportion of the active trenches formed in the first region.
[0127] (Note 9)
[0128] The semiconductor device according to any one of Supplementary Notes 2 to 6, characterized in that:
[0129] The semiconductor substrate has a third region,
[0130] The second area is arranged between the first area and the third area,
[0131] One or more control gate trenches are formed in the third region.
[0132] (Note 10)
[0133] The semiconductor device according to any one of Supplementary Notes 1 to 9, characterized in that:
[0134] The number of the grooves included in the second region is greater than or equal to the number of the grooves included in the first region.
[0135] (Note 11)
[0136] The semiconductor device according to any one of Supplementary Notes 1 to 10, characterized in that
[0137] The invention further includes a first conductivity type carrier storage layer formed below the base layer.
[0138] (Note 12)
[0139] The semiconductor device according to Supplementary Note 11, characterized in that
[0140] An impurity concentration of the carrier accumulation layer in the first region is higher than an impurity concentration of the carrier accumulation layer in the second region.
[0141] (Note 13)
[0142] The semiconductor device according to Supplementary Note 4 is characterized in that
[0143] further comprising a first conductivity type carrier storage layer formed below the base layer,
[0144] The impurity concentration of the carrier accumulation layer in contact with the control gate trench is higher than the impurity concentration of the carrier accumulation layer in contact with the active trench.
[0145] (Note 14)
[0146] The semiconductor device according to any one of Supplementary Notes 1 to 13, wherein the semiconductor device is an RC-IGBT.
[0147] (Note 15)
[0148] The semiconductor device according to any one of Supplementary Notes 1 to 14, wherein the semiconductor substrate is formed of a wide bandgap semiconductor.
Claims
1. A semiconductor device, characterized in that: have: A semiconductor substrate of a first conductivity type having a first region and a second region adjacent to each other; A base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; A source layer of a first conductivity type formed on an upper surface side of the base layer; a plurality of gate electrodes formed through a gate insulating film in the interior of a plurality of trenches penetrating the source layer and the base layer from the upper surface side of the semiconductor substrate; an emitter electrode formed on the upper surface of the semiconductor substrate; A collector layer of a second conductivity type formed on the lower surface side of the semiconductor substrate; as well as a collector electrode formed on the lower surface of the semiconductor substrate, The grooves in the first region include: a first groove and two or more second grooves sandwiching the first groove from both sides, The gate electrodes formed in the two or more second trenches are connected to each other and are not connected to the gate electrode formed in the first trench. The gate electrode of the trench formed in the second region is connected to the emitter electrode, The base layer is connected to the emitter electrode in a region sandwiched by the first region and the second region.
2. The semiconductor device according to claim 1, wherein: A control unit is further provided which turns off the gate electrode of the control gate trench earlier than the gate electrode of the active trench when the gate electrode is turned off. The first trench is the active trench, The second trench is the control gate trench.
3. The semiconductor device according to claim 2, wherein: In the first region, the number of the control gate trenches is more than three times the number of the active trenches.
4. The semiconductor device according to claim 1, wherein: A control unit is further provided which turns on the gate electrode of the control gate trench at a timing later than the gate electrode of the active trench when the gate electrode is turned on. The first trench is the active trench, The second trench is the control gate trench.
5. The semiconductor device according to claim 1, wherein: A control unit is further provided which turns off the gate electrode of the control gate trench earlier than the gate electrode of the active trench when the gate electrode is turned off. The first trench is the control gate trench, The second trench is the active trench.
6. The semiconductor device according to claim 5, wherein: In the first region, the number of the active trenches is more than three times the number of the control gate trenches.
7. The semiconductor device according to any one of claims 2 to 4, characterized in that The semiconductor substrate has a third region, The second area is arranged between the first area and the third area, The control gate trench and two or more active trenches sandwiching the control gate trench from both sides are formed in the third region.
8. The semiconductor device according to any one of claims 2 to 6, wherein: The semiconductor substrate has a third region, The second area is arranged between the first area and the third area, A proportion of the active trenches formed in the third region is greater than a proportion of the active trenches formed in the first region.
9. The semiconductor device according to any one of claims 2 to 6, wherein: The semiconductor substrate has a third region, The second area is arranged between the first area and the third area, One or more control gate trenches are formed in the third region.
10. The semiconductor device according to any one of claims 1 to 6, wherein: The number of the grooves included in the second region is greater than or equal to the number of the grooves included in the first region.
11. The semiconductor device according to any one of claims 1 to 6, wherein: The invention further includes a first conductivity type carrier storage layer formed below the base layer.
12. The semiconductor device according to claim 11, wherein: An impurity concentration of the carrier accumulation layer in the first region is higher than an impurity concentration of the carrier accumulation layer in the second region.
13. The semiconductor device according to claim 4, wherein: further comprising a first conductivity type carrier storage layer formed below the base layer, The impurity concentration of the carrier accumulation layer in contact with the control gate trench is higher than the impurity concentration of the carrier accumulation layer in contact with the active trench.
14. The semiconductor device according to any one of claims 1 to 6, wherein: The semiconductor device is an RC-IGBT.
15. The semiconductor device according to any one of claims 1 to 6, characterized in that The semiconductor substrate is formed of a wide bandgap semiconductor.