Miniature multifunctional artificial nerve component based on two-dimensional WSe2 transistor and preparation method and application thereof

Abstract

The invention belongs to the field of artificial nerve devices, and provides a preparation method of a miniature multifunctional artificial nerve device based on a two-dimensional WSe2 transistor in order to solve the problems that an existing artificial prominent function is single, the manufacturing process is complex and large-scale production cannot be adapted, and the preparation method comprises the following steps that a single-layer / few-layer selenium disulfide thin channel is prepared; evaporating a Se / Au electrode to manufacture a P-type WSe2 transistor; evaporating a Bi / Au electrode to manufacture an N-type WSe2 transistor and connecting the N-type WSe2 transistor by adopting a CMOS structure; the electrical performance and the activation function input and output curve of the prepared device are tested, various indexes of the device are simulated, the accuracy of the simulation result is obtained, and it is proved that the method can be applied to achieving the activation function function and the artificial synapse function.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor artificial neuron devices, and in particular to a micro multifunctional artificial neuron device based on a two-dimensional WSe2 transistor, and a preparation method and application thereof. Background Art

[0002] The large number of interconnections between neurons in artificial neural networks (ANNs) allows information to be quickly transmitted to each neuron for parallel processing after input. In the process of value transmission, the data calculation and storage functions are completed at the same time, and the mapping relationship between input and output is stored in the form of inter-neuron connection strength (weight), so the operation efficiency is higher than the traditional serial data processing method. The more neurons and layers, the stronger the neural network's ability to process data and the faster the learning speed. In recent years, neural networks have achieved unprecedented development and success in many aspects such as the Internet of Things, cloud data processing, and machine learning. Therefore, artificial neurons are particularly important as a basic component of artificial neural networks. Two-dimensional materials are considered to be emerging materials with ideal properties for building next-generation electronic products. They have advantages such as atomically thin thickness and no dangling bonds on the surface, which have attracted the attention of many researchers. Research on neuromorphic devices based on two-dimensional materials has achieved many results. Various artificial synaptic devices, such as memristors, photoelectric synapses, and heterosynapses that can achieve memory effects such as conductivity weight updates and short-term / long-term plasticity (STP / LTP) have been widely studied.

[0003] However, in artificial neural networks, the functions of neurons include not only inputs (synapses) with different weight changes, but also important functions such as signal accumulation and summation, and nonlinear activation output. In the early research on neuromorphic devices based on two-dimensional materials, the activation function was implemented by traditional metal oxide semiconductor (CMOS) circuits and digital-to-analog converter (ADC) circuits with reconfigurable function mapping. With the rapid development of artificial neural networks in recent years, the number of layers of neural networks has increased dramatically, the number of activation functions required has become increasingly large, and energy consumption has soared. To this end, researchers have also made new explorations on neuromorphic devices with activation functions, such as using two-dimensional materials to implement common ReLU, Sigmoid, and Tanh activation functions. However, for these synaptic functions, accumulation and summation, and nonlinear activation functions, they all exist in discrete devices, and their structures and processes are complex. In the future, when deep neural networks have higher requirements for hardware resources and a higher degree of integration, it is inevitable that system manufacturing steps and costs will be added, and more space will be occupied.

[0004] Traditional artificial neurons, such as artificial synapses and activated neurons, are made by stacking different types of materials in a specific structure. However, these devices have the problem of single function and can only be used as artificial synapses to achieve perception, or can only store stimulation signals. Most of the current artificial synaptic devices based on two-dimensional materials rely on TMDs, graphene, boron nitride, ferroelectric materials, etc. for artificial superposition. The required materials are of various types, and the production process is complicated and time-consuming, which is not conducive to the application of large-scale neuromorphic devices in the future. Summary of the invention

[0005] The purpose of the present invention is to provide a method for manufacturing a micro-multifunctional artificial neuron device based on a two-dimensional WSe2 transistor. The preparation method produces a micro-multifunctional artificial neuron device, which can solve the current problems that the synaptic function and activation function are in discrete devices and the manufacturing is complex and requires many materials.

[0006] A multifunctional platform based on WSe2 transistors produced by the present invention can realize the functions of Sigmoid activation function and artificial synapse, and has a simple structure and low manufacturing complexity. It adjusts the output voltage to realize the output sigmoid curve by controlling the common gate input voltage. Programming different gate electrical stimulation signals successfully simulates a variety of synaptic functions, including excitatory / inhibitory postsynaptic potentials (EPSC / IPSC), double pulse excitation / inhibition (PPF / PPD) and LTP / LTD, etc. The present invention aims to overcome the limitations of the existing artificial neuromorphic devices in which artificial synapses and nonlinear activation functions are in a discrete state, and achieves a stable effect with simple materials and manufacturing methods, providing a simpler manufacturing process for the realization of full hardware artificial neural networks in the future.

[0007] The present invention provides a method for preparing a micro multifunctional artificial neuron device based on a two-dimensional WSe2 transistor, comprising the following steps:

[0008] S1 obtains a silicon wafer composed of an insulating silicon oxide layer and a heavily doped conductive silicon layer, and transfers a WSe2 thin film to the insulating silicon oxide layer in the silicon wafer as a channel; the WSe2 thin film is composed of a single two-dimensional WSe2 layer of less than 10 layers;

[0009] S2: preparing two mutually parallel strip-shaped Au electrodes on the WSe2 film; wherein the two mutually parallel strip-shaped Au electrodes serve as the source and drain of the P-type WSe2 transistor respectively; and obtaining a silicon wafer including the P-type WSe2 transistor;

[0010] S3: preparing two parallel strip-shaped Bi / Au electrodes on the WSe2 thin film; wherein the two parallel strip-shaped Bi / Au electrodes serve as the source and drain of the N-type WSe2 transistor respectively; obtaining a silicon wafer including a P-type WSe2 transistor and an N-type WSe2 transistor; the heavily doped conductive silicon layer in the silicon wafer serves as a common gate of the P-type WSe2 transistor and the N-type WSe2 transistor at the same time; connecting the source of the P-type WSe2 transistor and the source of the N-type WSe2 transistor to each other to form a common source and common gate structure.

[0011] Preferably, in step S2, two parallel strip Au electrodes are prepared on the WSe2 thin film, specifically comprising the following steps: coating the WSe2 thin film with photoresist, obtaining two parallel strip electrode patterns through ultraviolet exposure and development, sequentially evaporating Se with a thickness of 8-15nm and Au with a thickness of 40-100nm, and after degumming treatment, removing the Se layer through vacuum drying to obtain a silicon wafer including a P-type WSe2 transistor.

[0012] Preferably, in step S3, two parallel strip-shaped Bi / Au electrodes are prepared on the WSe2 film, specifically comprising the following steps: coating the WSe2 film with photoresist, performing ultraviolet exposure and development to obtain two parallel strip-shaped electrode patterns, sequentially evaporating a Bi layer with a thickness of 2-10 nm and an Au layer with a thickness of 40-100 nm, and obtaining a silicon wafer including a P-type WSe2 transistor and an N-type WSe2 transistor after degumming treatment;

[0013] The present invention also provides a micro multifunctional artificial neuron device based on a two-dimensional WSe2 transistor, comprising: a silicon wafer composed of an insulating silicon oxide layer and a heavily doped conductive silicon layer, wherein a WSe2 film is provided on the insulating silicon oxide layer as a channel; the WSe2 film is composed of less than 10 single-layer two-dimensional WSe2 layers;

[0014] Two parallel strip-shaped Au electrodes are arranged on the WSe2 film; the two parallel strip-shaped Au electrodes serve as the source and drain of the P-type WSe2 transistor respectively; the thickness of the strip-shaped Au electrodes is 40-100 nm;

[0015] Two parallel strip-shaped Bi / Au electrodes are also arranged on the WSe2 film; wherein the two parallel strip-shaped Bi / Au electrodes serve as the source and drain of the N-type WSe2 transistor respectively; the Bi / Au electrode is composed of a Bi layer with a thickness of 2-10nm and an Au layer with a thickness of 40-100nm, wherein the Bi layer is located between the Au layer and the WSe2 film;

[0016] The heavily doped conductive silicon layer in the silicon wafer serves as a common gate of the P-type WSe2 transistor and the N-type WSe2 transistor at the same time; the source of the P-type WSe2 transistor and the source of the N-type WSe2 transistor are connected to each other as a common source.

[0017] Preferably, in the micro multifunctional artificial neuron device based on the two-dimensional WSe2 transistor, the thickness of the insulating silicon oxide layer is 260-500nm; the channel width between two parallel strip Au electrodes is 4-7μm; and the channel width between two parallel strip Bi / Au electrodes is 4-7μm.

[0018] The present invention also provides an application of a micro multifunctional artificial neuron device based on a two-dimensional WSe2 transistor in realizing an activation function function, comprising the following steps: inputting a level signal varying between a positive level and a negative level to a common gate, wherein the positive level is not greater than 60V, and the negative level is not less than -60V; the drain of the P-type WSe2 transistor is connected to a constant level signal; the drain of the N-type WSe2 transistor is grounded; a signal varying with the common gate level is output through the common source; the relationship between the signal output by the common source and the level signal input to the common gate conforms to the functional relationship of the activation function.

[0019] Preferably, the activation function is a Sigmoid function, the level signal varying between the positive level and the negative level is specifically a level signal varying from -20V to 20V, and the drain of the N-type WSe2 transistor is connected to a constant level signal of 1V.

[0020] The present invention also provides an application of a micro multifunctional artificial neuron device based on a two-dimensional WSe2 transistor in realizing synaptic function, comprising the following steps: maintaining a constant common source voltage, using the common gate as an electrical signal stimulation input terminal, inputting electrical signal stimulation, and using the leakage current of the drain of the P-type WSe2 transistor as output. Preferably, the constant common source voltage is 1 volt.

[0021] The present invention also provides an application of a micro multifunctional artificial neuron device based on a two-dimensional WSe2 transistor in realizing a full hardware artificial neural network, comprising the following steps: the full hardware artificial neural network comprises no less than two micro multifunctional artificial neuron devices based on a two-dimensional WSe2 transistor, wherein at least one of the micro multifunctional artificial neuron devices based on a two-dimensional WSe2 transistor is used as an artificial neuron node device, and at least one of the micro multifunctional artificial neuron devices based on a two-dimensional WSe2 transistor is used as an activation function device.

[0022] Preferably, the common gate of the artificial neuron node device serves as the stimulation signal input terminal, and a voltage signal in the range of 5V-30V is applied, and its common source is connected to a constant level signal of 1V, and the drain of the P-type WSe2 transistor is grounded by connecting a resistor element; a node is set between the resistor element and the drain of the P-type WSe2 transistor, and a lead is drawn from the node to connect the common gate of the activation function device as the input of the activation function device, and the common source of the activation function device is used as the output; the drain of the N-type WSe2 transistor of the activation function device is connected to a constant voltage level signal of 1V, and the drain of the P-type WSe2 transistor of the activation function device is grounded; when the full hardware artificial neural network includes more than one artificial neuron node device, the node between the resistance and the drain of each artificial neuron node device is connected together, and they are used together as the input of the activation function device to achieve parallel superposition and the purpose of cumulative summation.

[0023] In order to solve the problems of single function, complex manufacturing process and inability to adapt to large-scale production of existing artificial protrusions, the present invention uses multilayer WSe2 as channel material and uses metals with different work functions to construct contact electrodes, thereby obtaining different channel types, and then constructing a transistor-type device that realizes the Sigmoid function. The polarity of the WSe2 transistor is changed by metal contact. This method only requires one material, no additional chemical doping is required, and multiple materials are superimposed, which reduces the complexity of neuromorphic device manufacturing, and ensures the stability of its modulation effect through repeated experiments. At the same time, the WSe2 transistor has a memory function due to the adsorption of water and oxygen molecules in the air and defects on the surface of the dielectric layer, and can realize the functions of artificial synapses and activation functions on one device.

[0024] Compared with the prior art, the technical solution conceived by the present invention can achieve the following beneficial effects:

[0025] (1) The present invention can realize synaptic and nonlinear activation functions on one device, thereby increasing the diversity of device functions and simplifying the manufacturing process. This can reduce the space occupied by components in future large-scale integrated circuits and improve the space efficiency and availability of components.

[0026] (2) The present invention changes the polarity of the WSe2 transistor by a metal contact method, and only one material is needed to achieve both n-type and p-type effects. Compared with other artificial neuron devices, the present invention only needs one material, does not require superposition, has the characteristics of simple raw materials and stable production effects, does not have any chemical doping, has a simple production process, and has the advantages of low cost and easy manufacturing. The present invention has good stability and excellent reproducibility, which enhances the reliability and repeatability of the method. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the specific implementation of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the specific implementation or the prior art description. Some specific embodiments of the present invention will be described in detail in an exemplary but not restrictive manner with reference to the drawings. The same reference numerals in the drawings indicate the same or similar components or parts. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0028] Figure 1 It is a structural schematic diagram of a micro multifunctional artificial neuron device based on a two-dimensional WSe2 transistor of the present invention.

[0029] Figure 2 The present invention is a schematic flow chart of the mechanical peeling and material transfer process in the preparation method of the micro multifunctional artificial neuron device based on the two-dimensional WSe2 transistor of the present invention. In which, the number (1) represents the transfer of the two-dimensional material mechanically peeled off from the tape to the PDMS, the number (2) represents the PDMS with the two-dimensional material already transferred on the surface, the number (3) represents the PDMS with the two-dimensional material close to the silicon wafer substrate, the number (4) represents the PDMS with the two-dimensional material close to the silicon wafer substrate and heating to 60 degrees to assist the transfer, the number (5) represents the PDMS slowly lifted up, and the number (6) represents that the two-dimensional material has been transferred to the silicon wafer.

[0030] Figure 3 The present invention is a schematic flow chart of the ultraviolet lithography and thermal evaporation steps in the preparation method of the micro multifunctional artificial neuron device based on the two-dimensional WSe2 transistor. In which, the reference numeral (1) represents spinning the photoresist onto the silicon wafer with the two-dimensional material, the reference numeral (2) represents drawing the electrode pattern after ultraviolet light irradiation, the reference numeral (3) represents the display of the electrode pattern after the sample is developed by the developer, and the reference numeral (4) represents the metal evaporation upper electrode.

[0031] Figure 4 This is an optical microscope picture of a micro multifunctional artificial neuron device of a two-dimensional WSe2 transistor in an embodiment of the present invention and a schematic diagram of its electrical connections.

[0032] Figure 5 This is a scanning electron microscope image of a micro multifunctional artificial neuron device of a two-dimensional WSe2 transistor in an embodiment of the present invention.

[0033] Figure 6 It is an electrical characterization image of the polarity adjustment of the metal contact in the micro multifunctional artificial neuron device of the two-dimensional WSe2 transistor in the embodiment of the present invention; wherein (a) is the output characteristic curve of the P-type transistor, (b) is the transfer curve of the P-type transistor, (c) is the output characteristic curve of the N-type transistor, and (d) is the transfer characteristic curve of the N-type transistor.

[0034] Figure 7The Sigmoid activation function and its simulation accuracy are realized in the micro multifunctional artificial neuron device of the two-dimensional WSe2 transistor in the embodiment of the present invention, wherein (a) is the comparison image of the test curve and its fitting image with the original Sigmoid curve, and (b) is the simulation recognition accuracy of the fitting curve and the Sigmoid curve in the convolutional neural network (CNN) and the multi-layer perceptron (MLP).

[0035] Figure 8 The artificial synaptic function is realized in the micro multifunctional artificial neuron device of the two-dimensional WSe2 transistor in the embodiment of the present invention and its simulation results, wherein (a) is the different amplitudes V GS (b) is the PPF exponential fitting image, (c) is the PPD exponential fitting image, and (d) is the postsynaptic current at different frequencies (V GS =20V, V DS =1V), (e) is the synaptic enhancement / depression image, and (f) is the accuracy of handwritten digit recognition of artificial synapses in the CrossIM platform.

[0036] Fig. 9 The synaptic characteristics of the micro multifunctional artificial neuron device of the two-dimensional WSe2 transistor in a closed environment are obtained for the example. In (a) and (b), the excitatory postsynaptic current images (V) at the frequencies of 1 Hz and 5 Hz under air and vacuum conditions are shown in Figure 2. GS =20V, V DS =1V), (c) and (d) inhibitory postsynaptic current images at 1Hz and 5Hz in air and vacuum conditions respectively (V GS =20V, V DS =1V). DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0038] (1) Fabrication of WSe2 channel: Place a small piece of WSe2 crystal on the tape, peel it off mechanically by tearing it apart, stick the tape with the material onto the prepared PDMS, and find the WSe2 film under microscope observation. Then use the transfer table to transfer the WSe2 film to the silicon wafer by stamp transfer.

[0039] (2) Evaporation of Se / Au electrodes to make P-type WSe2 transistors: Use a spin-coater to spin on a layer of photoresist LOR3A, dry at 180 degrees for 5 minutes, then spin on photoresist S1805, and dry at 120 degrees for 1 minute. After UV exposure to make the electrode pattern, soak it in a developer for 30-45 seconds. After development, place it in a thermal evaporator to evaporate 10nm of Se and 50nm of Au. After soaking in N-methylpyrrolidone solution for two hours to remove excess metal, the prepared device is placed in a vacuum drying oven for annealing, and dried at 160 degrees for 4 hours to remove the Se layer;

[0040] (3) Evaporation of Bi / Au electrodes to make N-type WSe2 transistors and connect them with a common gate and common drain structure: The device annealed in step (2) is further spun on a layer of photoresist LOR3A using a spin-coater, dried at 180 degrees for 5 minutes, and then spun on photoresist S1805 and dried at 120 degrees for 1 minute. After ultraviolet exposure to make electrode patterns, the device is placed in a developer and soaked for 30-45 seconds, and then placed in a thermal evaporator to evaporate 5nm of Bi and 50nm of Au in a vacuum. After soaking in N-methylpyrrolidone solution for two hours to remove excess metal, the prepared device is placed in a vacuum drying oven and dried at 100 degrees for 0.5 to 2 hours to remove excess moisture. The two Au electrodes, the WSe2 thin film material sandwiched between them, the 280nm thick insulating silicon oxide layer with a high withstand voltage value, and the heavily doped conductive silicon wafer constitute a P-type transistor. The two parallel electrodes form the source and drain, and the heavily doped silicon wafer is the global gate. The width of the electrode is 1 to 3 μm, and the channel width between the two parallel electrodes is 4 to 7 μm. Similarly, Bi / Au and WSe2 thin film insulation layers and heavily doped silicon wafers form an N-type transistor, a three-terminal device with a source, a drain and a gate. In the process of patterning the Bi / Au electrode, the source of the N and P-type transistors is connected to form a common source and common gate structure. The device optics obtained, its image and scanning electron microscope image are detailed in Figure 4 , Figure 5 ;

[0041] (4) Test various electrical properties of artificial synapses and their activation function input-output curves, simulate various indicators and obtain the accuracy of simulation results: test the metal contact polarity regulation effect of the multifunctional device prepared in step (3), as well as the postsynaptic current (PSC) in artificial synapses, including excitatory / inhibitory postsynaptic current (EPSC / IPSC), paired pulse facilitation (PPF), paired pulse depression (PPD), and synaptic enhancement, the effect of renewable conversion conductance brought about by inhibition. And by controlling the input of the common gate electrical signal to obtain the sigmoid test curve, test its feasibility and recognition effect in the artificial neural network simulation. For specific test methods, refer to Figure 4 Structure, first test the performance of N and P transistors separately, apply 1V voltage to both ends of the source and drain, and the gate voltage is from -60V to 60V to obtain its characteristic curve. Figure 6 , indicating that WSe2 is modulated from bipolar to N,P characteristic transistor. To test the sigmoid curve, a voltage level varying from -20V to 20V is applied to the common gate, and at the same time, the Au electrode not connected to the Bi / Au electrode is connected to a constant voltage signal of 1V. The Bi / Au electrode not connected to the Au electrode is grounded. The Bi / Au electrode is connected to the Au electrode as a common source to output a signal that changes with the common gate voltage level. Figure 7 As shown in a, the experimental test curve in the figure is compared with the standard curve. The simulation accuracy of convolutional neural network (CNN) and multi-layer perceptron (MLP) reaches more than 98%. In its synaptic function, the gate is used as the electrical signal stimulation input, and the source-drain current is used as the output. We read the source-drain current with a constant 1V source-drain voltage through the encoded input voltage signal. The synaptic effect diagram is shown in Figure 8 There is an obvious hysteresis window in the transfer characteristic curve of the transistor bidirectional scanning, showing memory performance. The main reason is the adsorption / desorption of water and oxygen molecules on the surface of the two-dimensional material and the interface charge capture / desorption between the two-dimensional material and the dielectric layer. Based on the gate voltage on I DS We regard the gate electrode signal input end of the transistor as the presynaptic membrane, and the source electrode signal output end as the postsynaptic membrane. DS As the postsynaptic current (PSC), the synaptic weight change function is realized to simulate the plasticity of biological synapses.

[0042] Set 1V as the fixed read voltage V DS The value of VGS is programmed to be different as the presynaptic membrane stimulation signal to study V GS Effects of pulse amplitude and width on PSCs. Figure 6 It can be clearly seen from a in Figure 1 that V GS When the voltage signal pulse width is 1ms, the excitatory postsynaptic current (EPSC) gradually increases from 10nA to nearly 100nA during the increase of the amplitude from 5V to 30V. These phenomena indicate that the postsynaptic current can have different changes through different electrical stimulations, which is consistent with the biological potential changes produced by the synapse under the action of neurotransmitters. In addition, applying two consecutive V GS The input pulse successfully simulated the behavior of paired pulse facilitation (PPF) and paired pulse depression (PPD). In the enhancement / inhibition of postsynaptic current changes, the PSC generated by the second electrical signal stimulation is different from the PSC generated by the first electrical signal stimulation, and the postsynaptic current generated by the second signal stimulation is larger (ΔI2>ΔI1), which is paired pulse enhancement / depression. This is similar to the release of neurotransmitters from the presynaptic membrane to the postsynaptic membrane in biological synapses to produce excitation / inhibition effects. We used V DS =1V, V GSWhen the pulse width is 1 ms and the PPF and PPD at different time intervals are measured, the PPF and PPD indexes are calculated according to formula (1).

[0043] PPF / PPD index=[|ΔI2-ΔI1| / ΔI1]*100% (1)

[0044] Where ΔI1 and ΔI2 are the absolute values ​​of the difference between the PSC and the presynaptic current of each pulse stimulation. According to the PPF and PPD index at different time intervals, we get the nonlinear fitting, such as Figure 8 b and c in Figure 2. At larger voltage pulse intervals, both the PPF and PPD indices are significantly reduced. This downward trend is consistent with the biological memory double exponential function, which means that transistor synapses can mimic the memory learning function of biological synapses.

[0045] According to the PPF and PPD indices calculated by formula (1), we can further calculate their relaxation time. Formula (2) is the fitting formula of the double exponential function, from which the relaxation time τ of the two stages of rapid and slow decline of the PPF and PPD indices when the time interval changes is calculated. They are 3.1ms (τ1, PPF), 154.9ms (τ2, PPF), 2.9ms (τ1, PPD) and 454.3ms (τ2, PPD) respectively. These data show that the memory effect of our device can be enhanced / suppressed in a short time interval.

[0046] PPF / PPD index =A+B1exp(-t / τ1)+B2exp(-t / τ2) (2)

[0047] Moreover, in V GS The postsynaptic current also changes differently when the signal is applied at different frequencies (1Hz, 5Hz, 10Hz). Figure 7 It can be clearly seen in d that the EPSC frequency increases significantly from 1Hz to 5Hz, indicating that our device can also achieve the purpose of weight update by applying voltage pulses of different frequencies. Then we apply the programmed pulse train stimulation to verify the stability of the continuous change of the enhancement / inhibition effect under continuous stimulation. GS =30V, negative pulse V GS=-5V, the pulse width and interval time of the continuous pulse signal are both 50ms to obtain the change image of PSC after 60 pulses. The positive (negative) pulse induces PSC to increase (decrease). Under the positive pulse, PSC gradually increases from 200nA to 800nA, showing weak linearity until it approaches saturation. Under the negative voltage pulse, PSC gradually decreases to saturation. We use this enhanced / inhibited postsynaptic current data to calculate the data of changing conductance, and then import it into the built model for simulation verification. A perceptron artificial neural network (MLP) based on the crossim simulation platform is constructed and supervised learning is performed using the MNIST data set. 20 cycles are trained with 8,000 handwritten digit images for recognition in each training cycle. Its accuracy is as follows Figure 6 As shown in a in the figure, the data in the figure shows that the recognition accuracy of the standard model reaches 98.05% after several training cycles, while the accuracy of the experimental data simulation obtained by our synaptic device is 90.53%. These results prove that our synaptic device can recognize numbers more accurately after learning. In order to explore the effect of its synaptic characteristics in a closed environment, we first tested it in air and high vacuum (4.5×10 -5 Pa) to test its electrical and memory properties. DS =1V, Width = 10ms, V GS =20V is the positive bias voltage and the EPSC is obtained. Fig. 9 a, b in the figure). Negative bias voltage V GS = -10V stimulation to obtain inhibitory postsynaptic current (IPSC) Fig. 9 As shown in c and d in the figure. Under 20 consecutive signal stimulations at frequencies of 10 Hz and 5 Hz, it can be seen that the transistor synapse still retains memory properties in a vacuum. That is, the capture / detrapping of electrons by interface defects between the two-dimensional material and the dielectric layer is the cause of this phenomenon. It can be observed from the figure that the PSC is reduced compared to the results measured in air, indicating that the adsorption of water and oxygen molecules and the interface charge capture / detrapping between the material and the dielectric layer show a synergistic effect on the synaptic behavior.

[0048] In the present invention, metal contact is used to adjust the polarity of WSe2 transistor to achieve the purpose of constructing activation function connection structure and artificial synaptic characteristics. The metal materials and two-dimensional semiconductor materials that can be realized are not limited to Au / Bi, WSe2, etc. In the preparation process, other metals with high work functions can also change the polarity of two-dimensional semiconductor materials to construct sigmoid circuit structures to achieve the purpose of realizing activation function and artificial synaptic function. And the preparation method of the present invention can be extended to other transition metal selenium compound two-dimensional materials.

[0049] The present invention provides an application of a micro multifunctional artificial neuron device based on a two-dimensional WSe2 transistor in realizing an activation function. A level signal varying between a positive level and a negative level is first input to a common gate, wherein the positive level is not greater than 60V, and the negative level is not less than -60V;

[0050] The drain of the N-type WSe2 transistor is connected to a constant level signal;

[0051] The drain of the P-type WSe2 transistor is grounded; a signal that changes with the common gate level is output through the common source; the relationship between the signal output by the common source and the level signal input to the common gate conforms to the functional relationship of the activation function. The level signal that changes between the positive level and the negative level is specifically a level signal that changes from -20V to 20V, and the drain of the N-type WSe2 transistor is connected to a constant 1V level signal.

[0052] The present invention provides an application of a micro multifunctional artificial neuron device based on a two-dimensional WSe2 transistor in realizing synaptic function, maintaining a constant common source voltage, using the common gate as an electrical signal stimulation input terminal, inputting electrical signal stimulation, and using the leakage current of the drain of the P-type WSe2 transistor as output.

[0053] The present invention provides an application of a micro multifunctional artificial neuron device based on a two-dimensional WSe2 transistor in realizing a full hardware artificial neural network, characterized in that it includes the following steps: the full hardware artificial neural network includes no less than two micro multifunctional artificial neuron devices based on the two-dimensional WSe2 transistor, wherein at least one of the micro multifunctional artificial neuron devices based on the two-dimensional WSe2 transistor is used as an artificial neuron node device, and at least one of the micro multifunctional artificial neuron devices based on the two-dimensional WSe2 transistor is used as an activation function device. The common gate of the artificial neuron node device is used as the stimulation signal input terminal, and a voltage signal in the range of 5V-30V is applied. Its common source is connected to a constant level signal of 1V, and the drain of the P-type WSe2 transistor is grounded by connecting a resistor element; a node is set between the resistor element and the drain of the P-type WSe2 transistor, and a lead is drawn from the node to connect the common gate of the activation function device as the input of the activation function device, and the common source of the activation function device is used as the output; the drain of the N-type WSe2 transistor of the activation function device is connected to a constant voltage level signal of 1V, and the drain of the P-type WSe2 transistor of the activation function device is grounded; when the full hardware artificial neural network includes more than one artificial neuron node device, the node between the resistor and the drain of each artificial neuron node device is connected together, and they are used together as the input of the activation function device to achieve parallel superposition and the purpose of cumulative summation.

[0054] The above descriptions are only some specific implementation methods of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any person familiar with the art within the technical scope disclosed in the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for preparing a micro multifunctional artificial neuron device based on a two-dimensional WSe2 transistor, characterized in that: The following steps are involved: S1 obtains a silicon wafer composed of an insulating silicon oxide layer and a heavily doped conductive silicon layer, and transfers a WSe2 thin film to the insulating silicon oxide layer in the silicon wafer as a channel; the WSe2 thin film is composed of a single two-dimensional WSe2 layer of less than 10 layers; S2: preparing two mutually parallel strip-shaped Au electrodes on the WSe2 film; wherein the two mutually parallel strip-shaped Au electrodes serve as the source and drain of the P-type WSe2 transistor respectively; and obtaining a silicon wafer including the P-type WSe2 transistor; S3: preparing two parallel strip-shaped Bi / Au electrodes on the WSe2 thin film; wherein the two parallel strip-shaped Bi / Au electrodes serve as the source and drain of the N-type WSe2 transistor respectively; obtaining a silicon wafer including a P-type WSe2 transistor and an N-type WSe2 transistor; the heavily doped conductive silicon layer in the silicon wafer serves as a common gate of the P-type WSe2 transistor and the N-type WSe2 transistor at the same time; connecting the source of the P-type WSe2 transistor and the source of the N-type WSe2 transistor to each other to form a common source and common gate structure.

2. A method for preparing a micro multifunctional artificial neuron device based on a two-dimensional WSe2 transistor as claimed in claim 1, characterized in that: In step S2, two parallel strip Au electrodes are prepared on the WSe2 film, which specifically includes the following steps: applying photoresist on the WSe2 film, obtaining two parallel strip electrode patterns through ultraviolet exposure and development, sequentially evaporating Se with a thickness of 8-15nm and Au with a thickness of 40-100nm, and after degumming treatment, removing the Se layer through vacuum drying to obtain a silicon wafer including a P-type WSe2 transistor.

3. A method for preparing a micro multifunctional artificial neuron device based on a two-dimensional WSe2 transistor as claimed in claim 1, characterized in that: In step S3, two parallel strip-shaped Bi / Au electrodes are prepared on the WSe2 thin film, which specifically includes the following steps: coating the WSe2 thin film with photoresist, obtaining two parallel strip-shaped electrode patterns through ultraviolet exposure and development, and sequentially evaporating a Bi layer with a thickness of 2-10nm and an Au layer with a thickness of 40-100nm, and obtaining a silicon wafer including a P-type WSe2 transistor and an N-type WSe2 transistor after degumming treatment.

4. A micro multifunctional artificial neuron device based on a two-dimensional WSe2 transistor obtained by the method for preparing a micro multifunctional artificial neuron device based on a two-dimensional WSe2 transistor as described in any one of claims 1 to 3, characterized in that: include: A silicon wafer composed of an insulating silicon oxide layer and a heavily doped conductive silicon layer, wherein a WSe2 film is provided on the insulating silicon oxide layer as a channel; the WSe2 film is composed of less than 10 single-layer two-dimensional WSe2 layers; Two parallel strip-shaped Au electrodes are arranged on the WSe2 film; the two parallel strip-shaped Au electrodes serve as the source and drain of the P-type WSe2 transistor respectively; the thickness of the strip-shaped Au electrodes is 40-100 nm; Two parallel strip-shaped Bi / Au electrodes are also arranged on the WSe2 film; wherein the two parallel strip-shaped Bi / Au electrodes serve as the source and drain of the N-type WSe2 transistor respectively; the Bi / Au electrode is composed of a Bi layer with a thickness of 2-10nm and an Au layer with a thickness of 40-100nm, wherein the Bi layer is located between the Au layer and the WSe2 film; The heavily doped conductive silicon layer in the silicon wafer serves as a common gate of the P-type WSe2 transistor and the N-type WSe2 transistor at the same time; the source of the P-type WSe2 transistor and the source of the N-type WSe2 transistor are connected to each other as a common source.

5. The micro multifunctional artificial neuron device based on the two-dimensional WSe2 transistor as claimed in claim 4, characterized in that: The thickness of the insulating silicon oxide layer is 260-500nm; the width of the channel between two mutually parallel strip-shaped Au electrodes is 4-7μm; the width of the channel between two mutually parallel strip-shaped Bi / Au electrodes is 4-7μm.

6. The application of the micro multifunctional artificial neuron device based on the two-dimensional WSe2 transistor as claimed in claim 4 in realizing the activation function function, characterized in that: The following steps are involved: Inputting a level signal varying between a positive level and a negative level to the common gate, wherein the positive level is not greater than 60V and the negative level is not less than -60V; The drain of the N-type WSe2 transistor is connected to a constant level signal; The drain of the P-type WSe2 transistor is grounded; a signal that changes with the common gate level is output through the common source; the relationship between the signal output by the common source and the level signal input to the common gate conforms to the functional relationship of the activation function.

7. The use according to claim 6, characterized in that The activation function is a Sigmoid function. The level signal changing between the positive level and the negative level is specifically a level signal changing from -20V to 20V, and the drain of the N-type WSe2 transistor is connected to a constant level signal of 1V.

8. The application of the micro multifunctional artificial neuron device based on the two-dimensional WSe2 transistor in realizing synaptic function as claimed in claim 4, characterized in that: The following steps are involved: Maintain a constant common source voltage, use the common gate as an electrical signal stimulation input terminal, input electrical signal stimulation, and use the leakage current of the drain of the P-type WSe2 transistor as output.

9. The application of the micro multifunctional artificial neuron device based on the two-dimensional WSe2 transistor in realizing a full hardware artificial neural network as claimed in claim 4, characterized in that: The following steps are involved: The all-hardware artificial neural network includes no less than 2 micro-multifunctional artificial neuron devices based on two-dimensional WSe2 transistors, wherein at least 1 micro-multifunctional artificial neuron device based on two-dimensional WSe2 transistors serves as an artificial neuron node device, and at least 1 micro-multifunctional artificial neuron device based on two-dimensional WSe2 transistors serves as an activation function device.

10. The use according to claim 9, characterized in that The common gate of the artificial neuron node device is used as the stimulus signal input terminal, a voltage signal in the range of 5V-30V is applied, the common source is connected to a constant level signal of 1V, and the drain of the P-type WSe2 transistor is grounded by connecting a resistor element; a node is set between the resistor element and the drain of the P-type WSe2 transistor, a lead is drawn from the node to connect the common gate of the activation function device as the input of the activation function device, and the common source of the activation function device is used as the output; the drain of the N-type WSe2 transistor of the activation function device is connected to a constant voltage level signal of 1V, and the drain of the P-type WSe2 transistor of the activation function device is grounded; When the full hardware artificial neural network includes more than one artificial neuron node device, the node between the resistance and the drain of each artificial neuron node device is connected together as the input of the activation function device to achieve parallel superposition and cumulative summation.

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