Super junction MOSFET device
By dividing the polysilicon layer into units of different resistances in the superjunction MOSFET device, and using these units to control the current respectively when on and off, the problems of stress and oscillation during use are solved, and the reduction of the current rate of change and the optimization of device performance are achieved.
Patent Information
- Application Number
- CN202411615486.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-13
- Publication Date
- 2025-02-28
AI Technical Summary
During use, super junction MOSFET devices may damage the power components due to the fast switching speed and high current change rate, resulting in stress and oscillation.
By dividing the polysilicon layer into a first polysilicon unit with a smaller resistance and a second polysilicon unit with a larger resistance, and driving current through these units when the device is on and off, the first diode and the second diode are arranged to control the current path.
It effectively reduces the current change rate of the SJ MOSFET when it is turned on, reduces the device's turn-on speed but does not reduce the shutdown speed, and improves the stress and oscillation generated during use of the device.
Smart Images
Figure CN119545848A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor power devices, and in particular to a super junction MOSFET device. Background Art
[0002] Super junction MOSFET, also known as super junction metal oxide semiconductor field effect transistor (SJ-MOSFET), is a rapidly developing and widely used new power semiconductor device. It has been widely used in power supplies or adapters for consumer electronic products such as personal computers, laptops, netbooks, mobile phones, high-pressure gas discharge lamp products, LCD TVs, plasma TVs and game consoles.
[0003] At present, due to the very fast switching speed of super junction MOSFET devices, the current change rate of the device is very high, which also causes super junction MOSFET devices to generate excessive stress during use, which may damage the power components. Summary of the invention
[0004] The present application provides a super junction MOSFET device, which can improve the stress and vibration generated during the use of the MOSFET device.
[0005] In order to achieve the above objectives, this application adopts the following technical solutions: The present application provides a super junction MOSFET device, the device comprising: A substrate, a pillar structure located on the substrate, a gate structure located on the pillar structure, and a source region formed in the pillar structure; The gate structure comprises: a gate lead and a gate region, the gate region comprises: a polysilicon layer and a metal layer located on the polysilicon layer, the polysilicon layer comprises: a first polysilicon unit and a second polysilicon unit arranged at intervals, the resistance of the first polysilicon unit is less than the resistance of the second polysilicon unit; The first ends of the first polysilicon unit and the second polysilicon unit are both connected to the gate lead, and the second ends of the first polysilicon unit and the second polysilicon unit are both connected to the metal layer; The first polysilicon unit includes a first diode, the cathode of the first diode is close to the source structure, and the second polysilicon unit includes a second diode, the anode of the second diode is close to the source region.
[0006] As a possible implementation manner, the volume of the first polysilicon unit is greater than the volume of the second polysilicon unit.
[0007] As a possible implementation manner, both the first diode and the second diode are formed by a plurality of PN junctions connected in series.
[0008] As a possible implementation manner, the pillar structure includes an oxide layer, and the polysilicon layer is disposed on the oxide layer.
[0009] As a possible implementation manner, a dielectric layer is included between the polysilicon layer and the metal layer to isolate the polysilicon layer from the metal layer.
[0010] As a possible implementation manner, the substrate has a first conductivity type, and the substrate has a first surface and a second surface opposite to each other; The device further includes a drain formed on the first surface of the substrate.
[0011] As a possible implementation manner, the column structure is disposed on the second surface of the substrate, and the column structure includes first columns having a first conductivity type and second columns having a second conductivity type, and the first columns and the second columns are arranged alternately.
[0012] As a possible implementation manner, the second pillar includes a heavily doped region of the first conductivity type, and the source region is formed in the heavily doped region.
[0013] As a possible implementation manner, the device further includes: a source metal, and the source region is connected to the source metal through a contact hole.
[0014] As a possible implementation manner, the first conductivity type is N-type, and the second conductivity type is P-type, or the first conductivity type is P-type, and the second conductivity type is N-type.
[0015] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least: A super junction MOSFET device provided in an embodiment of the present application comprises: a substrate, a column structure located on the substrate, a gate structure located on the column structure, and a source region formed in the column structure; wherein the gate structure comprises: a gate lead and a gate region, the gate region comprises: a polysilicon layer and a metal layer located on the polysilicon layer, the polysilicon layer comprises: a first polysilicon unit and a second polysilicon unit arranged at intervals, the resistance of the first polysilicon unit is less than the resistance of the second polysilicon unit; the first ends of the first polysilicon unit and the second polysilicon unit are both connected to the gate lead, and the second ends of the first polysilicon unit and the second polysilicon unit are both connected to the metal layer; the first polysilicon unit comprises a first diode, the cathode of the first diode is close to the source region, the second polysilicon unit comprises a second diode, the anode of the second diode is close to the source region. The super junction MOSFET device provided in the embodiment of the present application is achieved by dividing the polysilicon layer into a first polysilicon unit with smaller resistance and a second polysilicon unit with larger resistance, and the first ends of the first polysilicon unit and the second polysilicon unit are connected to the gate lead, the second ends of the first polysilicon unit and the second polysilicon unit are connected to the metal layer, and a first diode is arranged in the first polysilicon unit, and a second diode is arranged in the second polysilicon unit, and the cathode of the first diode is close to the source region, and the anode of the second diode is close to the source region. In this way, when the super junction MOSFET device is turned on, the driving current can go through the second polysilicon unit with larger resistance, and when the device is turned off, the driving current can go through the polysilicon unit with smaller resistance. In this way, the current change rate of the SJ MOSFET when it is turned on can be effectively reduced, and the turn-on speed of the device can be reduced, but the turn-off speed of the device will not be reduced. At the same time, the stress and oscillation generated by the device during use can be improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 A schematic diagram of a plane section of a polysilicon layer of a super junction MOSFET device provided in an embodiment of the present application; Figure 2 A schematic diagram of a longitudinal section of a super junction MOSFET device at a first polysilicon unit provided in an embodiment of the present application.
[0017] Reference numerals: 1-substrate, 2-first column, 3-second column, 4-source region, 5-drain, 6-source metal, 7-contact hole, 8-oxide layer, 9-first polysilicon unit, 10-metal layer, 11-first diode, 12-gate lead, 13-second polysilicon unit, 14-second diode. DETAILED DESCRIPTION
[0018] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0019] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
[0020] It should be understood that when an element or layer is referred to as being “on,” “adjacent to,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers.
[0021] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner, and therefore the illustrations only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0022] The present application embodiment provides a super junction MOSFET device, such as Figure 1 and Figure 2 As shown, the device comprises: A substrate 1, a pillar structure located on the substrate 1, a gate structure located on the pillar structure, and a source region 4 formed in the pillar structure; The gate structure includes: a gate lead 12 and a gate region, the gate region includes: a polysilicon layer and a metal layer 10 located on the polysilicon layer, the polysilicon layer includes: a first polysilicon unit 9 and a second polysilicon unit 13 arranged at intervals, and the resistance of the first polysilicon unit 9 is smaller than the resistance of the second polysilicon unit 13; The first ends of the first polysilicon unit 9 and the second polysilicon unit 13 are both connected to the gate lead 12, and the second ends of the first polysilicon unit 9 and the second polysilicon unit 13 are both connected to the metal layer 10; The first polysilicon unit 9 includes a first diode 11 , the cathode of the first diode 11 is close to the source region 4 , and the second polysilicon unit 13 includes a second diode 14 , the anode of the second diode 14 is close to the source region 4 .
[0023] It should be noted that Figure 1 This is a schematic diagram of a plane section of a superjunction MOSFET device on a polysilicon layer. Figure 2 FIG. 1 is a schematic diagram of a longitudinal section of a super junction MOSFET device at the first polysilicon unit 9. The longitudinal section of the super junction MOSFET device at the second polysilicon unit 13 can be referred to FIG. Figure 2 , except that the direction of the second diode 14 in the second polysilicon unit 13 is opposite to the direction of the first diode 11 in the first polysilicon unit 9.
[0024] The super junction MOSFET device provided in the embodiment of the present application is achieved by dividing the polysilicon layer into a first polysilicon unit 9 with a smaller resistance and a second polysilicon unit 13 with a larger resistance, and the first ends of the first polysilicon unit 9 and the second polysilicon unit 13 are connected to the gate lead 12, the second ends of the first polysilicon unit 9 and the second polysilicon unit 13 are connected to the metal layer 10, and a first diode 11 is arranged in the first polysilicon unit 9, and a second diode 14 is arranged in the second polysilicon unit 13, and the cathode of the first diode 11 is close to the source region 4, and the anode of the second diode 14 is close to the source region 4. In this way, when the super junction MOSFET device is turned on, the driving current can go through the second polysilicon unit 13 with a larger resistance, and when the device is turned off, the driving current can go through the polysilicon unit with a smaller resistance. In this way, the current change rate of the SJ MOSFET when it is turned on can be effectively reduced, and the turn-on speed of the device can be reduced, but the turn-off speed of the device will not be reduced. At the same time, the stress and oscillation generated by the device during use can be improved.
[0025] Optionally, the first ends of the first polysilicon unit 9 and the second polysilicon unit 13 are connected to the gate lead 12 through the contact hole 7 , and the second ends of the first polysilicon unit 9 and the second polysilicon unit 13 are connected to the metal layer 10 through the contact hole 7 .
[0026] Optionally, the volume of the first polysilicon unit 9 is larger than the volume of the second polysilicon unit 13. By providing a larger first polysilicon unit 9 and a smaller second polysilicon unit 13, the resistance of the first polysilicon unit 9 can be made smaller than the resistance of the second polysilicon unit 13.
[0027] In the actual preparation process, the polysilicon layer may be etched into a wider first polysilicon unit 9 and a narrower second polysilicon unit 13 , so that the resistance of the first polysilicon unit 9 can be smaller than the resistance of the second polysilicon unit 13 .
[0028] In addition, the width and length of the first polysilicon unit 9 and the second polysilicon unit 13 are easily adjusted, so that the device on-resistance and off-resistance can have a variety of different combinations.
[0029] Optionally, both the first diode 11 and the second diode 14 are formed by a plurality of PN junctions connected in series.
[0030] In the actual preparation process, N injection and P injection can be performed in the first polysilicon unit 9 and the second polysilicon unit 13 respectively, and two layers of mask plates can be added during the injection process, so that the first diode 11 structure and the second diode 14 structure can be formed, except that the cathode of the first diode 11 is close to the source region 4, and the anode of the second diode 14 is close to the source region 4.
[0031] Optionally, the pillar structure includes an oxide layer 8, and the polysilicon layer is disposed on the oxide layer 8. A dielectric layer is included between the polysilicon layer and the metal layer 10, for isolating the polysilicon layer from the metal layer 10.
[0032] Optionally, the substrate 1 has a first conductivity type, and the substrate 1 has a first surface and a second surface opposite to each other; the device further includes a drain 5 formed on the first surface of the substrate 1 .
[0033] Wherein, the substrate 1 has a first conductivity type, and the substrate 1 has a first surface and a second surface opposite to each other. The substrate 1 is used as a carrier of the super junction MOSFET and mainly plays a supporting role. The material of the substrate 1 can be a silicon substrate, a germanium substrate, or a germanium silicon substrate, etc. In this embodiment, the material of the substrate 1 is preferably a silicon substrate, and silicon is the most common, cheap and stable semiconductor material.
[0034] Optionally, the column structure is disposed on the second surface of the substrate 1 , and the column structure includes first columns 2 having a first conductivity type and second columns 3 having a second conductivity type, and the first columns 2 and the second columns 3 are alternately arranged.
[0035] The first conductivity type is N-type, and the second conductivity type is P-type, or the first conductivity type is P-type, and the second conductivity type is N-type.
[0036] It is understandable that the material of the first column 2 may be silicon, and the material of the second column 3 may be SiC. The height of the first column 2 and the second column 3 is the same. Optionally, the doping concentration of the first column 2 and the second column 3 may be 1×10 14 ~8×10 15 cm -3 .
[0037] In addition, the minority carrier lifetime of the column of the super junction MOSFET can be 0.1μs to 100μs, for example, it can be 0.1μs, 0.5μs, 1μs, 5μs, 10μs, 20μs, 30μs, 40μs, 50μs, 60μs, 70μs, 80μs, 90μs or 100μs.
[0038] Among them, minority carriers are minority carriers, as opposed to majority carriers. There are two types of carriers in semiconductor materials: electrons and holes. If a certain type of carrier is in the minority in semiconductor materials and plays a minor role in conduction, it is called minority carrier. For example, in N-type semiconductors, holes are minority carriers and electrons are majority carriers; in P-type semiconductors, holes are majority carriers and electrons are minority carriers.
[0039] Optionally, the second pillar 3 includes a heavily doped region of the first conductivity type, and the source region 4 is formed in the heavily doped region. Optionally, the device further includes: a source metal 6 , and the source region 4 is connected to the source metal 6 through a contact hole 7 .
[0040] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
[0041] In addition, those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the above claims, any one of the claimed embodiments may be used in any combination. The information disclosed in this background technology section is intended only to deepen the understanding of the overall background technology of the present application and should not be regarded as an admission or in any form of implication that the information constitutes prior art known to those skilled in the art.
Claims
1. A super junction MOSFET device, characterized in that: The device comprises: A substrate, a pillar structure located on the substrate, a gate structure located on the pillar structure, and a source region formed in the pillar structure; The gate structure comprises: a gate lead and a gate region, the gate region comprises: a polysilicon layer and a metal layer located on the polysilicon layer, the polysilicon layer comprises: a first polysilicon unit and a second polysilicon unit arranged at intervals, the resistance of the first polysilicon unit is less than the resistance of the second polysilicon unit; The first ends of the first polysilicon unit and the second polysilicon unit are both connected to the gate lead, and the second ends of the first polysilicon unit and the second polysilicon unit are both connected to the metal layer; The first polysilicon unit includes a first diode, the cathode of the first diode is close to the source region, and the second polysilicon unit includes a second diode, the anode of the second diode is close to the source region.
2. The device according to claim 1, characterized in that The volume of the first polysilicon unit is greater than the volume of the second polysilicon unit.
3. The device according to claim 1, characterized in that The first diode and the second diode are both formed by a plurality of PN junctions connected in series.
4. The device according to claim 1, characterized in that The column structure includes an oxide layer, and the polysilicon layer is arranged on the oxide layer.
5. The device according to claim 1, characterized in that A dielectric layer is included between the polysilicon layer and the metal layer, for isolating the polysilicon layer from the metal layer.
6. The device according to claim 1, characterized in that The substrate has a first conductivity type, and the substrate has a first surface and a second surface opposite to each other; The device further includes a drain formed on the first surface of the substrate.
7. The device according to claim 6, characterized in that The column structure is disposed on the second surface of the substrate, and includes first columns having a first conductivity type and second columns having a second conductivity type, wherein the first columns and the second columns are alternately arranged.
8. The device according to claim 7, characterized in that The second pillar includes a heavily doped region of the first conductivity type, and the source region is formed in the heavily doped region.
9. The device according to claim 1, characterized in that The device further comprises: a source metal, and the source region is connected to the source metal through a contact hole.
10. The device according to claim 7, characterized in that The first conductivity type is N type and the second conductivity type is P type, or the first conductivity type is P type and the second conductivity type is N type.