Thin film transistor and preparation method thereof, array substrate, display panel and display device

Abstract

The invention provides a thin film transistor and a preparation method thereof, an array substrate, a display panel and a display device. The thin film transistor comprises a substrate, a first electrode, a first insulating layer, a second electrode, an active layer, a second insulating layer and a control electrode. The first pole is arranged on one side of the substrate, the first insulating layer is arranged on one side, away from the substrate, of the first pole and comprises a first hole, the first pole is at least partially exposed in the first hole, and the second pole is arranged on one side, away from the substrate, of the first insulating layer. The active layer is arranged on the sides, away from the substrate, of the first electrode and the second electrode and connected between the first electrode and the second electrode, the active layer is partially attached to the side wall of the first hole in the circumferential direction of the first hole, and the second insulating layer is arranged on the side, away from the substrate, of the active layer and partially attached to the side wall of the first hole. The control electrode is arranged on the side, away from the substrate, of the second insulating layer. And the orthographic projection part of the second pole on the substrate surrounds the orthographic projection of the first hole on the substrate.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to a thin film transistor and a preparation method thereof, an array substrate, a display panel, and a display device. Background Art

[0002] With the diversification of consumer market demands, consumers have higher and higher requirements for display devices. For most consumers, high-resolution and high-refresh-rate displays can bring smoother gaming and visual experiences. In order to achieve higher-specification display effects, higher requirements are placed on the performance of thin-film transistor devices in the array substrate that drives the panel display. Summary of the invention

[0003] The embodiments of the present application provide a thin film transistor and a manufacturing method thereof, an array substrate, a display panel, and a display device, which can improve display uniformity.

[0004] In a first aspect, an embodiment of the present application provides a thin film transistor, the thin film transistor comprising a substrate, a first electrode, a first insulating layer, a second electrode, an active layer, a second insulating layer and a control electrode. The first electrode is arranged on one side of the substrate, the first insulating layer is arranged on a side of the first electrode away from the substrate and comprises a first hole, the first electrode is at least partially exposed to the first hole, and the second electrode is arranged on a side of the first insulating layer away from the substrate.

[0005] The active layer is arranged on the side of the first pole and the second pole away from the substrate, and is connected between the first pole and the second pole. The active layer is partially aligned with the side wall of the first hole in the circumferential direction of the first hole. The second insulating layer is arranged on the side of the active layer away from the substrate, and is partially aligned with the side wall of the first hole. The control pole is arranged on the side of the second insulating layer away from the substrate. The orthographic projection of the second pole on the substrate surrounds the orthographic projection of the first hole on the substrate.

[0006] In some embodiments, the active layer includes a first portion connected to the first pole, a second portion connected to the second pole, and a third portion connected between the first portion and the second portion;

[0007] The third portion is disposed in contact with a portion of the side wall of the first hole;

[0008] In some embodiments, the third portion at least partially overlaps the control electrode in the radial direction of the first hole;

[0009] In some embodiments, an orthographic projection of the second portion on the substrate is located within an orthographic projection of the second pole on the substrate;

[0010] In some embodiments, the control electrode portion is located on a side of the second portion away from the substrate;

[0011] In some embodiments, an orthographic projection of the second portion on the substrate is at least partially located outside an orthographic projection of the control electrode on the substrate;

[0012] In some embodiments, the material of the first pole includes metallic titanium, and the material of the second pole includes metallic molybdenum.

[0013] In some embodiments, the sidewall includes a first wall portion and a second wall portion disposed opposite to each other in a first direction, and the first direction is parallel to a plane where the substrate is located;

[0014] The third part is disposed in close contact with the first wall portion, and the first part is disposed in close contact with the first wall portion and is spaced apart from the second wall portion in the first direction;

[0015] In some embodiments, the second pole is located on a side of the first wall portion away from the second wall portion;

[0016] In some embodiments, the second insulating layer is disposed in close contact with the second wall portion;

[0017] In some embodiments, the second insulating layer is disposed in close contact with a portion of the structure in the first electrode.

[0018] In some embodiments, the orthographic projection of the first hole on the substrate is located outside the orthographic projection of the control electrode on the substrate;

[0019] In some embodiments, the control electrode and the second wall portion are spaced apart in the first direction;

[0020] In some embodiments, the first electrode includes a first portion exposed to the first hole, and an orthographic projection of the first portion on the substrate is located outside an orthographic projection of the control electrode on the substrate.

[0021] In some embodiments, the orthographic projection of the first hole on the substrate is partially located outside the orthographic projection of the first pole on the substrate;

[0022] In some embodiments, the first pole and the second wall portion are spaced apart in the first direction;

[0023] In some embodiments, the control electrode portion is located on a side of the first electrode close to the second wall portion;

[0024] In some embodiments, an orthographic projection of the first portion on the substrate is located within an orthographic projection of the first pole on the substrate.

[0025] In some embodiments, an orthographic projection of the first pole on the substrate is outside an orthographic projection of the second pole on the substrate;

[0026] In some embodiments, the first pole is located on a side of the first wall portion facing the second wall portion, and the first pole and the first wall portion are spaced apart in the first direction to form a gap space;

[0027] In some embodiments, the active layer includes a fourth portion located in the gap space, and the fourth portion is connected to the first electrode.

[0028] In a second aspect, an embodiment of the present application provides an array substrate, the array substrate comprising a thin film transistor in any of the aforementioned embodiments.

[0029] In a third aspect, an embodiment of the present application provides a display panel, and the display panel includes an array substrate as described in any of the aforementioned embodiments.

[0030] In a fourth aspect, an embodiment of the present application provides a display device, wherein the display panel includes a display panel as in any of the aforementioned embodiments.

[0031] In a fifth aspect, an embodiment of the present application provides a method for preparing a thin film transistor, comprising:

[0032] Forming a first electrode and a first initial insulating layer covering the first electrode in sequence on one side of the substrate;

[0033] An initial electrode is formed on the side of the first initial insulating layer facing away from the substrate, wherein the initial electrode comprises a second hole, and an orthographic projection of the second hole on the substrate overlaps with an orthographic projection of the first electrode on the substrate;

[0034] Performing a hole digging process on the first initial insulating layer at a position corresponding to the second hole to form a first hole connected to the second hole, wherein the first electrode is at least partially exposed to the first hole;

[0035] Removing the structure of the initial electrode at a portion of the outer periphery of the first hole to form a second electrode;

[0036] An active layer is formed on the side of the first pole and the second pole facing away from the substrate, the active layer is connected to the first pole and the second pole, and is arranged in contact with a portion of the side wall of the first hole;

[0037] A second insulating layer and a control electrode are sequentially formed on the side of the active layer away from the substrate, and the second insulating layer is disposed in contact with a portion of the side wall of the first hole.

[0038] The embodiments of the present application provide a thin film transistor and a manufacturing method thereof, an array substrate, a display panel, and a display device, wherein the shape and size of the active layer and the second electrode are adjusted so that the drain region in the active layer and the orthographic projection of the second electrode on the substrate are only partially arranged around the orthographic projection of the first hole on the substrate. This design helps to reduce the overlapping area of ​​the second electrode and the drain region in the active layer relative to at least one of the first electrode or the control electrode, thereby reducing the size of the parasitic capacitance, thereby reducing signal delay, and improving display uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] Figure 1 It is a schematic diagram of a cross-sectional structure of a thin film transistor in the related art;

[0041] Figure 2 is a schematic structural diagram of a thin film transistor provided in an embodiment of the present application;

[0042] Figure 3 yes Figure 2 Schematic diagram of the cross-sectional structure at AA in the middle;

[0043] Figure 4 is a schematic cross-sectional structure diagram of another thin film transistor provided in an embodiment of the present application;

[0044] Figure 5 is a schematic cross-sectional structure diagram of another thin film transistor provided in an embodiment of the present application;

[0045] Figure 6 is a schematic cross-sectional structure diagram of another thin film transistor provided in an embodiment of the present application;

[0046] Figure 7 is a structural schematic diagram of a display device provided in an embodiment of the present application;

[0047] Figure 8 is a flow chart of a method for preparing a thin film transistor provided in an embodiment of the present application;

[0048] Figures 9a to 9f It is a process structure schematic diagram of a method for preparing a thin film transistor provided in an embodiment of the present application.

[0049] Marking Description:

[0050] 10. Substrate;

[0051] 20. First Pole; 21. First Division;

[0052] 30. first insulating layer; 31. first hole; 311. side wall;

[0053] 40. second pole; 41. second hole;

[0054] 50. active layer; 51. first part; 52. second part; 53. third part; 54. fourth part;

[0055] 60. A second insulating layer;

[0056] 70. Control pole;

[0057] 81, source; 82, drain; 83, gate;

[0058] 30', first initial insulating layer; 40', initial electrode;

[0059] B1, first wall portion; B2, second wall portion;

[0060] X, first direction. DETAILED DESCRIPTION

[0061] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0062] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0063] In high refresh rate, low energy consumption, and demultiplexing drive products, thin film transistors need to have a larger on-state current to meet the charging rate requirements, or reduce the size of thin film transistors to achieve narrow borders and high transmittance. Short channel technology can greatly increase the on-state current of the device and reduce the size of the device. If the channel is reduced to within 1 micron, the on-state current can be increased by more than 4 times compared to conventional thin film transistors.

[0064] See also Figure 1In the related art, the channel structure in the thin film transistor can be set as a vertical channel, which can greatly reduce the channel size and improve the current passing capacity of the thin film transistor per unit area. However, in this scheme, the overlapping area between the source 81, the drain 82 and the gate 83 in the thin film transistor is large, and a large overlapping area will produce a large parasitic capacitance. The presence of parasitic capacitance will increase the signal delay of the signal line, resulting in uneven display or reduced brightness, and it is also easy to increase power consumption, which is not conducive to long-term use.

[0065] Regarding the above issues, please refer to Figure 2 and Figure 3 The embodiment of the present application provides a thin film transistor, which includes a substrate 10, a first electrode 20, a first insulating layer 30, a second electrode 40, an active layer 50, a second insulating layer 60, and a control electrode 70. The first electrode 20 is disposed on one side of the substrate 10, the first insulating layer 30 is disposed on the side of the first electrode 20 away from the substrate 10 and includes a first hole 31, the first electrode 20 is at least partially exposed to the first hole 31, and the second electrode 40 is disposed on the side of the first insulating layer 30 away from the substrate 10.

[0066] The active layer 50 is arranged on the side of the first pole 20 and the second pole 40 away from the substrate 10, and is connected between the first pole 20 and the second pole 40. The active layer 50 is partially aligned with the side wall 311 of the first hole 31 in the circumferential direction of the first hole 31. The second insulating layer 60 is arranged on the side of the active layer 50 away from the substrate 10, and is partially aligned with the side wall 311 of the first hole 31. The control pole 70 is arranged on the side of the second insulating layer 60 away from the substrate 10. The orthographic projection of the second pole 40 on the substrate 10 partially surrounds the orthographic projection of the first hole 31 on the substrate 10.

[0067] A thin film transistor is a transistor made of thin film materials. It is an insulated gate effect transistor, mainly composed of a conductive structure and a semiconductor structure. The conductive structure includes a first electrode 20, a second electrode 40 and a control electrode 70, and the semiconductor structure includes an active layer 50. The first insulating layer 30 and the second insulating layer 60 are used to insulate and separate different conductive structures and semiconductor structures.

[0068] Optionally, the control electrode 70 is a gate electrode in a thin film transistor, one of the first electrode 20 and the second electrode 40 is a source electrode in the thin film transistor, and the other is a drain electrode in the thin film transistor. Since the first electrode 20 is located on the side of the active layer 50 facing the substrate 10, the first electrode 20 can not only serve as a source electrode or a drain electrode, but also play a light shielding role to reduce the part of the ambient light passing through the first electrode 20 to irradiate the active layer 50 and affect the structural stability of the active layer 50, thereby improving the overall structural stability of the thin film transistor.

[0069] The substrate 10 is a film layer structure used to support the thin film transistor. The substrate 10 may include various materials, such as glass, metal or plastic. Optionally, the substrate 10 may include a flexible material. The flexible material mentioned here refers to a material that can be twisted, bent, folded or curled. The flexible material may include ultra-thin glass, metal or plastic.

[0070] The first pole 20 is arranged on one side of the substrate 10, the first insulating layer 30 is arranged on the side of the first pole 20 facing away from the substrate 10, and the second pole 40 is arranged on the side of the first insulating layer 30 facing away from the substrate 10. The first pole 20 and the second pole 40 are both conductive, and the first insulating layer 30 can insulate and separate the first pole 20 from the second pole 40. There can be multiple positional relationships between the first pole 20 and the first insulating layer 30. Specifically, the first insulating layer 30 includes a first hole 31, and the orthographic projection of the first pole 20 on the substrate 10 can completely cover the orthographic projection of the first hole 31 on the substrate 10, or the orthographic projection of the first hole 31 on the substrate 10 can also completely cover the orthographic projection of the first pole 20 on the substrate 10, or the orthographic projection of the first hole 31 on the substrate 10 can also be partially located within the orthographic projection of the first pole 20 on the substrate 10, as long as the first pole 20 is at least partially exposed to the first hole 31.

[0071] The active layer 50 is disposed on the side of the first electrode 20 and the second electrode 40 facing away from the substrate 10, and is connected to the first electrode 20 and the second electrode 40. The active layer 50 includes a semiconductor material. Further, the active layer 50 includes a channel region corresponding to the control electrode 70 and a source region and a drain region located on different sides of the channel region. One of the source region and the drain region is connected to the first electrode 20, and the other is connected to the second electrode 40. For the convenience of description, the embodiments of the present application are described below by taking the first electrode 20 connected to the source region and the second electrode 40 connected to the drain region as an example.

[0072] In order to meet the connection requirements of the active layer 50 with the first pole 20 and the second pole 40, the active layer 50 needs to partially penetrate into the first hole 31 and connect with the partial structure of the first pole 20 exposed to the first hole 31. On this basis, the active layer 50 also needs to extend along the sidewall 311 of the first hole 31 to the side of the first insulating layer 30 and the second pole 40 away from the substrate 10, and connect with the second pole 40.

[0073] The second insulating layer 60 is used to insulate and separate the control electrode 70 from the active layer 50, the first electrode 20 and the second electrode 40, and the control electrode 70 is located on the side of the second insulating layer 60 away from the substrate 10. In this case, the control electrode 70 will overlap with the active layer 50 in the radial direction of the first hole 31, and the part of the active layer 50 that is arranged in contact with the side wall 311 of the first hole 31 is the channel region of the active layer 50.

[0074] Next, the working process of the thin film transistor will be described in the embodiment of the present application. After the voltage is applied to the control electrode 70, the partial structure of the active layer 50 opposite to the control electrode 70, that is, the partial structure of the active layer 50 that is arranged in contact with the side wall 311 of the first hole 31, will form a channel region for carrier migration. Specifically, when the thin film transistor is working, the control electrode 70 is applied with voltage and generates an electric field. The direction of the electric field is directed from the control electrode 70 to the surface of the channel region of the active layer 50, and induced charges are generated on the surface. As the voltage of the control electrode 70 increases, the surface of the channel region will be transformed from a depletion layer to an electron accumulation layer, forming an inversion layer. When the voltage of the control electrode 70 reaches the threshold voltage, a voltage is applied between the source region and the drain region, and carriers will pass through the channel region.

[0075] In the related art, the active layer 50 will completely surround and adhere to the side wall 311 of the first hole 31 in the circumferential direction of the first hole 31, and the second pole 40 will be completely arranged around the outer circumferential side of the first hole 31, that is, the outer contour of the orthographic projection of the part of the structure of the active layer 50 located in the first hole 31 on the substrate 10 will coincide with the orthographic projection of the first hole 31 on the substrate 10, and the orthographic projection of the second pole 40 on the substrate 10 will completely surround the orthographic projection of the first hole 31 on the substrate 10. In this case, the structures of the second pole 40 located at various positions in the circumferential direction of the first hole 31 will overlap with the orthographic projection of at least one of the first pole 20 and the control pole 70 on the substrate 10, thereby causing a large parasitic capacitance, generating a large signal delay, and affecting display uniformity.

[0076] In the embodiment of the present application, in order to reduce the existence of parasitic capacitance, the active layer 50 and the second pole 40 are adjusted. Specifically, for the second pole 40, the orthographic projection of the second pole 40 on the substrate 10 is only partially arranged around the orthographic projection of the first hole 31 on the substrate 10, that is, the second pole 40 is not completely arranged around the first hole 31, and the second pole 40 does not exist at some positions of the first hole 31 in the circumferential direction.

[0077] For the active layer 50, the active layer 50 and the side wall 311 of the first hole 31 are partially fitted in the circumferential direction of the first hole 31. The "partially fitted" mentioned here means that the active layer 50 and the side wall 311 of the first hole 31 are fitted at some positions in the circumferential direction, and the two are not in contact at other positions in the circumferential direction. Under this design, the first insulating layer 30 is partially fitted with the side wall 311 of the first hole 31, and the drain region in the active layer 50 is only partially arranged around the orthographic projection of the first hole 31 on the substrate 10, rather than completely surrounding the first hole 31.

[0078] In summary, in the embodiment of the present application, by adjusting the shape and size of the active layer 50 and the second electrode 40, the drain region in the active layer 50 and the orthographic projection of the second electrode 40 on the substrate 10 are only partially arranged around the orthographic projection of the first hole 31 on the substrate 10. This design helps to reduce the overlapping area of ​​the second electrode 40 and the drain region in the active layer 50 relative to at least one of the first electrode 20 or the control electrode 70, thereby reducing the size of the parasitic capacitance, thereby reducing signal delay and improving display uniformity.

[0079] In some embodiments, Figure 3 As shown, the active layer 50 includes a first portion 51 connected to the first pole 20, a second portion 52 connected to the second pole 40, and a third portion 53 connected between the first portion 51 and the second portion 52, and the third portion 53 is arranged to fit a portion of the side wall 311 of the first hole 31.

[0080] The first portion 51 is used to connect the first electrode 20, that is, the first portion 51 is a source region in the active layer 50. The second portion 52 is used to connect the second electrode 40, that is, the second portion 52 is a drain region in the active layer 50. The third portion 53 is connected between the first portion 51 and the second portion 52, that is, the third portion 53 is a channel region in the active layer 50. Further optionally, in the radial direction of the first hole 31, the third portion 53 at least partially overlaps with the control electrode 70.

[0081] In the related art, the orthographic projection of the third portion 53 on the substrate 10 is usually a closed annular structure, but in the embodiment of the present application, the third portion 53 is only arranged in affixed with a portion of the side wall 311 of the first hole 31, that is, the orthographic projection of the third portion 53 on the substrate 10 is not a closed annular structure, and the embodiment of the present application does not limit the specific size relationship between the third portion 53 and the side wall 311 of the first hole 31. Exemplarily, within the range of 360° in the circumferential direction of the first hole 31, the third portion 53 can be arranged in affixed with the side wall 311 of the first hole 31 within a range of one of 45°, 90°, 150°, 180° and 270°.

[0082] In some embodiments, an orthographic projection of the second portion 52 on the substrate 10 is located within an orthographic projection of the second pole 40 on the substrate 10 .

[0083] Similar to the second pole 40, the overlapping arrangement of the second portion 52 relative to at least one of the first pole 20 and the control pole 70 will also generate parasitic capacitance. Therefore, in order to reduce the parasitic capacitance, the above-mentioned embodiment arranges the third portion 53 to fit partially with the side wall 311 of the first hole 31, so that the second portion 52 connected to the third portion 53 only surrounds a portion of the outer peripheral side of the first hole 31, thereby reducing the overlapping area of ​​the third portion 53 relative to at least one of the first pole 20 and the control pole 70.

[0084] Furthermore, the embodiment of the present application further limits the size corresponding to the second portion 52 so that its orthographic projection on the substrate 10 is located within the orthographic projection of the second pole 40 on the substrate 10, thereby further reducing the impact of the existence of the second portion 52 on the parasitic capacitance, reducing signal delay, and improving display uniformity.

[0085] The embodiment of the present application does not limit the positional relationship between the control electrode 70 and the second portion 52. In some embodiments, the control electrode 70 is partially located on a side of the second portion 52 away from the substrate 10. Further optionally, the orthographic projection of the second portion 52 on the substrate 10 is at least partially located outside the orthographic projection of the control electrode 70 on the substrate 10.

[0086] In the embodiment of the present application, the relative position relationship between the control electrode 70 and the second portion 52 can be adjusted, or the size and shape of the control electrode 70 can be adjusted, so that the orthographic projection of the second portion 52 on the substrate 10 is at least partially located outside the orthographic projection of the control electrode 70 on the substrate 10, thereby reducing the overlapping area corresponding to the second portion 52 and the control electrode 70, reducing the parasitic capacitance and the corresponding signal delay, and helping to improve display uniformity. Similarly, optionally, the orthographic projection of the second electrode 40 on the substrate 10 is partially located outside the orthographic projection of the control electrode 70 on the substrate 10.

[0087] The material composition of the first pole 20 and the second pole 40 is not limited in the embodiments of the present application. Optionally, the material of the first pole 20 includes metallic titanium, and the material of the second pole 40 includes metallic molybdenum. Under the same etching medium and etching conditions, the etching rates of metallic titanium and metallic molybdenum are not the same. Specifically, the etching rate of metallic titanium is lower than the etching rate of metallic molybdenum. Furthermore, this design can enable the first pole 20 to withstand etching during the etching process corresponding to the second pole 40, thereby improving the structural integrity of the first pole 20 and improving the corresponding preparation reliability and preparation yield of the thin film transistor.

[0088] In some optional embodiments, the material of the first electrode 20 may include only metal titanium, or the first electrode 20 may be a three-layer metal structure composed of titanium / aluminum / titanium. Similarly, the material of the second electrode 40 may include only metal molybdenum, or the second electrode 40 may be a three-layer metal structure composed of molybdenum aluminum / molybdenum.

[0089] In some embodiments, the sidewall 311 includes a first wall portion B1 and a second wall portion B2 that are oppositely disposed in a first direction X, and the first direction X is parallel to the plane where the substrate 10 is located. The third portion 53 is disposed in contact with the first wall portion B1, and the first portion 51 is disposed in contact with the first wall portion B1 and is spaced apart from the second wall portion B2 in the first direction X.

[0090] The first wall portion B1 and the second wall portion B2 are different parts of the side wall 311, wherein the first wall portion B1 is a part of the side wall 311 that is aligned with the active layer 50, and the second wall portion B2 is a part of the side wall 311 that is not aligned with the active layer 50. Further, the second wall portion B2 may be aligned with the second insulating layer 60.

[0091] The first wall portion B1 and the second wall portion B2 have various shapes and positional relationships. For example, the first hole 31 is a square hole or other polygonal hole, in which case the first wall portion B1 and the second wall portion B2 are both straight, and the first wall portion B1 and the second wall portion B2 are spaced apart from each other, with other wall structures between them. Alternatively, the first hole 31 may also be a circular hole, in which case the first wall portion B1 and the second wall portion B2 are both arc-shaped, and the first wall portion B1 and the second wall portion B2 may be connected to each other.

[0092] It should be noted that the first wall portion B1 and the second wall portion B2 may have various size relationships. For example, the size of the first wall portion B1 may be equal to the size of the second wall portion B2, or the size of the first wall portion B1 may be smaller than or larger than the size of the second wall portion B2.

[0093] In combination with the above content, it can be known that the first part 51 is the source region in the active layer 50, the second part 52 is the drain region in the active layer 50, and the third part 53 is the channel region in the active layer 50. In the related art, the source region of the active layer 50 is in contact with different positions of the side wall 311 at both ends parallel to the plane direction of the substrate 10. In the embodiment of the present application, the first part 51 is only arranged in contact with the first wall B1, and is spaced from the second wall B2, that is, the active layer 50 will not extend along the second wall B2, so that no channel region will be formed at the corresponding position of the second wall B2, and then no drain region structure arranged around the outer peripheral side of the second wall B2 will be formed, so that the corresponding size of the second part 52 can be reduced, and the overlapping area of ​​the second part 52 relative to at least one of the first pole 20 and the control pole 70 can be reduced, signal delay can be reduced, and display uniformity can be improved.

[0094] In some embodiments, the second pole 40 is located on a side of the first wall portion B1 away from the second wall portion B2 .

[0095] In the embodiment of the present application, the second electrode 40 is not completely arranged to surround the first hole 31, but is only arranged correspondingly on the side of the first wall portion B1 away from the second wall portion B2, and there is no second electrode 40 on the side of the second wall portion B2 away from the first wall portion B1. This design can reduce the overlapping area of ​​the second electrode 40 relative to at least one of the first electrode 20 and the control electrode 70 on the substrate 10, reduce signal delay, and improve display uniformity.

[0096] In some embodiments, Figure 3 As shown, the second insulating layer 60 is disposed in close contact with the second wall portion B2.

[0097] In the embodiment of the present application, the active layer 50 will not extend along the second wall portion B2, that is, the active layer 50 will not form a channel region at the position corresponding to the second wall portion B2. On this basis, the second insulating layer 60 can be arranged in contact with the second wall portion B2, thereby achieving a covering and protective effect on the side wall 311 of the first hole 31.

[0098] In some embodiments, the second insulating layer 60 is disposed in close contact with a portion of the structure in the first electrode 20 .

[0099] In the related art, the surface of the first electrode 20 facing away from the substrate 10 is covered by the first insulating layer 30 and the active layer 50, so that the second insulating layer 60 is completely separated from the first electrode 20. However, in the embodiment of the present application, due to the adjustment of the size and shape of the active layer 50, the surface of the first electrode 20 facing away from the substrate 10 cannot be completely covered by the active layer 50 and the first insulating layer 30. On this basis, the second insulating layer 60 can be arranged in a fit with part of the structure in the first electrode 20, so as to achieve the insulation protection effect of the first electrode 20 with the help of the second insulating layer 60, and improve the reliability of the thin film transistor.

[0100] In some embodiments, see Figure 4 The orthographic projection of the first hole 31 on the substrate 10 is located outside the orthographic projection of the control electrode 70 on the substrate 10 .

[0101] In addition to adjusting the structures of the second electrode 40 and the active layer 50, the structural size of the control electrode 70 can also be adjusted. Specifically, in the related art, the orthographic projection of the control electrode 70 on the substrate 10 usually completely covers the orthographic projection of the first hole 31 on the substrate 10. In the embodiment of the present application, the size of the control electrode 70 is limited and reduced, so that the orthographic projection of the first hole 31 on the substrate 10 is located outside the orthographic projection of the control electrode 70 on the substrate 10, that is, the orthographic projection of the control electrode 70 on the substrate 10 does not completely cover the first hole 31. Optionally, the control electrode 70 and the second wall portion B2 are spaced apart in the first direction X.

[0102] In this design, the orthographic projection of the partial structure of the first electrode 20 corresponding to the first hole 31 on the substrate 10 can be partially located outside the orthographic projection of the control electrode 70 on the substrate 10, thereby reducing the orthographic projection area of ​​the first electrode 20 and the control electrode 70 on the substrate 10, reducing signal delay, and improving display uniformity. Further optionally, the first electrode 20 includes a first sub-portion 21 exposed to the first hole 31, and the orthographic projection of the first sub-portion 21 on the substrate 10 is partially located outside the orthographic projection of the control electrode 70 on the bottom.

[0103] In some embodiments, see Figure 5 The orthographic projection portion of the first hole 31 on the substrate 10 is located outside the orthographic projection of the first pole 20 on the substrate 10 .

[0104] Similar to the above-mentioned embodiment, in addition to adjusting the structures of the second pole 40 and the active layer 50, the structural size of the first pole 20 can also be adjusted. Specifically, in the related art, the orthographic projection of the first pole 20 on the substrate 10 usually completely covers the orthographic projection of the first hole 31 on the substrate 10. In the embodiment of the present application, the size of the first pole 20 is limited and reduced, so that the orthographic projection of the first hole 31 on the substrate 10 is located outside the orthographic projection of the first pole 20 on the substrate 10, that is, the orthographic projection of the first pole 20 on the substrate 10 does not completely cover the first hole 31. Optionally, the first pole 20 and the second wall portion B2 are spaced apart in the first direction X.

[0105] In this design, the orthographic projection of the portion of the structure of the control electrode 70 corresponding to the first hole 31 on the substrate 10 can be partially located outside the orthographic projection of the first electrode 20 on the substrate 10, thereby reducing the orthographic projection area of ​​the first electrode 20 and the control electrode 70 on the substrate 10, reducing signal delay, and improving display uniformity. Further optionally, the control electrode 70 is partially located on the side of the first electrode 20 close to the second wall portion B2.

[0106] It should be noted that the embodiment of the present application does not limit the positional relationship of the first portion 51 in the active layer 50 relative to the first pole 20, and the positional relationship of the second pole 40 relative to the first pole 20. Optionally, the orthographic projection of the first portion 51 on the substrate 10 is located within the orthographic projection of the first pole 20 on the substrate 10.

[0107] In some embodiments, see Figure 6 , the orthographic projection of the first pole 20 on the substrate 10 is located outside the orthographic projection of the second pole 40 on the substrate 10 .

[0108] In the embodiment of the present application, by reducing the size of the first pole 20, the orthographic projection of the first pole 20 on the substrate 10 can be located outside the orthographic projection of the second pole 40 on the substrate 10, thereby eliminating the overlapping area between the first pole 20 and the second pole 40, thereby reducing signal delay and improving display uniformity.

[0109] In some embodiments, the first pole 20 is located on a side of the first wall portion B1 facing the second wall portion B2 , and the first pole 20 and the first wall portion B1 are spaced apart in the first direction X to form a gap space.

[0110] In combination with the above content, it can be known that the first pole 20 can be arranged around the first wall portion B1 and located on the side of the first wall portion B1 away from the second wall portion B2. On this basis, in the embodiment of the present application, the first pole 20 is arranged to be spaced apart from the first wall portion B1, so that the orthographic projection of the first pole 20 on the substrate 10 is located outside the orthographic projection of the second pole 40 on the substrate 10, thereby eliminating the overlapping area generated between the first pole 20 and the second pole 40, thereby reducing signal delay and improving display uniformity.

[0111] Further optionally, the active layer 50 includes a fourth portion 54 located in the gap space, and the fourth portion 54 is connected to the first pole 20 .

[0112] In the embodiment of the present application, the fourth portion 54 in the active layer 50 can fill the gap space and contact and connect with the first pole 20. This design can increase the contact area between the active layer 50 and the first pole 20, thereby improving the connection reliability between the active layer 50 and the first pole 20.

[0113] In a second aspect, an embodiment of the present application provides an array substrate, the array substrate comprising a thin film transistor in any of the aforementioned embodiments.

[0114] It should be noted that the array substrate provided in the embodiment of the present application has the beneficial effects of the thin film transistor in any of the aforementioned embodiments. Please refer to the aforementioned description of the beneficial effects of the thin film transistor for details, and the embodiment of the present application will not be repeated.

[0115] In addition, the array substrate may have a display area and a frame area located around the display area, wherein the array substrate may include a pixel circuit located in the display area and a drive circuit located in the frame area. On this basis, the thin film transistor provided in the embodiment of the present application may be used only in the pixel circuit, or only in the drive circuit, or simultaneously in the pixel circuit and the drive circuit, and the embodiment of the present application does not limit this.

[0116] In a third aspect, an embodiment of the present application provides a display panel, and the display panel includes an array substrate as described in any of the aforementioned embodiments.

[0117] It should be noted that the display panel in the embodiment of the present application can be a variety of types of display panels, for example, it can be a liquid crystal display panel including a liquid crystal layer, or it can be an organic light-emitting display panel including organic light-emitting materials, or it can be an inorganic light-emitting display panel including inorganic light-emitting materials.

[0118] Fourth, please refer to Figure 7 An embodiment of the present application provides a display device, wherein the display panel includes a display panel as in any of the aforementioned embodiments.

[0119] Fifth, please refer to Figure 8 9 , the present application embodiment provides a method for manufacturing a thin film transistor, including:

[0120] S100: forming a first electrode and a first initial insulating layer covering the first electrode in sequence on one side of the substrate.

[0121] In step S100, refer to Figure 9a The first electrode 20 can be a source or drain of a thin film transistor, and the first initial insulating layer 30' includes an insulating material for subsequently forming the first insulating layer 30. The first initial insulating layer 30' is arranged to cover the first electrode 20, that is, the orthographic projection of the first electrode 20 on the substrate 10 is located within the orthographic projection of the first initial insulating layer 30' on the substrate 10.

[0122] S110: forming an initial electrode on a side of the first initial insulating layer facing away from the substrate.

[0123] In step S110, refer to Figure 9b The initial electrode 40' is used to subsequently form the second electrode 40, and the initial electrode 40' includes a second hole 41, and the orthographic projection of the second hole 41 on the substrate 10 overlaps with the orthographic projection of the first electrode 20 on the substrate 10. There may be multiple positions between the initial electrode 40' and the second electrode 40, for example, the orthographic projection of the initial electrode 40' on the substrate 10 may overlap with the orthographic projection of the second electrode 40 on the substrate 10, or the orthographic projection of the initial electrode 40' on the substrate 10 may be located outside the orthographic projection of the second electrode 40 on the substrate 10.

[0124] S120: performing a hole digging process on the first initial insulating layer at a position corresponding to the second hole.

[0125] In step S120, refer to Fig.9c , the first initial insulating layer is processed by digging a hole, so that the first initial insulating layer is transformed into the first insulating layer 30, and a first hole 31 connected to the second hole 41 is formed in the first insulating layer 30. Further, since the orthographic projection of the second hole 41 on the substrate 10 overlaps with the orthographic projection of the first pole 20 on the substrate 10, the orthographic projection of the first hole 31 formed by the second hole 41 on the substrate 10 also overlaps with the orthographic projection of the first pole 20 on the substrate 10, that is, the first pole 20 is at least partially exposed to the first hole 31.

[0126] S130: removing the structure of the initial electrode located at a portion of the outer periphery of the first hole.

[0127] In step S130, refer to Figure 9dThe second electrode 40 is formed by removing part of the structure in the initial electrode, wherein one of the first electrode 20 and the second electrode 40 is the source electrode in the thin film transistor, and the other is the drain electrode in the thin film transistor.

[0128] S140: forming an active layer on a side of the first pole and the second pole facing away from the substrate.

[0129] In step S140, refer to Fig.9e , the active layer 50 is connected to the first electrode 20 and the second electrode 40, and is partially laminated with the side wall 311 of the first hole 31. In the related art, the active layer 50 will completely surround and laminate with the side wall 311 of the first hole 31 in the circumferential direction of the first hole 31, and the second electrode 40 will completely surround the outer peripheral side of the first hole 31. In the embodiment of the present application, the second electrode 40 is only arranged to surround a portion of the outer peripheral side of the first hole 31, and the active layer 50 and the side wall 311 of the first hole 31 are partially laminated in the circumferential direction of the first hole 31. This design helps to reduce the overlapping area of ​​the drain region in the second electrode 40 and the active layer 50 relative to at least one of the first electrode 20 or the control electrode 70 formed subsequently, thereby reducing the size of the parasitic capacitance, thereby reducing signal delay and improving display uniformity.

[0130] S150: forming a second insulating layer and a control electrode in sequence on a side of the active layer facing away from the substrate.

[0131] In step S150, refer to Figure 9f The second insulating layer 60 is disposed in contact with a portion of the side wall 311 of the first hole 31 .

[0132] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted for facilitating the understanding of this application and are not intended to limit the present invention. Any technician in the technical field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be subject to the scope defined in the attached claims.

[0133] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the replacement of other connection methods described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of the present application.

Claims

1. A thin film transistor, characterized in that: include: substrate; A first electrode is arranged on one side of the substrate; A first insulating layer, disposed on a side of the first electrode away from the substrate and comprising a first hole, wherein the first electrode is at least partially exposed to the first hole; A second electrode is arranged on a side of the first insulating layer away from the substrate; An active layer is arranged on a side of the first pole and the second pole away from the substrate and connected between the first pole and the second pole, wherein the active layer is partially attached to the side wall of the first hole in a circumferential direction of the first hole; A second insulating layer is disposed on a side of the active layer away from the substrate and is disposed in contact with a portion of the side wall of the first hole; A control electrode, arranged on a side of the second insulating layer away from the substrate; The orthographic projection of the second pole on the substrate surrounds the orthographic projection of the first hole on the substrate.

2. The thin film transistor according to claim 1, characterized in that: The active layer includes a first portion connected to the first pole, a second portion connected to the second pole, and a third portion connected between the first portion and the second portion; The third portion is disposed in contact with a portion of the side wall of the first hole; Preferably, in the radial direction of the first hole, the third portion at least partially overlaps with the control electrode; Preferably, the orthographic projection of the second portion on the substrate is located within the orthographic projection of the second pole on the substrate; Preferably, the control electrode portion is located on a side of the second portion away from the substrate; Preferably, the orthographic projection of the second portion on the substrate is at least partially located outside the orthographic projection of the control electrode on the substrate; Preferably, the material of the first pole includes metal titanium, and the material of the second pole includes metal molybdenum.

3. The thin film transistor according to claim 2, characterized in that: The side wall comprises a first wall portion and a second wall portion which are arranged opposite to each other in a first direction, wherein the first direction is parallel to the plane where the substrate is located; The third portion is disposed in close contact with the first wall portion, and the first portion is disposed in close contact with the first wall portion and is spaced apart from the second wall portion in the first direction; Preferably, the second pole is located on a side of the first wall portion away from the second wall portion; Preferably, the second insulating layer is disposed in close contact with the second wall portion; Preferably, the second insulating layer is arranged in close contact with a part of the structure in the first pole.

4. The thin film transistor according to claim 3, characterized in that: The orthographic projection of the first hole on the substrate is located outside the orthographic projection of the control electrode on the substrate; Preferably, the control electrode and the second wall portion are spaced apart in the first direction; Preferably, the first electrode includes a first portion exposed to the first hole, and an orthographic projection portion of the first portion on the substrate is located outside the orthographic projection of the control electrode on the substrate.

5. The thin film transistor according to claim 3, characterized in that: The orthographic projection of the first hole on the substrate is located outside the orthographic projection of the first pole on the substrate; Preferably, the first pole and the second wall portion are spaced apart in the first direction; Preferably, the control electrode portion is located on a side of the first electrode close to the second wall portion; Preferably, an orthographic projection of the first portion on the substrate is located within an orthographic projection of the first pole on the substrate.

6. The thin film transistor according to claim 5, characterized in that: The orthographic projection of the first pole on the substrate is located outside the orthographic projection of the second pole on the substrate; Preferably, the first pole is located on a side of the first wall portion facing the second wall portion, and the first pole and the first wall portion are spaced apart in the first direction to form a gap space; Preferably, the active layer includes a fourth portion located in the gap space, and the fourth portion is connected to the first pole.

7. An array substrate, characterized in that: Comprising the thin film transistor according to any one of claims 1 to 6.

8. A display panel, characterized in that: Comprising the array substrate as claimed in claim 7.

9. A display device, characterized in that: Comprising the display panel as claimed in claim 8.

10. A method for preparing a thin film transistor, characterized in that: include: Forming a first electrode and a first initial insulating layer covering the first electrode in sequence on one side of the substrate; An initial electrode is formed on a side of the first initial insulating layer away from the substrate, the initial electrode comprising a second hole, and an orthographic projection of the second hole on the substrate overlaps with an orthographic projection of the first electrode on the substrate; Performing a hole digging process on the first initial insulating layer at a position corresponding to the second hole to form a first hole connected to the second hole, wherein the first electrode is at least partially exposed to the first hole; Removing the structure of the initial electrode at a portion of the outer periphery of the first hole to form a second electrode; An active layer is formed on a side of the first pole and the second pole away from the substrate, the active layer is connected to the first pole and the second pole, and is disposed in contact with a portion of the side wall of the first hole; A second insulating layer and a control electrode are sequentially formed on a side of the active layer away from the substrate, and the second insulating layer is disposed in contact with a portion of the side wall of the first hole.

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