Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof. The semiconductor element comprises a first oxide layer and a gate structure. The first oxide layer is disposed on a substrate. The gate structure is arranged on the first oxide layer, the gate structure comprises a gate and a gap wall, the gap wall surrounds the gate, the first oxide layer comprises an exposed section which is not covered by the gate structure, the thickness of the first oxide layer under the gate is fixed, and the thickness of the first oxide layer under the gate is larger than that of the exposed section.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a semiconductor element with an oxide layer having an asymmetric cross-section and a manufacturing method thereof. Background Art

[0002] In the manufacture of medium and high voltage integrated circuits, double-diffusion drain MOS (DDDMOS) is often used to provide a larger output current. However, when the operating voltage is high, DDDMOS is prone to gate induced drain leakage (GIDL), which greatly limits the application of DDDMOS.

[0003] Therefore, how to improve the structure and manufacturing method of DDDMOS to reduce the probability of GIDL has become an important issue for relevant industry players. Summary of the invention

[0004] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same to solve the above-mentioned problem.

[0005] According to one embodiment of the present invention, a semiconductor element is provided, comprising a first oxide layer and a gate structure. The first oxide layer is disposed on a substrate. The gate structure is disposed on the first oxide layer, wherein the gate structure comprises a gate and a spacer, the spacer surrounds the gate, the first oxide layer comprises an exposed segment not covered by the gate structure, the thickness of the first oxide layer directly below the gate is fixed, and the thickness of the first oxide layer directly below the gate is greater than the thickness of the exposed segment.

[0006] According to another embodiment of the present invention, a method for manufacturing a semiconductor device is provided, comprising the following steps. A thermal oxidation process is performed to form an oxide layer on a substrate, wherein the oxide layer includes a first oxide layer and a second oxide layer, and the thickness of the first oxide layer is greater than the thickness of the second oxide layer. A gate structure is formed on the oxide layer, wherein the gate structure partially covers the first oxide layer, and the first oxide layer includes an exposed segment that is not covered by the gate structure. A portion of the exposed segment is removed so that the thickness of the exposed segment is less than the thickness of the portion of the first oxide layer outside the exposed segment.

[0007] Compared to the prior art, the present invention provides an asymmetric cross-section of the first oxide layer by including an exposed section that is not covered by the gate structure, which is beneficial for increasing the distance between the gate structure and the drain region and reducing the probability of GIDL occurrence, so that the semiconductor element can withstand higher voltage and has the advantage of power saving, thereby helping to expand its application range. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 is a schematic cross-sectional view of steps for manufacturing a semiconductor element according to one embodiment of the present invention;

[0009] Figure 7 It is a schematic cross-sectional view of a semiconductor element according to another embodiment of the present invention.

[0010] Main component symbols

[0011] 1.1a: Semiconductor components

[0012] 10: Base

[0013] 10a, 220a, 230a, 310a, 320a, 330a: top surface

[0014] 110, 112: Insulation structure

[0015] 110a, 112a: inner surface

[0016] 120: First lightly doped drain region

[0017] 122: Second lightly doped drain region

[0018] 130: Well region

[0019] 140: Source region

[0020] 142, 142a: drain region

[0021] 143a: Drain extension

[0022] 200: Patterned material layer

[0023] 210: Opening area

[0024] 211: Left edge

[0025] 212: Right edge

[0026] 220: First Materials Department

[0027] 230: Second Materials Department

[0028] 300: Oxide layer

[0029] 310: First oxide layer

[0030] 311, 312: Side

[0031] 310b: Bottom surface

[0032] 320, 330: Second oxide layer

[0033] 340, 350: Bird beak structure

[0034] 400: Gate structure

[0035] 402: Outside edge

[0036] 410: Gate

[0037] 411: Side surface

[0038] 420: Spacer

[0039] 421, 422: Sidewall

[0040] 510, 520: Metal silicide

[0041] D1: Horizontal direction

[0042] D2: Vertical direction

[0043] H1, H2: Maximum height

[0044] L1, L2: distance

[0045] O: Centerline

[0046] P: exposed segment

[0047] P1: The first ion implantation process

[0048] P2: Thermal Oxidation Process

[0049] P3: Second ion implantation process

[0050] T0, T1, T2, T3: thickness

[0051] W1, W2, W3, W4: Width DETAILED DESCRIPTION

[0052] The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the accompanying drawings. In order to make the contents of the present invention clearer and easier to understand, the following drawings may be simplified schematic diagrams, and the elements therein may not be drawn to scale. In addition, the number and size of each element in the drawings are for illustration only and are not intended to limit the present invention. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, back, bottom, top, etc., are only for reference to the directions of the accompanying drawings. Therefore, the directional terms used are for illustration, not for limitation of the present invention. In addition, in the following embodiments, the same or similar elements will use the same or similar reference numerals.

[0053] The description below regarding “a first feature is formed on or above a second feature” may refer to “the first feature is in direct contact with the second feature” or “there are other features between the first feature and the second feature” such that the first feature and the second feature are not in direct contact with each other.

[0054] The present invention uses the terms "first", "second", etc. to describe elements, regions, layers, and / or sections, but it should be understood that these terms are only used to distinguish a certain element, region, layer, and / or section from another element, region, layer, and / or section, and they do not imply or represent any previous ordinal number of the element, nor do they represent the arrangement order of a certain element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, region, layer, and / or section discussed below may also be referred to as the second element, region, layer, and / or section. These terms in the claims may not be the same as those in the specification, but may be replaced by "first", "second", "third", etc. according to the order of the elements declared in the claims.

[0055] Please refer to Figures 1 to 6 , which is a cross-sectional schematic diagram of the steps of manufacturing a semiconductor device according to one embodiment of the present invention. Figure 1 As shown, a substrate 10 is first provided. The substrate 10 may be a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate or a silicon on insulator (SOI) substrate. Then, at least one shallow trench isolation (STI) structure surrounding each active region is formed in the substrate 10, such as Figure 1 The two insulating structures 110 and 112 in the substrate 10 may be the left and right parts of a shallow trench isolation structure, and the area between the two insulating structures 110 and 112 may be an active region. The materials of the insulating structures 110 and 112 are, for example, silicon dioxide. Next, one or more first ion implantation processes P1 are performed to form a well region 130 in the substrate 10, and to form a first lightly doped drain region 120 and a second lightly doped drain region 122 separated from each other in the substrate 10. The first lightly doped drain region 120 and the second lightly doped drain region 122 have the same conductivity type, and the conductivity type of the well region 130 is different from the conductivity type of the first lightly doped drain region 120 and the second lightly doped drain region 122. For example, when the well region 130 is an N-type well region, the well region 130 may be doped with N-type dopants, such as arsenic, phosphorus, etc. At this time, the first lightly doped drain region 120 and the second lightly doped drain region 122 may be doped with P-type dopants, such as boron, indium, etc. For another example, when the well region 130 is a P-type well region, the well region 130 may be doped with P-type dopants, such as boron, indium, etc. At this time, the first lightly doped drain region 120 and the second lightly doped drain region 122 may be doped with N-type dopants, such as arsenic, phosphorus, etc.

[0056] The first lightly doped drain region 120 is disposed adjacent to the insulating structure 110 and in direct contact with the insulating structure 110, and the second lightly doped drain region 122 is disposed adjacent to the insulating structure 112 and in direct contact with the insulating structure 112. The width W2 of the second lightly doped drain region 122 is greater than the width W1 of the first lightly doped drain region 120. In detail, the insulating structures 110 and 112 define a center line O, and the cross-sections of the first lightly doped drain region 120 and the second lightly doped drain region 122 are configured to be asymmetric relative to the center line O. The center line O may be a line connecting all midpoints of the inner surface 110a of the insulating structure 110 and the inner surface 112a of the insulating structure 112 in the horizontal direction D1. The widths W1 and W2 may be the maximum widths of the first lightly doped drain region 120 and the second lightly doped drain region 122 parallel to the horizontal direction D1.

[0057] Then, if Figure 2 As shown, a patterned material layer 200 is formed on the substrate 10, wherein the patterned material layer 200 has an opening area 210. For example, a material layer (not shown) may be first formed on the substrate 10, and then a hard mask (not shown) may be formed on the material layer, and a portion of the material layer may be removed by using semiconductor manufacturing processes such as photolithography and etching to obtain the patterned material layer 200 having the opening area 210. The material of the patterned material layer 200 may be a nitride, such as silicon nitride. As long as the oxidation rate is lower than that of the material of the substrate 10, it can be used as the material of the patterned material layer 200.

[0058] In detail, the patterned material layer 200 includes a first material portion 220 and a second material portion 230. The first material portion 220, the opening region 210, and the second material portion 230 are sequentially disposed on the substrate 10 along the horizontal direction D1. The first material portion 220 covers the insulating structure 110 and a portion of the first lightly doped drain region 120, and the second material portion 230 covers the insulating structure 112 and a portion of the second lightly doped drain region 122.

[0059] The opening region 210 is located between the first material portion 220 and the second material portion 230, and exposes the remaining portion of the first lightly doped drain region 120 and the remaining portion of the second lightly doped drain region 122. A distance L1 between a left edge 211 of the opening region 210 and the central axis O in the horizontal direction D1 is smaller than a distance L2 between a right edge 212 of the opening region 210 and the central axis O in the horizontal direction D1. In other words, the setting position of the opening region 210 is asymmetric relative to the central line O.

[0060] Then, if Figure 3As shown, a thermal oxidation process P2 is performed to form an oxide layer 300 on the substrate 10. The oxide layer 300 includes a first oxide layer 310 and two second oxide layers 320 and 330, and the thickness T1 of the first oxide layer 310 is greater than the thickness T2 of the second oxide layers 320 and 330. The first oxide layer 310 corresponds to the opening area 210, and the second oxide layers 320 and 330 are formed by oxidation of the patterned material layer 200. For example, the thermal oxidation process P2 can be performed in an oxygen-containing environment, and the oxygen-containing environment can be achieved by passing oxygen or an oxygen-containing gas (such as water vapor) into the process chamber of the thermal oxidation process P2. According to one embodiment of the present invention, the thermal oxidation process P2 may include an in-situ steam generation (ISSG) oxidation process, a wet furnace oxidation process, or a dry furnace oxidation process, but is not limited thereto.

[0061] In the thermal oxidation process P2, the surface layer (not separately labeled) of the substrate 10 corresponding to the opening area 210 is oxidized to form a first oxide layer 310, the first material portion 220 of the patterned material layer 200 is oxidized to form a second oxide layer 320, and the second material portion 230 of the patterned material layer 200 is oxidized to form a second oxide layer 330. Since the opening area 210 is disposed asymmetrically relative to the center line O, the first oxide layer 310 is also disposed asymmetrically relative to the center line O.

[0062] Since the oxidation rate of the substrate 10 is greater than the oxidation rate of the patterned material layer 200, the thickness T1 of the first oxide layer 310 is greater than the thickness T2 of the second oxide layers 320 and 330. According to one embodiment of the present invention, the oxidation rate of the substrate 10 and the oxidation rate of the patterned material layer 200 are greater than 2 (that is, the oxidation rate selectivity of the substrate 10 and the patterned material layer 200 is greater than 2), for example, it can be equal to 10. According to one embodiment of the present invention, the thickness T1 of the first oxide layer 310 can be greater than 300 angstroms, and the thickness T2 of the second oxide layers 320 and 330 can be greater than 0 angstroms and less than or equal to 300 angstroms. However, the present invention is not limited to this, and a material having an appropriate oxidation rate selectivity with the substrate 10 can be selected as the material of the patterned material layer 200, and the thickness T0 of the patterned material layer 200 can be controlled (see Figure 2 ) and the parameters of the thermal oxidation process P2 to adjust the thickness T1 of the first oxide layer 310 and the thickness T2 of the second oxide layers 320 and 330.

[0063] In the thermal oxidation process P2, oxygen atoms in the oxygen-containing gas will enter the substrate 10 and combine with silicon in the substrate 10 to form silicon oxide. After the thermal oxidation process P2, the top surface 310a of the first oxide layer 310 will be slightly higher than the top surface 10a of the substrate 10 before the thermal oxidation process P2 (see Figure 2), the bottom surface 310b of the first oxide layer 310 is slightly lower than the top surface 10a of the substrate 10 before the thermal oxidation process P2 (see Figure 2 In the thermal oxidation process P2, oxygen atoms in the oxygen-containing gas may enter the patterned material layer 200 to replace other atoms, and the top surface 320a of the second oxide layer 320 and the top surface 330a of the second oxide layer 330 may be slightly higher, slightly lower, or substantially flush with the top surface 220a of the first material portion 220 before the thermal oxidation process P2 (see Figure 2 ) and the top surface 230a of the second material portion 230 (see Figure 2 ), depending on the volume size of the oxygen atoms and the other atoms. According to one embodiment of the present invention, the patterned material layer 200 may be silicon nitride. After the thermal oxidation process P2, the nitrogen atoms in the silicon nitride may be completely or partially replaced by oxygen atoms. When the nitrogen atoms in the silicon nitride are completely replaced by oxygen atoms, the silicon nitride may be converted into silicon oxide. At this time, the second oxide layer 320, 330 is the same material as the first oxide layer 310, both of which are silicon oxide. When the nitrogen atoms in the silicon nitride are partially replaced by oxygen atoms, the silicon nitride may be converted into silicon nitride oxide. At this time, the second oxide layer 320, 330 is different from the first oxide layer 310 in material. Here, the example that the second oxide layer 320, 330 is the same material as the first oxide layer 310 is used, so Figure 3 The dotted lines are used to distinguish different regions in the oxide layer 300 (eg, the first oxide layer 310 , the second oxide layers 320 , 330 , and the bird's beak structures 340 , 350 ).

[0064] Since the oxidation rate of the substrate 10 is different from the oxidation rate of the patterned material layer 200, a bird's beak structure 340 is formed at the connection between the first oxide layer 310 and the second oxide layer 320, and a bird's beak structure 350 is formed at the connection between the first oxide layer 310 and the second oxide layer 330. In other words, the oxide layer 300 further includes two bird's beak structures 340 and 350 extending integrally on the two sides 311 and 312 of the first oxide layer 310, respectively. The thickness of the bird's beak structure 340 (not separately labeled) gradually changes (here gradually decreases) from the first oxide layer 310 to the second oxide layer 320, and the thickness of the bird's beak structure 350 (not separately labeled) gradually changes (here gradually decreases) from the first oxide layer 310 to the second oxide layer 330. According to one embodiment of the present invention, the materials of the first oxide layer 310, the second oxide layers 320, 330, and the bird's beak structures 340 and 350 are all silicon oxide. In addition, at this stage, the first oxide layer 310 refers to a portion of the oxide layer 300 having a uniform or substantially fixed thickness T1, the second oxide layers 320 and 330 refer to portions of the oxide layer 300 having a uniform or substantially fixed thickness T2, the bird's beak structure 340 is a portion located between the first oxide layer 310 and the second oxide layer 320 and having a gradient thickness, and the bird's beak structure 350 is a portion located between the first oxide layer 310 and the second oxide layer 330 and having a gradient thickness, such as Figure 3 That is, in this stage, the first oxide layer 310 has a uniform or substantially constant thickness T1, and the second oxide layers 320 and 330 have a uniform or substantially constant thickness T2.

[0065] Then, if Figure 4 As shown, a gate structure 400 is formed on the oxide layer 300, wherein the gate structure 400 partially covers the first oxide layer 310, and the first oxide layer 310 includes an exposed section P that is not covered by the gate structure 400. In addition, the second lightly doped drain region 122 is located below the exposed section P. Forming the gate structure 400 on the oxide layer 300 includes forming the gate 410 on the oxide layer 300, and forming a spacer 420 to surround the gate 410. For example, a deposition process can be performed to deposit a gate material on the oxide layer 300, and then a patterning process can be used to remove part of the gate material to form the gate 410. The material of the gate 410 can include a non-metallic conductive material, such as polysilicon. Then, a spacer 420 is formed to surround the gate 410, and the material of the spacer 420 can each independently include an oxide and / or a nitride, such as silicon dioxide, silicon nitride, silicon oxynitride, or silicon carbide nitride.

[0066] like Figure 4As shown, the gate 410 is disposed on the first oxide layer 310, and a side 311 of the first oxide layer 310 away from the exposed section P is flush with the side surface 411 of the gate 410. The spacer 420 has two side walls 421 and 422 opposite to each other, wherein one side wall 421 is disposed above the bird's beak structure 340, and the other side wall 422 is disposed above the first oxide layer 310. Since the thickness of the bird's beak structure 340 gradually changes from the first oxide layer 310 to the second oxide layer 320, the maximum height H1 of the side wall 421 is different from the maximum height H2 of the side wall 422. Here, the maximum height H1 of the side wall 421 is greater than the maximum height H2 of the side wall 422, that is, the cross-section of the side wall 421 and the side wall 422 is configured to be asymmetric relative to the center line O. The sidewall 422 is disposed adjacent to the exposed section P, and the ratio (W3 / W4) of the width W3 of the exposed section P to the width W4 of the sidewall 422 may be greater than or equal to 2, for example, the ratio of the width W3 to the width W4 may be 2 to 3. The aforementioned width W4 may be the maximum width of the sidewall 422 parallel to the horizontal direction D1.

[0067] The first oxide layer 310 directly below the gate 410 has a uniform thickness T1, that is, the thickness T1 of the first oxide layer 310 directly below the gate 410 is fixed. The aforementioned "the thickness T1 of the first oxide layer 310 directly below the gate 410 is fixed" means that the thickness T1 of the first oxide layer 310 directly below the gate 410 is substantially fixed, that is, the thickness T1 of the first oxide layer 310 at different positions directly below the gate 410 is roughly the same, but there may be a small error due to manufacturing process factors or other factors, and the difference between the thickness T1 at different positions and the predetermined thickness T1 size may be less than or equal to 20%, for example.

[0068] Of the two bird's beak structures 340 and 350, the bird's beak structure 340 is completely covered by the gate structure 400 and is located below the sidewall 421 of the spacer 420, while the bird's beak structure 350 is not covered by the gate structure 400 and is located outside the other sidewall 422 of the spacer 420 and integrally extends from the exposed section P of the first oxide layer 310. Figure 4 As shown, the two bird's beak structures 340 , 350 and the gate 410 do not overlap in the vertical direction D2 .

[0069] Then, if Figure 5As shown, one or more cleaning steps can be used to completely remove the second oxide layers 320 and 330, so that the area of ​​the substrate 10 originally covered by the second oxide layers 320 and 330 is exposed. In the process of removing the second oxide layers 320 and 330, a portion of the exposed section P is removed at the same time, so that the thickness T3 of the exposed section P is less than the thickness T1 of the first oxide layer 310 outside the exposed section P. The portion of the first oxide layer 310 outside the exposed section P includes the portion of the first oxide layer 310 located directly under the gate 410 and the portion of the first oxide layer 310 located directly under the sidewall 422 of the spacer 420. The difference between the thickness T1 and the thickness T3 (i.e., T1-T3) is approximately equal to the thickness T2 of the second oxide layers 320 and 330. In other words, the first oxide layer 310 has an asymmetric cross-section.

[0070] Next, please continue to refer to Figure 5 , a second ion implantation process P3 is performed to form a source region 140 and a drain region 142 in the region of the substrate 10 corresponding to the original location of the second oxide layers 320 and 330, wherein the drain region 142 is adjacent to the exposed section P. The first lightly doped drain region 120 surrounds the source region 140, and the second lightly doped drain region 122 surrounds the drain region 142. The conductivity type of the source region 140 and the drain region 142 is the same as that of the first lightly doped drain region 120 and the second lightly doped drain region 122, but the doping concentration of the source region 140 and the drain region 142 is higher than that of the first lightly doped drain region 120 and the second lightly doped drain region 122. In other embodiments, the second ion implantation process P3 may be performed first, and then the second oxide layers 320 and 330 may be removed, and the second oxide layers 320 and 330 may be used to protect the top surface 10a of the substrate 10 during the second ion implantation process P3.

[0071] Then, if Figure 6 As shown, a self-aligned silicide process can be performed to form metal silicides 510 and 520 respectively above the source region 140 and the drain region 142. For example, a metal layer (not shown) can be formed to cover the source region 140 and the drain region 142, and then a heat treatment process is used to react the silicon in the source region 140 and the drain region 142 that is in direct contact with the metal layer to form metal silicides 510 and 520. How to form the metal silicides 510 and 520 is well known in the art and will not be described in detail here.

[0072] Although not shown in the figure, the non-metallic conductive material of the gate 410 can be replaced with a single-layer structure or a multi-layer structure containing a metal conductive material by using a metal gate replacement (RMG) manufacturing process according to actual needs. The aforementioned single-layer structure may only include a low-impedance metal layer, and the material of the low-impedance metal layer can be selected from copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP) or a combination thereof. The aforementioned multi-layer structure can be formed by a low-impedance metal layer and a high dielectric constant dielectric layer and / or a barrier layer and / or a work function metal layer. The metal gate replacement manufacturing process is well known in the art and will not be described in detail here.

[0073] The above-mentioned film layers, such as the patterned material layer 200, the gate 410, the spacer 420, etc., can be formed by any suitable method, such as but not limited to molecular beam epitaxy (MBE), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD), etc.

[0074] Please refer to Figure 6 , Figure 6 A cross-sectional view of a semiconductor device 1 according to an embodiment of the present invention is shown. The semiconductor device 1 is a double diffused drain metal oxide half field effect transistor.

[0075] The semiconductor device 1 includes a substrate 10, a first oxide layer 310, and a gate structure 400. The first oxide layer 310 is disposed on the substrate 10, and the gate structure 400 is disposed on the first oxide layer 310, wherein the gate structure 400 includes a gate 410 and a spacer 420, the spacer 420 surrounds the gate 410, the first oxide layer 310 includes an exposed section P that is not covered by the gate structure 400, the thickness T1 of the first oxide layer 310 directly below the gate 410 is fixed (that is, substantially fixed), and the thickness T1 of the first oxide layer 310 directly below the gate 410 is greater than the thickness T3 of the exposed section P. By providing the exposed section P, the first oxide layer 310 has an asymmetric cross-section, which is beneficial to increase the distance between the gate structure 400 and the drain region 142, and is beneficial to reduce the probability of GIDL, so that the semiconductor device 1 can withstand a higher voltage and has the advantage of power saving, thereby helping to expand its application range. For example, it can be applied to a display device with an always on display (AOD) function, or a virtual reality (VR) device or an augmented reality (AR) device that requires low power consumption.

[0076] In the semiconductor device 1 , the ratio of the width W3 of the exposed section P to the width W4 of the sidewall 422 of the spacer 420 may be greater than or equal to 2. For example, the ratio of the width W3 to the width W4 may be 2 to 3.

[0077] In the semiconductor device 1 , a side 311 of the first oxide layer 310 away from the exposed section P is aligned with a side surface 411 of the gate 410 . Thus, the first oxide layer 310 below the gate 410 has a uniform thickness, which is beneficial to improving the electrical performance of the semiconductor device 1 .

[0078] The semiconductor device 1 further includes insulating structures 110, 112, a well region 130, a first lightly doped drain region 120, a second lightly doped drain region 122, a source region 140, a drain region 142, and metal silicides 510, 520. The well region 130 is formed in the substrate 10, and the first lightly doped drain region 120 and the second lightly doped drain region 122 are formed in the substrate 10 and are respectively located on both sides of the gate structure 400. The second lightly doped drain region 122 is located below the exposed section P, and the width W2 of the second lightly doped drain region 122 is greater than the width W1 of the first lightly doped drain region 120. The source region 140 and the drain region 142 are respectively located on both sides of the gate structure 400, wherein the drain region 142 is adjacent to the exposed section P. The first lightly doped drain region 120 surrounds the source region 140, and the second lightly doped drain region 122 surrounds the drain region 142.

[0079] The semiconductor device 1 further includes two bird's beak structures 340 and 350, which are integrally extended on the two sides 311 and 312 of the first oxide layer 310, respectively, and the two bird's beak structures 340 and 350 do not overlap with the gate 410 in the vertical direction D2. One of the bird's beak structures 340 is located below the side wall 421 of the spacer 420, and the other bird's beak structure 350 is located outside the other side wall 422 of the spacer 420. Thus, the bird's beak structures 340 and 350 with gradually varying thickness are avoided from being arranged directly below the gate 410, which is beneficial to improving the electrical performance of the semiconductor device 1.

[0080] Please refer to Figure 7 , which is a cross-sectional view of a semiconductor device 1a according to another embodiment of the present invention. The difference between the semiconductor device 1a and the semiconductor device 1 is mainly that the second ion implantation process P3 (refer to Figure 5 ), the implantation energy of the second ion implantation process P3 is adjusted so that the drain region 142a can extend to the bottom of the exposed section P to form a drain extension 143a. Specifically, the implantation energy of the second ion implantation process P3 can be increased so that the ions can pass through the exposed section P and enter the substrate 10 below the exposed section P. At the same time, the gate structure 400 blocks the ions from entering the substrate 10 below the gate structure 400. Therefore, a portion of the drain region 142a (i.e., the drain extension 143a) is located below the exposed section P and is aligned with the outer edge 402 of the gate structure 400. By providing the exposed section P, the first oxide layer 310 has an asymmetric cross-section, which is beneficial to increase the distance between the gate structure 400 and the drain region 142a.

[0081] Compared with the prior art, the present invention has a first oxide layer including an exposed segment not covered by the gate structure, which is beneficial to increase the distance between the gate structure and the drain region, thereby reducing the probability of GIDL, allowing the semiconductor element to withstand higher voltage and have the advantage of power saving, thereby helping to expand its application range.

[0082] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device comprising: A first oxide layer is disposed on the substrate; and A gate structure is arranged on the first oxide layer, wherein the gate structure includes a gate and a spacer, the spacer surrounds the gate, the first oxide layer includes an exposed segment not covered by the gate structure, the thickness of the first oxide layer directly below the gate is fixed, and the thickness of the first oxide layer directly below the gate is greater than the thickness of the exposed segment.

2. The semiconductor device according to claim 1, further comprising: The first lightly doped drain region and the second lightly doped drain region are respectively located at two sides of the gate structure. 3 . The semiconductor device as claimed in claim 2 , wherein the second lightly doped drain region is located below the exposed segment, and a width of the second lightly doped drain region is greater than a width of the first lightly doped drain region.

4. The semiconductor device according to claim 2, further comprising: The source region and the drain region are respectively located at two sides of the gate structure, wherein the drain region is adjacent to the exposed section. 5 . The semiconductor device as claimed in claim 4 , wherein a portion of the drain region is located below the exposed segment and is aligned with an outer edge of the gate structure. 6 . The semiconductor device as claimed in claim 4 , wherein the first lightly doped drain region surrounds the source region, and the second lightly doped drain region surrounds the drain region. 7 . The semiconductor device as claimed in claim 1 , wherein a ratio of a width of the exposed section to a width of a sidewall of the spacer is greater than or equal to 2. 8 .

8. The semiconductor structure of claim 1, further comprising: The two bird's beak structures are respectively and integrally extended on both sides of the first oxide layer, and the two bird's beak structures do not overlap with the gate in a vertical direction. 9 . The semiconductor structure as claimed in claim 8 , wherein one of the bird's beak structures is located below a sidewall of the spacer, and another of the bird's beak structures is located outside another sidewall of the spacer. 10 . The semiconductor structure as claimed in claim 1 , wherein a side of the first oxide layer away from the exposed segment is flush with a side surface of the gate.

11. A method for manufacturing a semiconductor device, comprising: Performing a thermal oxidation process to form an oxide layer on the substrate, wherein the oxide layer includes a first oxide layer and a second oxide layer, and the thickness of the first oxide layer is greater than the thickness of the second oxide layer; forming a gate structure on the oxide layer, wherein the gate structure partially covers the first oxide layer, and the first oxide layer includes an exposed section not covered by the gate structure; and A portion of the exposed section is removed so that the thickness of the exposed section is smaller than the thickness of the first oxide layer outside the exposed section.

12. The method according to claim 11, before performing the thermal oxidation process, further comprising: A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening area, the first oxide layer corresponds to the opening area, and the second oxide layer is formed by oxidizing the patterned material layer.

13. The method according to claim 12, before forming the patterned material layer on the substrate, further comprising: A first ion implantation process is performed to form a first lightly doped drain region and a second lightly doped drain region separated from each other in the substrate. 14 . The method according to claim 13 , wherein the second lightly doped drain region is located below the exposed segment, and a width of the second lightly doped drain region is greater than a width of the first lightly doped drain region.

15. The method of claim 14, further comprising: removing the second oxide layer; and A second ion implantation process is performed to form a source region and a drain region in the area of ​​the substrate corresponding to the area where the second oxide layer is originally disposed, wherein the drain region is adjacent to the exposed section. 16 . The method according to claim 15 , wherein a portion of the drain region is located below the exposed segment and is aligned with an outer edge of the gate structure. 17 . The method of claim 15 , wherein the first lightly doped drain region surrounds the source region, and the second lightly doped drain region surrounds the drain region.

18. The method of claim 11, wherein forming the gate structure on the oxide layer comprises: forming a gate on the oxide layer; and A spacer is formed to surround the gate. 19 . The method of claim 18 , wherein a ratio of a width of the exposed segment to a width of a sidewall of the spacer is greater than or equal to 2. 20 . The method of claim 18 , wherein the oxide layer further comprises two bird's beak structures extending integrally on two sides of the first oxide layer, and the two bird's beak structures do not overlap with the gate in a vertical direction. 21 . The method according to claim 20 , wherein one of the bird's beak structures is located below a sidewall of the spacer, and another of the bird's beak structures is located outside another sidewall of the spacer. 22 . The method according to claim 18 , wherein a side of the first oxide layer away from the exposed segment is flush with a side surface of the gate.

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