Array substrate and preparation method thereof, display panel and display device

Abstract

The invention discloses an array substrate and a preparation method thereof, a display panel and a display device.The array substrate comprises a substrate and a first grid electrode arranged on the substrate, and a second grid electrode is arranged on the side, away from the substrate, of the first grid electrode; the first grid electrode and the second grid electrode are arranged in a staggered mode in the direction of the plane where the substrate is located and form a discontinuous area, and a first interlayer dielectric layer is arranged on the side, away from the first grid electrode, of the second grid electrode; wherein a third grid electrode is arranged between the second grid electrode and the first interlayer dielectric layer, and the third grid electrode is arranged in an area opposite to the discontinuous area; or, a hollow area is arranged in the area, opposite to the discontinuous area, of the first interlayer dielectric layer. According to the array substrate, the etching uniformity of the source-drain metal layer can be effectively improved and the photoresist residue can be reduced by utilizing the added third grid electrode or the formed hollowed-out region.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a display panel and a display device. Background Art

[0002] With the development of display technology, narrow bezels have become a common design for mobile phone screens. The narrow bezel design leads to a narrower spacing between the first gate and the second gate in the display panel. During film formation, masking and etching of the source and drain metal layers, it is easy to cause uneven etching of the source and drain metal layers in the area opposite to the discontinuous area between the first gate and the second gate, and cause photoresist residue to form in the area. The residual photoresist can cause a signal short circuit and thus cause poor screen display. Summary of the invention

[0003] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide an array substrate and a manufacturing method thereof, a display panel and a display device.

[0004] In a first aspect, an array substrate is provided, comprising: a substrate, a first gate disposed on the substrate, a second gate disposed on a side of the first gate away from the substrate, the first gate and the second gate are staggered in a plane direction of the substrate and form a discontinuous region, and a first interlayer dielectric layer is disposed on a side of the second gate away from the first gate; wherein A third gate is disposed between the second gate and the first interlayer dielectric layer, and the third gate is disposed at a region opposite to the discontinuous region; or, A hollowing area is arranged in an area of ​​the first interlayer dielectric layer opposite to the discontinuous area.

[0005] In addition, the array substrate of the present invention may also have the following additional technical features: In some embodiments, the third gate includes a recessed portion, and the recessed portion conforms to the discontinuity region.

[0006] In some embodiments, the third gate further includes an extension portion, the extension portion is disposed on both sides of the recessed portion along the plane direction of the substrate, and the extension portion is extended along the plane direction of the substrate and toward a side away from the recessed portion.

[0007] In some embodiments, the extension portion has a first end face and a second end face that are relatively arranged in a direction perpendicular to the plane where the substrate is located, the first end face and the second end face are at least partially staggered in the direction of the plane where the substrate is located, the first end face is arranged close to the recessed portion relative to the second end face, and the first end face and the second end face are connected at one end away from the recessed portion to form an inclined surface.

[0008] In some embodiments, the recessed portion and the extending portion are integrally formed.

[0009] In some embodiments, a first gate insulating layer is disposed between the second gate and the first interlayer dielectric layer, and the third gate is disposed between the first gate insulating layer and the first interlayer dielectric layer.

[0010] In some other embodiments, along a direction perpendicular to the plane of the substrate, a projection of the hollowed-out area on the substrate at least covers a projection of the discontinuous area on the substrate.

[0011] In other embodiments, the first interlayer dielectric layer has a first inclined side surface and a second inclined side surface relatively arranged in the hollowed-out area along the plane direction of the substrate, and the first inclined side surface and the second inclined side surface extend from an end surface of the first interlayer dielectric layer on one side close to the second gate to an end surface of the side away from the second gate, and are inclined toward a side away from the discontinuity area.

[0012] In some other embodiments, a second interlayer dielectric layer, a buffer layer and a first gate insulating layer are disposed between the second gate and the first interlayer dielectric layer; wherein the second interlayer dielectric layer is disposed on a side of the second gate away from the first gate, the buffer layer is disposed on a side of the second interlayer dielectric layer away from the second gate, and the first gate insulating layer is disposed on a side of the buffer layer away from the second interlayer dielectric layer; The hollowed-out region extends along a direction perpendicular to a plane where the substrate is located and toward a side close to the substrate, and spans over at least one layer among the first gate insulating layer, the buffer layer and the second interlayer dielectric layer.

[0013] In a second aspect, a method for preparing an array substrate is provided, comprising: forming a first gate on the substrate; A second gate is formed on a side of the first gate away from the substrate, wherein the first gate and the second gate are staggered in a direction of a plane where the substrate is located and form a discontinuous region; forming a third gate on a side of the second gate away from the first gate, the third gate being formed at a region opposite to the discontinuous region, and forming a first interlayer dielectric layer on a side of the third gate away from the second gate; or, A first interlayer dielectric layer is formed on a side of the second gate away from the first gate, and a hollowing area is formed in an area of ​​the first interlayer dielectric layer opposite to the discontinuity area.

[0014] In some embodiments, forming a third gate on a side of the second gate away from the first gate includes: A first gate insulating layer is formed on a side of the second gate away from the first gate, and the third gate is formed on a side of the first gate insulating layer away from the second gate by a patterning process.

[0015] In some other implementations, a hollow region is formed in the first interlayer dielectric layer in a region opposite to the discontinuous region through a patterning process.

[0016] In some other embodiments, before forming the first interlayer dielectric layer on the side of the second gate away from the first gate, the method further includes: forming a second interlayer dielectric layer on a side of the second gate away from the first gate; forming a buffer layer on a side of the second interlayer dielectric layer away from the second gate; forming a first gate insulating layer on a side of the buffer layer away from the second interlayer dielectric layer; The first interlayer dielectric layer is formed on a side of the first gate insulating layer away from the buffer layer, and the hollow region extends in a direction perpendicular to the plane of the substrate and toward a side close to the substrate, and spans over at least one of the first gate insulating layer, the buffer layer and the second interlayer dielectric layer.

[0017] In some embodiments, the method further comprises: A source-drain metal layer is formed on a side of the first interlayer dielectric layer away from the second gate, and the source-drain metal layer is patterned at least twice in an area opposite to the discontinuity area to remove residual structures of the source-drain metal layer in the area opposite to the discontinuity area.

[0018] In some embodiments, the patterning process includes coating photoresist, mask exposure, development, etching and stripping.

[0019] In a third aspect, a display panel is provided, wherein the display panel comprises the array substrate described in any embodiment of the present application, or comprises the array substrate prepared by the method for preparing the array substrate described in any embodiment of the present application or an array substrate obtained.

[0020] In a fourth aspect, a display device is provided, wherein the display device comprises the display panel described in any embodiment of the present application.

[0021] The present application provides an array substrate and a method for preparing the same, a display panel and a display device. The array substrate reduces the aspect ratio of the groove formed by the SD layer by changing the stacking structure and morphology of the array substrate film layer, effectively improves the SD etching uniformity of the SD layer in the area opposite to the discontinuous area, and can reduce the PR residue of the SD layer, thereby avoiding the problem of poor screen display caused by signal short circuit caused by the PR residue. BRIEF DESCRIPTION OF THE DRAWINGS In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0022] Figure 1 is an exemplary structural diagram of an existing array substrate; Figure 2 is an exemplary structural diagram of an existing array substrate (forming PR residue); Figure 3 A first exemplary structural diagram of an array substrate provided in an embodiment of the present application; Figure 4 for Figure 3 The third gate structure diagram in FIG. Figure 5 A second exemplary structural diagram of an array substrate (without showing the source-drain metal layer) provided in an embodiment of the present application; Figure 6 A second exemplary structural diagram of an array substrate provided in an embodiment of the present application; Figure 7 A schematic diagram of coating photoresist on the first interlayer dielectric layer of the array substrate provided in an embodiment of the present application; Figure 8 A structural diagram of the array substrate after mask exposure and development provided in an embodiment of the present application; Fig. 9 A structural diagram of the array substrate after etching provided in an embodiment of the present application; Fig.10 This is a structural diagram of the array substrate after the photoresist is stripped off provided in an embodiment of the present application.

[0023] In the above picture: 10 array substrate; 11 substrate; 12 first gate; 13 second gate; 14 first interlayer dielectric; 141 hollowing area; 142 first inclined side; 143 second inclined side; 15 third gate; 151 recessed portion; 152 extension portion; 16 first gate insulating layer; 17 buffer layer; 18 second interlayer dielectric layer; 19 second gate insulating layer; 20 third gate insulating layer; 21 source-drain metal layer; 210 groove; 211 PR residue; 22 photoresist; 23 discontinuity area. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0025] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0026] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0027] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0028] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0029] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0030] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing.

[0031] like Figure 1 As shown, the existing array substrate 10 includes a substrate 11 and a first gate 12 (Gate1), a second gate 13 (Gate2) and a source-drain metal layer 21 (SD layer) sequentially arranged on the substrate 11, wherein the first gate 12 and the second gate 13 are staggered in the plane direction of the substrate 11 to form a discontinuous region 23. As the film layers of the array substrate 10 are stacked on the substrate 11, each film layer will form a groove 210 at the position of the discontinuous region 23. The groove 210 is a V-shaped groove structure, and the depth-to-width ratio of the V-shaped groove structure shows a trend of first increasing and then decreasing. Under the existing spatial layout of the first gate 12 and the second gate 13 and the thickness of the packaging layer, the depth-to-width ratio of the V-shaped groove structure formed by the source-drain metal layer 21 at the discontinuous region 23 will reach a maximum, wherein the packaging layer is formed by a chemical vapor deposition (CVD) process.

[0032] like Figure 2As shown, the V-groove structure will easily cause the SD layer to form photoresist residues (PR residues 211) in the area opposite to the discontinuous area 23 of the first gate 12 and the second gate 13 during film formation, masking and etching, and the etching of the area will be uneven, and the PR residues 211 will cause signal short circuits and poor screen display; wherein, the etching rate of the SD layer is slow in the V-groove structure area, and the etching rate is fast in the non-V-groove structure area, which leads to the problem of uneven etching. In particular, the narrow frame design of the existing display screen leads to dense routing of the bottom frame (Pad) of the display screen and the punching position (AA Hole) of the display area, and the routing spacing between Gate1 and Gate2 becomes narrower, resulting in the further increase of the depth-to-width ratio of the V-groove structure formed in the SD layer in the area opposite to the alternating routing position of Gate1 and Gate2, which leads to worse etching uniformity of the SD layer in this area and more PR residues 211 formed.

[0033] In order to solve the above technical problems, the first aspect of the embodiment of the present application is as follows: Figures 3 to 6 As shown, an array substrate 10 is provided, comprising: a substrate 11, a first gate 12 arranged on the substrate 11, a second gate 13 is arranged on a side of the first gate 12 away from the substrate 11, the first gate 12 and the second gate 13 are staggered in a plane direction of the substrate 11 and form a discontinuity region 23, and a first interlayer dielectric layer 14 is arranged on a side of the second gate 13 away from the first gate 12; wherein, A third gate 15 is disposed between the second gate 13 and the first interlayer dielectric layer 14, and the third gate 15 is disposed at a region opposite to the discontinuous region 23; or, A hollowing area 141 is disposed in an area of ​​the first interlayer dielectric layer 14 opposite to the discontinuity area 23 .

[0034] Specifically, the array substrate 10 includes a substrate 11 and a first gate 12, a second gate 13 and a first interlayer dielectric layer 14 sequentially arranged on the substrate 11; wherein the first gate 12 and the second gate 13 are staggered in the plane direction of the substrate 11 and form a discontinuity region 23, and when the source-drain metal layer 21 (SD layer) is formed on the side of the first interlayer dielectric layer 14 away from the second gate 13, the discontinuity region 23 causes the side of the SD layer away from the second gate 13 to form a groove 210 at a region opposite to the discontinuity region 23, and the groove 210 may be a V-shaped groove The V-groove structure has a large depth-to-width ratio, and the depth-to-width ratio refers to the ratio of the depth of the V-groove structure in a direction perpendicular to the plane of the substrate 11 to the width in a direction parallel to the plane of the substrate 11. The SD layer may cause uneven etching at the V-groove structure during film formation, masking and etching, and form a PR residue 211 on the side close to the second gate 13. The larger the depth-to-width ratio of the groove 210, the more PR residue 211 is formed on the SD layer on the side close to the second gate 13 and in the area opposite to the discontinuity area 23; conversely, the less PR residue 211 is formed.

[0035] In the present application embodiment, Figure 3 and Figure 4 As shown, by setting the third gate 15 between the second gate 13 and the first interlayer dielectric layer 14, and the third gate 15 is set at the area opposite to the discontinuity area 23, the third gate 15 acts as a dummy wiring (Dummy wiring) to pad the groove formed by the discontinuity area 23 of the first gate 12 and the second gate 13, so that the groove 210 formed by the SD layer reaches the shallowing stage in advance, reducing the aspect ratio of the groove 210, thereby improving the etching uniformity of the SD layer and reducing the PR residue 211 of the SD layer.

[0036] Or, if Figure 5 and Figure 6 As shown, a hollow region 141 is set in the area of ​​the first interlayer dielectric layer 14 opposite to the discontinuity area 23. When the source-drain metal layer 21 (SD layer) is formed on the side of the first interlayer dielectric layer 14 away from the second gate 13, the setting of the hollow region 141 can increase the depth and width of the groove 210 formed in the SD layer at the area opposite to the discontinuity area 23, and can reduce the aspect ratio of the groove 210, thereby improving the uniformity of the SD layer etching and reducing the SD layer PR residue 211.

[0037] It can be understood that the array substrate 10 provided in the embodiment of the present application has a wide range of applications and can be used at positions where the display area punching (AA Hole) and fan-out (Fanout) positions have small wiring spacing, to improve the SD layer PR residue 211 and etching unevenness at the AA Hole and Fanout positions, and can effectively improve the SD layer PR residue 211 and etching unevenness at positions where there are similar wiring on display panels such as organic light emitting diode (OLED) display panels, and can increase the space margin (Space Margin) between the first gate 12 and the second gate 13, which is beneficial to the narrow frame design of the display panel.

[0038] In the embodiment of the present application, the stacking structure and morphology of the film layer of the array substrate 10 are changed to reduce the aspect ratio of the groove 210 formed by the DEP (dielectrophoresis technology) of the SD layer, thereby effectively improving the etching uniformity of the SD layer in the area opposite to the discontinuous area 23, and reducing the PR residue 211 of the SD layer, thereby avoiding the problem of poor screen display caused by signal short circuit caused by the PR residue 211, and improving the etching uniformity of the SD layer and the PR residue 211 by adopting the existing mask and process method, with little impact on production capacity, and optimizing the film layer stacking structure of the SD layer PR residue 211 that is easy to form, with less film layer changes, easy to implement in design, less changes to the overall structure of the display panel, and no impact on the overall performance.

[0039] In some embodiments, Figure 3 and Figure 4 As shown, the third gate 15 includes a recessed portion 151 , and the recessed portion 151 conforms to the discontinuous region 23 .

[0040] Specifically, the third gate 15 has a recessed portion 151, and the shape of the recessed portion 151 matches the shape of the discontinuous region 23 formed by the first gate 12 and the second gate 13, so that the recessed portion 151 can pad the groove formed by the discontinuous region 23 of the first gate 12 and the second gate 13, so that the groove 210 formed by the SD layer reaches the shallowing stage in advance, and the aspect ratio of the groove 210 is reduced, thereby improving the etching uniformity of the SD layer and reducing the SD layer PR residue 211. Exemplarily, the groove formed by the discontinuous region 23 of the first gate 12 and the second gate 13 is a trapezoidal structure that is wide at the top and narrow at the bottom, and the shape of the recessed portion 151 is a trapezoidal structure that matches the shape of the groove. It can be understood that when the bottom end spacing of the trapezoidal structure formed on the side of the recessed portion 151 away from the second gate 13 is small, the trapezoidal structure on this side can be formed into a V-shaped structure, thereby further reducing the aspect ratio of the groove 210 formed by the SD layer.

[0041] In some embodiments, Figure 3 and Figure 4 As shown, the third gate 15 further includes an extension portion 152 , which is disposed on both sides of the recess 151 along the plane direction of the substrate 11 , and extends along the plane direction of the substrate 11 and toward a side away from the recess 151 .

[0042] Specifically, extension portions 152 are fixedly provided on both sides of the recessed portion 151. The cooperation between the extension portions 152 and the recessed portion 151 can raise the first interlayer dielectric layer 14 as a whole in the area opposite to the discontinuity area 23, and can reduce the aspect ratio of the groove 210 formed on the side of the first interlayer dielectric layer 14 away from the second gate 13, thereby reducing the aspect ratio of the groove 210 formed in the SD layer.

[0043] In some embodiments, Figure 3 and Figure 4 As shown, the extension portion 152 has a first end face and a second end face that are relatively arranged in a direction perpendicular to the plane where the substrate 11 is located, the first end face and the second end face are at least partially staggered in the direction of the plane where the substrate 11 is located, the first end face is arranged close to the recessed portion 151 relative to the second end face, and the first end face and the second end face are connected at one end away from the recessed portion 151 to form an inclined surface.

[0044] Specifically, the extension portion 152 has a first end face and a second end face, and an inclined surface is formed between the first end face and the second end face, so that when the extension portion 152 and the recessed portion 151 cooperate to form the third gate 15, the structural design of the two extension portions 152 can form two protrusions on the first interlayer dielectric layer 14 at positions corresponding to the extension portions 152, and the two protrusions are located on both sides of the groove 210 of the first interlayer dielectric layer 14, thereby making the overall height of the groove 210 formed by the formed first interlayer dielectric layer 14 rise relative to the large surface area of ​​the first interlayer dielectric layer 14. When the SD layer is formed on the side of the first interlayer dielectric layer 14 away from the second gate 13, the overall height of the groove 210 formed by the SD layer is increased. When the SD layer is etched, the photoresist of the SD layer located in the groove 210 area will be etched first, further improving the etching uniformity of the SD layer and reducing the photoresist residue of the SD layer.

[0045] In some embodiments, Figure 3 and Figure 4 As shown, the recessed portion 151 and the extending portion 152 are integrally formed.

[0046] Specifically, the recessed portion 151 and the extending portion 152 can be integrally formed by a patterning process, which has a simple processing technology and low cost, thereby simplifying the manufacturing process of the third gate 15 .

[0047] In some embodiments, Figure 3 As shown, a first gate insulating layer 16 is disposed between the second gate 13 and the first interlayer dielectric layer 14 , and the third gate 15 is disposed between the first gate insulating layer 16 and the first interlayer dielectric layer 14 .

[0048] Specifically, the third gate 15 is disposed on a side of the first gate insulating layer 16 away from the second gate 13, and the film layer stacking structure of the SD layer PR residue 211 that is easily formed is optimized, and the changes to the film layer structures of the array substrate 10 are small, which is easy to implement, and the changes to the overall structure of the display panel are small, and the overall performance is not affected. In this example, the third gate 15 is disposed before the SD layer is formed, and the problem of the PR residue 211 formed in the SD layer is solved from the root cause, and the SD layer PR residue 211 is improved and the SD layer etching uniformity is improved.

[0049] In other embodiments, Figure 5 and Figure 6 As shown, along the direction perpendicular to the plane of the substrate 11 , the projection of the hollowed-out area 141 on the substrate 11 at least covers the projection of the discontinuous area 23 on the substrate.

[0050] Another solution to solve the problem of PR residue 211 and uneven etching of the SD layer in the embodiment of the present application is: a hollow region 141 is set in the area of ​​the first interlayer dielectric layer 14 opposite to the discontinuity region 23, and the projection of the hollow region 141 on the substrate 11 at least covers the projection of the discontinuity region 23 on the substrate 11, so that the cross-sectional area of ​​the hollow region 141 along the direction parallel to the plane of the substrate 11 is larger than the cross-sectional area of ​​the discontinuity region 23, and when the SD layer is formed on the side of the first interlayer dielectric layer 14 away from the second gate 13, the SD layer is partially located in the hollow region 141 and the width and depth of the groove 210 formed in the SD layer are increased, and the aspect ratio of the groove 210 can be reduced, thereby improving the uniformity of the SD layer etching and reducing the SD layer PR residue 211.

[0051] In other embodiments, Figure 5 and Figure 6 As shown, the first interlayer dielectric layer 14 has a first inclined side surface 142 and a second inclined side surface 143 that are relatively arranged in the hollow area 141 along the plane direction of the substrate 11, and the first inclined side surface 142 and the second inclined side surface 143 extend from the end surface of one side of the first interlayer dielectric layer 14 close to the second gate 13 to the end surface of one side away from the second gate 13, and are inclined toward the side away from the discontinuity area 23.

[0052] Specifically, a hollow area 141 is formed between the first inclined side surface 142 and the second inclined side surface 143, and the formed hollow area 141 is a trapezoidal structure that is narrow at the bottom and wide at the top, and the projections of the upper end surface and the lower end surface of the trapezoidal structure in a direction perpendicular to the plane of the substrate 11 are both located outside the discontinuous area 23. The hollow area 141 with a trapezoidal structure can increase the deposition area of ​​the hollow area 141 when the SD layer is formed, and make the photoresist of the SD layer in the hollow area 141 easier to be etched.

[0053] In other embodiments, Figure 5 and Figure 6 As shown, a second interlayer dielectric layer 18, a buffer layer 17 and a first gate insulating layer 16 are arranged between the second gate 13 and the first interlayer dielectric layer 14; wherein the second interlayer dielectric layer 18 is arranged on a side of the second gate 13 away from the first gate 12, the buffer layer 17 is arranged on a side of the second interlayer dielectric layer 18 away from the second gate 13, and the first gate insulating layer 16 is arranged on a side of the buffer layer 17 away from the second interlayer dielectric layer 18; The hollowed-out region 141 extends in a direction perpendicular to the plane of the substrate 11 and toward a side close to the substrate 11 , and spans over at least one layer of the first gate insulating layer 16 , the buffer layer 17 , and the second interlayer dielectric layer 18 .

[0054] Specifically, the first interlayer dielectric layer 14 can form a hollow region 141 in the region opposite to the discontinuity region 23 through a patterning process, and the extension depth of the hollow region 141 can be controlled by controlling the parameters of the patterning process (such as temperature, time, etc.), such as the hollow region 141 penetrates the first interlayer dielectric layer 14 and extends toward the side close to the substrate 11, and crosses at least one of the first gate insulating layer 16, the buffer layer 17 and the second interlayer dielectric layer 18. Preferably, Figure 5 and Figure 6 As shown, the hollowed-out area 141 penetrates the first interlayer dielectric layer 14 and the first gate insulating layer 16. It can be understood that the hollowed-out area 141 can also further penetrate the buffer layer 17, etc., and technicians in this field can set the penetration depth of the hollowed-out area 141 according to actual needs.

[0055] In this example, the organic layers (such as the first interlayer dielectric layer 14 and the first gate insulating layer 16) at high-risk positions that cause PR residues 211 of the SD layer at the fan-out position are removed, so as to reduce the aspect ratio of the groove 210 formed in the SD layer, effectively reduce the PR residues 211 formed during masking and etching of the SD layer, and improve the etching uniformity of the SD layer.

[0056] In a second aspect, a method for preparing an array substrate is provided, comprising: forming a first gate 12 on a substrate 11; A second gate 13 is formed on a side of the first gate 12 away from the substrate 11, and the first gate 12 and the second gate 13 are staggered in a direction of the plane where the substrate 11 is located to form a discontinuous region 23; A third gate 15 is formed on a side of the second gate 13 away from the first gate 12, the third gate 15 is formed at a region opposite to the discontinuous region 23, and a first interlayer dielectric layer 14 is formed on a side of the third gate 15 away from the second gate 13; or, A first interlayer dielectric layer 14 is formed on a side of the second gate 13 away from the first gate 12 , and a hollowing region 141 is formed in a region of the first interlayer dielectric layer 14 opposite to the discontinuity region 23 .

[0057] Specifically, Figure 3 and Figure 4 As shown, by adding a third gate 15 between the second gate 13 and the first interlayer dielectric layer 14 in the array substrate 10, or as Figure 5 and Figure 6 As shown, a hollow area 141 is opened in the first interlayer dielectric layer 14, which effectively improves the aspect ratio of the groove 210 formed in the SD layer in the area opposite to the discontinuity area 23, thereby improving the etching uniformity of the SD and reducing the PR residue 211 of the SD layer, thereby avoiding the problem of signal short circuit caused by the PR residue 211 resulting in poor screen display.

[0058] It can be understood that the method for preparing the array substrate provided in the embodiment of the present application is used to obtain the array substrate 10 provided in any embodiment of the present application. The specific technical features and technical effects of the method for preparing the array substrate are consistent with those of the array substrate 10, and the embodiments of the present application will not be repeated.

[0059] In some embodiments, Figure 3 As shown, the third gate 15 is formed on a side of the second gate 13 away from the first gate 12, including: A first gate insulating layer 16 is formed on a side of the second gate 13 away from the first gate 12 , and the third gate 15 is formed on a side of the first gate insulating layer 16 away from the second gate 13 by a patterning process.

[0060] Specifically, the third gate 15 is formed on the side of the first gate insulating layer 16 away from the second gate 13 through a composition process, and the film layer stacking structure of the SD layer PR residue 211 that is easy to form is optimized. The changes to the film layer structures of the array substrate 10 are small, easy to implement, do not increase production capacity, and the overall structure of the display panel is changed less, and has no impact on the overall performance.

[0061] Among them, the patterning process includes conventional technical means such as depositing a film layer, coating a photoresist 22, exposing a mask, developing, etching, and stripping the photoresist 22. Photolithography is a technology that uses a photochemical reaction to transfer the pattern on the mask to the substrate 11 material (such as a glass substrate). Based on the principle of selective exposure of light, the surface of the substrate 11 coated with the photoresist 22 is irradiated by a light source such as ultraviolet light (UV) to cause a chemical reaction in the photoresist 22. The chemical properties of the exposed part of the photoresist 22 will change during the subsequent development process, so that it can be selectively removed or retained, thereby forming a pattern corresponding to the mask pattern. For example, in a positive photoresist, the exposed part will be dissolved in the developer, while the unexposed part will be retained; the opposite is true in a negative photoresist.

[0062] In other embodiments, Figure 5 As shown, a hollow region 141 is formed in the first interlayer dielectric layer 14 in a region opposite to the discontinuous region 23 through a patterning process.

[0063] Specifically, during the formation of the first interlayer dielectric layer 14 by the patterning process, a hollowing area 141 is simultaneously formed in an area opposite to the discontinuity area 23 , thereby saving process flow and not affecting the formation of the original first interlayer dielectric layer 14 .

[0064] In other embodiments, Figure 5 As shown, before forming the first interlayer dielectric layer 14 on the side of the second gate 13 away from the first gate 12, the method further includes: A second interlayer dielectric layer 18 is formed on a side of the second gate 13 away from the first gate 12; forming a buffer layer 17 on a side of the second interlayer dielectric layer 18 away from the second gate 13; Forming a first gate insulating layer 16 on a side of the buffer layer 17 away from the second interlayer dielectric layer 18; The first interlayer dielectric layer 14 is formed on the side of the first gate insulating layer 16 away from the buffer layer 17, and the hollow area 141 extends in a direction perpendicular to the plane of the substrate 11 and toward the side close to the substrate 11, and spans at least one layer of the first gate insulating layer 16, the buffer layer 17 and the second interlayer dielectric layer 18.

[0065] Specifically, the first interlayer dielectric layer 14 can form a hollowed-out area 141 in the area opposite to the discontinuity area 23 through a composition process, and the extension depth of the hollowed-out area 141 can be controlled by controlling the parameters of the composition process (such as temperature, time, etc.). For example, the hollowed-out area 141 penetrates the first interlayer dielectric layer 14 and the first gate insulating layer 16.

[0066] In some embodiments, Figure 2 , Figures 7 to 10 As shown, the method also includes: A source-drain metal layer 21 is formed on a side of the first interlayer dielectric layer 14 away from the second gate 13, and the source-drain metal layer 21 is subjected to at least two patterning processes in an area opposite to the discontinuity area 23 to remove the residual structure of the source-drain metal layer 21 in the area opposite to the discontinuity area 23.

[0067] Specifically, although the SD layer PR residue 211 can be reduced by adding the third gate 15 and forming the hollow region 141 in the first interlayer dielectric layer 14, the PR residue 211 is not completely removed. The SD layer is formed on the side of the first interlayer dielectric layer 14 away from the second gate 13. The SD layer will still form a PR residue 211 at the position of the groove 210 of the first interlayer dielectric layer 14 during film formation, masking and etching. In order to completely remove the SD layer PR residue 211, at least two patterning processes are performed on the SD layer in the area opposite to the discontinuity area 23 to completely remove the source and drain metal layer 21 PR residue 211.

[0068] Exemplarily, the patterning process includes depositing a film layer, coating a photoresist 22, mask exposure, development, etching, and stripping the photoresist 22, etc. The SD layer forms a PR residue 211 at the position of the groove 210 of the first interlayer dielectric layer 14, and then a mask is added on the side of the first interlayer dielectric layer 14 away from the second gate 13, that is, a mask is added between the first interlayer dielectric layer 14 and the protective layer (PVX), and the mask can be a TTE Mask (top titanium etching). The mask locally exposes, develops, and etches the area where the first gate 12 and the second gate 13 are alternately routed, wherein the photoresist 22 protects the area of ​​the SD layer without the PR residue 211, so as to repeatedly etch the PR residue 211 of the SD layer, thereby reducing the risk of the PR residue 211 of the SD layer, and finally, the remaining photoresist 22 is stripped off to complete the removal of the PR residue 211.

[0069] It should be noted that the method provided in this example of performing at least two patterning processes on the source-drain metal layer 21 in the area opposite to the discontinuity area 23 to remove the residual structure of the source-drain metal layer 21 in the area opposite to the discontinuity area 23 can be used as an independent method to remove the PR residue 211 of the SD layer without changing the film layer structure of the array substrate 10, and the preparation method is simple and does not affect the overall performance of the array substrate 10.

[0070] It can be understood that the array substrate 10 provided in the embodiment of the present application also includes a second gate insulation layer 19 and a third gate insulation layer 20, wherein the second gate insulation layer 19 is arranged between the first gate 12 and the second gate 13 to insulate and disconnect the wiring of the first gate 12 and the second gate 13, and the third gate insulation layer 20 is arranged on the side of the first gate 12 away from the second gate 13.

[0071] Among them, the materials of the first gate insulating layer 16, the second gate insulating layer 19 and the third gate insulating layer 20 can be the same or different, and exemplarily, they are silicon oxide, silicon nitride, and carbon nanotube oxide (CNT-O). The materials of the first interlayer dielectric layer 14 and the second interlayer dielectric layer 18 can be the same or different, and exemplarily, they are silicon oxide, aluminum oxide, silicon dioxide, fluorosilicone glass, organic silicon glass, CNT-O, etc., which can isolate different conductive layers and thin film transistors in the array substrate 10 from each other to prevent electrical faults such as short circuits between different components. The buffer layer 17 can effectively absorb and disperse these stresses to prevent problems such as material rupture and peeling caused by stress concentration. Its material is silicon oxide, silicon nitride, amorphous silicon, etc.

[0072] The following is a description of the method for preparing the array substrate of the present application with some specific embodiments, which are as follows: Example 1 A method for preparing an array substrate, such as Figure 3 As shown, including: S210: forming a third gate insulating layer 20 on the substrate 11, forming a first gate 12 on a side of the third gate insulating layer 20 away from the substrate 11, forming a second gate insulating layer 19 on a side of the first gate 12 away from the third gate insulating layer 20, and forming a second gate 13 on a side of the second gate insulating layer 19 away from the first gate 12, the first gate 12 and the second gate 13 are staggered in a plane direction of the substrate 11 and form a discontinuity region 23; S220: forming a second interlayer dielectric layer 18 on a side of the second gate 13 away from the second gate insulating layer 19, forming a buffer layer 17 on a side of the second interlayer dielectric layer 18 away from the second gate 13, and forming a first gate insulating layer 16 on a side of the buffer layer 17 away from the second interlayer dielectric layer 18; S230: forming a third gate 15 on a side of the first gate insulating layer 16 away from the buffer layer 17, wherein the third gate 15 is formed at a region opposite to the discontinuous region 23, and the third gate 15 may be formed by a patterning process; S240 : forming a first interlayer dielectric layer 14 on a side of the third gate 15 away from the first gate insulating layer 16 ; forming a source-drain metal layer 21 on a side of the first interlayer dielectric layer 14 away from the third gate 15 , wherein the source-drain metal layer 21 covers the upper end surface of the first interlayer dielectric layer 14 .

[0073] Example 2 A method for preparing an array substrate, such as Figure 5 and Figure 6 As shown, including: S210: forming a third gate insulating layer 20 on the substrate 11, forming a first gate 12 on a side of the third gate insulating layer 20 away from the substrate 11, forming a second gate insulating layer 19 on a side of the first gate 12 away from the third gate insulating layer 20, and forming a second gate 13 on a side of the second gate insulating layer 19 away from the first gate 12, the first gate 12 and the second gate 13 are staggered in a plane direction of the substrate 11 and form a discontinuity region 23; S220: forming a second interlayer dielectric layer 18 on a side of the second gate 13 away from the second gate insulating layer 19, forming a buffer layer 17 on a side of the second interlayer dielectric layer 18 away from the second gate 13, and forming a first gate insulating layer 16 on a side of the buffer layer 17 away from the second interlayer dielectric layer 18; S230: forming a first interlayer dielectric layer 14 on a side of the first gate insulating layer 16 away from the buffer layer 17, and forming a hollow region 141 in the first interlayer dielectric layer 14 at a region opposite to the discontinuity region 23 through a patterning process, wherein the hollow region 141 extends in a direction perpendicular to the plane of the substrate 11 and penetrates the first interlayer dielectric layer 14 and the first gate insulating layer 16; S240: A source-drain metal layer 21 is formed on a side of the first interlayer dielectric layer 14 away from the first gate insulating layer 16 . The source-drain metal layer 21 covers two opposite side surfaces of the first interlayer dielectric layer 14 and the first gate insulating layer 16 in the hollowed-out area 141 , and contacts and cooperates with the upper end surface of the buffer layer 17 .

[0074] Example 3 The method for preparing the array substrate of Example 3 is the same as the method for preparing the array substrate of Example 1, except that after preparing and forming the source-drain metal layer 21, Example 3 further includes: S250: Figure 2 As shown, a film layer is deposited on the source-drain metal layer 21 in the area opposite to the discontinuity area 23, a photoresist 22 is coated, a mask is exposed, developed and etched, so that the source-drain metal layer 21 forms a PR residue 211 at the position of the groove 210 of the first interlayer dielectric layer 14, and the PR at the position other than the groove 210 is removed; S260: once again uniformly coating the photoresist 22 on the first interlayer dielectric layer 14 and the remaining PR surface of the source / drain metal layer 21 (eg Figure 7As shown); a mask is added on the side of the first interlayer dielectric layer 14 away from the second gate 13, and ultraviolet (UV) or other short-wavelength light (such as extreme ultraviolet light EUV) is used to irradiate the first interlayer dielectric layer 14 coated with photoresist 22 and the PR remaining in the source and drain metal layer 21 through a mask with a pattern, and the area of ​​the first interlayer dielectric layer 14 without PR remaining is protected by the newly coated photoresist 22, and the area with PR remaining is exposed and developed by mask (as shown); Figure 8 As shown), and then etching is performed, the morphology after etching is as shown Fig. 9 As shown, the final stripping is performed to completely remove the remaining photoresist (such as Fig.10 as shown).

[0075] Example 4 The method for preparing the array substrate of Example 4 is the same as the method for preparing the array substrate of Example 1, except that after preparing and forming the source-drain metal layer 21, Example 4 further includes: S250: Figure 2 As shown, a film layer is deposited, a photoresist 22 is coated, a mask is exposed, developed and etched in the area of ​​the source / drain metal layer 21 opposite to the discontinuity area 23, so that the source / drain metal layer 21 forms a PR residue 211 at the position of the groove 210 of the first interlayer dielectric layer 14, and the PR at the position other than the groove 210 is removed; S260: once again uniformly coating the photoresist 22 on the first interlayer dielectric layer 14 and the remaining PR surface of the source / drain metal layer 21 (eg Figure 7 As shown, a mask is added on the side of the first interlayer dielectric layer 14 away from the second gate 13, and ultraviolet (UV) or other short-wavelength light (such as extreme ultraviolet light EUV) is used to irradiate the first interlayer dielectric layer 14 coated with photoresist 22 and the residual PR of the source-drain metal layer 21 through a mask with a pattern, and the area of ​​the first interlayer dielectric layer 14 without residual PR is protected by the newly coated photoresist 22, and the area with residual PR is exposed and developed by mask (such as Figure 8 As shown), and then etching is performed, the morphology after etching is as shown Fig. 9 As shown, the final stripping is performed to completely remove the remaining photoresist (such as Fig.10 as shown).

[0076] Example 5 A method for preparing an array substrate, such as Figure 8 As shown, including: S210: forming a third gate insulating layer 20 on the substrate 11, forming a first gate 12 on a side of the third gate insulating layer 20 away from the substrate 11, forming a second gate insulating layer 19 on a side of the first gate 12 away from the third gate insulating layer 20, and forming a second gate 13 on a side of the second gate insulating layer 19 away from the first gate 12, the first gate 12 and the second gate 13 are staggered in a plane direction of the substrate 11 and form a discontinuity region 23; S220: forming a second interlayer dielectric layer 18 on a side of the second gate 13 away from the second gate insulating layer 19, forming a buffer layer 17 on a side of the second interlayer dielectric layer 18 away from the second gate 13, and forming a first gate insulating layer 16 on a side of the buffer layer 17 away from the second interlayer dielectric layer 18; S230: forming a first interlayer dielectric layer 14 on a side of the first gate insulating layer 16 away from the buffer layer 17; forming a source-drain metal layer 21 on a side of the first interlayer dielectric layer 14 away from the first gate insulating layer 16, wherein the source-drain metal layer 21 covers an upper end surface of the first interlayer dielectric layer 14; S240: Figure 2 As shown, a film layer is deposited, a photoresist 22 is coated, a mask is exposed, developed and etched in the area of ​​the source / drain metal layer 21 opposite to the discontinuity area 23, so that the source / drain metal layer 21 forms a PR residue 211 at the position of the groove 210 of the first interlayer dielectric layer 14, and the PR at the position other than the groove 210 is removed; S250: once again uniformly coating the photoresist 22 on the first interlayer dielectric layer 14 and the remaining PR surface of the source / drain metal layer 21 (eg Figure 7 As shown); a mask is added on the side of the first interlayer dielectric layer 14 away from the second gate 13, and ultraviolet (UV) or other short-wavelength light (such as extreme ultraviolet light EUV) is used to irradiate the first interlayer dielectric layer 14 coated with photoresist 22 and the PR remaining in the source and drain metal layer 21 through a mask with a pattern, and the area of ​​the first interlayer dielectric layer 14 without PR remaining is protected by the newly coated photoresist 22, and the area with PR remaining is exposed and developed by mask (as shown); Figure 8 As shown), and then etching is performed, the morphology after etching is as shown Fig. 9 As shown, the final stripping is performed to completely remove the remaining photoresist (such as Fig.10 as shown).

[0077] In a third aspect, a display panel is provided, wherein the display panel comprises the array substrate described in any embodiment of the present application, or comprises the array substrate prepared by the method for preparing the array substrate described in any embodiment of the present application or an array substrate obtained.

[0078] Specifically, the specific technical features and technical effects of the display panel are consistent with the array substrate and its preparation method, and this application will not repeat them. Exemplarily, the display panel is an LTPO (Low Temperature Polysilicon Oxide) display panel. The LTPO technology combines the LTPS (Low Temperature Poly-silicon) technology for producing polycrystalline silicon thin-film transistors with the technology for producing oxide thin-film transistors. Among them, oxide thin-film transistors are used as switching tubes in the driving circuit to prepare a display panel with the advantages of high resolution, high response speed, high brightness, low production cost, and low power consumption.

[0079] In a fourth aspect, a display device is provided, which includes the display panel as described above, and of course may also include other components, for example, may include a circuit for providing an electrical signal to the display panel to drive the display panel to emit light, and the circuit may be called a control circuit, and may include a circuit board and / or IC (Integrate Circuit) electrically connected to the display panel. In some embodiments, the display device may be a lighting device, in which case the display device is used as a light source to achieve a lighting function. For example, the display device may be a backlight module in a liquid crystal display device, a lamp for internal or external lighting, or various signal lights. In some other embodiments, the display device may be a display device, in which case the display panel is a display substrate for realizing the function of displaying an image (i.e., a picture). The display device may include a display or a product including a display. Among them, the display may be a flat panel display (Flat Panel Display, FPD), a micro display, etc. If divided according to whether the user can see the back of the display, the display may be a transparent display or an opaque display. If divided according to whether the display can be bent or curled, the display may be a flexible display or a normal display (which may be called a rigid display). Examples of products incorporating a display may include: computer monitors, televisions, billboards, laser printers with display capabilities, telephones, cell phones, personal digital assistants (PDAs), laptop computers, digital cameras, camcorders, viewfinders, vehicles, large-area walls, theater screens or stadium signs, etc.

[0080] The technical features and beneficial effects of the above-mentioned display device are the same as the technical features and beneficial effects of the display panel provided in the above-mentioned embodiment of the present disclosure, and will not be repeated here.

[0081] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

Claims

1. An array substrate (10), characterized in that: include: A substrate (11), a first gate (12) arranged on the substrate (11), a second gate (13) being arranged on a side of the first gate (12) away from the substrate (11), the first gate (12) and the second gate (13) being staggered in a plane direction of the substrate (11) to form a discontinuity region (23), and a first interlayer dielectric layer (14) being arranged on a side of the second gate (13) away from the first gate (12); wherein: A third gate (15) is arranged between the second gate (13) and the first interlayer dielectric layer (14), and the third gate (15) is arranged at a region opposite to the discontinuity region (23); or, A hollowed-out area (141) is provided in an area of ​​the first interlayer dielectric layer (14) opposite to the discontinuous area (23).

2. The array substrate (10) according to claim 1, characterized in that: The third gate (15) comprises a recessed portion (151), and the recessed portion (151) is conformally matched with the discontinuous region (23).

3. The array substrate (10) according to claim 2, characterized in that: The third gate (15) further comprises an extension portion (152), wherein the extension portion (152) is arranged on both sides of the recessed portion (151) along the plane direction of the substrate (11), and the extension portion (152) is extended along the plane direction of the substrate (11) and towards a side away from the recessed portion (151).

4. The array substrate (10) according to claim 3, characterized in that: The extension portion (152) has a first end face and a second end face arranged opposite to each other in a direction perpendicular to the plane where the substrate (11) is located, the first end face and the second end face are at least partially staggered in the direction where the substrate (11) is located, the first end face is arranged close to the recessed portion (151) relative to the second end face, and the first end face and the second end face are connected at one end away from the recessed portion (151) to form an inclined surface.

5. The array substrate (10) according to any one of claims 1 to 4, characterized in that: A first gate insulating layer (16) is provided between the second gate (13) and the first interlayer dielectric layer (14), and the third gate (15) is provided between the first gate insulating layer (16) and the first interlayer dielectric layer (14).

6. The array substrate (10) according to claim 1, characterized in that: Along a direction perpendicular to the plane on which the substrate (11) is located, a projection of the hollowed-out area (141) on the substrate (11) at least covers a projection of the discontinuous area (23) on the substrate (11).

7. The array substrate (10) according to claim 1, characterized in that: The first interlayer dielectric layer (14) has a first inclined side surface (142) and a second inclined side surface (143) which are arranged opposite to each other in the hollowed-out area (141) along the plane direction of the substrate (11); the first inclined side surface (142) and the second inclined side surface (143) extend from an end surface of the first interlayer dielectric layer (14) close to the second gate (13) to an end surface of the first interlayer dielectric layer (14) away from the second gate (13), and are inclined toward a side away from the discontinuity area (23).

8. The array substrate (10) according to claim 1, characterized in that: A second interlayer dielectric layer (18), a buffer layer (17) and a first gate insulating layer (16) are arranged between the second gate (13) and the first interlayer dielectric layer (14); wherein the second interlayer dielectric layer (18) is arranged on a side of the second gate (13) away from the first gate (12), the buffer layer (17) is arranged on a side of the second interlayer dielectric layer (18) away from the second gate (13), and the first gate insulating layer (16) is arranged on a side of the buffer layer (17) away from the second interlayer dielectric layer (18); The hollowed-out region (141) extends in a direction perpendicular to the plane of the substrate (11) and towards a side close to the substrate (11), and spans over at least one of the first gate insulating layer (16), the buffer layer (17) and the second interlayer dielectric layer (18).

9. A method for preparing an array substrate, characterized in that: include: Forming a first gate (12) on a substrate (11); A second gate (13) is formed on a side of the first gate (12) away from the substrate (11), the first gate (12) and the second gate (13) being staggered in a direction of a plane where the substrate (11) is located and forming a discontinuous region (23); A third gate (15) is formed on a side of the second gate (13) away from the first gate (12), the third gate (15) is formed in a region opposite to the discontinuous region (23), and a first interlayer dielectric layer (14) is formed on a side of the third gate (15) away from the second gate (13); or, A first interlayer dielectric layer (14) is formed on a side of the second gate (13) away from the first gate (12), and a hollowing area (141) is formed in an area of ​​the first interlayer dielectric layer (14) opposite to the discontinuity area (23).

10. The method for preparing an array substrate according to claim 9, characterized in that: The third gate (15) is formed on a side of the second gate (13) away from the first gate (12), comprising: A first gate insulating layer (16) is formed on a side of the second gate (13) away from the first gate (12), and the third gate (15) is formed on a side of the first gate insulating layer (16) away from the second gate (13) through a patterning process.

11. The method for preparing an array substrate according to claim 9, characterized in that: A patterning process is used to form a hollowed-out area (141) in the first interlayer dielectric layer (14) in an area opposite to the discontinuity area (23).

12. The method for preparing an array substrate according to claim 11, characterized in that: Before forming a first interlayer dielectric layer (14) on a side of the second gate (13) away from the first gate (12), the method further comprises: forming a second interlayer dielectric layer (18) on a side of the second gate (13) away from the first gate (12); forming a buffer layer (17) on a side of the second interlayer dielectric layer (18) away from the second gate (13); forming a first gate insulating layer (16) on a side of the buffer layer (17) away from the second interlayer dielectric layer (18); The first interlayer dielectric layer (14) is formed on a side of the first gate insulating layer (16) away from the buffer layer (17), and the hollowed-out region (141) extends in a direction perpendicular to the plane of the substrate (11) and toward a side close to the substrate (11), and spans over at least one of the first gate insulating layer (16), the buffer layer (17) and the second interlayer dielectric layer (18).

13. The method for preparing an array substrate according to any one of claims 9 to 12, characterized in that: The method further comprises: A source-drain metal layer (21) is formed on a side of the first interlayer dielectric layer (14) away from the second gate (13), and the source-drain metal layer (21) is subjected to at least two patterning processes in an area opposite to the discontinuity area (23) to remove a residual structure of the source-drain metal layer (21) in the area opposite to the discontinuity area (23).

14. A display panel, characterized in that: The display panel comprises the array substrate (10) according to any one of claims 1 to 8, or comprises the array substrate (10) obtained by the method for preparing the array substrate according to any one of claims 9 to 13.

15. A display device, characterized in that: The display device comprises the display panel according to claim 14.

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