Transverse PIN type photosensitive element, preparation method thereof and photosensitive detector

Abstract

The invention relates to the technical field of semiconductor electronic devices, and provides a transverse PIN type photosensitive element, a preparation method thereof and a photosensitive detector. The transverse PIN type photosensitive element at least comprises an I-type layer which is provided with a first surface and a second surface which are oppositely arranged; the P-type layer is formed on the first surface of the I-type layer, and the upper surface of the P-type layer and the first surface of the I-type layer are located on the same plane; the N-type layer is formed on the first surface of the I-type layer, the upper surface of the N-type layer and the first surface of the I-type layer are on the same plane, and the I-type layer exists between the N-type layer and the P-type layer; and a passivation layer is arranged below the second surface of the I-type layer. According to the transverse PIN type light-sensitive element adopting the structure, an N-type back surface field is not designed on the back surface of the light-sensitive element, but the passivation layer is added, so that the response time of the transverse PIN type light-sensitive element can be greatly reduced, and meanwhile, the light current, especially the long-wave light current, in the transverse PIN type light-sensitive element is not influenced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor electronic devices, and in particular to a lateral PIN type photosensitive element, a preparation method thereof, and a photosensitive detector. Background Art

[0002] In the optocoupler (or optocoupler, photoelectric coupler, optoelectronic isolator) series of products, photodiodes (also called photodiodes, Photodiode) are mainly used to receive light signals and are photodetectors that can convert light into current or voltage signals according to the way it is used. Photodiodes have a certain spectral response range. In recent years, with the expansion of the application field of optocoupler series products, the requirements for the response performance of photodiodes have gradually increased.

[0003] Currently, if Figure 1 As shown, in the existing horizontal (also called "lateral") PIN photodiode, an N-type back field (back electrode) is generally provided on the back (below) of the I layer (intrinsic layer). When light irradiates the P-type layer, a vertical electric field loop from the front to the back can be formed, which is beneficial to increase the photocurrent of the long-wave photodiode. At the same time, the setting of the back electrode in the horizontal PIN photodiode will make the transmission path of the horizontal structure carrier longer, lengthen the carrier transit time, and thus increase the response time of the horizontal PIN photodiode.

[0004] Therefore, in a horizontal PIN type photosensitive element, how to shorten the transmission path of the horizontal structure carriers and reduce or lower the response time of the horizontal structure to increase the response speed and thereby improve the photoelectric performance of the horizontal PIN type photosensitive element has become one of the technical problems that technicians in this field need to solve urgently. Summary of the invention

[0005] In order to solve the shortcomings of the prior art in the response speed of the aforementioned lateral PIN type photosensitive element, the present invention provides a lateral PIN type photosensitive element and a preparation method thereof, and a photosensitive detector, which can shorten the transmission path of horizontal structure carriers, reduce the response time, and improve the response speed.

[0006] In order to achieve at least one of the above advantages or other advantages, the present invention provides a lateral PIN-type photosensitive element, which at least includes: an I-type layer having a first surface and a second surface arranged opposite to each other; a P-type layer formed on the first surface of the I-type layer, and the upper surface of the P-type layer and the first surface of the I-type layer are located in the same plane; an N-type layer formed on the first surface of the I-type layer, and the upper surface of the N-type layer and the first surface of the I-type layer are located in the same plane, and the I-type layer exists between the N-type layer and the P-type layer; wherein a passivation layer is provided below the second surface of the I-type layer.

[0007] In some embodiments, the thickness of the type I layer ranges from 150 to 350 microns.

[0008] In some embodiments, the material of the passivation layer includes at least one selected from the group consisting of silicon oxide (SiOx), aluminum oxide (AlOx), and SiNx; the thickness of the passivation layer ranges from 1 to 500 nanometers.

[0009] In some embodiments, the passivation layer is a single layer or a stacked layer. The passivation layer is not doped. It can be understood that the passivation layer is not doped with boron ions or phosphorus ions.

[0010] In some embodiments, the P-type ions doped in the P-type layer are boron ions. The doping concentration of the boron ions is in the range of 1×10 18 cm -3 ~1×10 19 cm -3 , doping depth is 0.5 to 1.5 microns.

[0011] In some embodiments, the N-type ions doped in the N-type layer are phosphorus ions. The doping concentration of the phosphorus ions is in the range of 1×10 20 cm -3 ~1×10 21 cm -3 , doping depth is 2 to 4 microns.

[0012] In some embodiments, the lateral PIN type photosensitive element may also include: a cut-off ring, located at the edge of the first surface of the I-type layer, an I-type layer exists between the P-type layer and the cut-off ring, and the upper surface of the cut-off ring is located in the same plane as the first surface; an N-type layer is located in the cut-off ring area; an oxide ring, located above the first surface of the I-type layer between the P-type layer and the cut-off ring; a dielectric layer, located above the first surface of the I-type layer and covering the oxide ring; an anti-reflection layer, covering the dielectric layer; wherein the material of the dielectric layer includes at least one selected from the group consisting of silicon oxide (SiOx), aluminum oxide (AlOx), nickel oxide (NiOx), titanium oxide (TiOx), and SiNx, the dielectric layer is a single layer or a stacked layer, and the optical thickness of the dielectric layer is n / 4 of the desired absorption wavelength, where n is a positive odd number.

[0013] In some embodiments, the lateral PIN type photosensitive element may further include a first electrode and a second electrode, the first electrode and the second electrode are located above the anti-reflection layer and are spaced apart from each other, and the first electrode and the second electrode are electrically connected to the P-type layer and the N-type layer, respectively.

[0014] In some embodiments, the excitation wavelength of the lateral PIN photosensitive element is 300 nm to 1100 nm.

[0015] In order to achieve at least one of the above advantages or other advantages, the present invention also provides a method for preparing a lateral PIN type photosensitive element, comprising the following steps: providing a substrate, the substrate having a first surface and a second surface arranged opposite to each other; oxidizing the substrate at a high temperature to form an initial oxide layer on the first surface of the substrate; etching the initial oxide layer to form a photosensitive region above the first surface of the substrate, performing P-type ion diffusion on the substrate in the photosensitive region to form a P-type layer, and forming a first oxide layer on the initial oxide layer and the photosensitive region, wherein the upper surface of the P-type layer is located in the same plane as the first surface of the substrate; forming a cutoff ring in the edge region of the first surface of the substrate, and etching the cutoff ring at the edge region of the cutoff ring. N-type ion diffusion is performed in the stop ring region to form an N-type layer, and a second oxide layer is formed in the first oxide layer and the stop ring region at the same time, the upper surface of the N-type layer is located in the same plane as the first surface of the substrate, and the substrate is provided between the P-type layer and the N-type layer; the first surface of the substrate is etched to expose the upper surfaces of the P-type layer and the N-type layer on the first surface, and an oxide ring is formed between the photosensitive region and the stop ring region, the oxide ring including an initial oxide layer, a first oxide layer and a second oxide layer; a dielectric layer is grown above the first surface of the substrate and covers the oxide ring; the lower portion of the second surface of the substrate is etched, and then a passivation layer is grown below the second surface.

[0016] In some embodiments, after the step of forming the passivation layer, the following steps are also included: growing an anti-reflection layer above the dielectric layer, the anti-reflection layer covering the dielectric layer; performing photolithography etching on the dielectric layer and the anti-reflection layer to form a first electrode through hole and a second electrode through hole to expose the P-type layer and the N-type layer respectively; forming a first electrode and a second electrode on the anti-reflection layer, the first electrode and the second electrode being electrically connected to the P-type layer and the N-type layer through the first electrode through hole and the second electrode through hole respectively.

[0017] In some embodiments, the substrate is a high-resistance silicon substrate and the substrate is an I-type layer, the P-type ions are boron ions, and the N-type ions are phosphorus ions.

[0018] In order to achieve at least one of the above advantages or other advantages, the present invention also provides a photosensitive detector, comprising at least: a circuit board and a plurality of photosensitive elements arranged in an array on the circuit board, the plurality of photosensitive elements being electrically connected to the circuit board, and the photosensitive elements being lateral PIN type photosensitive elements as described in any of the above.

[0019] The lateral PIN type photosensitive element and its preparation method and photosensitive detector provided by the present invention have at least the following advantages compared with the existing lateral PIN type photosensitive element with back electrode: 1. The passivation layer does not have the function of an N-type electrode. After light irradiates the P-type layer, the photogenerated carriers form a lateral current loop on the first surface of the I-type layer, which shortens the response path of the carriers and thus shortens or reduces the response time.

[0020] 2. A passivation layer is provided below the second surface of the I-type layer, which can reduce or minimize backside recombination below the second surface and reduce defects on the second surface, thereby enhancing the photocurrent of the long-wave transverse PIN-type photosensitive element. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 It is a structural schematic diagram of an embodiment of a lateral PIN type photosensitive element in the prior art; Figure 2 It is a schematic side cross-sectional structure diagram of an embodiment of a lateral PIN type photosensitive element in the present invention; Figure 3(a) to Figure 3(d) It is a trtf test curve diagram of the present invention and the existing lateral PIN type photosensitive element; Figure 4 It is a schematic flow chart of an embodiment of a method for preparing a lateral PIN type photosensitive element in the present invention; Figures 5 to 11 It is a schematic diagram of the structure of each stage in the manufacturing process of an embodiment of a method for preparing a lateral PIN type photosensitive element in the present invention; Fig.12 FIG. 4 is a schematic diagram of an embodiment of a photosensitive detector in the present invention.

[0023] Figure numerals: 1-lateral PIN type photosensitive element, 10'-substrate, 10a-first surface, 10b-second surface, 10-I type layer, 12-P type layer, 14-N type layer, 16-passivation layer, 20-cutoff ring, 30-oxide ring / oxide layer, 40-dielectric layer, 41-first electrode through hole, 42-second electrode through hole, 50-anti-reflection layer, 60-first electrode, 70-second electrode, 200-photosensitive area, 3-photosensitive detector, 301-circuit board, 302-photosensitive element, 303-wire. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] In the description of the present invention, it should be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more. In addition, the term "including" and any variation thereof all mean "at least including".

[0026] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integrally formed connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] The terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "one", "one" and "item" used herein are also intended to include plural numbers. It should also be understood that the terms "include" and / or "comprise" used herein specify the existence of stated features, integers, steps, operations, units and / or components, without excluding the existence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0028] Please compare Figure 1 See also Figure 2 , Figure 2 FIG. 1 is a schematic diagram of a side cross-sectional structure of an embodiment of a lateral PIN type photosensitive element in the present invention. To achieve at least one of the above advantages or other advantages, an embodiment of the present invention provides a lateral PIN type photosensitive element. Figure 2 As shown, the lateral PIN type photosensitive element 1 may include at least: an I-type layer 10 , a P-type layer 12 , an N-type layer 14 and a passivation layer 16 .

[0029] The I-type layer 10 has a first surface 10a and a second surface 10b that are arranged opposite to each other. The I-type layer 10 refers to an unintentionally doped layer, and can also be called an intrinsic semiconductor layer. The I-type layer 10 can be used as an internal light absorbing layer, which can effectively absorb light radiated therein. In order to further shorten the transmission distance of photogenerated carriers and thus improve the response speed, in some embodiments, the thickness of the I-type layer 10 ranges from 150 to 350 microns, for example, it can be 150 microns, 200 microns, 250 microns, 300 microns, 350 microns, etc.

[0030] The P-type layer 12 is formed on the first surface 10a of the I-type layer 10, and the upper surface of the P-type layer 12 is located in the same plane as the first surface 10a of the I-type layer 10. The N-type layer 14 is formed on the first surface 10a of the I-type layer 10, and the upper surface of the N-type layer 14 is located in the same plane as the first surface 10a of the I-type layer 10, and the I-type layer 10 exists between the N-type layer and the P-type layer. In other words, in the top view direction of the first surface 10a of the I-type layer 10, the N-type layer 14 is located around the P-type layer 12 and has the I-type layer 10 between it and the P-type layer 12, thereby forming a PIN structure in the lateral direction.

[0031] In some embodiments, the P-type ions doped into the P-type layer 12 are boron ions. Boron ions can be doped by high-temperature deposition diffusion or high-energy ion implantation to form the P-type layer 12. The doping concentration of boron ions ranges from 1×10 18 cm -3 ~1×10 19 cm -3 , the doping depth is 0.5 to 1.5 microns. Specifically, for example, the doping depth of boron ions is 0.5 microns, 0.8 microns, 1 micron, 1.2 microns, 1.5 microns, etc. The N-type ions doped in the N-type layer 14 are phosphorus ions. The phosphorus ions can be doped by high-temperature deposition diffusion or high-energy ion implantation to form the N-type layer 14. The doping concentration of phosphorus ions ranges from 1×10 20 cm -3 ~1×10 21 cm -3 , the doping depth is 2 to 4 microns. Specifically, for example, the doping depth of phosphorus ions is 2 microns, 2.5 microns, 3 microns, 3.5 microns, 4 microns, etc. The above-mentioned P-type layer 12 can be used as a light receiving side, and the P-type layer 12 and the N-type layer 14 constitute the photosensitive part of the lateral PIN type photosensitive element 1, which can realize the photoelectric conversion function of the photosensitive element.

[0032] The cut-off ring 20 is located at the edge of the first surface 10a of the I-type layer 10, and the I-type layer 10 exists between the P-type layer 12 and the cut-off ring 20. The cut-off ring 20 can be used to block the leakage problem caused by the sidewall defects of the cutting path. As shown in the figure, in some embodiments, the upper surface of the cut-off ring 20 and the first surface 10a of the I-type layer 10 are located in the same plane, and the cut-off ring 20 is doped with N-type ions, thereby forming the above-mentioned N-type layer 14 in the cut-off ring 20 area. The upper surface of the cut-off ring 20 (with the N-type layer 14), the first surface 10a of the I-type layer 10, and the upper surface of the P-type layer 12 are all located in the same plane, thereby forming a lateral PIN structure on the first surface 10a of the I-type layer 10.

[0033] The oxide ring 30 is located above the first surface 10a of the I-type layer 10 between the P-type layer 12 and the cut-off ring 20. The oxide ring 30 may be an oxide material layer formed above the first surface 10a of the I-type layer 10 by high-temperature oxidation. In the top view direction of the first surface 10a of the I-type layer 10, the oxide ring 30 surrounds the P-type layer 12. The oxide ring 30 may protect the first surface 10a of the I-type layer 10 around the P-type layer 12. The oxide ring 30 may also play an isolating role, such as isolating leakage problems caused by contamination, or protecting the lateral PIN-type photosensitive element 1 from being damaged by external forces during the cutting process, which is beneficial to improving the yield and reliability of the lateral PIN-type photosensitive element 1.

[0034] As shown in the figure, in some embodiments, in the top view direction of the first surface 10a of the I-type layer 10, the projection surface of the oxide ring 30 partially overlaps with the projection surface of the P-type layer 12. The thickness of the oxide ring 30 is greater than or equal to 5000 angstroms. The material of the oxide ring 30 may include SiO2.

[0035] The dielectric layer 40 is located above the first surface 10 a of the I-type layer 10 . The dielectric layer 40 covers the upper surface of the P-type layer 12 , the upper surface of the stop ring 20 (including the N-type layer 14 ), and the oxide ring 30 .

[0036] In some embodiments, the material of the dielectric layer 40 includes at least one selected from the group consisting of silicon oxide (SiOx), aluminum oxide (AlOx), nickel oxide (NiOx), titanium oxide (TiOx), and SiNx. The dielectric layer 40 can be a single-layer structure of one of the material groups or a stacked structure of two or more.

[0037] The dielectric layer 40 may have a variety of functions, such as passivation and the surface of the P-type layer 12 and the N-type layer 14, and an anti-reflection layer for blue-green light, etc. Different functions have different requirements for the thickness of the dielectric layer 40. The optical thickness of the dielectric layer 40 is n / 4 (n is a positive odd number) of the desired absorption wavelength, which can minimize the reflectivity of the dielectric layer 40. Generally, the desired absorption wavelength is represented by λ, and the optical thickness of the dielectric layer 40 can be 1 / 4λ, 3 / 4λ, 5 / 4λ, 7 / 4λ... The desired absorption wavelength refers to the device detection wavelength of the photosensitive element.

[0038] An anti-reflection layer 50 may also be formed on the first surface 10a of the I-type layer 10. The anti-reflection layer 50 covers the dielectric layer 40. The material of the anti-reflection layer 50 may be at least one of silicon nitride and titanium oxide or a combination of multiple thereof. The anti-reflection layer 50 is mainly provided to reduce the amount of light reflection and increase the amount of light transmission, and also to reduce the energy loss of light in the photosensitive area 200, thereby improving the light transmission effect and enhancing the photoelectric conversion efficiency of the lateral PIN type photosensitive element 1.

[0039] The lateral PIN type photosensitive element 1 may further include an electrode structure, which includes a first electrode 60 and a second electrode 70. The first electrode 60 and the second electrode 70 are located above the anti-reflection layer 50 and are spaced apart from each other. The first electrode 60 is electrically connected to the P-type layer 12, and the second electrode 70 is electrically connected to the N-type layer 14. A good ohmic contact is formed between the first electrode 60 and the P-type layer 12, and a good ohmic contact is formed between the second electrode 70 and the N-type layer 14. The material of the first electrode 60 and the second electrode 70 can be a metal material, such as Al, Ag, Pt, Au, Ti and other metal materials.

[0040] A passivation layer 16 is provided below the second surface 10b of the I-type layer 10. The material of the passivation layer 16 includes at least one selected from the group consisting of silicon oxide (SiOx), aluminum oxide (AlOx), and SiNx. The passivation layer 16 can be a single-layer structure of one of the material groups or a stacked structure of two or more. The thickness of the passivation layer 16 ranges from 1 to 500 nanometers. The passivation layer 16 is not doped. In other words, the passivation layer 16 is neither doped with boron ions nor doped with phosphorus ions. In the present application, the conductive properties of the passivation layer 16 are not limited. For example, the passivation layer 16 can be a fully conductive type or a semi-conductive type.

[0041] In some embodiments, for example, the passivation layer 16 can be a stacked structure composed of SiOx and SiNx, a stacked structure composed of AlOx and SiNx, etc. Considering the production cost, in actual production, the preferred material of the passivation layer 16 is SiO2, Al2O3, etc. In the actual manufacturing process, the chemical formula of the thin film material of the passivation layer 16 formed by the passivation layer 16, the dielectric layer 40, etc. is not unique according to the growth mode and the growth environment setting conditions (such as gas type, ratio, etc.). In the scheme of the present application, according to the actual production situation, X in the materials SiOx, AlOx and SiNx can be any feasible value. In some embodiments, the excitation wavelength of the lateral PIN type photosensitive element is 300nm to 1100nm.

[0042] The passivation layer 16 in the lateral PIN photosensitive element 1 does not have the function of an N-type electrode. After light irradiates the P-type layer 12, the photogenerated carriers form a current loop on the first surface 10a of the I-type layer 10, which shortens the response path of the carriers, thereby shortening or reducing the response time. Secondly, the passivation layer 16 is arranged below the second surface 10b of the I-type layer 10, which can reduce or reduce the backside recombination below the second surface 10b, thereby enhancing the photocurrent of the long-wave lateral PIN photosensitive element.

[0043] When light irradiates the surface of the lateral PIN photosensitive element 1 (above the P-type layer 12), the energy of the photon excites the covalent electrons in the PN junction into free electrons, and generates corresponding holes at the same time. These carriers (electron-hole pairs) are separated under the action of the built-in electric field of the PN junction, thereby forming a photocurrent. In the present application, the lateral PIN photosensitive element 1 is designed without a back field (without a back electrode), so the transmission path of the carriers is directly completed in the horizontal PN structure, the transmission path becomes shorter, and the response time becomes shorter; at the same time, the design of adding a passivation layer 16 in the back field area can reduce the recombination phenomenon on the back side, and the photocurrent of all bands (especially long waves) of the lateral PIN photosensitive element 1 will not be reduced due to the design without a back field.

[0044] Table 1 shows the test data of photocurrent and response time of the conventional lateral PIN photosensitive element with back field electrode and the lateral PIN photosensitive element 1 of the present invention.

[0045] Table 1 Comparison of photocurrent test data, difference percentage and response time in different bands

[0046] Notes for Table 1: ①TR is the rise time, TF is the fall time. ②The difference percentage is defined as 100% for comparison.

[0047] Figure 3(a) to Figure 3(d)The conditions of the trtf test curve are: applying a pulse light signal to the photosensitive element (a rectangular pulse signal is applied to the photosensitive element during the test corresponding to Table 1), measuring the data voltage change of the photosensitive element under the conditions of a frequency of 1KHz, an external bias of 0V, and a series resistance of 1KΩ, and then obtaining the trtf curve.

[0048] According to Table 1 and Figure 3(a) to Figure 3(d) It can be seen from the experimental parameters in that the lateral PIN type photosensitive element 1 provided by the present invention can improve the response speed of the photosensitive element, reduce or decrease the response time of the photosensitive element, thereby improving the photoelectric performance of the lateral PIN type photosensitive element 1.

[0049] To achieve at least one of the above advantages or other advantages, an embodiment of the present invention provides a method for preparing a lateral PIN type photosensitive element, which can be used to prepare a lateral PIN type photosensitive element 1 having the structure as described above.

[0050] See also Figures 4 to 11 , Figure 4 FIG. 1 is a flow chart of an embodiment of a method for preparing a lateral PIN type photosensitive element in the present invention. Figures 5 to 11 It is a schematic diagram of the structures of various stages in the manufacturing process of an embodiment of a method for preparing a lateral PIN type photosensitive element in the present invention.

[0051] Please combine Figure 2 See also Figures 4 to 11 ,use Figures 4 to 11 The preparation method shown is as follows Figure 2 The process method of the lateral PIN type photosensitive element shown is described as follows.

[0052] S100: Provide a substrate, wherein the substrate has a first surface and a second surface that are oppositely disposed.

[0053] See also Figure 5 , a substrate 10' is provided, and the substrate 10' has a first surface 10a and a second surface 10b arranged opposite to each other. In the figure, the first surface 10a is defined as the front side (upper side) of the photosensitive element, and the second surface 10b is defined as the back side (lower side) of the photosensitive element. In some embodiments, as shown in the figure, the substrate 10' is a high-resistance silicon substrate, which is an N-type substrate, has a crystal orientation of 111, and a resistivity of 1500-5000Ω.cm. The initial thickness of the substrate 10' is generally 150 to 350 microns. For example, the initial thickness of the substrate 10' can be 150 microns, 200 microns, 250 microns, 300 microns, 350 microns, etc.

[0054] S200: oxidizing the substrate at a high temperature to form an initial oxide layer on the first surface.

[0055] See again Figure 5The initial oxide layer of the mask is formed on the first surface 10a of the substrate 10' by a high temperature oxidation process. The thickness of the initial oxide layer is greater than or equal to 5000 angstroms. The initial oxide layer eventually forms an oxide ring 30 after subsequent etching processes. Figure 5 In the following figures, the oxide layer or oxide ring is indicated by reference numeral 30. In the substrate 10', the undoped portion is the I-type layer 10 later.

[0056] S300: etching the initial oxide layer, opening the photosensitive region and performing P-type ion diffusion to form a P-type layer.

[0057] See also Figure 6 , the initial oxide layer is photolithographically and etched to remove the initial oxide layer in the central area of ​​the first surface 10a of the substrate 10', exposing the first surface 10a of the substrate 10' as a photosensitive area 200. The photosensitive area 200 serves as a light receiving area of ​​the photosensitive element and receives light. P-type ion diffusion is performed on the substrate 10' in the photosensitive area 200 to form a P-type layer 12, and a first oxide layer is formed on the initial oxide layer and the photosensitive area 200. The upper surface of the P-type layer 12 is located in the same plane as the first surface 10a of the substrate 10'.

[0058] In a specific embodiment, boron oxide is used as a raw material for P-type ion diffusion / implantation. When the boron ions are diffused in the photosensitive region 200, a first oxide layer (not shown in the figure) is formed on the initial oxide layer and above the photosensitive region 200 to chemically react with the boron oxide, thereby diffusing boron ions in the substrate 10' corresponding to the photosensitive region 200 to form a P-type layer 12.

[0059] In some embodiments, as shown in the figure, the P-type ions are boron ions. Boron ions can be doped and diffused by high-temperature deposition diffusion or high-energy ion implantation to form the P-type layer 12. In the substrate 10', the square resistance of the boron ion doped and diffused area is about 500-1000Ω.cm. The doping concentration of boron ions ranges from 1×10 18 cm -3 ~1×10 19 cm -3 , the doping depth is 0.5 to 1.5 microns. Specifically, for example, the doping depth of boron ions is 0.5 microns, 0.8 microns, 1 micron, 1.2 microns, 1.5 microns, etc.

[0060] S400: forming a cut-off ring in an edge region of the first surface of the substrate, and performing N-type ion diffusion in the cut-off ring region to form an N-type layer.

[0061] See also Figure 7A cut-off ring 20 is formed in the edge region of the first surface 10a of the substrate 10', N-type ion diffusion is performed in the region of the cut-off ring 20 to form an N-type layer 14, and a second oxide layer is formed in the region of the first oxide layer and the cut-off ring 20. The upper surface of the N-type layer 14 is located in the same plane as the first surface 10a of the substrate 10', and the substrate 10' is provided between the P-type layer 12 and the N-type layer 14.

[0062] In a specific embodiment, phosphorus oxide is used as a raw material for N-type ion diffusion / implantation. When phosphorus ion diffusion is performed in the cutoff ring 20 region, a second oxide layer (not shown in the figure) is formed on the first oxide layer and the cutoff ring 20 at the same time.

[0063] In some embodiments, as shown in the figure, the N-type ions are phosphorus ions. The phosphorus ions can be doped and diffused by high-temperature deposition diffusion or high-energy ion implantation to form the N-type layer 14. The N-type layer 14 is located at least in a portion of the cutoff ring 20 in the substrate 10'. In the substrate 10', the square resistance of the phosphorus ion doped and diffused area is about 4-5Ω.cm. The doping concentration of the phosphorus ions ranges from 1×10 20 cm -3 ~1×10 21 cm -3 , the doping depth is 2 to 4 microns. Specifically, for example, the doping depth of phosphorus ions is 2 microns, 2.5 microns, 3 microns, 3.5 microns, 4 microns, etc.

[0064] S500: etching the first surface of the substrate to expose upper surfaces of the P-type layer and the N-type layer on the first surface, and forming an oxide ring between the photosensitive region and the cut-off ring.

[0065] See again Figure 7 , the first surface 10a of the substrate 10' is etched again to remove the second oxide layer in the photosensitive region 200 and the cut-off ring 20 region, so as to expose the upper surfaces of the P-type layer 12 and the N-type layer 14 on the first surface 10a of the substrate 10', and form an oxide ring 30 on the first surface 10a between the photosensitive region 200 and the cut-off ring 20. In a specific embodiment, the oxide ring 30 includes an initial oxide layer, a first oxide layer (formed when the P-type ions are diffused), and a second oxide layer (formed when the N-type ions are diffused).

[0066] S600: growing a dielectric layer above the first surface of the substrate, wherein the dielectric layer covers the oxide ring.

[0067] See also Figure 8, a dielectric layer 40 is grown on the first surface 10a of the substrate 10'. In some embodiments, the dielectric layer 40 covers the upper surface of the P-type layer 12, the upper surface of the stop ring 20 (including the N-type layer 14), and the oxide ring 30. The optical thickness of the dielectric layer 40 is n / 4 (n is a positive odd number) of the desired absorption wavelength, which can minimize the reflectivity of the dielectric layer 40. The desired absorption wavelength refers to the device detection wavelength of the photosensitive element.

[0068] In some embodiments, the material of the dielectric layer 40 includes at least one selected from the group consisting of silicon oxide (SiOx), aluminum oxide (AlOx), nickel oxide (NiOx), titanium oxide (TiOx), and SiNx. The dielectric layer 40 can be a single-layer structure of one of the material groups or a stacked structure of two or more.

[0069] S700: growing a passivation layer below the second surface of the substrate.

[0070] See also Fig. 9 , etching below the second surface 10b of the substrate 10' to remove the back field, and then growing a passivation layer 16 below the second surface 10b. In some embodiments, the second surface 10b of the substrate 10' can be corroded by a KOH solution to remove the back field formed by phosphorus diffusion in the area below the second surface 10b. The material of the passivation layer 16 includes at least one selected from the group consisting of silicon oxide (SiOx), aluminum oxide (AlOx), and SiNx. The passivation layer 16 can be a single-layer structure of one of the material groups or a stacked structure of two or more. The thickness of the passivation layer 16 ranges from 1 to 500nm. Providing a passivation layer 16 on the back of the photosensitive element can inhibit back recombination (such as metal recombination) and reduce / reduce surface defects on the back, thereby increasing long-wave photocurrent.

[0071] S800: growing an anti-reflection layer on the dielectric layer, wherein the anti-reflection layer covers the dielectric layer.

[0072] See also Fig.10 , an anti-reflection layer 50 is grown on the dielectric layer 40, and the anti-reflection layer 50 covers the dielectric layer 40. The material of the anti-reflection layer 50 can be at least one of silicon nitride and titanium oxide, or a combination of multiple thereof. The anti-reflection layer 50 can reduce the reflection of light incident to the P-type layer 12, increase the transmission of light, and improve the photoelectric conversion efficiency.

[0073] S900: forming a first electrode through hole and a second electrode through hole on the anti-reflection layer and the dielectric layer, and forming a first electrode and a second electrode on the anti-reflection layer.

[0074] See also Fig.11, the dielectric layer 40 and the anti-reflection layer 50 are photolithographically and etched, and a first electrode through hole 41 and a second electrode through hole 42 are formed on the dielectric layer 40 and the anti-reflection layer 50, and the first electrode through hole 41 and the second electrode through hole 42 expose the P-type layer 12 and the N-type layer 14 respectively, and then the first electrode 60 and the second electrode 70 are formed in the first electrode through hole 41 and the second electrode through hole 42 respectively; finally, the entire substrate 10' is cut to obtain a single lateral PIN-type photosensitive element 1. The material of the first electrode 60 and the second electrode 70 can be a metal material, such as Al, Ag, Pt, Au, Ti and other metal materials. In some embodiments, the first electrode through hole 41 and the second electrode through hole 42 are both ohmic contact holes. The first electrode 60 and the second electrode 70 are electrically connected to the P-type layer 12 and the N-type layer 14 respectively through the first electrode through hole 41 and the second electrode through hole, and further, the connection mode is ohmic contact. For example, metal Al is sputtered on the upper surface of the anti-reflection layer 50, and photolithography etching is performed again to retain the Al on the first electrode through hole 41 and the second electrode through hole 42, and annealing is performed to form an ohmic contact of the PN electrode.

[0075] In order to achieve at least one of the above advantages or other advantages, the present invention also provides a photosensitive detector, comprising at least: a circuit board and a plurality of photosensitive elements arranged in an array on the circuit board, the plurality of photosensitive elements being electrically connected to the circuit board, and the photosensitive elements being lateral PIN type photosensitive elements 1 as described above.

[0076] Combination Figure 1 See also Fig.12 , Fig.12 Schematic diagram of an embodiment of a photosensitive detector in the present invention. The illustrated embodiment provides a photosensitive detector 3 , which includes a circuit board 301 and a plurality of photosensitive elements 302 .

[0077] The circuit board 301 may be provided with one or more of an analog-to-digital conversion circuit, a comparison circuit, and an amplification circuit. A plurality of photosensitive elements 302 are fixed to the circuit board 301 and are electrically connected to the response circuit of the circuit board via an electrode structure. In the illustrated embodiment, the photosensitive element 302 is a lateral PIN type photosensitive element 1 provided in the above embodiment of the present application. Fig.12 As shown, one side of the photosensitive element 302, i.e., the back side, is directly fixed to the circuit board 301, and the other side, i.e., the second electrode 70 side, is connected to the circuit board 301 by wire bonding via the wire 303. Therefore, it also has good photoelectric conversion efficiency and better photon response speed.

[0078] Compared with the existing lateral PIN photosensitive element with a back electrode, the lateral PIN photosensitive element 1 and its preparation method and photosensitive detector provided by the present invention are provided with a passivation layer 16 below the second surface 10b of the I-type layer 10. The passivation layer 16 does not have the function of an N-type electrode. After light irradiates the P-type layer 12, the photogenerated carriers form a lateral current loop on the first surface 10a of the I-type layer 10, so that the response path of the carriers becomes shorter, thereby shortening or reducing the response time. Furthermore, the passivation layer 16 provided below the second surface 10b of the I-type layer 10 can reduce or reduce the back metal recombination below the second surface 10b and improve the surface defects in this area, thereby enhancing the long-wave photocurrent of the lateral PIN photosensitive element 1.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A lateral PIN type photosensitive element, characterized in that: At least: The I-type layer has a first surface and a second surface disposed opposite to each other; A P-type layer is formed on the first surface of the I-type layer, and an upper surface of the P-type layer and the first surface of the I-type layer are located in the same plane; An N-type layer is formed on the first surface of the I-type layer, an upper surface of the N-type layer and the first surface of the I-type layer are located in the same plane, and the I-type layer is located between the N-type layer and the P-type layer; Wherein, a passivation layer is provided below the second surface of the I-type layer.

2. The lateral PIN type photosensitive element according to claim 1, characterized in that: The thickness of the type I layer ranges from 150 to 350 microns.

3. The lateral PIN type photosensitive element according to claim 1, characterized in that: The material of the passivation layer includes at least one selected from the group consisting of silicon oxide (SiOx), aluminum oxide (AlOx), and SiNx; the thickness of the passivation layer ranges from 1 to 500 nanometers.

4. The lateral PIN type photosensitive element according to claim 1, characterized in that: The passivation layer is a single layer or a stacked layer; the passivation layer is not doped.

5. The lateral PIN type photosensitive element according to claim 1, characterized in that: The P-type ions doped in the P-type layer are boron ions, and the doping concentration of the boron ions is in the range of 1×10 18 cm -3 ~1×10 19 cm -3 , doping depth is 0.5 to 1.5 microns.

6. The lateral PIN type photosensitive element according to claim 1, characterized in that: The N-type ions doped in the N-type layer are phosphorus ions, and the doping concentration of the phosphorus ions is in the range of 1×10 20 cm -3 ~1×10 21 cm -3 , doping depth is 2 to 4 microns.

7. The lateral PIN type photosensitive element according to claim 1, characterized in that: The lateral PIN type photosensitive element further comprises: a cut-off ring, located at an edge of the first surface of the I-type layer, the I-type layer exists between the P-type layer and the cut-off ring, and the upper surface of the cut-off ring and the first surface are located in the same plane; the N-type layer is located in the cut-off ring area; an oxide ring located above the first surface of the I-type layer between the P-type layer and the cutoff ring; a dielectric layer, located above the first surface of the I-type layer and covering the oxide ring; an anti-reflection layer, covering the dielectric layer; The material of the dielectric layer includes at least one selected from the group consisting of silicon oxide (SiOx), aluminum oxide (AlOx), nickel oxide (NiOx), titanium oxide (TiOx), and SiNx. The dielectric layer is a single layer or a stacked layer. The optical thickness of the dielectric layer is n / 4 of the desired absorption wavelength, where n is a positive odd number.

8. The lateral PIN type photosensitive element according to claim 7, characterized in that: The lateral PIN type photosensitive element further includes a first electrode and a second electrode, wherein the first electrode and the second electrode are located above the anti-reflection layer and are spaced apart from each other, and the first electrode and the second electrode are electrically connected to the P-type layer and the N-type layer, respectively.

9. The lateral PIN type photosensitive element according to claim 1, characterized in that: The excitation wavelength of the lateral PIN type photosensitive element is 300nm to 1100nm.

10. A method for preparing a lateral PIN type photosensitive element, characterized in that: The following steps are involved: Providing a substrate, the substrate having a first surface and a second surface disposed opposite to each other; Oxidizing the substrate at a high temperature to form an initial oxide layer on the first surface of the substrate; Etching the initial oxide layer to form a photosensitive region above the first surface of the substrate, performing P-type ion diffusion on the substrate in the photosensitive region to form a P-type layer, and simultaneously forming a first oxide layer on the initial oxide layer and the photosensitive region, wherein the upper surface of the P-type layer is located in the same plane as the first surface of the substrate; A cut-off ring is formed in an edge region of the substrate, N-type ions are diffused in the cut-off ring region to form an N-type layer, and a second oxide layer is formed in the first oxide layer and the cut-off ring region, wherein the upper surface of the N-type layer and the first surface of the substrate are located in the same plane, and the substrate is located between the P-type layer and the N-type layer; Etching the first surface of the substrate to expose the upper surfaces of the P-type layer and the N-type layer on the first surface and to form an oxide ring between the photosensitive region and the cut-off ring; Growing a dielectric layer above the first surface of the substrate and covering the oxide ring; The substrate is etched below the second surface, and then a passivation layer is grown below the second surface.

11. The method for preparing a lateral PIN type photosensitive element according to claim 10, characterized in that: After the step of forming the passivation layer, the method further comprises the following steps: Growing an anti-reflection layer on the dielectric layer, wherein the anti-reflection layer covers the dielectric layer; Performing photolithographic etching on the dielectric layer and the anti-reflection layer to form a first electrode through hole and a second electrode through hole to expose the P-type layer and the N-type layer respectively; A first electrode and a second electrode are formed on the anti-reflection layer, and the first electrode and the second electrode are electrically connected to the P-type layer and the N-type layer through the first electrode through hole and the second electrode through hole, respectively.

12. The method for preparing a lateral PIN type photosensitive element according to claim 11, characterized in that: The substrate is a high-resistance silicon substrate and the substrate is an I-type layer, the P-type ions are boron ions, and the N-type ions are phosphorus ions.

13. A photosensitive detector, characterized in that: At least: A circuit board and a plurality of photosensitive elements arrayed on the circuit board, wherein the plurality of photosensitive elements are electrically connected to the circuit board, and the photosensitive elements are transverse PIN type photosensitive elements as claimed in any one of claims 1 to 9.

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