Preparation method and system of low-cost heterojunction battery assembly

Abstract

The invention provides a preparation method and system of a low-cost heterojunction battery assembly, and the method comprises the steps: taking the maintenance of the yield and the conversion efficiency of a heterojunction battery as a constraint condition, and preparing a large-size ultrathin N-type silicon wafer with the thickness smaller than a preset thickness threshold value through an optimized slicing technology; a transparent conductive thin film TCO with the optimized target material is deposited on the silicon wafer, and the transparent conductive thin film TCO with the optimized target material comprises a metal nanowire structure; preparing a high-molecular resin carrier of a corresponding type according to the low-temperature process requirement of the large-size ultrathin N-type silicon wafer, and carrying out silk-screen printing on the coated silicon wafer through silver-coated copper slurry; the heterojunction battery after silk-screen printing is packaged through multiple packaging materials, and the multiple packaging materials comprise a waterproof material based on butyl rubber. According to the method, the production cost of the heterojunction cell module can be reduced on the basis of ensuring that the efficiency of the heterojunction cell module is basically unchanged.

Description

Technical Field

[0001] The present application relates to the technical field of photovoltaic module preparation, and in particular to a method and system for preparing a low-cost heterojunction battery module. Background Art

[0002] Intrinsic thin-film heterojunction cells (Heterojunction Technology, referred to as HJT) are widely favored in various fields due to their advantages such as high yield, simple structure, high conversion efficiency and double-sided power generation. However, in actual battery component production applications, the process route of heterojunction cells is not interoperable with other more mature solar cell processes. The costs of coating targets and silver paste used in HJT cells are much higher than other types of solar cells.

[0003] Therefore, how to reduce the production cost of HJT batteries has become an urgent problem that needs to be solved. Summary of the invention

[0004] The present application aims to solve one of the technical problems in the related art at least to some extent.

[0005] To this end, the first purpose of the present application is to propose a low-cost method for preparing heterojunction battery modules, which can significantly reduce the production cost of heterojunction battery modules while ensuring that the efficiency of the heterojunction battery modules remains basically unchanged, which is beneficial to cost reduction and efficiency improvement of heterojunction battery modules.

[0006] The second objective of the present application is to provide a low-cost heterojunction battery assembly preparation system.

[0007] A third object of the present application is to provide a non-transitory computer-readable storage medium.

[0008] To achieve the above-mentioned object, the first aspect of the present application is to propose a method for preparing a low-cost heterojunction battery component, the method comprising the following steps:

[0009] Under the constraint of maintaining the yield rate and conversion efficiency of heterojunction cells, large-size ultra-thin N-type silicon wafers with a thickness less than a preset thickness threshold are prepared through an optimized slicing process;

[0010] Depositing an amorphous silicon film and a transparent conductive film TCO after target material optimization on the large-size ultra-thin N-type silicon wafer after texturing and cleaning, wherein the transparent conductive film TCO after target material optimization includes a metal nanowire structure;

[0011] According to the low-temperature process requirements of the large-size ultra-thin N-type silicon wafer, a corresponding type of polymer resin carrier is prepared, and a silver-coated copper slurry is prepared according to the polymer resin carrier, and the coated silicon wafer is screen-printed by the silver-coated copper slurry;

[0012] The screen-printed heterojunction battery is packaged by using a variety of packaging materials, wherein the various packaging materials include a butyl rubber-based water-blocking material.

[0013] Optionally, in one embodiment of the present application, maintaining the yield rate of the heterojunction battery includes: performing electroluminescence detection EL on the large-size ultra-thin N-type silicon wafer prepared under low temperature conditions, ensuring that the EL image obtained by the detection does not contain various types of defects, and the various types of defects include warping; maintaining the conversion efficiency of the heterojunction battery includes: in a solar cell simulation application, simulating and calculating the open circuit voltage and short circuit current of the heterojunction battery prepared according to the large-size ultra-thin N-type silicon wafer, and analyzing the expected efficiency change of the heterojunction battery based on the simulated open circuit voltage and short circuit current; ensuring that the expected efficiency change is within the allowable variation range.

[0014] Optionally, in one embodiment of the present application, depositing the transparent conductive film TCO after the target material is optimized includes: adding a metal nanowire structure to the target material of the transparent conductive film TCO; and reducing the amount of the target material of the transparent conductive film TCO according to the added metal nanowire structure.

[0015] Optionally, in one embodiment of the present application, depositing the transparent conductive film TCO after the target material is optimized also includes: coating a graphene film on the composite TCO film to which the metal nanowire structure is added; and reducing the target material dosage of the composite TCO film according to the dosage of the graphene film.

[0016] Optionally, in one embodiment of the present application, the preparing of a corresponding type of polymer resin carrier according to the low-temperature process requirements of the large-size ultra-thin N-type silicon wafer comprises: according to the low-temperature process requirements of the large-size ultra-thin N-type silicon wafer, selecting a plurality of constituent materials of the polymer resin carrier so that the generated polymer resin carrier can be cured at the temperature required by the low-temperature process; the preparing of silver-coated copper slurry according to the polymer resin carrier comprises: adjusting the ratio of silver powder, copper powder and the polymer resin carrier in the silver-coated copper slurry with maintaining the conversion efficiency of the heterojunction battery as a constraint condition.

[0017] Optionally, in one embodiment of the present application, the packaging of the screen-printed heterojunction battery using a variety of packaging materials also includes: based on the water vapor sensitivity of the heterojunction battery, mixing butyl rubber and silica gel as the water-blocking material; adding a corresponding amount of light-converting material to the anti-reflection film coated on the photovoltaic glass, and replacing the light-converting adhesive film with an ordinary photovoltaic adhesive film.

[0018] To achieve the above-mentioned purpose, the second aspect of the present application also proposes a low-cost heterojunction battery assembly preparation system, comprising the following modules:

[0019] The slicing module is used to prepare large-size ultra-thin N-type silicon wafers with a thickness less than a preset thickness threshold through an optimized slicing process, with the yield and conversion efficiency of heterojunction cells as constraints;

[0020] A deposition module, used for depositing an amorphous silicon film and a transparent conductive film TCO after target material optimization on the large-size ultra-thin N-type silicon wafer after texturing and cleaning, wherein the transparent conductive film TCO after target material optimization includes a metal nanowire structure;

[0021] A printing module, used for preparing a corresponding type of polymer resin carrier according to the low-temperature process requirements of the large-size ultra-thin N-type silicon wafer, preparing a silver-coated copper slurry according to the polymer resin carrier, and screen-printing the coated silicon wafer with the silver-coated copper slurry;

[0022] A packaging module is used to package heterojunction batteries after screen printing using a variety of packaging materials, wherein the various packaging materials include a water-blocking material based on butyl rubber.

[0023] In order to implement the above-mentioned embodiments, the third aspect of the present application also proposes a non-temporary computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the method for preparing a low-cost heterojunction battery component in the above-mentioned first aspect is implemented.

[0024] The technical solution provided by the embodiment of the present application brings at least the following beneficial effects: the present application firstly takes the yield rate and conversion efficiency of the heterojunction battery as the constraint condition, and prepares a large-sized ultra-thin N-type silicon wafer with a thickness less than the preset thickness threshold through the optimized slicing process; then deposits the transparent conductive film TCO after the target material is optimized on the silicon wafer, wherein the transparent conductive film TCO after the target material is optimized includes a metal nanowire structure; then prepares the corresponding type of polymer resin carrier according to the low-temperature process requirements of the large-sized ultra-thin N-type silicon wafer, and screen-prints the coated silicon wafer with silver-coated copper slurry; finally, the screen-printed heterojunction battery is packaged with a variety of packaging materials, wherein the various packaging materials include a water-blocking material based on butyl rubber. Thus, the present application starts from multiple angles such as preparing ultra-large and ultra-thin silicon wafers to reduce silicon consumption, using silver-coated copper slurry to reduce silver paste costs, optimizing TCO processes to achieve target material cost reduction and reduce component packaging material costs, and reduces the production cost of heterojunction battery components in various ways at different stages of battery component preparation. And while reducing costs, the conversion efficiency of the battery component is basically unchanged. Therefore, the present application can significantly reduce the production cost of heterojunction battery components, is conducive to the promotion and application of heterojunction battery components, and improves the practicality of heterojunction battery components.

[0025] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0027] Figure 1 A flow chart of a method for preparing a low-cost heterojunction battery assembly proposed in an embodiment of the present application;

[0028] Figure 2 A flow chart of a method for optimizing target material for a transparent conductive film proposed in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of the structure of a low-cost heterojunction battery assembly preparation system proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0030] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0031] A method and system for preparing a low-cost heterojunction battery assembly according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

[0032] Figure 1 A flow chart of a method for preparing a low-cost heterojunction battery assembly proposed in an embodiment of the present application, such as Figure 1 As shown, the method comprises the following steps:

[0033] Step S101, maintaining the yield and conversion efficiency of the heterojunction battery as constraints, preparing a large-size ultra-thin N-type silicon wafer with a thickness less than a preset thickness threshold through an optimized slicing process.

[0034] It should be noted that since the heterojunction process route is not interoperable with traditional PERC cells, it cannot be extended and can only be newly put into production. In addition, the heterojunction battery production equipment is incompatible with the PERC production equipment. The introduction of PECVD film making machines and vacuum equipment has increased the production cost of heterojunction batteries. In addition, since the amorphous silicon film of the heterojunction battery has a high hydrogen content, low-temperature silver paste must be used in the screen printing process. The consumption of low-temperature silver paste is large and the cost of silver paste is high, which leads to the cost of heterojunction batteries being much higher than that of PERC batteries. This application investigates and analyzes the overall preparation process of heterojunction battery components, and compares and concludes that the large cost gap is mainly reflected in the target material and silver paste of the TCO film. Based on this, this application conducts cost reduction design in multiple major links in the preparation process of heterojunction battery components.

[0035] Specifically, the present application starts with the preparation of the battery end of the heterojunction battery assembly for the purpose of cost reduction, and the first step is the initial preparation of the silicon wafer substrate of the heterojunction battery. Since the substrate of the heterojunction battery is an N-type silicon wafer, this type of silicon wafer has a higher potential for thinning, and the structure of the heterojunction battery wafer is highly compatible with thin silicon wafers, the thinning technology is conducive to reducing silicon consumption and silicon wafer costs. Therefore, the present application first optimizes the slicing process to prepare large-size ultra-thin N-type silicon wafers with a thickness less than a preset thickness threshold.

[0036] Among them, when the thickness of the silicon wafer is less than the preset thickness threshold, it indicates that the silicon wafer is an ultra-thin N-type silicon wafer that meets the requirements. Through experiments and research, this application has determined that every 10μm thinning of a general silicon wafer can reduce the cost of silicon per watt by about 0.01 yuan. This application can set a thickness threshold based on the current silicon material price and cost requirements. For example, the thickness threshold can be set to 130μm, or the thickness of the heterojunction cell can be set to less than 100μm based on the structural characteristics analysis of the silicon wafer and the development of slicing technology.

[0037] During specific implementation, in order to ensure the photoelectric conversion efficiency of the battery while reducing costs, the present application also takes maintaining the yield rate and conversion efficiency of the heterojunction battery basically unchanged from the current heterojunction battery as a constraint condition, and adjusts the thickness of the prepared ultra-thin N-type silicon wafer under this condition.

[0038] In one embodiment of the present application, maintaining the yield rate of heterojunction cells includes: performing electroluminescence detection EL on large-size ultra-thin N-type silicon wafers prepared under low temperature conditions, ensuring that the EL image obtained by the detection does not contain various types of defects, and the various types of defects include warping; maintaining the conversion efficiency of the heterojunction cell includes: in a solar cell simulation application, simulating and calculating the open circuit voltage and short circuit current of the heterojunction cell prepared based on the large-size ultra-thin N-type silicon wafer, analyzing the expected efficiency change of the heterojunction cell based on the simulated open circuit voltage and short circuit current, and ensuring that the expected efficiency change is within the allowable variation range.

[0039] Specifically, due to the use of thin-film technology, the same silicon rod can be cut into more slices, and the large size makes the power generation efficiency higher and more cost-effective. At the same time, in order to ensure the quality of the silicon wafer, it is also necessary to ensure that the silicon wafer will not warp or have other defects at low temperatures under the low-temperature process below 200°C, so as to ensure the yield rate of the battery. Among them, the ultra-thin N-type silicon wafer prepared in this application may require a lower process temperature. For this reason, this embodiment performs electroluminescence detection EL on the prepared large-size ultra-thin N-type silicon wafer, and ensures that various types of defects do not occur in the silicon wafer through EL detection, that is, ensure that various types of defects such as warping and hidden cracks do not exist on the EL image obtained by the detection. If the above defects are found through EL detection, the preset thickness threshold can be adjusted until the prepared large-size ultra-thin N-type silicon wafer can pass the EL detection.

[0040] Furthermore, this embodiment also ensures that the efficiency of the heterojunction battery remains basically unchanged after the silicon wafer is thinned. Due to the thinning of the silicon wafer substrate, the open circuit voltage will increase and the short circuit current will decrease, and the larger the open circuit voltage and short circuit current, the more beneficial to the efficiency of the battery. Therefore, in this application, a virtual model is first constructed in the solar cell simulation application, such as SCAPS-1D and Griddler, etc., to simulate and calculate the open circuit voltage and short circuit current of the heterojunction battery generated according to the current ultra-thin N-type silicon wafer, and then the expected conversion efficiency of the heterojunction battery is analyzed based on the simulated open circuit voltage and short circuit current, and then the conversion efficiency of the heterojunction battery is compared with the efficiency of the conventional heterojunction battery to ensure that the expected efficiency change is within the allowable change range, that is, the change difference is small and basically remains unchanged. If the efficiency of the heterojunction battery prepared with a large-size ultra-thin N-type silicon wafer does not meet the requirements, return to adjust the thickness of the ultra-thin N-type silicon wafer until the expected efficiency change is within the allowable change range.

[0041] Therefore, this embodiment continuously adjusts the thickness of the ultra-thin N-type silicon wafer in the simulation application until the thickness meets the above requirements, and finally can prepare a large-size ultra-thin N-type silicon wafer that meets the constraints of maintaining the yield and conversion efficiency of heterojunction cells. Thinning can make silicon wafers more flexible, which is conducive to enriching the application scenarios of batteries and components.

[0042] When optimizing the slicing process for silicon wafer preparation, as a possible implementation method, the diamond wire cutting technology can be optimized to enable silicon wafers to be thinned while maintaining a low fracture and breakage rate. Among them, the thinning of silicon wafers is achieved by continuously optimizing cutting wire management, tension control, clamping feed, multi-spindle dynamic balancing and crystal line detection technologies.

[0043] Specifically, for optimizing high-precision cutting wire management technology: ensuring that the diamond wire maintains a stable line speed and tension in high-speed reciprocating bidirectional motion is crucial for thin wire cutting. By controlling the speed of the retracting and unwinding rollers in real time, the tension of the diamond wire can be kept stable, reducing the risk of wire breakage. For high-precision tension control technology: During the cutting process, it is key to keep the tension of the diamond wire stable. Too little or too much tension may lead to cutting quality problems, such as TTV exceeding the standard, obvious line marks, silicon wafer bending and warping, etc. For high-precision clamping and feeding technology: the stability of the clamping and feeding system directly affects the cutting quality and efficiency. The system needs to have high positioning accuracy and high dynamic response characteristics. For multi-spindle dynamic balancing control technology: when the single crystal silicon round bar is squared, the multi-spindle dynamic balancing control technology is used to ensure the stable operation of the wire network, thereby reducing the wire breakage rate and cutting cost. For high-precision crystal wire detection technology: using high-precision sensors and closed-loop automatic adjustment technology, the crystal wire detection time can be reduced, the cutting efficiency can be improved, and the silicon rod miscutting rate can be ensured to be close to zero.

[0044] Step S102, depositing an amorphous silicon film and a transparent conductive film TCO after target material optimization on the large-size ultra-thin N-type silicon wafer after texturing and cleaning, wherein the transparent conductive film TCO after target material optimization includes a metal nanowire structure.

[0045] Specifically, the texturing cleaning is to first clean the prepared large-size ultra-thin silicon wafer. At the same time, in order to increase the energy absorption of light and improve the passivation effect, a pyramid morphology is etched on the surface of the silicon wafer as a light trapping structure. Then, the chemical vapor deposition method is used to deposit an intrinsic amorphous silicon film and a doped amorphous silicon film of the opposite conductivity type on both sides of the silicon wafer, and the effectiveness of the passivation of the heterojunction battery is improved by depositing an amorphous silicon film. Then, the transparent conductive film TCO is deposited by physical vapor deposition and other methods. Among them, since the target material cost of TCO film is relatively high at present, the present application achieves target material cost reduction in this step by optimizing the TCO process, including adding a metal nanowire structure to the transparent conductive film TCO.

[0046] It should be noted that the current TCO film preparation mainly uses four target materials: ITO, SCOT, IWO and ICO. Currently, TCO coating mainly uses PVD or RPD technology, and the target material is the key material for depositing TCO films. For example, ITO (indium tin oxide) film is a preferred target material because of its high conductivity, high visible light transmittance, and strong physical and chemical stability. However, the indium in the target raw material is expensive, resulting in a high cost for TCO films. To this end, this application optimizes the ITO thin film deposition process, reduces the target material consumption, and thus achieves target material cost reduction.

[0047] In order to more clearly describe the specific implementation process of optimizing the TCO thin film target material in the present application, a target material optimization method proposed in an embodiment of the present application is exemplified below. Figure 2 A flow chart of a method for optimizing target material for a transparent conductive film proposed in an embodiment of the present application, such as Figure 2 As shown, the method comprises the following steps:

[0048] Step S201, adding a metal nanowire structure into a target material of a transparent conductive film TCO.

[0049] Specifically, in this embodiment, the TCO film material and processing technology are optimized from the perspectives of film structure and film material, combining multiple optimization methods, including constructing a TCO film with a gradient refractive index multilayer structure and adding a metal nanowire structure to the TCO film.

[0050] For example, in this embodiment, a metal nanowire structure is added to the ITO composite film of a photovoltaic cell to improve the photoelectric performance of the cell. Since the metal nanowire has excellent conductivity and flexibility and is lower in cost, it can be used as a substitute or supplementary material for the ITO transparent conductive film. In this embodiment, the metal nanowire is combined with ITO to generate a network structure with good conductivity and light transmission properties, thereby improving the photoelectric conversion efficiency of the HJT cell.

[0051] In specific implementation, silver nanowires can be used as metal nanowires combined with ITO, and then a high-performance composite transparent conductive film can be prepared through relevant processes. This film combines the high conductivity of metal nanowires and the high light transmittance of ITO. Then, according to actual experimental data, the ratio and structure of the two can be optimized to further improve the photoelectric performance of the film.

[0052] It is understandable that the introduction of metal nanowires can reduce the amount of ITO used. As a low-cost alternative, metal nanowires can reduce the amount of materials required to manufacture solar cells, thereby reducing target material costs while maintaining or even improving the conductivity and light transmittance of the film. In addition, the liquid phase preparation process of metal nanowire films avoids the expensive equipment and costs required for ITO film production, which is conducive to low-cost large-scale production.

[0053] Step S202, reducing the amount of target material used for the transparent conductive film TCO according to the added metal nanowire structure.

[0054] Specifically, as described above, according to the amount of metal nanowires added to the metal nanowire structure in step S201, the amount of target material of the transparent conductive film TCO is reduced accordingly, and the specific amount of target material reduced is based on the amount of target material that can be replaced by the metal nanowires as a supplementary material.

[0055] Step S203, coating a graphene film on the composite TCO film to which the metal nanowire structure is added.

[0056] Specifically, a layer of graphene is transferred onto the surface of the TCO composite film containing the metal nanowire structure obtained in step S202 to further improve the reliability of the HJT cell. Transferring graphene onto the TCO composite film can improve the performance of the photovoltaic cell. Since graphene has excellent conductivity and light transmittance, it can be used as a transparent conductive film.

[0057] In specific implementation, the graphene-assisted metal electrode transfer technology can non-destructively transfer the metal electrode array from the pre-deposited substrate to the target substrate with a very high transfer success rate. This technology can be used to form a graphene layer on the surface of the ITO film, thereby improving the conductivity and light transmittance of the photovoltaic cell.

[0058] It can be understood that in practical applications, due to the excellent conductivity and light transmittance of graphene, after coating graphene on the I composite TCO film, the introduction of graphene can reduce the use of ITO and reduce costs while maintaining or even improving the conductivity and light transmittance of the film.

[0059] Step S204, reducing the target material dosage of the composite TCO film according to the dosage of the graphene film.

[0060] Specifically, as described above, according to the amount of graphene added in step S203, the amount of target material of the transparent conductive film TCO is reduced accordingly, and the specific amount of target material reduced is based on the amount of target material that can be replaced by graphene as a supplementary material.

[0061] Therefore, the present application can reduce the target material cost of the TCO film by reducing the target material usage of the TCO film.

[0062] Step S103, preparing a corresponding type of polymer resin carrier according to the low temperature process requirements of large-size ultra-thin N-type silicon wafers, preparing silver-coated copper slurry based on the polymer resin carrier, and screen-printing the coated silicon wafers with the silver-coated copper slurry.

[0063] Specifically, since the cost of silver paste used in the screen printing process of heterojunction batteries is relatively high, it is necessary to reduce the amount of silver powder used to reduce the material cost of printing. Among them, silver-coated copper is to introduce a silver film of uniform thickness on the copper surface. The resulting core-shell structure silver-coated copper powder not only has the physical and chemical properties of the original metal copper core, but also has the excellent metal properties of the silver plating layer. The use of silver-coated copper powder can reduce the amount of silver powder used, thereby significantly reducing the metallization cost.

[0064] Among them, the present application prepares the polymer resin carrier in the silver-coated copper slurry in view of the special temperature requirements in the low-temperature process of the ultra-thin N-type silicon wafer prepared in step S101, so that the silver-coated copper slurry finally prepared can meet the process requirements of large-size ultra-thin N-type silicon wafers.

[0065] In one embodiment of the present application, a corresponding type of polymer resin carrier is prepared according to the low temperature process requirements of a large-size ultra-thin N-type silicon wafer, including: selecting a plurality of constituent materials of the polymer resin carrier according to the low temperature process requirements of the large-size ultra-thin N-type silicon wafer, so that the generated polymer resin carrier can be cured at the temperature required by the low temperature process;

[0066] Specifically, the production of silver-coated copper paste involves the selection of a key material, resin. As part of the organic carrier, the resin has an important influence on the printing performance of the paste and the bonding strength after sintering. The resin usually selected needs to be cured at low temperature to meet the low temperature process requirements of HJT cells. However, due to the low temperature process of the large-sized ultra-thin N-type silicon wafers of this application, there are more special requirements for temperature, such as lower temperatures. Therefore, when selecting the various constituent materials of the polymer resin carrier, this application needs to meet the requirement that the resin can be cured at the low temperature required by the large-sized ultra-thin N-type silicon wafers.

[0067] For example, the polymer resin carrier is composed of the following materials: polyester, polyacrylate, ethylene glycol ether ester, silicone resin and other polymers. Among them, the embodiments of the present application can use other polymers of the corresponding type as carriers according to specific low-temperature curing application requirements to meet the performance requirements of curing under specific low-temperature conditions.

[0068] Further, according to the prepared polymer resin carrier, the silver-coated copper slurry is prepared. In one embodiment of the present application, it may include: adjusting the ratio of silver powder, copper powder and polymer resin carrier in the silver-coated copper slurry to maintain the conversion efficiency of the heterojunction battery as a constraint. Specifically, the silver-coated copper slurry needs to meet certain performance requirements, including good printability, suitable sintering temperature, low resistivity and high heat resistance, and these performance indicators can be changed by adjusting the ratio of various materials in the slurry. In this embodiment, the ratio of silver powder, copper powder and polymer resin carrier in the silver-coated copper slurry can be adjusted to maintain the conversion efficiency of the heterojunction battery as a constraint. Then, according to first preparing the polymer resin carrier and then preparing the organic carrier mixture, the silver powder, silver-coated copper powder, resin, diluent, curing agent and rust inhibitor are finally mixed in a determined ratio to form a silver-coated copper slurry. Then, the obtained silver-coated copper slurry is used to screen print the coated silicon wafer.

[0069] Step S104, encapsulating the screen-printed heterojunction battery using a variety of encapsulation materials, wherein the variety of encapsulation materials include a butyl rubber-based water-blocking material.

[0070] Specifically, the present application further prepares the heterojunction battery assembly for the purpose of reducing costs, mainly by reducing the cost of the packaging materials of the assembly to reduce the cost of preparing the heterojunction battery assembly, including using lower-cost butyl rubber to make water-blocking materials for packaging.

[0071] In one embodiment of the present application, the screen-printed heterojunction battery is packaged using a variety of packaging materials, which also includes: based on the water vapor sensitivity of the heterojunction battery, mixing butyl rubber and silica gel as water-blocking materials; adding a corresponding amount of light-converting material to the anti-reflection film coated on the photovoltaic glass, and replacing the light-converting adhesive film with an ordinary photovoltaic adhesive film.

[0072] Specifically, in view of the characteristic that heterojunction batteries are sensitive to water vapor, this embodiment combines butyl rubber with the current traditional silica gel to prepare a water-blocking material to achieve the water-blocking function of the component. The material can be prepared by blending butyl rubber with polyisobutylene and other main raw materials.

[0073] Furthermore, since the power attenuation of heterojunction cells under ultraviolet irradiation is greater, higher requirements are placed on packaging materials. Therefore, in the relevant technology, a light-converting adhesive film is usually set to achieve cost reduction and efficiency improvement of heterojunction cells, that is, light-converting substances are added to the photovoltaic adhesive film to convert ultraviolet light into blue light, reduce the cell's absorption of short-wavelength light (ultraviolet light), and effectively increase the power generation of the components.

[0074] However, the solution of adding the light-converting substance into the photovoltaic film requires a lot of light-converting material because the thickness of the photovoltaic film is relatively large, which is much greater than the thickness of the anti-reflection film coated on the photovoltaic glass. Therefore, the present application transfers the light-converting process of the packaging material to the anti-reflection film coated on the surface of the photovoltaic glass, that is, adding the light-converting substance into the anti-reflection film, which can greatly reduce the amount of fluorescent material used compared to adding the fluorescent material into the photovoltaic film.

[0075] During specific implementation, light-converting substances can be added to the anti-reflection film of photovoltaic glass in different ways according to actual conditions.

[0076] As a first example, after the anti-reflection film is plated, a corresponding amount of light-converting material can be deposited on the surface of the first anti-reflection film by chemical vapor deposition (CVD) and other methods. Among them, the light-converting material can be a luminescent material doped with rare earth elements. As a second example, a mixed solution containing a photovoltaic glass coating liquid and a light-converting material can be coated on the surface of the photovoltaic glass, and then an anti-reflection type light-converting glass film layer is obtained by calcination and other processes. The specific content of the light-converting material added to the anti-reflection film can be determined according to the actual light-conversion requirements of the heterojunction battery assembly. Furthermore, the more expensive light-converting adhesive film in the related art can be replaced by an ordinary photovoltaic adhesive film, such as EVA, POE and EPE, three types of adhesive films that do not contain light-converting materials.

[0077] Therefore, the present application further reduces the cost of preparing the components by reducing the cost of the water-blocking material and the light-converting adhesive film in the packaging material of the heterojunction battery component.

[0078] In summary, the method for preparing a low-cost heterojunction battery assembly in the embodiment of the present application firstly takes the yield and conversion efficiency of the heterojunction battery as the constraint condition, and prepares a large-sized ultra-thin N-type silicon wafer with a thickness less than a preset thickness threshold through an optimized slicing process; then deposits a transparent conductive film TCO after the target material is optimized on the silicon wafer, wherein the transparent conductive film TCO after the target material is optimized includes a metal nanowire structure; then prepares a corresponding type of polymer resin carrier according to the low-temperature process requirements of the large-sized ultra-thin N-type silicon wafer, and screen-prints the coated silicon wafer with a silver-coated copper slurry; finally, the screen-printed heterojunction battery is encapsulated with a variety of packaging materials, wherein the various packaging materials include a water-blocking material based on butyl rubber. Thus, the method starts from multiple angles such as preparing ultra-large and ultra-thin silicon wafers to reduce silicon consumption, using silver-coated copper slurry to reduce silver paste costs, optimizing the TCO process to achieve target cost reduction and reduce component packaging material costs, and reduces the production cost of heterojunction battery assemblies in various ways at different stages of battery assembly preparation. And while reducing costs, the conversion efficiency of the battery assembly is basically unchanged. Therefore, the method can significantly reduce the production cost of heterojunction battery components, is conducive to the promotion and application of heterojunction battery components, and improves the practicality of heterojunction battery components.

[0079] In order to realize the above-mentioned embodiment, the present application also proposes a low-cost heterojunction battery assembly preparation system. Figure 3 A schematic diagram of the structure of a low-cost heterojunction battery assembly preparation system proposed in an embodiment of the present application is shown in FIG. Figure 3 As shown, the system includes: a slicing module 100 , a deposition module 200 , a printing module 300 and a packaging module 400 .

[0080] The slicing module 100 is used to prepare large-size ultra-thin N-type silicon wafers with a thickness less than a preset thickness threshold through an optimized slicing process, with the yield and conversion efficiency of the heterojunction battery maintained as constraints.

[0081] The deposition module 200 is used to deposit an amorphous silicon film and a transparent conductive film TCO after target material optimization on a large-sized ultra-thin N-type silicon wafer after texturing and cleaning, wherein the transparent conductive film TCO after target material optimization includes a metal nanowire structure.

[0082] The printing module 300 is used to prepare a corresponding type of polymer resin carrier according to the low-temperature process requirements of large-size ultra-thin N-type silicon wafers, prepare silver-coated copper slurry based on the polymer resin carrier, and screen-print the coated silicon wafers with the silver-coated copper slurry.

[0083] The packaging module 400 is used to package the screen-printed heterojunction battery using a variety of packaging materials, wherein the various packaging materials include a butyl rubber-based water-blocking material.

[0084] Optionally, in one embodiment of the present application, the slicing module 100 is specifically used to: perform electroluminescence detection EL on large-size ultra-thin N-type silicon wafers prepared under ultra-low temperature conditions, to ensure that the EL image obtained by the detection does not contain various types of defects, including warping; in solar cell simulation applications, simulate and calculate the open circuit voltage and short circuit current of the heterojunction battery prepared based on the large-size ultra-thin N-type silicon wafers, and analyze the expected efficiency change of the heterojunction battery based on the simulated open circuit voltage and short circuit current; ensure that the expected efficiency change is within the allowable change range.

[0085] Optionally, in one embodiment of the present application, the deposition module 200 is specifically used to: add a metal nanowire structure to the target material of the transparent conductive film TCO; and reduce the target material usage of the transparent conductive film TCO according to the added metal nanowire structure.

[0086] Optionally, in one embodiment of the present application, the deposition module 200 is specifically used to: plate a graphene film on the composite TCO film to which the metal nanowire structure is added; and reduce the amount of target material used in the composite TCO film according to the amount of the graphene film used.

[0087] Optionally, in one embodiment of the present application, the printing module 300 is specifically used to: select a variety of constituent materials of the polymer resin carrier according to the low-temperature process requirements of large-size ultra-thin N-type silicon wafers, so that the generated polymer resin carrier can be cured at the temperature required by the low-temperature process; adjust the ratio of silver powder, copper powder and polymer resin carrier in the silver-coated copper slurry with maintaining the conversion efficiency of the heterojunction battery as a constraint condition.

[0088] Optionally, in one embodiment of the present application, the sintering module 200 is specifically used to: combine the adjusted corrosiveness of the dedicated silver paste with the laser post-processing process to separate the passivation layer corrosion step and the contact point generation step in the silver electrode sintering process of the TOPCon battery; enhance the contact of the TOPCon battery through an effective conductive path generated by laser optimization processing; and open up the electron transmission channel that was not connected during the sintering process through the contact enhancement effect.

[0089] Optionally, in one embodiment of the present application, the packaging module 400 is specifically used to: based on the water vapor sensitivity of the heterojunction battery, mix butyl rubber and silica gel as a water-blocking material; add a corresponding amount of light-converting material to the anti-reflection film coated on the photovoltaic glass, and replace the light-converting adhesive film with an ordinary photovoltaic adhesive film.

[0090] It should be noted that the above explanation of the embodiment of the method for preparing a low-cost heterojunction battery assembly is also applicable to the system of this embodiment and will not be repeated here.

[0091] In summary, the low-cost heterojunction battery assembly preparation system of the embodiment of the present application reduces the production cost of heterojunction battery assemblies in various ways at different stages of battery assembly preparation from multiple perspectives, such as preparing ultra-large and ultra-thin silicon wafers to reduce silicon consumption, using silver-coated copper slurry to reduce silver paste costs, optimizing the TCO process to achieve target material cost reduction and reduce assembly packaging material costs. And while reducing costs, the conversion efficiency of the battery assembly is basically unchanged. As a result, the system can significantly reduce the production cost of heterojunction battery assemblies, is conducive to the promotion and application of heterojunction battery assemblies, and improves the practicality of heterojunction battery assemblies.

[0092] In order to implement the above embodiments, the present application also proposes a non-temporary computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, it implements a method for preparing a low-cost heterojunction battery component as described in any one of the above first aspect embodiments.

[0093] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0094] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0095] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0096] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute the instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0097] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0098] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0099] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0100] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for preparing a low-cost heterojunction battery assembly, characterized in that: The following steps are involved: Under the constraint of maintaining the yield rate and conversion efficiency of heterojunction cells, large-size ultra-thin N-type silicon wafers with a thickness less than a preset thickness threshold are prepared through an optimized slicing process; Depositing an amorphous silicon film and a transparent conductive film TCO after target material optimization on the large-size ultra-thin N-type silicon wafer after texturing and cleaning, wherein the transparent conductive film TCO after target material optimization includes a metal nanowire structure; According to the low-temperature process requirements of the large-size ultra-thin N-type silicon wafer, a corresponding type of polymer resin carrier is prepared, and a silver-coated copper slurry is prepared according to the polymer resin carrier, and the coated silicon wafer is screen-printed by the silver-coated copper slurry; The screen-printed heterojunction battery is packaged by using a variety of packaging materials, wherein the various packaging materials include a butyl rubber-based water-blocking material.

2. The preparation method according to claim 1, characterized in that: The method of maintaining the yield rate of heterojunction cells includes: Performing electroluminescence detection (EL) on the large-size ultra-thin N-type silicon wafer prepared under low temperature conditions to ensure that the EL image obtained by the detection does not have various types of defects, including warping; Maintaining the conversion efficiency of the heterojunction cell, comprising: In the solar cell simulation application, the open circuit voltage and short circuit current of the heterojunction battery prepared according to the large-size ultra-thin N-type silicon wafer are simulated and calculated, and the expected efficiency change of the heterojunction battery is analyzed based on the simulated open circuit voltage and short circuit current; Ensure that the expected efficiency change is within the allowable variation range.

3. The preparation method according to claim 1, characterized in that: Depositing the transparent conductive thin film TCO after the target material is optimized, comprising: Adding metal nanowire structures to the target material of transparent conductive thin film TCO; According to the added metal nanowire structure, the target material usage of the transparent conductive film TCO is reduced.

4. The preparation method according to claim 3, characterized in that: Depositing the transparent conductive film TCO after the target material is optimized, further comprising: Plating a graphene film on the composite TCO film to which the metal nanowire structure is added; According to the usage of the graphene film, the usage of the target material of the composite TCO film is reduced.

5. The preparation method according to claim 1, characterized in that: The method of preparing a corresponding type of polymer resin carrier according to the low temperature process requirements of the large-size ultra-thin N-type silicon wafer comprises: According to the low temperature process requirements of the large-size ultra-thin N-type silicon wafer, multiple constituent materials of the polymer resin carrier are selected so that the generated polymer resin carrier can be cured at the temperature required by the low temperature process; The method of preparing the silver-coated copper slurry according to the polymer resin carrier comprises: The ratio of the silver powder, the copper powder and the polymer resin carrier in the silver-coated copper slurry is adjusted under the constraint of maintaining the conversion efficiency of the heterojunction battery.

6. The preparation method according to claim 5, characterized in that: The method of packaging the screen-printed heterojunction battery using a variety of packaging materials also includes: Based on the water vapor sensitive characteristics of heterojunction batteries, butyl rubber and silica gel are mixed as the water blocking material; A corresponding amount of light-converting material is added to the anti-reflection film coated on the photovoltaic glass, and the light-converting adhesive film is replaced by an ordinary photovoltaic adhesive film.

7. A low-cost heterojunction battery assembly preparation system, characterized in that: include: The slicing module is used to prepare large-size ultra-thin N-type silicon wafers with a thickness less than a preset thickness threshold through an optimized slicing process, with the yield and conversion efficiency of heterojunction cells as constraints; A deposition module, used for depositing an amorphous silicon film and a transparent conductive film TCO after target material optimization on the large-size ultra-thin N-type silicon wafer after texturing and cleaning, wherein the transparent conductive film TCO after target material optimization includes a metal nanowire structure; A printing module, used for preparing a corresponding type of polymer resin carrier according to the low-temperature process requirements of the large-size ultra-thin N-type silicon wafer, preparing a silver-coated copper slurry according to the polymer resin carrier, and screen-printing the coated silicon wafer with the silver-coated copper slurry; A packaging module is used to package heterojunction batteries after screen printing using a variety of packaging materials, wherein the various packaging materials include a water-blocking material based on butyl rubber.

8. The preparation system according to claim 7, characterized in that: The slicing module is specifically used for: Performing electroluminescence detection (EL) on the large-size ultra-thin N-type silicon wafer prepared under low temperature conditions to ensure that the EL image obtained by the detection does not have various types of defects, including warping; In the solar cell simulation application, the open circuit voltage and short circuit current of the heterojunction battery prepared according to the large-size ultra-thin N-type silicon wafer are simulated and calculated, and the expected efficiency change of the heterojunction battery is analyzed based on the simulated open circuit voltage and short circuit current; Ensure that the expected efficiency change is within the allowable variation range.

9. The preparation system according to claim 7, characterized in that: The deposition module is specifically used for: Adding metal nanowire structures to the target material of transparent conductive thin film TCO; According to the added metal nanowire structure, the target material usage of the transparent conductive film TCO is reduced.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for preparing a low-cost heterojunction battery assembly as described in any one of claims 1 to 6 is implemented.

Images