Diode device with hole injection enhancement structure and preparation method thereof

Abstract

The invention discloses a diode device with a hole injection enhancement structure and a preparation method of the diode device, and belongs to the technical field of semiconductor devices.The diode device comprises a planar n-type doped III-nitride semiconductor substrate; the columnar structures are arranged in a random or periodic array mode, the diameters of the columnar structures are the same or different, the columnar structures are located on the surface of the planar n-type doped III-nitride semiconductor substrate, and each columnar structure comprises an n-type semiconductor column, an active area and a hole injection enhancement structure from bottom to top; wherein the hole injection enhancement structure wraps the upper surface and at least part of the side surface of the active region, the n-type semiconductor column and the hole injection enhancement structure are made of doped III-group nitride semiconductors, and the doping types are n type and p type respectively. The hole injection enhancing structure introduced by the invention enhances the injection of holes to the active region, is beneficial to improving the radiation recombination efficiency, can reduce the turn-on voltage and the working voltage of the device, and improves the carrier injection efficiency and the external quantum efficiency.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a diode device with a hole injection enhancement structure and a preparation method thereof. Background Art

[0002] At present, GaN-based LEDs generally use heterogeneous substrates such as sapphire substrates or silicon substrates. The large lattice mismatch between the substrates leads to poor epitaxial crystal quality of GaN-based LEDs. At the same time, the carrier transport in InGaN / GaN multiple quantum wells is mainly limited by the movement of holes, and its radiative recombination rate is a key factor in determining the device's electro-optical conversion efficiency.

[0003] In conventional LED structures, holes are affected by the high hole injection barrier brought by the polarization field and the electron blocking layer, and most holes are concentrated in the last few quantum wells close to the p-type semiconductor. This uneven distribution of holes causes the radiation recombination efficiency to decrease, limiting the photoelectric efficiency of the LED. In the LED with a V-pit structure, the sidewall of the V-pit has a smaller structural thickness and a smaller polarization field with a semi-polar surface, making it easier to inject holes and providing a path for holes to be directly injected into deep quantum wells. When the injection ratio of the V-pit increases, the high barrier layer containing Al suppresses the injection of holes into the quantum well through the c-plane, so as to induce more holes to be directly transported to deeper quantum wells through the hole injection path provided by the V-pit, thereby improving the hole injection efficiency. However, the V-pit has the problem of random position and uncontrollable, so it is difficult to stably promote hole injection and improve the photoelectric efficiency of devices for micron-sized and smaller LED devices. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a diode device with a hole injection enhancement structure and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] In a first aspect, the present invention provides a diode device having a hole injection enhancement structure, comprising:

[0006] A planar n-type doped III-nitride semiconductor substrate;

[0007] A plurality of columnar structures with the same or different diameters arranged in a random or periodic array are located on the surface of the planar n-type doped III-nitride semiconductor substrate, each of the columnar structures comprising: an n-type semiconductor column, an active region, and a hole injection enhancement structure;

[0008] The active area is located on the upper surface of the n-type semiconductor column, the hole injection enhancement structure is wrapped around the upper surface and at least part of the side surface of the active area, and the material of the n-type semiconductor column and the hole injection enhancement structure is a doped III-group nitride semiconductor, and the doping types are n-type and p-type, respectively.

[0009] In one embodiment of the present invention, the hole injection enhancement structure comprises a first sub-portion located on the upper surface of the active region and a second sub-portion located on the side of the active region; wherein,

[0010] The thickness of the first sub-portion and the second sub-portion is not less than 20 nm.

[0011] In one embodiment of the present invention, the thickness of the second sub-portion in the hole injection enhancement structure is equal to the distance between the columnar structure and an adjacent columnar structure, so that the hole injection enhancement structures of two adjacent columnar structures touch each other.

[0012] In one embodiment of the present invention, the side surface of the n-type semiconductor column is covered with a thin film, and the thin film is used to prevent current conduction between materials on both sides of the thin film.

[0013] In one embodiment of the present invention, the thin film is a multilayer material, and the outermost layer of the multilayer material has the property of reducing or inhibiting nucleation during the epitaxial process;

[0014] Alternatively, the thin film is a single layer material having the property of reducing or inhibiting nucleation during the epitaxial process.

[0015] In one embodiment of the present invention, in each columnar structure, the active region includes, from bottom to top, a stress adjustment layer and an intermediate layer, and the intermediate layer includes a plurality of quantum wells and barrier layers stacked alternately.

[0016] In one embodiment of the present invention, the height of the columnar structure is 0.1 μm to 10 μm, and the diameter of the circumscribed circle is 0.01 μm to 50 μm.

[0017] In a second aspect, the present invention further provides a method for preparing a diode device having a hole injection enhancement structure as described in the first aspect, comprising:

[0018] Providing a planar n-type doped III-nitride semiconductor substrate, the planar n-type doped III-nitride semiconductor substrate comprising an n-type doped III-nitride semiconductor layer and an etching mask layer located on a surface of the n-type doped III-nitride semiconductor layer;

[0019] Performing photolithography and etching on the etching mask layer and the n-type doped group III nitride semiconductor layer to form a plurality of n-type semiconductor pillars;

[0020] Using a conformal thin film deposition process, after depositing a thin film on the surface of an n-type doped III-nitride semiconductor substrate with n-type semiconductor pillars, etching away the thin film on the upper surface of each n-type semiconductor pillar and retaining the thin film on the side surface of each n-type semiconductor pillar;

[0021] growing an active region on the upper surface of each of the n-type semiconductor pillars;

[0022] A hole injection enhancement structure is grown on the surface of the active region so that the hole injection enhancement structure wraps around the upper surface and at least a portion of the side surface of the active region, thereby obtaining a completed diode device.

[0023] In one embodiment of the present invention, the step of growing a hole injection enhancement structure on the outer surface of the active region comprises:

[0024] The pressure in the reaction chamber of the metal organic vapor deposition system is reduced by 15% to 40%, and a p-type doped GaN or AlGaN layer is grown on the outer surface of the active area at a temperature of 800°C to 980°C to form a hole injection enhancement structure.

[0025] In one embodiment of the present invention, the step of growing an active region on the upper surface of each of the n-type semiconductor pillars comprises:

[0026] Placing a planar n-type doped GaN substrate in a reaction chamber of a metal organic vapor deposition system, growing an InGaN / GaN superlattice structure at a temperature of 800° C. to 980° C. to form a stress adjustment layer; wherein the In content of the InGaN layer in the stress adjustment layer is not less than 5%;

[0027] 2 to 20 periods of quantum well / barrier layers are grown on the surface of the stress adjustment layer; wherein the quantum well comprises an InGaN layer with a growth temperature of 600°C to 690°C and a thickness of 1nm to 10nm, and the barrier layer comprises a GaN layer with a growth temperature of 700°C to 850°C and a thickness of 5nm to 20nm.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] The present invention provides a diode device with a hole injection enhancement structure and a preparation method thereof. In the diode device, the upper surface of each n-type semiconductor column is an active region, and a p-type doped GaN or AlGaN layer is grown on the outer surface of the active region as a hole injection enhancement structure, so as to promote more holes to be directly transported to a deeper quantum well through the injection path provided by the above structure, that is, the injection of holes into the active region is enhanced, which is not only beneficial to improving the radiation recombination efficiency, but also can reduce the turn-on voltage and the operating voltage of the diode device, and improve the carrier injection efficiency and the external quantum efficiency.

[0030] In addition, since p-type semiconductors will grow on the side of n-type semiconductor columns when epitaxy is performed using conventional methods, resulting in significant electron overflow when the device is operating, the present invention deposits a thin film on the sidewall of the n-type semiconductor column, thereby inhibiting electrons or holes from passing through the thin film along the radial direction of the n-type semiconductor column and moving to the material on the surface of the film, and also inhibiting material growth on the surface of the film. Furthermore, the thin film in the present invention is a multilayer material or a single layer material, which contains a dielectric with poor conductivity such as SiO2, SiN x Or TiO2, etc., this insulating or low-conductivity film can inhibit or eliminate the current generated between the n-type semiconductor column wrapped inside and the material on the surface of the film (if any) under an external bias.

[0031] The diode device provided by the present invention has small size, high luminous efficiency, high power density and other characteristics, and can be used as a core electronic device in the fields of lighting, display, biomedicine and communication.

[0032] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figures 1 to 7 is a schematic diagram of a preparation process of a diode device with a hole injection enhancement structure provided by an embodiment of the present invention;

[0034] Figure 8 is a schematic structural diagram of a diode device with a hole injection enhancement structure provided by an embodiment of the present invention;

[0035] Fig. 9 yes Figure 8 A partial schematic diagram of the dotted box in the diode device shown;

[0036] Fig.10 It is a flow chart of a method for preparing a diode device with a hole injection enhancement structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0038] Figure 8 is a schematic structural diagram of a diode device with a hole injection enhancement structure provided by an embodiment of the present invention, Fig. 9 yes Figure 8 The schematic diagram of the part of the diode device shown in the dashed box. Figure 8-9 , an embodiment of the present invention provides a diode device with a hole injection enhancement structure, comprising:

[0039] A planar n-type doped III-nitride semiconductor substrate 1;

[0040] A plurality of columnar structures 2 with the same or different diameters arranged in a random or periodic array are located on the surface of a planar n-type doped III-nitride semiconductor substrate 1, and each columnar structure 2 includes: an n-type semiconductor column 201, an active region 202, and a hole injection enhancement structure 203;

[0041] Among them, the active area 202 is located on the upper surface of the n-type semiconductor column 201, and the hole injection enhancement structure 203 is wrapped around the upper surface and at least part of the side surface of the active area 202. The materials of the n-type semiconductor column 201 and the hole injection enhancement structure 203 are doped Group III nitride semiconductors, and the doping types are n-type and p-type respectively.

[0042] Specifically, the diode device provided by the present invention includes: a planar n-type doped III-nitride semiconductor substrate 1 and a plurality of columnar structures 2 located on the surface thereof, the height of the columnar structure is 0.1 μm to 10 μm, and the diameter of the circumscribed circle is 0.01 μm to 50 μm; the planar n-type doped III-nitride semiconductor substrate 1 includes, from bottom to top, a substrate 101, a GaN nucleation layer 102, an unintentionally doped GaN layer 103, an n-type doped GaN layer 104 and an etching mask layer 105, wherein the substrate 101, the GaN nucleation layer 102, the unintentionally doped GaN layer 103 and the n-type doped GaN layer 104 constitute an n-type doped III-nitride semiconductor layer, the material of the substrate 101 can be sapphire, silicon, silicon carbide, gallium oxide, zinc oxide, boron nitride, lithium aluminate, lithium niobate, germanium, aluminum nitride or lithium gallate, and the etching mask layer 105 includes SiO2.

[0043] Furthermore, each columnar structure 2 includes, from bottom to top, an n-type semiconductor column 201, an active region 202, and a hole injection enhancement structure 203, such as Figure 8 As shown, the hole injection enhancement structure 203 is located on the upper side and the surrounding side of the active region 202. Exemplarily, the material of the hole injection enhancement structure 203 is p-type doped GaN or AlGaN. It should be understood that since there is a quantum confinement structure inside the active region 202, the present invention introduces the hole injection enhancement structure 203, and by epitaxially growing a p-type doped III-group nitride semiconductor on the side and top of the active region 202, holes are injected into the quantum confinement structure, thereby increasing the hole injection rate and the radiation recombination rate, improving the photoelectric efficiency of the device, and reducing the turn-on voltage and operating voltage of the diode device, thereby improving the carrier injection efficiency and the external quantum efficiency.

[0044] Optionally, the hole injection enhancement structure 203 includes a first sub-portion located on the upper surface of the active region 202 and a second sub-portion located on the side of the active region 202 , and the thickness of both sub-portions is not less than 20 nm.

[0045] like Figure 8 As shown, in one embodiment of the present invention, the thickness of the second sub-portion in the hole injection enhancement structure 203 may be less than the distance between the columnar structure 2 and the adjacent columnar structure 2, that is, a gap is left between the hole injection enhancement structures 203 of two adjacent columnar structures 2. In another embodiment of the present invention, the thickness of the second sub-portion in the hole injection enhancement structure 203 may also be equal to the distance between the columnar structure 2 and the adjacent columnar structure 2, so that the hole injection enhancement structures 203 of two adjacent columnar structures 2 touch each other, and the present invention is not limited to this.

[0046] In this embodiment, the side surface of the n-type semiconductor pillar 201 is also covered with a thin film 204 to prevent current conduction between materials on both sides of the thin film.

[0047] Specifically, the material of the thin film 204 is generally a dielectric material with poor conductivity. The thin film 204 can be a multi-layer material or a single-layer material. When it is a single-layer material, the single-layer material has the characteristic of reducing or inhibiting nucleation during the epitaxial process, such as SiO2, and when it is a multi-layer material, the outermost layer of the multi-layer material has the characteristic of reducing or inhibiting nucleation during the epitaxial process, such as SiO2. Depositing the thin film 204 on the side of the n-type semiconductor column 201 can inhibit or eliminate the occurrence of a pn junction or pin junction that can conduct current between the n-type semiconductor column 201 inside and the material on the surface of the thin film 204.

[0048] In each columnar structure 2 , the active region 202 includes, from bottom to top, a stress adjustment layer and an intermediate layer, wherein the intermediate layer includes a plurality of quantum wells and barrier layers stacked alternately.

[0049] Fig.10 FIG. 1 is a flow chart of a method for preparing a diode device having a hole injection enhancement structure provided by an embodiment of the present invention. Figure 1-10 As shown, an embodiment of the present invention provides a method for preparing a diode device with a hole injection enhancement structure, comprising:

[0050] S1, providing a planar n-type doped III-nitride semiconductor substrate 1, wherein the planar n-type doped III-nitride semiconductor substrate comprises an n-type doped III-nitride semiconductor layer and an etching mask layer 105 located on a surface of the n-type doped III-nitride semiconductor layer;

[0051] S2, performing photolithography and etching on the etching mask layer 105 and the n-type doped group III nitride semiconductor layer to form a plurality of n-type semiconductor pillars;

[0052] S3, after depositing a thin film 204 on the surface of the n-type doped III-nitride semiconductor substrate 1 with the n-type semiconductor pillars by using a conformal thin film deposition process, etching away the thin film 204 on the upper surface of each n-type semiconductor pillar 201, and retaining the thin film 204 on the side surface of each n-type semiconductor pillar 201;

[0053] S4, growing an active region 202 on the upper surface of each n-type semiconductor pillar 201;

[0054] S5. Growing a hole injection enhancement structure 203 on the surface of the active region 202 so that the hole injection enhancement structure 203 wraps around the upper surface and at least part of the side surface of the active region 202 to obtain a completed diode device.

[0055] See also Figure 1 In this embodiment, a substrate 101 with a thickness of 650 μm, such as a sapphire substrate, is first provided, and placed in a metal organic vapor deposition system reaction chamber, heated to 1100° C., and then the sapphire substrate is subjected to high temperature treatment for 20 minutes in a hydrogen atmosphere, and then the temperature is lowered to 515° C., ammonia is introduced for 3 minutes, and then TMGa is introduced to epitaxially grow a GaN nucleation layer 102 with a thickness of 20 nm; further, the temperature is raised to 1050° C., TMGa and ammonia are introduced, and an unintentionally doped GaN layer 103 with a thickness of 1 μm and an n-type doped GaN layer 104 with a thickness of 2 μm are epitaxially grown, and SiH4 is introduced simultaneously when growing the n-type doped GaN layer 104, and the doping concentration is 5×10 18 cm -3 Finally, SiO2 with a thickness of 500 nm is deposited on the surface of the n-type doped GaN layer 104 using a plasma enhanced chemical vapor deposition process to form an etching mask layer 105, thereby obtaining a planar n-type doped Group III nitride semiconductor substrate 1.

[0056] In steps S2 to S3, a photoresist with a thickness of 700 nm is evenly spin-coated on the surface of the etching mask layer 105 of the planar n-type doped Group III nitride semiconductor substrate 1, and a pattern containing a nanoscale circular array is exposed using a stepper lithography machine, and then developed to obtain a photoresist column array, the period of the photoresist column array is 800 nm, the diameter of the photoresist column is 400 nm, and the distance between the photoresist columns is 400 nm. The substrate with the surface patterned photoresist column array is placed in the chamber of an inductively coupled plasma etcher, and the patterned photoresist column array is used as a mask. The etching mask layer 105 is etched by an inductively coupled plasma etching process in a carbon tetrafluoride and argon atmosphere, so that the etching mask layer 105 not covered by the photoresist column array is etched, and the area covered by nickel forms a SiO2 column array; further, the planar n-type doped III-group nitride semiconductor substrate 1 is placed in a degumming solution, and heated in a water bath at 80° C. until the residual photoresist columns are removed, and the obtained SiO2 column array is as shown in FIG. Figure 2 shown.

[0057] A planar n-type doped III-group nitride semiconductor substrate 1 having a patterned SiO2 column array on its surface is placed in the chamber of an inductively coupled plasma etcher, and the n-type doped GaN layer 104 is etched using an inductively coupled plasma etching process in an atmosphere of chlorine and argon. Optionally, the area of ​​the n-type doped GaN layer 104 not covered by the SiO2 column array is etched by 600 nm, and the area covered by the SiO2 column array is not etched, that is, an array of n-type semiconductor columns 201 is formed in the area originally covered by the SiO2 columns. The substrate is placed in a buffered oxide etching solution until the SiO2 column array mask is etched to form a Figure 3 It should be noted that SiO2 is also consumed in the process of etching the n-type doped GaN layer 104. Therefore, after the etching of the n-type semiconductor column 201 is completed, the SiO2 column above is also consumed. Figure 3 The SiO2 column array is no longer shown.

[0058] like Figure 4 As shown, taking the case where the thin film is a single-layer material as an example, a substrate with an n-type semiconductor column 201 is placed in an atomic layer deposition device, and SiO2 with a thickness of 10 nm is deposited on the surface of the substrate using a conformal thin film deposition process. The conformal thin film deposition process includes: sputtering, atomic layer deposition, chemical vapor deposition and chemical liquid deposition. Due to the conformality of the atomic layer deposition process, the thin film 204 can also cover the side wall of the n-type semiconductor column 201.

[0059] Further, a photoresist with a thickness of 400 nm is evenly spin-coated on the surface of the substrate, and the upper surface of the n-type semiconductor column 201 is exposed and developed using a stepper photolithography machine with high overlay accuracy to expose the thin film 204 on its upper surface; then, the substrate is placed in the chamber of an inductively coupled plasma etcher, and the thin film 204 on the upper surface of the n-type semiconductor column 201 is etched away using an inductively coupled plasma etching process in a carbon tetrafluoride and argon atmosphere, and then placed in a degumming solution, and heated in a water bath at 80° C. until the photoresist in other areas is removed, so that an array of n-type semiconductor columns 201 with side walls covered by the thin film 204 and the upper surface uncovered can be obtained, as shown in FIG. Figure 5 and Figure 6 shown.

[0060] In this embodiment, the active region 202 includes, from bottom to top, a stress adjustment layer and an intermediate layer, wherein the intermediate layer includes a plurality of quantum wells and GaN barrier layers stacked alternately. After the active region 202 is grown, the structure obtained is as follows: Figure 7 In step S4, the step of growing the active region 202 on the upper surface of the n-type semiconductor column 201 includes:

[0061] S401, placing a planar n-type doped GaN substrate in a reaction chamber of a metal organic vapor deposition system, growing an InGaN / GaN superlattice structure at a temperature of 800° C. to 980° C. to form a stress adjustment layer; wherein the In content of the InGaN layer in the stress adjustment layer is not less than 5%;

[0062] S402. Grow 2 to 20 periods of quantum well / barrier layers on the surface of the stress adjustment layer; wherein the quantum well comprises an InGaN layer having a growth temperature of 600°C to 690°C and a thickness of 1nm to 10nm, and the barrier layer comprises a GaN layer having a growth temperature of 700°C to 850°C and a thickness of 5nm to 20nm.

[0063] In step S5, the step of growing the hole injection enhancement structure 203 on the outer surface of the active region 202 includes:

[0064] The pressure in the reaction chamber of the metal organic vapor deposition system is reduced by 15% to 40%, and a p-type doped GaN or AlGaN layer is grown on the surface outside the active region 202 at a temperature of 800° C. to 980° C. to form a hole injection enhancement structure 203 .

[0065] It should be understood that the hole injection enhancement structure 203 is formed by epitaxially growing a p-type doped GaN layer on the side and upper surface of the active area 202, which is beneficial to enhancing the injection of holes into the active area 202 at the side of the active area 202, thereby improving the radiation recombination efficiency; at the same time, since the resistance of SiO2 in the sidewall film 204 is relatively large, even if material is deposited on the sidewall, the current will not directly pass through the sidewall film 204 from the n-type semiconductor column 201 inside the sidewall film 204 and flow to the material deposited on the sidewall surface, but will flow along the axial direction of the n-type semiconductor column 201, thereby improving the carrier injection efficiency.

[0066] In addition, an AlGaN electron blocking layer with a thickness of 10 to 50 nm can be grown below the first quantum well / barrier layer or above the last quantum well / barrier layer in the active region 202, and its Al content is not less than 5% to reduce electron overflow, that is, to prevent electrons from reaching the hole injection enhancement structure 203 without participating in recombination.

[0067] It can be seen from the above embodiments that the beneficial effects of the present invention are:

[0068] The present invention provides a diode device with a hole injection enhancement structure and a preparation method thereof. In the diode device, the upper surface of each n-type semiconductor column is an active region, and a p-type doped GaN or AlGaN layer is grown on the outer surface of the active region as a hole injection enhancement structure, so as to promote more holes to be directly transported to a deeper quantum well through the injection path provided by the above structure, that is, the injection of holes into the active region is enhanced, which is not only beneficial to improving the radiation recombination efficiency, but also can reduce the turn-on voltage and the operating voltage of the diode device, and improve the carrier injection efficiency and the external quantum efficiency.

[0069] In addition, since p-type semiconductors will grow on the side of n-type semiconductor columns when epitaxy is performed using conventional methods, resulting in significant electron overflow when the device is operating, the present invention deposits a thin film on the sidewall of the n-type semiconductor column, thereby inhibiting electrons or holes from passing through the thin film along the radial direction of the n-type semiconductor column and moving to the material on the surface of the film, and also inhibiting material growth on the surface of the film. Furthermore, the thin film in the present invention is a multilayer material or a single layer material, which contains a dielectric with poor conductivity such as SiO2, SiN x Or TiO2, etc., this insulating or low-conductivity film can inhibit or eliminate the current generated between the n-type semiconductor column wrapped inside and the material on the surface of the film (if any) under an external bias.

[0070] The diode device provided by the present invention is small in size, has the characteristics of high luminous efficiency and high power density, and can be used as a core electronic device in the fields of lighting, display, biomedicine and communication. In the description of the present invention, the description of the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0071] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the present application for which protection is sought, a person skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims.

[0072] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A diode device with a hole injection enhancement structure, characterized in that: include: A planar n-type doped III-nitride semiconductor substrate; A plurality of columnar structures with the same or different diameters arranged in a random or periodic array are located on the surface of the planar n-type doped III-nitride semiconductor substrate, each of the columnar structures comprising: an n-type semiconductor column, an active region, and a hole injection enhancement structure; The active area is located on the upper surface of the n-type semiconductor column, the hole injection enhancement structure is wrapped around the upper surface and at least part of the side surface of the active area, and the material of the n-type semiconductor column and the hole injection enhancement structure is a doped III-group nitride semiconductor, and the doping types are n-type and p-type, respectively.

2. The diode device with hole injection enhancement structure according to claim 1, characterized in that: The hole injection enhancement structure includes a first sub-portion located on the upper surface of the active region and a second sub-portion located on the side of the active region; wherein, The thickness of the first sub-portion and the second sub-portion is not less than 20 nm.

3. The diode device with hole injection enhancement structure according to claim 2, characterized in that: The thickness of the second sub-portion in the hole injection enhancement structure is equal to the distance between the columnar structure and an adjacent columnar structure, so that the hole injection enhancement structures of two adjacent columnar structures touch each other.

4. The diode device with hole injection enhancement structure according to claim 1, characterized in that: The side surface of the n-type semiconductor column is covered with a thin film, and the thin film is used to prevent current conduction between materials on both sides of the thin film.

5. The diode device with hole injection enhancement structure according to claim 4, characterized in that: The film is a multilayer material, and the outermost layer of the multilayer material has the property of reducing or inhibiting nucleation during the epitaxial process; Alternatively, the thin film is a single layer material having the property of reducing or inhibiting nucleation during the epitaxial process.

6. The diode device with hole injection enhancement structure according to claim 1, characterized in that: In each columnar structure, the active region includes, from bottom to top, a stress adjustment layer and an intermediate layer, wherein the intermediate layer includes a plurality of quantum wells and barrier layers stacked alternately.

7. The diode device with hole injection enhancement structure according to claim 1, characterized in that: The columnar structure has a height of 0.1 μm to 10 μm and a diameter of an circumscribed circle of 0.01 μm to 50 μm.

8. A method for preparing a diode device having a hole injection enhancement structure according to any one of claims 1 to 7, characterized in that: include: Providing a planar n-type doped III-nitride semiconductor substrate, the planar n-type doped III-nitride semiconductor substrate comprising an n-type doped III-nitride semiconductor layer and an etching mask layer located on a surface of the n-type doped III-nitride semiconductor layer; Performing photolithography and etching on the etching mask layer and the n-type doped group III nitride semiconductor layer to form a plurality of n-type semiconductor pillars; Using a conformal thin film deposition process, after depositing a thin film on the surface of an n-type doped III-nitride semiconductor substrate with n-type semiconductor pillars, etching away the thin film on the upper surface of each n-type semiconductor pillar and retaining the thin film on the side surface of each n-type semiconductor pillar; growing an active region on the upper surface of each of the n-type semiconductor pillars; A hole injection enhancement structure is grown on the surface of the active region so that the hole injection enhancement structure wraps around the upper surface and at least a portion of the side surface of the active region, thereby obtaining a completed diode device.

9. The method for preparing a diode device with a hole injection enhancement structure according to claim 8, characterized in that: The step of growing a hole injection enhancement structure on the outer surface of the active region comprises: The pressure in the reaction chamber of the metal organic vapor deposition system is reduced by 15% to 40%, and a p-type doped GaN or AlGaN layer is grown on the outer surface of the active area at a temperature of 800°C to 980°C to form a hole injection enhancement structure.

10. The method for preparing a diode device with a hole injection enhancement structure according to claim 8, characterized in that: The step of growing an active region on the upper surface of each of the n-type semiconductor pillars comprises: Placing a planar n-type doped GaN substrate in a reaction chamber of a metal organic vapor deposition system, growing an InGaN / GaN superlattice structure at a temperature of 800° C. to 980° C. to form a stress adjustment layer; wherein the In content of the InGaN layer in the stress adjustment layer is not less than 5%; 2 to 20 periods of quantum well / barrier layers are grown on the surface of the stress adjustment layer; wherein the quantum well comprises an InGaN layer having a growth temperature of 600°C to 690°C and a thickness of 1nm to 10nm, and the barrier layer comprises a GaN layer having a growth temperature of 700°C to 850°C and a thickness of 5nm to 20nm.

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