Array substrate and display panel

Abstract

The present application discloses an array substrate and a display panel. The array substrate includes a thin film transistor (TFT). The gate insulating layer of the TFT includes a first portion and a second portion, wherein the first portion covers the edge portion and the second portion covers the main portion. The TFT is an N-type TFT, wherein the amount of positive charge in the first portion is less than the amount of positive charge in the second portion; or the TFT is a P-type TFT, wherein the amount of negative charge in the first portion is less than the amount of negative charge in the second portion. In the present application, the charge of the first portion of the gate insulating layer is set to be less than the charge of the second portion. When the TFT is turned on, the smaller charge in the first portion eliminates the difference in threshold voltage between the edge TFT having the edge portion and the main TFT having the main portion under the same gate voltage, thereby improving the hump effect of the TFT.

Description

[0001] This application is a divisional application of the Chinese patent application with the application date of August 27, 2024, application number 202411179214.X, and invention name “Array substrate and display panel”. Technical Field

[0002] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0003] Low-temperature polysilicon (LTPS) thin-film transistors (TFTs) are key components in the active drive and peripheral circuits of display devices such as liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs). Currently, N-type LTPS TFTs exhibit a hump effect, resulting in poor electrical properties in the subthreshold region, which limits the charging capabilities of high-performance products. The hump effect is caused by the fact that N-type LTPS TFTs manufactured using current processes can be considered to consist of two parallel TFTs (edge ​​TFTs) on either side and a central TFT. The threshold voltage (Vth) of the edge TFTs is more negative than that of the main TFT, resulting in an abnormal increase in the subthreshold current of the main TFT. Summary of the Invention

[0004] The embodiments of the present application provide an array substrate and a display panel, which can reduce the risk of a hump effect in thin film transistors.

[0005] In one aspect, an embodiment of the present application provides an array substrate, comprising:

[0006] substrate; and

[0007] a thin film transistor disposed on the substrate, the thin film transistor comprising an active layer, a gate insulating layer, a gate, a source electrode, and a drain electrode; the active layer comprising a channel, a first contact portion, and a second contact portion; the channel comprising a main portion and an edge portion, the edge portion having a slope angle less than 90 degrees; the gate insulating layer covering a side of the active layer away from the substrate; the gate insulating layer comprising a first portion and a second connected portion, the first portion covering the edge portion, and the second portion covering the main portion;

[0008] The gate is disposed on a side of the gate insulating layer away from the substrate, the source is connected to the first contact portion, and the drain is connected to the second contact portion;

[0009] In a plan view of the array substrate, in a first direction, the first contact portion, the channel, and the second contact portion are arranged in sequence; in a second direction perpendicular to the first direction, one of the edge portions is located on one side of the main body portion;

[0010] Wherein, the thin film transistor is an N-type thin film transistor, and the amount of positive charges in the first portion is less than the amount of positive charges in the second portion; or

[0011] The thin film transistor is a P-type thin film transistor, and the amount of negative charges in the first portion is smaller than the amount of negative charges in the second portion.

[0012] Optionally, in some embodiments of the present application, the thin film transistor is an N-type thin film transistor, and the number of positive charges per unit area of ​​the second portion is greater than or equal to ten times the number of positive charges per unit area of ​​the first portion.

[0013] Optionally, in some embodiments of the present application, the thickness of the first portion is smaller than the thickness of the second portion.

[0014] Optionally, in some embodiments of the present application, the thickness difference between the first portion and the second portion is between 80 angstroms and 200 angstroms.

[0015] Optionally, in some embodiments of the present application, the thickness of the second portion is between 600 angstroms and 2000 angstroms.

[0016] Optionally, in some embodiments of the present application, the slope angle of the edge portion is between 30 degrees and 80 degrees.

[0017] Optionally, in some embodiments of the present application, the thickness of the main body is between 300 angstroms and 600 angstroms.

[0018] Optionally, in some embodiments of the present application, the array substrate further includes a light-shielding layer, a buffer layer, an interlayer dielectric layer, a planarizing layer, and a pixel electrode, the light-shielding layer is located on the substrate, the buffer layer covers the light-shielding layer and the substrate, the active layer is arranged on a side of the buffer layer away from the substrate, the gate insulating layer covers the active layer, the interlayer dielectric layer covers the gate, the source and the drain are arranged on a side of the interlayer dielectric layer away from the substrate, the planarizing layer covers the source and the drain, the pixel electrode is arranged on a side of the planarizing layer away from the substrate, and the pixel electrode is connected to the source or the drain.

[0019] Optionally, in some embodiments of the present application, the gate insulating layer further includes a third portion connected to one side of the first portion, the third portion directly covers the buffer layer, and the number of positive charges of the third portion is greater than the number of positive charges of the first portion.

[0020] Optionally, in some embodiments of the present application, the amount of positive charges in the first portion and the second portion decreases in a direction from the active layer toward the gate.

[0021] On the other hand, an embodiment of the present application further provides a method for preparing an array substrate, which includes the following steps:

[0022] An active layer and a gate insulating layer are sequentially formed on a substrate; the active layer is N-type, the active layer includes a channel, a first contact portion, and a second contact portion, the channel includes a main portion and an edge portion, the edge portion has a slope angle less than 90 degrees, the gate insulating layer covers a side of the active layer away from the substrate, the gate insulating layer includes a first portion and a second portion connected, the first portion covers the edge portion, and the second portion covers the main portion; in a plan view of the array substrate, in a first direction, the first contact portion, the channel, and the second contact portion are sequentially arranged; in a second direction perpendicular to the first direction, the edge portion is located on one side of the main portion;

[0023] Performing ion implantation on the gate insulating layer to fix positive charges in the gate insulating layer; wherein the amount of positive charges fixed in the first portion is less than the amount of positive charges fixed in the second portion;

[0024] A gate, an interlayer dielectric layer, a source electrode, and a drain electrode are sequentially formed on the gate insulating layer. The source electrode is connected to the first contact portion, and the drain electrode is connected to the second contact portion.

[0025] Optionally, in some embodiments of the present application, the gate insulating layer is processed using a plasma injection technique, and a gas source of the plasma injection technique includes at least one of nitrous oxide and nitrogen.

[0026] On the other hand, an embodiment of the present application further provides a display panel, which includes the array substrate as described in any one of the above embodiments.

[0027] The array substrate of the embodiment of the present application includes a thin film transistor, which includes an active layer, a gate insulating layer, a gate, a source and a drain. The active layer includes a channel, a first contact portion and a second contact portion. The channel includes a main portion and an edge portion, and the edge portion has a slope angle less than 90 degrees; the gate insulating layer covers at least the side of the channel away from the substrate, and the gate insulating layer includes a first portion and a second portion connected to each other, the first portion covers the edge portion, and the second portion covers the main portion; the gate is arranged on the side of the gate insulating layer away from the substrate, the source is connected to the first contact portion, and the drain is connected to the second contact portion; wherein the thin film transistor is an N-type thin film transistor, and the number of positive charges in the first portion is less than the number of positive charges in the second portion; or the thin film transistor is a P-type thin film transistor, and the number of negative charges in the first portion is less than the number of negative charges in the second portion.

[0028] In the embodiment of the present application, in the case of charges of the same polarity, the charge amount of the first part of the gate insulating layer is smaller than the charge amount of the second part. When the thin film transistor is turned on, due to the smaller charge amount of the first part, under the same gate voltage, the negative or positive movement of the threshold voltage of the edge part is smaller, and the corresponding negative or positive movement of the threshold voltage of the main part is larger. In this way, the difference in threshold voltage between the edge thin film transistor with the edge part and the main thin film transistor with the main part is eliminated, thereby achieving the effect of improving the hump effect of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic plan view of a portion of an array substrate provided by one or more embodiments of the present application;

[0030] Figure 2 yes Figure 1 Schematic diagram of the cross-sectional structure along line AA;

[0031] Figure 3 yes Figure 1 Schematic diagram of the cross-sectional structure along line BB;

[0032] Figure 4 Schematic diagram of step B1 of the method for preparing an array substrate provided in an embodiment of the present application;

[0033] Figure 5 2 is a schematic diagram of step B2 of the method for preparing an array substrate provided in an embodiment of the present application;

[0034] Figure 6 2 is a schematic diagram of step B3 of the method for preparing an array substrate provided in an embodiment of the present application;

[0035] Figure 7 4 is a schematic diagram of step B4 of the method for preparing an array substrate provided in an embodiment of the present application;

[0036] Figure 8 1 is a comparison diagram of transfer curves of thin film transistors of comparative example 1, comparative example 2 and the experimental example of the present application at a drain voltage Vd=0.1V and a drain voltage Vd=10V;

[0037] Figure 9 Schematic diagram of the structure of the display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described here are only used to illustrate and explain the present application and are not used to limit the present application. In this application, the various embodiments can be combined with each other but will not be repeated one by one. In addition, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inner" and "outer" refer to the outline of the device; the terms "first", "second", "third", etc. are used only as labels and do not impose numerical requirements or establish an order.

[0039] The present invention provides an array substrate and a method for manufacturing the same, as well as a display panel, which are described in detail below. It should be noted that the order in which the following embodiments are described does not limit the preferred order of the embodiments.

[0040] Please refer to Figures 1 to 3 , Figure 1 This is a schematic plan view of a portion of an array substrate provided by one or more embodiments of the present application. Figure 2 yes Figure 1 The cross-sectional structure diagram along the AA line is shown in the figure. Figure 3 yes Figure 1 Schematic diagram of the cross-sectional structure along line BB.

[0041] exist Figures 1 to 3 In the embodiment, the first direction DR1 may be a direction parallel to one side of the array substrate 100 in a plan view, for example, the longitudinal direction of the array substrate 100, but not limited thereto. The second direction DR2 may be a direction parallel to the other side of the array substrate 100 in a plan view, for example, the transverse direction of the array substrate 100, but not limited thereto. The third direction DR3 may be the thickness direction of the array substrate 100.

[0042] One or more embodiments of the present application provide an array substrate 100, which includes a substrate su and a thin film transistor tft. The thin film transistor tft is disposed on the substrate su.

[0043] The thin film transistor TFT includes an active layer Py, a gate insulating layer Gi, a gate G01, a source S01, and a drain D01. The active layer Py includes a channel Gd, a first contact P1, and a second contact P2. The channel Gd includes a main portion Gd1 and an edge portion Gd2. The edge portion Gd2 has a slope angle α less than 90 degrees.

[0044] The gate insulating layer gi covers the side of the active layer py away from the substrate su and includes a first portion gi1 and a second portion gi2 connected to each other. The first portion gi1 covers the edge portion gd2, and the second portion gi2 covers the main portion gd1.

[0045] The gate g01 is disposed on a side of the gate insulating layer gi away from the substrate su, the source s01 is connected to the first contact portion p1, and the drain d01 is connected to the second contact portion p2.

[0046] In a plan view of the array substrate 100 , in a first direction DR1 , the first contact portion p1 , the channel gd and the second contact portion p2 are sequentially arranged; in a second direction DR2 perpendicular to the first direction DR1 , an edge portion gd2 is located on one side of the main portion gd1 .

[0047] The thin film transistor tft is an N-type thin film transistor, and the amount of positive charges in the first portion gi1 is less than the amount of positive charges in the second portion gi2.

[0048] Alternatively, the thin film transistor tft is a P-type thin film transistor, and the amount of negative charges in the first portion gi1 is smaller than the amount of negative charges in the second portion gi2.

[0049] In the array substrate 100 of the embodiment of the present application, the charge amount of the first part gi1 of the gate insulating layer gi is smaller than the charge amount of the second part gi2 in the case of charges of the same polarity. When the thin film transistor TFT is turned on, due to the smaller charge amount of the first part gi1, under the same gate voltage, the negative or positive movement of the threshold voltage of the edge part gd2 is smaller, and the corresponding negative or positive movement of the threshold voltage of the main part gd1 is larger. In this way, the difference in threshold voltage between the edge thin film transistor t2 with the edge part gd2 and the main thin film transistor t1 with the main part gd1 is eliminated, thereby achieving the effect of improving the hump effect of the thin film transistor TFT.

[0050] For example, in one embodiment, the thin film transistor TFT is an N-type thin film transistor, and the positive charge of the first part GI1 of the gate insulating layer GI is less than the positive charge of the second part GI2. When the thin film transistor TFT is turned on, due to the smaller positive charge of the first part GI1, under the same gate voltage, the threshold voltage of the edge part GD2 moves less negatively, and the corresponding threshold voltage of the main part GD1 moves more negatively. In this way, the difference in threshold voltage between the edge thin film transistor T2 with the edge part GD2 and the main thin film transistor T1 with the main part GD1 is eliminated, thereby achieving the effect of improving the hump effect of the thin film transistor TFT.

[0051] For example, in another embodiment, the thin film transistor TFT is a P-type thin film transistor, and the negative charge of the first part GI1 of the gate insulating layer GI is less than the negative charge of the second part GI2. When the thin film transistor TFT is turned on, due to the smaller amount of negative charge in the first part GI1, under the same gate voltage, the positive movement of the threshold voltage of the edge part GD2 is smaller, and the corresponding positive movement of the threshold voltage of the main part GD1 is larger. In this way, the difference in threshold voltage between the edge thin film transistor T2 with the edge part GD2 and the main thin film transistor T1 with the main part GD1 is eliminated, thereby achieving the effect of improving the hump effect of the thin film transistor TFT.

[0052] It should be explained that the test method for the charge in the gate insulating layer GI can be achieved by testing the CV (capacitance-gate voltage) curve of the thin film transistor TFT and extracting the fixed charge amount through the CV curve.

[0053] Among them, the flat band voltage V is obtained through the CV curve FB , then, through the formula: , calculate the amount of charge. Among them, Q f is the fixed charge quantity, Ø MS is the work function difference between metal and semiconductor, C OX is the gate semiconductor capacitance.

[0054] The following text application is explained by taking the thin film transistor TFT as an N-type thin film transistor as an example.

[0055] Please refer to Figure 1 The thin film transistor TFT includes a main thin film transistor t1 and edge thin film transistors t2 located on both sides of the main thin film transistor t1. The main thin film transistor t1 and the edge thin film transistor t2 share a common gate, a common source, and a common drain. The channel of the main thin film transistor t1 is the main portion gd1, and the channel of the edge thin film transistor t2 is the edge portion gd2.

[0056] It should be understood that the array substrate 100 of the embodiment of the present application is used for a liquid crystal panel. The array substrate 100 of the embodiment of the present application can be based on a Fringe Field Switching (FFS) technology driving architecture, or based on an In-Plane Switching (IPS) technology driving architecture, or based on a Vertical Alignment (VA) technology driving architecture, and so on.

[0057] In some embodiments, the array substrate 100 may also be used in an electroluminescent display panel, such as an organic light emitting diode display panel, a micro light emitting diode display panel, a sub-millimeter light emitting diode display panel, or a quantum dot light emitting diode display panel. In addition, in other embodiments, the array substrate 100 may also be used in an electrophoretic panel, etc.

[0058] The array substrate 100 of the embodiment of the present application is described below based on the FFS architecture, but is not limited thereto.

[0059] Please refer to Figure 2 and Figure 3 In one or more embodiments of the present application, the array substrate 100 further includes a light shielding layer Ls, a buffer layer buf, an interlayer dielectric layer Ld, a planarization layer Pn, and a pixel electrode pix.

[0060] A light-shielding layer Ls is located on the substrate su. A buffer layer buf covers the light-shielding layer Ls and the substrate su. The active layer py is located on the side of the buffer layer buf facing away from the substrate su. A gate insulating layer gi covers the active layer py, and an interlayer dielectric layer Ld covers the gate g01. The source electrode s01 and the drain electrode d01 are located on the side of the interlayer dielectric layer Ld facing away from the substrate su. A planarization layer Pn covers the source electrode s01 and the drain electrode d01. A pixel electrode pix is ​​located on the side of the planarization layer Pn facing away from the substrate su. The pixel electrode pix is ​​connected to the source electrode s01 or the drain electrode d01.

[0061] Optionally, in one or more embodiments, the array substrate 100 may further include a common electrode layer com and a passivation layer Pv. The common electrode layer com is disposed on a side of the planar layer Pn away from the substrate su. The passivation layer Pv covers the common electrode layer com. The pixel electrode pix is ​​disposed on a side of the passivation layer Pv away from the substrate su.

[0062] Optionally, in some embodiments, the substrate su may be a rigid substrate or a flexible substrate. The material of the substrate su includes one of glass, sapphire, silicon, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene diphthalate, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyethersulfone, aromatic fluorotoluene containing polyarylate, polycyclic olefin, polyimide, or polyurethane.

[0063] In some embodiments, the material of the light shielding layer Ls can be an inorganic metal material, such as chromium, molybdenum, manganese, etc., or a metal oxide material, such as CrO x 、MoO x , MnO2, etc., or a mixed film layer formed by metal and metal oxide; it can also be an organic black resin material, such as black polystyrene, black photoresist, etc.

[0064] In some embodiments, the buffer layer buf, the gate insulating layer gi, the interlayer dielectric layer Ld, and the passivation layer Pv may be formed of a plurality of inorganic layers stacked in an alternating manner. For example, the buffer layer buf, the gate insulating layer gi, the interlayer dielectric layer Ld, and the passivation layer Pv may be formed as a double layer formed by stacking inorganic layers including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide, or a multilayer formed by alternatingly stacking inorganic layers including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide. However, the present disclosure is not limited thereto, and the buffer layer buf, the gate insulating layer gi, the interlayer dielectric layer Ld, and the passivation layer Pv may be formed as a single inorganic layer including the above-mentioned insulating materials.

[0065] Furthermore, in one or more embodiments, the interlayer dielectric layer Ld may be made of an organic insulating material such as polyimide (PI).

[0066] Optionally, in one or more embodiments, the gate insulating layer gi further includes a third portion gi3 connected to one side of the first portion gi1, the third portion gi3 directly covers the buffer layer buf, and the number of positive charges of the third portion gi3 is greater than the number of positive charges of the first portion gi1.

[0067] It should be noted that the gate insulating layer gi entirely covers the buffer layer bug, so the gate insulating layer gi not only directly covers the active layer py but also extends to directly cover the buffer layer buf. Plasma injection is performed on the entire surface of the gate insulating layer gi, so the entire gate insulating layer gi is fixed with positive charges.

[0068] Since the relatively flat buffer layer buf is located below the gate insulating layer gi that directly covers the buffer layer buf, the thickness of the third portion gi3 is greater than that of the first portion gi1, and the amount of positive charge fixed in the third portion gi3 is also greater than that in the first portion gi1.

[0069] In some embodiments of the present application, the amount of positive charges in the first portion gi1 and the second portion gi2 decreases gradually from the active layer py toward the gate g01 to further improve the risk of the hump effect.

[0070] In some embodiments, the active layer py can be made of polycrystalline silicon or single crystal silicon. The first contact p1 and the second contact p2 are N-type contacts. Each of the first contact p1 and the second contact p2 includes a heavily doped region and a lightly doped region. The heavily doped region is located on the side of the lightly doped region away from the channel gd. The source s01 is connected to the heavily doped region of the first contact p1, and the drain d01 is connected to the heavily doped region of the second contact p2.

[0071] In some embodiments, the gate g01, source s01, and drain d01 can be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, neodymium, and cobalt, an alloy containing any of the foregoing metal elements, or an alloy combining any of the foregoing metal elements. Furthermore, the gate, source, and drain electrodes can have a single-layer structure or a stacked structure of two or more layers.

[0072] In some embodiments, the material of the planar layer Pn may be an organic transparent film layer, such as transparent photoresist, acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0073] In some embodiments, the materials of the pixel electrode pix and the common electrode layer com can be oxides such as indium tin oxide and indium zinc oxide; they can also be metals, alloys, compounds and mixtures thereof with various conductive properties, such as gold, silver or platinum.

[0074] In one or more embodiments of the present application, the thickness of the edge portion gd2 is gradually changed, and the thickness of the main portion gd1 is uniform. The thickness of the edge portion gd2 increases gradually from the edge of the edge portion gd2 toward the main portion gd1.

[0075] It should be understood that the increasing thickness of the edge portion gd2 does not necessarily mean a 100% increase in thickness. Due to process limitations, the thickness of the edge portion gd2 cannot be 100% accurate. Similarly, due to process limitations, the thickness of the main portion gd1 tends to be uniform, that is, the thickness of the main portion gd1 is generally uniform.

[0076] Optionally, in one or more embodiments of the present application, the thin film transistor tft is an N-type thin film transistor, and the number of positive charges per unit area of ​​the second portion gi2 is greater than or equal to twice the number of positive charges per unit area of ​​the first portion gi1, for example, it can be 2 times, 2.5 times, 3 times, 3.5 times, 4 times, 4.5 times, 5 times, 5.5 times, 6 times, 6.5 times, 7 times, 7.5 times, 8 times, 8.5 times, 9 times, 9.5 times, 10 times, 10.5 times, 11 times, 11.5 times, 12 times, 12.5 times, 13 times, 13.5 times, 14 times, 14.5 times, 15 times, 15.5 times, 16 times, 16.5 times, 17 times, 17.5 times, 18 times, 18.5 times, 19 times, 19.5 times or 20 times.

[0077] It can be understood that the smaller the number of positive charges fixed in the first part gi1 and the greater the number of positive charges fixed in the second part gi2, under the same gate voltage, the less the threshold voltage of the edge thin film transistor t2 moves in the negative direction, and the more the threshold voltage of the corresponding main thin film transistor t1 moves in the negative direction. In this way, the effect of eliminating the difference in threshold voltages between the two is better, so that the subthreshold region of the thin film transistor tft reflects the properties of the main thin film transistor t1 to improve the hump effect.

[0078] Optionally, the number of positive charges in the second portion gi2 per unit area is greater than or equal to ten times the number of positive charges in the first portion gi1 per unit area, so as to better eliminate the hump effect.

[0079] Optionally, in some embodiments of the present application, the thickness d1 of the first portion gi1 is smaller than the thickness d2 of the second portion gi2.

[0080] It can be understood that the smaller thickness d1 of the first portion gi1 of the gate insulating layer gi reduces the amount of positive charge that can be fixed in the first portion gi1, facilitating one-time ion implantation. Furthermore, the greater the difference in thickness between the first portion gi1 and the second portion gi2, the greater the difference in the amount of positive charge that can be fixed between the two portions. This means that it is easier to achieve a larger difference in the amount of fixed positive charge between the first portion gi1 and the second portion gi2, thereby further improving the hump effect.

[0081] Optionally, the thickness difference between the first portion gi1 and the second portion gi2 is between 80 angstroms and 200 angstroms. For example, the thickness difference between the first portion gi1 and the second portion gi2 may be 80 angstroms, 90 angstroms, 100 angstroms, 110 angstroms, 120 angstroms, 130 angstroms, 140 angstroms, 150 angstroms, 160 angstroms, 170 angstroms, 180 angstroms, 190 angstroms, or 200 angstroms.

[0082] It should be understood that the thickness difference between the first portion gi1 and the second portion gi2 is between 80 angstroms and 200 angstroms to avoid an excessive height difference between the two portions.

[0083] Optionally, in one or more embodiments, the first portion gi1 is a single film layer, and the second portion gi2 is a multi-film layer stacking structure.

[0084] For example, the second portion gi2 includes a first film layer directly covering the active layer py and a second film layer disposed on the first film layer, away from the active layer py. The first portion gi1 is made of the same material as the first film layer and is connected to the first film layer. The thickness of the first portion gi1 is slightly smaller than that of the first film layer, and the density of the second film layer is lower than that of both the first film layer and the first portion gi1.

[0085] The first portion gi1 is a single-layer structure deposited from the same material as the first film layer. Due to the slope angle gd2 at the edge, the thickness of the first portion gi1 is lower than that of the first film layer on flat terrain during deposition. The density of the second film layer is lower than that of the first film layer and the first portion gi1, making it easier for plasma to be injected into the second film layer, thereby fixing more positive charges.

[0086] Optionally, in one or more embodiments, the first portion gi1 and the second portion gi2 may both be single film layers, or the first portion gi1 and the second portion gi2 may both be multi-film layer stacking structures.

[0087] Optionally, in one or more embodiments, the thickness d2 of the second portion gi2 is between 600 angstroms and 2000 angstroms, for example, it can be 600 angstroms, 700 angstroms, 800 angstroms, 900 angstroms, 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms, 1500 angstroms, 1600 angstroms, 1700 angstroms, 1800 angstroms, 1900 angstroms or 2000 angstroms.

[0088] Optionally, in one or more embodiments, the slope angle α of the edge portion gd2 is between 30 degrees and 80 degrees.

[0089] It can be understood that the greater the slope angle α of edge portion gd2, the steeper edge portion gd2 becomes, and the smaller the orthographic projection area of ​​edge portion gd2 relative to substrate su becomes. Consequently, when forming gate insulating layer gi by vapor deposition, the thickness of first portion gi1 decreases; and during ion implantation, the effective area of ​​first portion gi1 exposed to plasma implantation also decreases. In other words, the smaller the thickness and effective area of ​​first portion gi1, the smaller the amount of positive charge that can be fixed by first portion gi1.

[0090] The slope angle α of the edge portion gd2 is between 30 degrees and 80 degrees, which takes into account the ability of the first portion gi1 to fix positive charges, avoids the thickness of the first portion gi1 being too small, and even avoids the risk of the first portion gi1 and the second portion gi2 being disconnected due to the slope angle being too steep.

[0091] Optionally, the slope angle α of the edge portion gd2 may be 30 degrees, 35 degrees, 40 degrees, 45 degrees, 50 degrees, 55 degrees, 60 degrees, 65 degrees, 70 degrees, 75 degrees, or 80 degrees.

[0092] Optionally, in one or more embodiments, the thickness of the main body portion gd1 is between 300 angstroms and 600 angstroms, for example, 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms, 500 angstroms, 550 angstroms, or 600 angstroms.

[0093] It is understood that, when the slope angle α of the edge portion gd2 is constant, the thicker the main portion gd1 is, the larger the effective area of ​​the edge portion gd2 for ion implantation. Therefore, the thickness of the main portion gd1 is also a factor affecting the ability of the edge portion gd2 to hold positive charges.

[0094] On the other hand, an embodiment of the present application further provides a method for preparing an array substrate 100, which includes the following steps:

[0095] Step B1: An active layer py and a gate insulating layer gi are sequentially formed on a substrate. The active layer py is N-type and includes a channel, a first contact portion, and a second contact portion. The channel gd includes a main portion gd1 and an edge portion gd2, with the edge portion gd2 having a slope angle less than 90 degrees. The gate insulating layer gi covers the side of the active layer py away from the substrate su. The gate insulating layer gi includes a first portion gi1 and a second portion gi2 connected to each other. The first portion gi1 covers the edge portion gd2, and the second portion gi2 covers the main portion gd1. In a plan view of the array substrate 100, the first contact portion p1, the channel gd, and the second contact portion p2 are sequentially arranged in a first direction. In a second direction DR2 perpendicular to the first direction DR1, an edge portion gd2 is located on one side of the main portion gd1.

[0096] Step B2: performing ion implantation on the gate insulating layer gi to fix positive charges in the gate insulating layer gi, wherein the amount of positive charges fixed in the first portion gi1 is less than the amount of positive charges fixed in the second portion gi2.

[0097] Step B3: forming a gate g01, an interlayer dielectric layer Ld, a source s01, and a drain d01 on the gate insulating layer gi in sequence. The source s01 is connected to the first contact portion p1, and the drain d01 is connected to the second contact portion p2.

[0098] It should be understood that the preparation method of the array substrate 100 of the embodiment of the present application adopts plasma injection to perform injection into the entire surface of the gate insulating layer gi. Due to the influence of the terrain of the edge portion gd2, the fixed positive charge of the first portion gi1 of the gate insulating layer gi is smaller than the fixed positive charge of the second portion gi2, thereby achieving the goal of improving the risk of the hump effect.

[0099] The following is based on Figures 1 to 3 The preparation methods are described in the corresponding embodiments, but are not limited thereto.

[0100] Please refer to Figure 4 , step B1,

[0101] Step B1: forming an active layer py and a gate insulating layer gi in sequence on a substrate.

[0102] Optionally, the material of the active layer py may be polysilicon.

[0103] Optionally, before forming the active layer py on the substrate su, the method further includes forming a light shielding layer Ls and a buffer layer buf on the substrate su. The active layer py is formed on the buffer layer buf.

[0104] Then go to step B2.

[0105] Please refer to Figure 5 , step B2, performing ion implantation treatment on the gate insulating layer gi to fix positive charges in the gate insulating layer gi.

[0106] Optionally, the gate insulating layer gi is treated using a plasma injection technique, wherein the gas source of the plasma injection technique includes at least one of nitrous oxide (N2O) and nitrogen (N2). This embodiment of the present application is described using nitrous oxide as the gas source, but is not limited thereto.

[0107] During the plasma injection step, nitrous oxide is dissociated into a plasma in which positively charged particles (NO + ) is injected into the gate insulating layer gi under the action of the vertical electric field, and some positively charged particles undergo charge exchange with the atoms in the gate insulating layer gi, so that the positive charge is fixed in the gate insulating layer gi.

[0108] During the plasma implantation step, the pressure in the chamber is between 800 and 1400 mtorr, such as 800 mtorr, 900 mtorr, 1000 mtorr, 1100 mtorr, 1200 mtorr, 1300 mtorr, or 140 mtorr.

[0109] The radio frequency power is between 3000 and 6000 KW, for example, 3000 KW, 3500 KW, 4000 KW, 4500 KW, 5000 KW, 5500 KW or 6000 KW.

[0110] The chamber temperature is between 300 and 400 degrees Celsius, such as 300 degrees Celsius, 310 degrees Celsius, 320 degrees Celsius, 330 degrees Celsius, 340 degrees Celsius, 350 degrees Celsius, 360 degrees Celsius, 370 degrees Celsius, 380 degrees Celsius, 390 degrees Celsius, or 400 degrees Celsius.

[0111] The duration of the plasma injection is between 10 and 90 seconds, such as 10 seconds, 20 seconds, 30 seconds, 40 seconds, 50 seconds, 60 seconds, 70 seconds, 80 seconds or 90 seconds.

[0112] Then go to step B3.

[0113] Please refer to Figure 6 , step B3, forming a gate g01, an interlayer dielectric layer Ld, a source s01 and a drain d01 in sequence on the gate insulating layer gi.

[0114] Optionally, step B3 includes: sequentially forming a gate g01 on the gate insulating layer gi; subsequently, forming an interlayer dielectric layer Ld on the gate g01; and thereafter, forming a source s01 and a drain d01 on the interlayer dielectric layer Ld.

[0115] In addition, the method for preparing the array substrate 100 according to the embodiment of the present application further includes the following steps:

[0116] Please refer to Figure 7 Step B4: forming a planarization layer Pn, a common electrode layer com, a passivation layer pv, and a pixel electrode pix on the source electrode s01 and the drain electrode d01 in sequence. The pixel electrode pix is ​​connected to the drain electrode d01 through a via hole.

[0117] Please note that, please refer to Figure 8 , Figure 8 This is a comparison diagram of transfer curves of thin film transistors of Comparative Example 1, Comparative Example 2 and an embodiment (experimental example) of the preparation method of the present application at a drain voltage of Vd=0.1 volt and a drain voltage of Vd=10 volt.

[0118] The only difference between Comparative Examples 1 and 2 and the experimental example is whether plasma implantation is used in the gate insulating layer gi during the manufacturing process. The gate insulating layer of the low-temperature polysilicon thin-film transistor in Comparative Example 1 is not implanted with plasma, while the gate insulating layer of the low-temperature polysilicon thin-film transistor in Comparative Example 2 is implanted with oxygen plasma. The experimental example is a low-temperature polysilicon thin-film transistor formed by the method for preparing the array substrate 100 according to an embodiment of the present application, and is implanted with nitrous oxide (N2O) plasma.

[0119] according to Figure 8 It can be seen that compared with Comparative Example 1, regardless of the drain voltage Vd=0.1V or the drain voltage Vd=10V, Comparative Example 2 using oxygen plasma for injection has no obvious improvement on the hump effect; while the experimental examples using nitrous oxide (N2O) plasma for injection have a better improvement effect on the hump effect.

[0120] On the other hand, please refer to Figure 9 , an embodiment of the present application further provides a display panel 1000, which includes the array substrate as described in any one of the above embodiments.

[0121] The display panel 1000 of the embodiment of the present application can be one of a liquid crystal panel, an electroluminescent display panel and an electrophoretic panel, for example, it can be an FFS liquid crystal display panel, an IPS liquid crystal display panel, a VA liquid crystal display panel, an organic light emitting diode display panel, a micro light emitting diode display panel, a sub-millimeter light emitting diode display panel, a quantum dot light emitting diode display panel or an electrophoretic panel, etc.

[0122] It should be noted that the structure of the thin film transistor of the array substrate of the display panel in the embodiment of the present application is similar to or the same as the structure of the thin film transistor TFT of the array substrate 100 in any of the above embodiments.

[0123] Optional, Figure 9 The display panel 1000 of one embodiment of the present application is shown. The display panel 1000 is a liquid crystal panel and includes an array substrate 100, an opposing substrate 200 disposed opposite to the array substrate 100, and a liquid crystal layer 300 disposed between the array substrate 100 and the opposing substrate 200.

[0124] The display panel of the embodiment of the present application includes a thin film transistor, which includes an active layer, a gate insulating layer, a gate, a source and a drain. The active layer includes a channel, a first contact portion and a second contact portion. The channel includes a main portion and an edge portion, and the edge portion has a slope angle less than 90 degrees; the gate insulating layer covers at least the side of the channel away from the substrate, and the gate insulating layer includes a first portion and a second portion connected to each other, the first portion covers the edge portion, and the second portion covers the main portion; the gate is arranged on the side of the gate insulating layer away from the substrate, the source is connected to the first contact portion, and the drain is connected to the second contact portion; wherein the thin film transistor is an N-type thin film transistor, and the number of positive charges in the first portion is less than the number of positive charges in the second portion; or the thin film transistor is a P-type thin film transistor, and the number of negative charges in the first portion is less than the number of negative charges in the second portion.

[0125] In the embodiment of the present application, in the case of charges of the same polarity, the charge amount of the first part of the gate insulating layer is smaller than the charge amount of the second part. When the thin film transistor is turned on, due to the smaller charge amount of the first part, under the same gate voltage, the negative or positive movement of the threshold voltage of the edge part is smaller, and the corresponding negative or positive movement of the threshold voltage of the main part is larger. In this way, the difference in threshold voltage between the edge thin film transistor with the edge part and the main thin film transistor with the main part is eliminated, thereby achieving the effect of improving the hump effect of the thin film transistor.

[0126] The above is a detailed introduction to an array substrate, a preparation method thereof, and a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: substrate; as well as a thin film transistor disposed on the substrate, the thin film transistor comprising an active layer, a gate insulating layer, and a gate, the active layer comprising a channel, the channel comprising a main portion and an edge portion, the edge portion having a slope angle less than 90 degrees, the gate insulating layer covering a side of the active layer away from the substrate, the gate insulating layer comprising a first portion and a second connected portion, the first portion covering the edge portion, and the second portion covering the main portion; The gate is arranged on a side of the gate insulating layer away from the substrate, and the gate and the channel are arranged correspondingly; In a plan view of the array substrate, the edge portion is located on one side of the main portion, and an arrangement direction of the main portion and the edge portion is parallel to an extension direction of the gate; Wherein, the thin film transistor is an N-type thin film transistor, and the amount of positive charges in the first portion is less than the amount of positive charges in the second portion; or The thin film transistor is a P-type thin film transistor, and the amount of negative charges in the first portion is smaller than the amount of negative charges in the second portion.

2. The array substrate according to claim 1, wherein: The thin film transistor is an N-type thin film transistor, and the amount of positive charges in the second portion per unit area is greater than or equal to ten times the amount of positive charges in the first portion per unit area.

3. The array substrate according to claim 2, wherein: The amounts of positive charges in the first portion and the second portion decrease gradually in a direction from the active layer toward the gate.

4. The array substrate according to claim 1, wherein: The thickness of the first portion is smaller than the thickness of the second portion.

5. The array substrate according to claim 4, wherein: A thickness difference between the first portion and the second portion is between 80 angstroms and 200 angstroms.

6. The array substrate according to claim 5, wherein: The thickness of the second portion is between 600 angstroms and 2000 angstroms.

7. The array substrate according to claim 4, wherein: The slope angle of the edge portion is between 30 degrees and 80 degrees.

8. The array substrate according to claim 7, wherein: The thickness of the main body is between 300 angstroms and 600 angstroms.

9. The array substrate according to any one of claims 1 to 8, wherein: The thin film transistor further includes a source electrode and a drain electrode, the active layer further includes a first contact portion and a second contact portion, the source electrode is connected to the first contact portion, and the drain electrode is connected to the second contact portion; The array substrate also includes a light-shielding layer, a buffer layer, an interlayer dielectric layer, a planarization layer, and a pixel electrode. The light-shielding layer is located on the substrate, the buffer layer covers the light-shielding layer and the substrate, the active layer is arranged on a side of the buffer layer away from the substrate, the gate insulating layer covers the active layer, the interlayer dielectric layer covers the gate, the source and the drain are arranged on a side of the interlayer dielectric layer away from the substrate, the planarization layer covers the source and the drain, the pixel electrode is arranged on a side of the planarization layer away from the substrate, and the pixel electrode is connected to the source or the drain.

10. The array substrate according to claim 9, wherein: The gate insulating layer further includes a third portion connected to one side of the first portion, the third portion directly covers the buffer layer, and the amount of positive charges in the third portion is greater than the amount of positive charges in the first portion.

11. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 10.

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