Power conversion device

Abstract

An inverter circuit (3) in which a plurality of branches, each of which is formed by connecting a plurality of switching elements (3a-3f) in series, are connected in parallel; and a switching circuit (4) having a plurality of switching elements (4a-4f), one end of which is connected to a connection point of the capacitor series circuits (2a, 2b), and the other end of which is connected to a plurality of connection points of the switching elements (3a-3f) of the inverter circuit (3). The inverter circuit (3) can perform a 2-level operation by turning off the switching elements (4a-4f) of the switching circuit (4), and can perform a 3-level operation by turning on / off the switching elements (4a-4f) of the switching circuit (4), and the control circuit (8) changes the switching speed of the switching elements (3a-3f, 4a-4f) when the operation level is switched between the 2-level operation and the 3-level operation.

Description

Technical Field

[0001] The present application relates to a power conversion device. Background Art

[0002] In the past, there was a power conversion device as follows: a first and a second DC power supply connected in series and a power converter for converting the DC power of each DC power supply into AC power, in which at least two switching elements consisting of semiconductor elements are connected in series to form one arm, and at least three arms are connected in parallel, and between the connection points between the switching elements in each arm and the connection points between the DC power supplies, an AC switch consisting of at least two switching elements consisting of a semiconductor element and a diode connected in anti-parallel to the semiconductor element connected in series is connected respectively, and by turning on or off each AC switch, the power converter can perform three-level operation or two-level operation (refer to Patent Document 1 below).

[0003] Patent Document 1: International Publication No. WO2012 / 025978 Summary of the invention

[0004] Problem that the invention aims to solve

[0005] In the power conversion device as described above, in the 2-level operation, the power supply voltage is applied to the switching elements connected in series, and in the 3-level operation, the half of the power supply voltage is applied to the switching elements connected in series. Here, if the state is switched from "a state in which the gate resistance value at the time of disconnection is adjusted to the optimal range in which the surge voltage generated during the switching operation is below the allowable surge voltage of the switching element in a manner that is low-loss in the 3-level operation" to the 2-level operation, the voltage applied to the switching elements connected in series is twice that of the 3-level operation. As a result, the surge voltage generated during the switching operation exceeds the allowable surge voltage of the switching element, and there is a concern that the switching element may fail.

[0006] The present application discloses a technology for solving the above-mentioned problems, and aims to provide a power conversion device capable of switching the operation level between 2-level operation and 3-level operation without the worry of failure of a switching element when switching the operation level.

[0007] Solutions for solving problems

[0008] The power conversion device disclosed in the present application comprises:

[0009] A capacitor series circuit has a plurality of capacitors connected in series, with both ends connected to the ends of a DC voltage source;

[0010] An inverter circuit is formed by connecting a plurality of branches formed by connecting a plurality of switching elements in series in parallel, wherein a DC input end is connected to both ends of the capacitor series circuit, and an AC output end is connected to a load;

[0011] a switching circuit having a plurality of switching elements, one end of which is connected to connection points of the plurality of capacitors and the other end of which is connected to a plurality of connection points of the switching elements of the inverter circuit; and

[0012] a control circuit, controlling the inverter circuit and the switch circuit,

[0013] The inverter circuit can perform a two-level operation by turning off the switch element included in the switch circuit, and can perform a three-level operation by turning on / off the switch element included in the switch circuit.

[0014] The control circuit changes the switching speeds of the switching elements of the inverter circuit and the switching circuit when switching the operation level between the two-level operation and the three-level operation.

[0015] Effects of the Invention

[0016] According to the power conversion device disclosed in the present application, it is possible to realize a power conversion device in which there is no risk of failure of a switching element even when switching the operation level. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a diagram showing the structure of the power conversion device according to the first embodiment.

[0018] Figure 2 This is a diagram showing the configuration of a gate input unit of the power conversion device according to the first embodiment.

[0019] Figure 3 This is a diagram showing the load current and the switch voltage in the case of 2-level operation and 3-level operation.

[0020] Figure 4 This is a schematic diagram showing the loss details of the power conversion device during 2-level operation and 3-level operation.

[0021] Figure 5 : is a diagram showing time series data of the WLTC mode driving pattern.

[0022] Figure 6 This is a schematic diagram showing the relationship between the current value of the level operation switching and the loss during WLTC mode driving.

[0023] Figure 7 This is a schematic diagram showing the relationship between the current value of the level operation switching and the volume of the power conversion device.

[0024] Figure 8 This is an operational concept diagram showing the characteristics of the control of the power conversion device according to the first embodiment.

[0025] Fig. 9 This is a diagram showing a specific control flow chart of the power conversion device according to the first embodiment.

[0026] Fig.10 This is a diagram showing a specific control flow chart of the power conversion device according to the first embodiment.

[0027] Fig.11 This is a diagram showing a specific control flow chart of the power conversion device according to the first embodiment.

[0028] Fig.12 This is a schematic diagram showing the switching of the operation level according to the motor operation point based on the first embodiment, and is a diagram mapping the relationship between the 2-level operation and the 3-level operation and the carrier frequency to the rotation speed and torque characteristics of the motor.

[0029] Fig.13 It means that the Figure 1 Diagram of the structure of the power conversion device other than .

[0030] Fig.14 This is an operational concept diagram showing the characteristics of the control of the power conversion device according to the second embodiment.

[0031] Fig.15 This is a diagram showing the configuration of a buffer circuit in a gate input portion of the power conversion device according to the first embodiment.

[0032] Fig.16 This is a diagram showing the hardware configuration of a control circuit of a power conversion device according to the first and second embodiments. DETAILED DESCRIPTION

[0033] Implementation method 1.

[0034] The power conversion device according to the first embodiment of the present disclosure will be described using drawings.

[0035] [Structure of power conversion device]

[0036] Figure 1 This is a diagram showing the structure of the power conversion device according to the first embodiment.

[0037] Figure 1 The power conversion device shown is connected between a DC voltage source 1 and a motor 7 as a load, and operates the motor (load) 7 by converting the DC power from the DC voltage source 1 into AC power and outputting it to the motor (load) 7.

[0038] The power conversion device includes: a capacitor series circuit 2 formed by connecting multiple capacitors 2a and 2b in series; an inverter circuit 3 having multiple switching elements 3a, 3b, 3c, 3d, 3e, and 3f; a switching circuit 4 having multiple switching elements 4a, 4b, 4c, 4d, 4e, and 4f; gate input parts 5a, 5b, 5c, 5d, 5e, and 5f of the switching elements 3a, 3b, 3c, 3d, 3e, and 3f; gate input parts 6a, 6b, 6c, 6d, 6e, and 6f of the switching elements 4a, 4b, 4c, 4d, 4e, and 4f; and a control circuit 8 for controlling the inverter circuit 3 and the switching circuit 4.

[0039] In addition, in this embodiment, a three-phase inverter device is shown as an example of a power conversion device, but it does not necessarily need to be a three-phase inverter device, and a single-phase or four-phase or more inverter device may also be used. In addition, a motor 7 is shown as an example of a load, but other load devices may also be used.

[0040] The capacitor 2a and the capacitor 2b are connected in series to form a capacitor series circuit 2. Here, the connection point between the capacitor 2a and the capacitor 2b is described as a first connection point. The two ends of the capacitor series circuit 2 are connected to the two ends of the DC voltage source 1 and the DC input end of the inverter circuit 3 described later. In addition, the case where the capacitor series circuit 2 is formed by connecting two capacitors in series is shown here, but it is not limited to this, and more than three capacitors can also be connected.

[0041] The inverter circuit 3 is a structure in which three branches consisting of two switching elements connected in series are connected in parallel, and both ends of each branch are connected to both ends of the capacitor series circuit 2 and both ends of the DC voltage source 1. Figure 1 In the example shown, the arm of the switching element 3a is connected in series with the arm of the switching element 3b to form a U-phase branch, the arm of the switching element 3c is connected in series with the arm of the switching element 3d to form a V-phase branch, and the arm of the switching element 3e is connected in series with the arm of the switching element 3f to form a W-phase branch. Here, the connection point between the switching element 3a and the switching element 3b, the connection point between the switching element 3c and the switching element 3d, and the connection point between the switching element 3e and the switching element 3f are described as the second, third, and fourth connection points, respectively. The second, third, and fourth connection points become the AC output ends of the inverter circuit 3. The motor 7 as a load is connected to the second, third, and fourth connection points, and the inverter circuit 3 supplies AC power to the motor 7 via the second, third, and fourth connection points.

[0042] In addition, as the switching elements 3a to 3f used in the inverter circuit 3, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having an anti-parallel diode between the source and the drain is used, and as the MOSFET, either SiC or Si can be applied, and as the anti-parallel diode, a diode built into the MOSFET can be used, or a diode can be provided in an external manner. In addition, an IGBT (Insulated Gate Bipolar Transistor) or a GaN-HEMT (Gallium nitride-High Mobility Transistor) in which a diode is connected in anti-parallel can also be used.

[0043] The switch circuit 4 includes a plurality of switch elements 4 a to 4 f , and by controlling the switch elements 4 a to 4 f , it is possible to switch between a two-level operation and a three-level operation described below. Figure 1 The switch circuit 4 shown is arranged between the second to fourth connection points of the inverter circuit 3 and the first connection point of the capacitors 2a and 2b, and uses a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having an anti-parallel diode between the source and the drain. Here, either SiC or Si can be applied as a MOSFET. In addition, as an anti-parallel diode, a diode built into the MOSFET can be used, or a diode can be set separately in an external manner. In addition, an IGBT (Insulated Gate Bipolar Transistor) or a GaN-HEMT (Gallium nitride-High Mobility Transistor) in which a diode is connected in anti-parallel can also be used.

[0044] In the switch circuit 4, the switch element 4a is connected in reverse series with the switch element 4b, the switch element 4c is connected in reverse series with the switch element 4d, and the switch element 4e is connected in reverse series with the switch element 4f. In addition, the source terminals of the switch elements 4a, 4c, and 4e are connected to the first connection point of the capacitor series circuit 2, and the source terminals of the switch elements 4b, 4d, and 4f are connected to the second to fourth connection points, respectively. As a reverse series connection structure, the drain terminals of the switch element 4a and the switch element 4b, the switch element 4c and the switch element 4d, and the switch element 4e and the switch element 4f are connected to each other.

[0045] With the structure of the switch circuit 4 as described above, by turning on the switch element 4a, the current can flow from the second connection point to the first connection point, and by turning on the switch element 4b, the current can flow from the first connection point to the second connection point. In addition, by turning on the switch element 4c, the current can flow from the third connection point to the first connection point, and by turning on the switch element 4d, the current can flow from the first connection point to the third connection point. Furthermore, by turning on the switch element 4e, the current can flow from the fourth connection point to the first connection point, and by turning on the switch element 4f, the current can flow from the first connection point to the fourth connection point. In addition, the switch circuit 4 is not limited to Figure 1 The structure shown may be any structure as long as the direction of current flow can be controlled by turning on or off one of the switching elements.

[0046] The gate input parts 5a~5f turn on and off the switching elements 3a~3f of the inverter circuit 3 based on the PWM (Pulse Width Modulation) signal output from the control circuit 8, and set the gate resistance value Rgoff of the switching elements 3a~3f of the inverter circuit 3 when they are turned off based on the gate resistance selection signal (Rg selection signal).

[0047] The gate input units 6a~6f turn on and off the switching elements 4a~4f of the switching circuit 4 based on the PWM signal output from the control circuit 8, and set the gate resistance value Rgoff of the switching elements 4a~4f of the switching circuit 4 when they are turned off based on the gate resistance selection signal (Rg selection signal).

[0048] [Gate input section of power conversion device]

[0049] Figure 2 1 is a diagram showing the structure of a gate input unit of a power conversion device according to Embodiment 1. Figure 2 , a configuration diagram focusing on the connection relationship between the gate input portion 5a corresponding to the switching element 3a and the control circuit 8 is shown.

[0050] like Figure 2As shown in FIG. 1 , the PWM signal P5a output from the control circuit 8 to the gate input portion 5a is input to a totem pole type buffer circuit 11 composed of, for example, a PNP transistor and an NPN transistor. Then, when the PWM signal P5a is ON, a current flows from the on-state power supply 12 to the switching element 3a via the gate resistance Rgon at the on-state and via the buffer circuit 11, and the switching element 3a is turned on. On the other hand, when the PWM signal P5a is OFF, a current flows from the switching element 3a to the off-state power supply 15 via the gate resistance value Rgoff at the off-state via the gate resistance switching circuit 10, and the switching element 3a is turned off, thereby performing the on-off operation of the switching element 3a.

[0051] In addition, the same operation as described above is performed on the PWM signals P5b, P5c, P5d, P5e, P5f and the PWM signals P6a, P6b, P6c, P6d, P6e, and P6f output from the control circuit 8 of the gate input parts 5b~5f and the gate input parts 4a~4f, to perform the on-off operation of the switching elements 3b~3f and the switching elements 4a~4f.

[0052] In addition, the Rg selection signal R5a output from the control circuit 8 performs the switching operation of the switches SW2, SW3, SW4, and SW5 to adjust the gate resistance value Rgoff of the gate resistance switching circuit 10. That is, the Rg selection signal R5a is a signal that expresses in a time-division manner whether the switches SW2, SW3, SW4, and SW5 are set to the on state or the off state. When the signal is input to the gate resistance determination unit 9, it is divided into the on or off signal of the switches SW2 to SW5 in the gate resistance determination unit 9 and input to each switch SW2 to SW5, thereby making the switches SW2 to SW5 perform on-off operations in any combination. Then, the gate resistance switching circuit 10 adjusts the gate resistance value Rgoff when the switch element 3a is off to the combined resistance value of the resistor Rg1 and the resistance values ​​of the resistors Rg2, Rg3, Rg4, and Rg5 when they are on.

[0053] In addition, Figure 1In order to simplify the control, as "Rg selection signal × 1", it is assumed that the Rg selection signals R5a, R5b, R5c, R5d, R5e, R5f, R6a, R6b, R6c, R6d, R6e, and R6f are 1 type (common). Here, since the switching elements 4a~4f are only applied with half the voltage (Vdc / 2) of the voltage (Vdc) of the DC voltage source 1, the maximum surge voltage is lower than that of the switching elements 3a~3f. In order to use the surplus of the surge voltage for loss reduction, it is considered to set the gate resistance value of the gate input part 6a~6f of the switching elements 4a~4f when it is disconnected to be smaller than the gate resistance value of the gate input part 5a~5f of the switching elements 3a~3f when it is disconnected. In this case, specifically, in Figure 2 This can be achieved by changing the resistance values ​​of the resistors Rg1~Rg5 of the gate input parts 5a~5f and the resistors Rg1~Rg5 of the gate input parts 6a~6f for the common Rg selection signals R5a~R5f and R6a~R6f transmitted to the gate input parts 5a~5f and the gate input parts 6a~6f.

[0054] [Power conversion device and motor]

[0055] The motor 7 is connected to the AC output terminal of the inverter circuit 3 and operates using the AC power output from the inverter circuit 3. The motor 7 may be in any form. Figure 1 In the embodiment, a control device (not shown) calculates a torque command and a speed command, and a control circuit 8 controls the switching elements 3a to 3f and the switching elements 4a to 4f of the power conversion device based on the torque command and the speed command, thereby driving and controlling the motor 7. In addition, the control circuit 8 may also serve as a control device for generating a torque command and a speed command.

[0056] The control circuit 8 controls the switching elements 3a to 3f of the inverter circuit 3 and the switching elements 4a to 4f of the switch circuit 4. That is, the control circuit 8 controls the AC power output to the motor 7 based on the operation state information of the power conversion device including the inverter circuit 3 and the switch circuit 4, the operation state information of the motor 7, and the command value information for the power conversion device and the motor 7. For example, the voltage of the DC voltage source 1, the voltage and current of the capacitors 2a and 2b, the temperature of the inverter circuit 3 and the switch circuit 4, the phase current of the motor 7, the information of the rotation position, the torque command, and the speed command information (NT characteristics) are taken in from the motor 7, and the inverter circuit 3 and the switch circuit 4 are controlled based on this information. In addition, the control circuit 8 appropriately sets the carrier frequency of the inverter circuit 3, the operation state of the two-level operation or the three-level operation, and the selection of the gate resistance value Rgoff of the gate resistance switching circuit 10 based on the preset operation state information and command value information of the power conversion device (inverter circuit 3, switch circuit 4) or the motor 7, for example, the operation map defined on the NT characteristics of the motor 7. The details will be described later.

[0057] [Two-level operation and three-level operation of power conversion device]

[0058] Here, based on Figure 3 A and Figure 3 B illustrates the 2-level operation and 3-level operation of the power conversion device.

[0059] Figure 3 A and Figure 3 B is a schematic diagram showing a motor current of one phase when the power conversion device is operated at two levels and when the power conversion device is operated at three levels.

[0060] First, use Figure 3 A describes a two-level operation. In the two-level operation of the power conversion device shown in this embodiment, Figure 1 By turning off the switch elements 4a to 4f of the switch circuit 4 and turning on / off the switch elements 3a to 3f of the inverter circuit 3, a positive voltage value and a negative voltage value as the total voltage of the capacitors 2a and 2b can be output to the motor 7 in each phase. By controlling the time ratio of the positive voltage and the negative voltage, a three-phase sinusoidal wave voltage can be provided to the motor 7. The two-level operation is an operation of a general three-phase inverter device, and a detailed description thereof is omitted.

[0061] Next, use Figure 3 B. The three-level operation is described. Here, the operation of one phase is described, and the operations of the other two phases are the same as the operation of the one phase, so the description is omitted.

[0062] First, the current flowing from the power conversion device to the motor 7 is described as an example. Figure 1The description starts from the state in which the current flows through the diode connected in antiparallel to the switching element 3b and flows back to the motor 7 when the switching elements 3a, 3b and the switching elements 4a, 4b are turned off. From this state, the switching element 4b is turned on, and the switching elements 3a, 3b and the switching element 4a are kept turned off, thereby the current flows through the motor 7 via the diode connected in antiparallel to the switching element 4a and the switching element 4b through the voltage of the capacitor 2b.

[0063] Next, when the switch element 4b is kept on and the switch element 3a is turned on (the switch element 3b and the switch element 4a are kept off), since the switch element 4a blocks the reverse current, the current does not flow through the switch elements 4a and 4b, and the current flowing through the motor 7 increases through the voltage of the capacitors 2a and 2b connected in series.

[0064] On the other hand, when reducing the current flowing to the motor 7, the following actions are performed in the reverse order of the above order: the switch element 4b is kept on and the switch elements 3a, 3b and the switch element 4a are disconnected, the current is reduced by flowing the voltage of the capacitor 2b to the motor 7, and finally all the switch elements are disconnected.

[0065] When the inverter circuit 3 and the switch circuit 4 are operated in this way, the voltage of each switch element becomes the voltage of the capacitors 2a and 2b, that is, half the voltage of the DC voltage source 1 (Vdc / 2), the switching loss is reduced, and the voltage of the control current is small, so the current distortion is reduced.

[0066] Next, a case where a current flows from the motor 7 to the inverter circuit 3 will be described.

[0067] First, when the switch element 4a is turned on, the switch element 3b is turned on, and the switch element 4b is turned off, the switch element 4a blocks the reverse current, so the current does not flow through the capacitor 2b, and the current from the motor 7 flows through the switch element 3b and flows back to the motor 7.

[0068] Next, when the switching element 3b is turned off (the switching element 3a and the switching element 4b remain off), the current of the motor 7 flows through the capacitor 2b via the diode connected in antiparallel to the switching element 4b and the switching element 4a.

[0069] Next, when the switch element 4a is turned off, the current of the motor 7 flows through the diode connected in antiparallel to the switch element 3a and flows through the capacitors 2a and 2b. After that, the switching operation is performed in the reverse order to the above order, thereby operating in a manner to reduce the current of the motor 7. The operation of one phase is described as an example, and the other phases are the same except that the phases are different.

[0070] Will Figure 3 The 2-level operation shown in A is Figure 3 Comparing the current waveforms of the motor phase currents during 3-level operation shown in B, it can be seen that the current waveform during 2-level operation is distorted compared to the current waveform during 3-level operation. This is because the voltage used to generate the current controls the current at a voltage that is twice that during 2-level operation compared to 3-level operation. During 2-level operation, the current distortion increases, so there is a disadvantage that the higher harmonic iron loss of the motor increases. In addition, during 2-level operation, the voltage during switching operation is twice, so there is a disadvantage that the switching loss of the inverter circuit 3 generated during switching operation increases.

[0071] Figure 4 A schematic diagram showing the breakdown of losses in a power converter during two-level operation and three-level operation.

[0072] Here, in the switch circuit 4 , the switch elements 4 a and 4 b , the switch elements 4 c and 4 d , and the switch elements 4 e and 4 f connected in series are referred to as arms of the switch circuit 4 .

[0073] Each arm of the switch circuit 4 (for example, the arm of the switch element 4a and the arm of the switch element 4b) is composed of two switch elements connected in series, so when current flows through the switch circuit 4, conduction loss of the switch element on the on side (for example, the switch element 4a) and conduction loss of the diode connected in anti-parallel with the other switch element (for example, the switch element 4b) are generated, and thus the conduction loss of the power conversion device is greater in the three-level operation using the switch circuit 4. However, as mentioned above, in the three-level operation, the voltage applied to the inverter circuit 3 is half compared to the two-level operation, so the switching loss and the recovery loss are greatly reduced, and the overall loss of the power conversion device is reduced.

[0074] On the other hand, a power conversion device capable of three-level operation requires the addition of a switch circuit 4 and an increase in capacitor capacity (connecting two capacitors 2a and 2b in series), which increases the size of the power conversion device.

[0075] Therefore, in order to minimize the increase in the volume of the power conversion device capable of 3-level operation and to minimize the loss of the power conversion device, the 2-level operation and the 3-level operation are switched according to the current value of the power conversion device. That is, the 3-level operation is used when the current threshold is frequently used, and the 2-level operation is set in the current region larger than the threshold. As a result, only the current below the specified current threshold flows through the switch circuit 4, so the size of the switch elements 4a~4f generally determined by the current amount can be reduced, and the large increase in the volume of the power conversion device can be suppressed.

[0076] Actually, regarding the amount of loss in the case of application to an electric vehicle, it is expressed by the fuel consumption rate in the WLTC (Worldwide-harmonized Light vehicles Test Cycle) mode, which is an international test method (a mode that constitutes each driving mode such as an urban mode, a suburban mode, and a highway mode based on the average usage time distribution). In most of the time specified in the WLTC mode, a region sufficiently smaller than the performance limit torque of the motor is used. That is, in order to improve the maximum WLTC mode fuel consumption rate (loss) with a minimum increase in the volume of the power conversion device, the switching level operation is performed such that the three-level operation is carried out only in the current region below the majority of the time specified in the WLTC mode.

[0077] Specifically, Figure 5 is a graph showing time-series data in which, for convenience, the vertical axis of the WLTC mode driving pattern is replaced with the current value and the horizontal axis is set to time. In Figure 5 the minimum value, A value, B value, and maximum value (minimum value < A value < B value < maximum value) are shown as the current values for the switching level operation.

[0078] Figure 6 represents an example of the total loss when the WLTC mode driving has been completed with the current values for performing the level operation switching changed to Figure 5 the entire region, A value, and B value.

[0079] Figure 7 Similarly to Figure 6 it represents an example of the volume of the power conversion device when the current values for performing the level operation switching are changed to Figure 5 the entire region, A value, and B value.

[0080] In Figure 6 and Figure 7 Condition 1 is the case where two-level operation is performed in all current regions. Although the loss of the power conversion device shown in Figure 6 is large, the switching circuit 4 is not required, so the volume of the power conversion device shown in Figure 7 is small.

[0081] Condition 2 is the case where three-level operation is performed in the region where the current is from 0 value to A value (A value is the upper limit value of the current occupied in most of the time in the WLTC mode driving pattern and is greater than 0 value) and two-level operation is performed in the region where the current is above A value. Since three-level operation is performed in most of the time compared to Condition 1, the loss of the power conversion device shown in Figure 6 is significantly improved. Due to the addition of the switching circuit 4, Figure 7The volume of the power conversion device shown increases.

[0082] Condition 3 is a case where three-level operation is performed in a region where the current is from 0 to B (A < B), and two-level operation is performed in a region where the current is equal to or greater than B. Compared with Condition 2, the time for three-level operation does not change significantly. Therefore, compared with Condition 2 Figure 6 The loss of the power conversion device shown is slightly improved. On the other hand, since the current flowing through the switching circuit 4 increases and the switching circuit 4 becomes larger, therefore Figure 7 The volume of the power conversion device shown increases.

[0083] Condition 4 is a case where three-level operation is performed in all current regions, and the Figure 6 loss improvement effect of the power conversion device shown is the largest. However, compared with Condition 2, there is also a slight degree of loss improvement. On the other hand, since the maximum current corresponding to the maximum torque of the motor 7 flows through the switching circuit 4 and the switching circuit 4 becomes larger, therefore Figure 7 The volume of the power conversion device shown increases to the maximum extent.

[0084] As described above, considering the relationship between the amount of loss reduction of the power conversion device and the amount of increase in the volume of the power conversion device, for example, the current threshold for switching the level operation is set to the value A as in Condition 2. Alternatively, conversely, the upper limit current value (level switching threshold) of the three-level operation can be determined according to the volume of the switching element of the switching circuit 4. The control circuit 8 switches between the two-level operation and the three-level operation based on such a predetermined current value.

[0085] In addition, according to the rotational speed of the motor 7, the ratio of the switching loss, conduction loss, and recovery loss in the loss (inverter loss) of the power conversion device changes. Therefore, regarding the switching of the operation level, it can also be determined according to the motor operating point instead of the current value.

[0086] That is, the losses of the power conversion device and the motor in the 2-level operation and the 3-level operation and the volume of the power conversion device are estimated based on the torque command, the speed command and the voltage of the DC voltage source, thereby determining the threshold of the operation level switching on the speed-torque map (NT map) representing the speed and torque characteristics of the motor. In addition, any method can be used for the loss estimation method, for example, a mathematical formula for calculating the loss of the inverter circuit in the 2-level operation and the 3-level operation (selecting the gate resistance value Rgoff at the time of disconnection so that the surge voltage is the same at each operation level) based on the torque command or the speed command can be used, or an operation table prepared in advance based on measured data can also be used. In the case of estimating the inverter loss, the motor phase current, the modulation rate of the switching operation of the inverter circuit 3, the carrier frequency, and the power factor are calculated based on the torque command and the speed command of the motor, and the inverter loss in the 2-level operation and the 3-level operation can be calculated based on these values, the switching loss (single pulse) data of each gate resistance value Rgoff at the time of disconnection, and the detected voltage of the DC voltage source.

[0087] Alternatively, the switching circuit 4 may be set to a volume (size) corresponding to the maximum current in the motor specifications, and only the loss reduction may be considered. Based on the total loss of the inverter circuit 3 during 2-level operation and 3-level operation calculated as described above, the control circuit 8 may switch the level operation in such a manner as to select the one with the smaller total loss between the 2-level operation and the 3-level operation at any time.

[0088] [Change in switching speed of power conversion device]

[0089] In this embodiment, in addition to the switching of the operation level as described above, the switching speed of the switching element is changed to further improve the loss. Specifically, the loss is improved by switching the gate resistance value Rgoff when the switching element is turned off.

[0090] In a range where a surge voltage generated when the switching element is turned off does not exceed the element withstand voltage of the switching element, the switching speed can be increased by adjusting the gate resistance value Rgoff when the switching element is turned off, thereby reducing the switching loss.

[0091] Generally, in a system where input / output operating conditions (current, voltage, temperature, etc.) change moment by moment, the gate resistance value is adjusted so that the surge voltage does not exceed the allowable voltage under the worst condition within the operating range.

[0092] In the present embodiment, even in an environment where input / output operating conditions vary, the gate resistance value at the time of OFF is switched to minimize loss while monitoring the surge voltage.

[0093] Specifically, for each fundamental wave cycle of the AC output of the power conversion device, the maximum surge voltage within the cycle is detected to confirm whether the maximum surge voltage falls within the range (VY~VX) between the allowable upper surge limit voltage VY determined by design factors such as the withstand voltage, deviation, and voltage detection accuracy of the switching element and the allowable lower surge limit voltage VX set to a certain maximum surge voltage target range relative to the allowable upper surge limit voltage VY.

[0094] When the maximum surge voltage is within the range from the allowable surge lower limit voltage VX to the allowable surge upper limit voltage VY, it is determined that the optimum gate resistance value Rgoff at the time of OFF is selected, and the gate resistance value Rgoff at the time of OFF is not changed.

[0095] On the other hand, when the maximum surge voltage is lower than the allowable surge lower limit voltage VX, it is determined that there is room for further loss improvement, and the gate resistance value Rgoff during off is reduced by one level, that is, the switching speed is set to be one level faster.

[0096] On the other hand, when the maximum surge voltage is equal to or higher than the allowable surge upper limit voltage VY, there is a concern that the switching element may fail if the allowable surge upper limit voltage VY is exceeded, so the gate resistance value Rgoff at the time of disconnection is increased by one level, that is, the switching speed is set to be one level slower.

[0097] In addition, in order to more reliably eliminate the concern about the failure of the switching element, the gate resistance value Rgoff when turned off may be set to the maximum value of the settable range instead of changing it to level 1. In addition, in order to eliminate the above concern more quickly, the "determination of whether the maximum surge voltage is greater than the allowable surge upper limit voltage VY" may be implemented in a control cycle with a cycle shorter than the fundamental wave cycle of the AC output, rather than being implemented for each fundamental wave cycle of the AC output.

[0098] Here, the gate resistance Rgoff can be set as described above. Figure 2 In addition, the gate resistance value Rgoff at the time of disconnection is changed step by step, but for example, when the maximum surge voltage is significantly lower than the allowable surge lower limit voltage VX, it can also be changed in two or three steps according to the deviation amount. In addition, the gate resistance value Rgoff at the time of disconnection can be calculated and set based on the switching speed (di / dt) and switching element characteristics required in terms of the relationship between the input voltage and the load operating point.

[0099] The change in switching speed for minimizing switching loss described above is not limited to being achieved by varying the gate resistance value Rgoff during off-state operation, but may also be achieved by varying the gate voltage, varying the buffer capability (current supply amount), or the like.

[0100] Regarding the variable gate voltage, Figure 2 The power supply voltage of the disconnection power supply 15 shown is set as a variable structure. If the surge voltage generated at both ends of the switching element or both ends of the plurality of capacitors has a margin relative to the allowable surge voltage, the disconnection power supply 15 is changed to the high voltage side. Regarding the variable structure of the disconnection power supply 15, for example, there is the following method: based on the instruction information from the control circuit 8, a desired power supply voltage is selected from a plurality of different power supply voltages prepared by a switch.

[0101] Regarding the change of buffer capacity (current supply amount), for example, Figure 2 The number of stages of the buffer circuit 11 is set as a variable structure, and if the surge voltage generated at both ends of the switching element or both ends of the plurality of capacitors has a margin relative to the allowable surge voltage, the number of stages of the buffer circuit 11 is increased. Fig.15 As shown in the figure, the buffer circuit 11 is configured as follows: the buffer circuit 11 is composed of a plurality of buffer circuits 11a, 11b, 11c, ..., 11N, and the switches SW1, SW2, SW3, ... of the buffer circuits 11a, 11b, 11c, ... are turned on / off. Then, based on the instruction information from the control circuit 8, the switch a or the switch b is turned on / off, thereby switching to a desired number of buffer circuit stages. For example, in Fig.15 In the case of , if switch a is turned off and switch b is turned on among all switches SW1, SW2, SW3, ..., the buffer circuit 11N of one stage is selected. Also, if switch a is turned on and switch b is turned off among all switches SW1, SW2, SW3, ..., the buffer circuits 11a, 11b, 11c, ..., 11N of the largest number of stages are selected.

[0102] Here, as a method of monitoring the maximum surge voltage within a period, for example, an A / D converter mounted on a microcomputer or the like may be used to utilize a high-speed sampling and sample-hold function.

[0103] Alternatively, the control voltage corresponding to the voltage detected analogously from the capacitors 2a and 2b may be charged into a separately provided control capacitor (discharged after being used for detection of the maximum surge voltage and determination of selection of the gate resistance value Rgoff).

[0104] Furthermore, the timing for determining the calculation of the maximum surge voltage in one cycle may be determined based on the phase of the phase current or the current detection value.

[0105] Here, in order to minimize the loss in the 3-level operation, the switching speed is increased (the gate resistance value Rgoff is set to a small value) until the maximum surge voltage generated at both ends of the switching element becomes within the range from the allowable surge lower limit voltage VX to the allowable surge upper limit voltage VY. If the operation is switched to the 2-level operation, the voltage applied to the switching element is doubled. Therefore, the maximum surge voltage generated at both ends of the switching element exceeds the allowable surge upper limit voltage VY, and there is a concern that the switching element may fail.

[0106] Therefore, in this embodiment, it is characterized in that the gate resistance value at the time of disconnection is changed to a large value before switching from 3-level operation to 2-level operation, thereby suppressing the surge voltage generated at both ends of the switching element, preventing the failure of the switching element caused by the surge voltage and minimizing the loss of the power conversion device.

[0107] [Control of power conversion device]

[0108] Figure 8 This is an operational conceptual diagram showing the characteristics of the control of the power conversion device according to the present embodiment.

[0109] based on Figure 8 The operation for switching the operation level of the power conversion device and switching the gate resistance value Rgoff when turned off will be described.

[0110] In this embodiment, the switching of the operation level and the switching of the gate resistance value Rgoff are performed at the control interval of the fundamental wave period of the output current of the power conversion device. Figure 8 A1 shows the U-phase current Iu of the inverter circuit 3, and the switching of the operation level and the switching of the gate resistance value Rgoff are performed in the peak region of the U-phase current Iu.

[0111] also, Figure 8 The switching of the operating level and the switching of the gate resistance value Rgoff are explained for the U-phase current Iu of the power conversion device, but the same is true for the V-phase current Iv and the W-phase current Iw of the power conversion device, and their explanation is omitted.

[0112] Figure 8 A2 is a diagram for explaining switching between the 3-level operation and the 2-level operation.

[0113] exist Figure 8 In A2, the level switching threshold when switching from the 3-level operation to the 2-level operation is set to Lvth3-2, and the level switching threshold when switching from the 2-level operation to the 3-level operation is set to Lvth2-3.

[0114] like Figure 8As shown in A2 of FIG. 1 , when a current command value (effective value) Iu(rms)* of the power conversion device is provided, when a 3-level operation is currently being performed, the power conversion device is judged to be operated in a 2-level operation or a 3-level operation based on a comparison between the current command value Iu(rms)* and a predetermined level switching threshold value Lvth3-2. In addition, when a 2-level operation is currently being performed, the power conversion device is judged to be operated in a 3-level operation or a 2-level operation based on a comparison between the current command value Iu(rms)* and a predetermined level switching threshold value Lvth2-3.

[0115] exist Figure 8 The example of A2 shows the following situation: currently a 3-level operation is performed, and based on the comparison between the current command value Iu(rms)* and the level switching threshold Lvth3-2, the power conversion device is switched from the 3-level operation to the 2-level operation.

[0116] like Figure 8 As shown in A2, when the current command value Iu(rms)* crosses the level switching threshold Lvth3-2, it is judged to be changed from 3-level action to 2-level action (the upward arrow of the solid line D indicates the switch from 3-level action to 2-level action. In addition, in the solid line D, "low" indicates 3-level action and "high" indicates 2-level action).

[0117] Furthermore, when it is determined that the 3-level operation is to be changed to the 2-level operation, first, Figure 8 As shown in A4 of FIG. 1, the gate resistance value at the time of disconnection (in Figure 8 The gate resistance value Rgoff16) is changed to the maximum value in the settable range (in Figure 8 Specifically, from Figure 2 The gate resistance value Rgoff16 realized by turning on all the switches SW2 to SW5 in the gate resistance switching circuit 10 is changed to the gate resistance value Rgoff1 realized by turning off all the switches SW2 to SW5. Here, Rgoff1>>Rgoff16.

[0118] Next, the gate resistance value Rgoff at the time of off is changed to the maximum value (at Figure 8 After that, the gate voltage slope is relaxed, the gate current is reduced, or the surge voltage is reduced when the switching element is turned off, thereby confirming that the gate resistance value Rgoff when turned off actually changes to a large value.

[0119] Next, after confirming the change corresponding to the result of changing the gate resistance value Rgoff when the switching element is turned off to the maximum value (such as the change of the gate voltage slope relaxation), as shown in FIG. Figure 8 As shown in A3, after time E, the operation level of the power conversion device is changed from 3-level operation to 2-level operation.

[0120] In this way, before the operation level is switched from the 3-level operation to the 2-level operation, the gate resistance value Rgoff at the time of OFF is changed from a small value to a large value.

[0121] That is, in the 3-level operation, a relatively small gate resistance value at the time of OFF is selected which is adjusted so that the maximum surge voltage is approximately equal to the allowable surge voltage ( Figure 8 In the case of Rgoff16), the voltage applied to both ends of the switching element of the inverter circuit 3 when changing to a two-level operation is doubled, thereby exceeding the allowable surge voltage (used by Figure 8 However, by performing control as in this embodiment, it is possible to prevent the failure of the switching element and minimize the loss.

[0122] Here, Figure 8 The thin solid line of A5 represents the voltage (instantaneous value) Va between the switching elements 3a, and the thick solid line represents the maximum voltage (maximum voltage between the arms) Vmaxa which maintains the maximum value of the voltage Va between the switching elements 3a.

[0123] Likewise, Figure 8 The thin solid line of A6 represents the voltage (instantaneous value) Vb between the switching elements 3b, and the thick solid line represents the maximum voltage (maximum voltage between the arms) Vmaxb which maintains the maximum value of the voltage Vb between the switching elements 3b.

[0124] The maximum values ​​of the voltages Vmaxa and Vmaxb between the arms can be realized by, for example, maintaining the maximum values ​​of the voltages (instantaneous values) Va and Vb using software in the control circuit 8, or by charging the maximum voltages (instantaneous values) Va and Vb into the capacitors using capacitors (hardware). In addition, the maximum values ​​of the voltages Vmaxa and Vmaxb between the arms are reset to zero at the same time as the operation level is switched.

[0125] in addition, Figure 8 A7 represents the on / off operation of the switch elements 3a, 3b, 4a, and 4b.

[0126] exist Figure 8In the description of , the judgment on the switching of the operation level is implemented based on the current command value Iu(rms)*, but the judgment standard calculated based on the table prepared in advance corresponding to the motor speed or required torque may be used instead of the current command value Iu(rms)*. In addition, it is also possible to determine based on the loss calculation results in the 2-level operation and the 3-level operation according to the motor speed or torque.

[0127] In this embodiment, whether to switch the action level is determined by comparing the current command value Iu (rms) * with the level switching threshold Lvth3-2 during 3-level action, and whether to switch the action level is determined by comparing Iu (rms) * with the level switching threshold Lvth2-3 during 2-level action. In this case, for each level switching threshold, (level switching threshold Lvth3-2)>(level switching threshold Lvth2-3). By providing hysteresis between the level switching thresholds Lvth3-2 and Lvth2-3 according to the current action level, frequent action level changes can be avoided.

[0128] Furthermore, it has been described so far that the current lower than the level switching threshold is set to 3-level operation and the current above the level switching threshold is set to 2-level operation in order to minimize the volume (size) of the power conversion device according to the current value, but without considering the volume (size) of the power conversion device, the current lower than the level switching threshold may be set to 2-level operation and the current above the level switching threshold may be set to 3-level operation. This can suppress the surge voltage in the current peak region of the sine wave where the surge voltage becomes large, thereby reducing the gate resistance value when disconnecting in the large current region, and achieving further low loss.

[0129] [Specific control flow chart of the power conversion device]

[0130] Fig. 9 , Fig.10 , Fig.11 An example of a specific control flow chart of the power conversion device of the present embodiment is shown and described below. In addition, in the description here, an example of the control of the power conversion device that can switch between 2-level operation and 3-level operation in two stages is described, and the control flow chart is implemented according to each fundamental wave cycle of the AC output of the power conversion device.

[0131] exist Fig. 9 In the control process, when the control process is implemented by "start", in step S1, based on the above-mentioned action conditions, it is determined whether the current action level is a 2-level action or a 3-level action. In addition, in step S1, the maximum value of the surge voltage in the fundamental wave period of the AC output is detected. That is, the detection Figure 8The arm voltage maximum values ​​Vmaxa and Vmaxb of A5 and A6 are indicated by thick solid lines.

[0132] In step S2, in order to confirm whether it is time to change the action level from 3-level action to 2-level action, first determine whether the previous action level was 3-level action. If the previous action level was 3-level action ("yes"), execute step S3. If the previous action level was 2-level action ("no"), execute Fig.11 Step S4.

[0133] exist Fig.11 In step S4, since the previous action level is a 2-level action, there is no concern that the surge voltage when the action level is changed will exceed the permissible surge upper voltage VY, and the optimization control of the gate resistance value when disconnected is continued. That is, in step S4, it is confirmed whether the maximum value of the surge voltage converges to the range from the permissible surge lower voltage VX to the permissible surge upper voltage VY. If it converges to the range from the permissible surge lower voltage VX to the permissible surge upper voltage VY ("Yes"), the optimal gate resistance value Rgoff when disconnected is selected, and the current gate resistance value Rgoff when disconnected is maintained (step S19), so that the action is performed at the current action level determined in step S1 (step S20), and the cycle ends.

[0134] On the other hand, if the maximum surge voltage value does not converge to the range from the allowable surge lower limit voltage VX to the allowable surge upper limit voltage VY in step S4 (in the case of "No"), it is determined whether the maximum surge voltage value is less than the allowable surge lower limit voltage VX or greater than the allowable surge upper limit voltage VY. That is, in step S21, it is confirmed whether the maximum surge voltage value is less than the allowable surge lower limit voltage VX. If the maximum surge voltage value is less than the allowable surge lower limit voltage VX ("Yes"), it is determined that there is room for further improvement in loss, and the gate resistance value Rgoff at the time of disconnection is reduced. However, if the gate resistance value Rgoff at the time of disconnection is already set to the minimum value, it cannot be further minimized, so in step S22, it is confirmed whether the current gate resistance value Rgoff at the time of disconnection is set to the minimum value. If the gate resistance value Rgoff when disconnected is not the minimum in step S22 ("Yes"), the gate resistance value Rgoff when disconnected is reduced by one level (step S23) so that the operation is performed at the current operation level determined in step S1 (step S20), and the cycle ends.

[0135] On the other hand, when the gate resistance value Rgoff when disconnected in step S22 is the minimum value ("No"), the gate resistance value Rgoff when disconnected cannot be further reduced, so it is set to the same minimum value as the current value (step S24), so that the action is performed at the current action level determined in step S1 (step S20), and the cycle ends.

[0136] In the case of "No" in step S21, the maximum value of the surge voltage is greater than the allowable surge upper voltage VY, so there is a concern that the switching element will fail, so the gate resistance value Rgoff when disconnected is set large. However, if the gate resistance value Rgoff when disconnected is already set to the maximum value, it cannot be maximized further, so in step S25, it is confirmed whether the current gate resistance value Rgoff when disconnected is set to the maximum value. In the case that the gate resistance value Rgoff when disconnected is not the maximum in step S25 ("Yes"), the gate resistance value Rgoff when disconnected is increased by 1 level (step S26), so that the action is performed at the current action level determined in step S1 (step S20), and the cycle ends.

[0137] On the other hand, when the gate resistance value Rgoff at the time of disconnection is the maximum value in step S25 ("No"), the gate resistance value Rgoff at the time of disconnection cannot be further increased, so it is set to the same maximum value as the current value (step S27), so that the operation level determined in step S1 is performed this time (step S20), and the cycle ends. In addition, since the gate resistance value Rgoff at the time of disconnection is already the maximum value and is in a state exceeding the allowable surge upper limit voltage VY, in order to prevent the failure of the switching element, countermeasures such as notifying this state to the upper system or limiting the output power (current) may be taken.

[0138] Here, return to Fig. 9 In step S3, since the previous action level was 3-level action (step S2), in order to confirm whether it is time to change from 3-level action to 2-level action, it is necessary to confirm whether the current action level is 2-level action. That is, in step S3, if the current action level is 2-level action ("yes"), then step S5 is executed; if the current action level is 3-level action ("no"), then step S6 is executed. Fig.10 Step S9.

[0139] exist Fig.10In step S9, the previous action level and the current action level are both 3-level actions, so there is no concern about the failure of the switching element caused by the surge voltage when the action level is switched, and the optimization control of the gate resistance value at the time of disconnection is continued. That is, in step S9, it is confirmed whether the maximum value of the surge voltage converges to the range from the allowable surge lower limit voltage VX to the allowable surge upper limit voltage VY. In the case of converging to the range from the allowable surge lower limit voltage VX to the allowable surge upper limit voltage VY ("Yes"), the optimal gate resistance value Rgoff at the time of disconnection is selected, and the current gate resistance value Rgoff at the time of disconnection is maintained (step S10). As determined in step S1, the operation is also performed in a 3-level operation this time (step S11), and the cycle ends.

[0140] On the other hand, in step S9, when the maximum value of the surge voltage does not converge to the range from the allowable surge lower limit voltage VX to the allowable surge upper limit voltage VY ("No"), in step S12, it is determined whether the maximum value of the surge voltage is less than the allowable surge lower limit voltage VX or greater than the allowable surge upper limit voltage VY. That is, in step S12, it is confirmed whether the maximum value of the surge voltage is less than the allowable surge lower limit voltage VX. If the maximum value of the surge voltage is less than the allowable surge lower limit voltage VX ("Yes"), it is determined that there is room for further improvement in loss, and the gate resistance value Rgoff at the time of disconnection is reduced. However, if the gate resistance value Rgoff at the time of disconnection is already set to the minimum value, it cannot be further minimized, so in step S13, it is confirmed whether the current gate resistance value Rgoff at the time of disconnection is set to the minimum value.

[0141] If the gate resistance value Rgoff at the time of turning off is not the minimum in step S13 (Yes), the gate resistance value Rgoff at the time of turning off is reduced by one level (step S14) so ​​that the three-level operation (step S11) is continued, and this cycle ends.

[0142] On the other hand, when the gate resistance value Rgoff is the minimum value when disconnected in step S13 ("No"), the gate resistance value Rgoff cannot be further reduced, so it is set to the same minimum value as the current value (step S15), so that the 3-level action continues (step S11), and the cycle ends.

[0143] In step S12, when the maximum value of the surge voltage is greater than the allowable surge upper limit voltage VY ("No"), there is a concern that the switching element may fail, so the gate resistance value Rgoff when disconnected is set large. However, if the gate resistance value Rgoff when disconnected is already set to the maximum value, it cannot be further maximized, so in step S16, it is confirmed whether the current gate resistance value Rgoff when disconnected is set to the maximum value. In step S16, when the gate resistance value Rgoff when disconnected is not the maximum value ("Yes"), the gate resistance value Rgoff when disconnected is increased by 1 level (step S17), so that the 3-level operation (step S11) continues, and the cycle ends.

[0144] On the other hand, when the gate resistance value Rgoff at the time of disconnection is the maximum value in step S16 ("No"), the gate resistance value Rgoff at the time of disconnection cannot be further increased, so it is set to the same maximum value as the current value (step S18), so that the operation level determined in step S1 is performed this time (step S11), and the cycle ends. In addition, since the gate resistance value Rgoff at the time of disconnection is already the maximum value and is in a state exceeding the allowable surge upper limit voltage VY, in order to prevent the failure of the switching element, countermeasures such as notifying this state to the upper system or limiting the output power (current) may be taken.

[0145] Back to Fig. 9 In step S5, since the previous operation level is 3-level operation ("Yes" in step S2) and the current operation level is 2-level operation ("Yes" in step S3), if the gate resistance value Rgoff adjusted to the optimum in the 3-level operation is used for the 2-level operation, there is a concern that an excessive surge voltage will be generated at both ends of the switching element. Therefore, in step S5, the gate resistance value Rgoff at the time of disconnection is set to the maximum value.

[0146] Here, if switching to 2-level operation is performed simultaneously with the change in gate resistance value Rgoff during disconnection, switching operation is performed in 2-level operation before switching of gate resistance value Rgoff is completed, and excessive surge voltage is generated between switching elements, which may cause failure of the switching elements.

[0147] Therefore, switching to the two-level operation is not performed until the switching of the gate resistance value Rgoff is completed.

[0148] In step S6, the switching speed of the switch SW of the gate resistance switching circuit 10 is taken into consideration, and the processing is put on hold until a time (for example, 1 us) sufficient to complete the switching operation has elapsed, after which the process moves to step S7.

[0149] In step S7 , the switching speed of the previous switching operation when the switch is turned off is compared with the switching speed of the current switching operation when the gate resistance value Rgoff is maximized to check whether the switching speed has become slower by a certain value or more.

[0150] In step S7 , when the switching speed is slowed down by a certain value or more (YES), it is determined that the gate resistance value Rgoff has been changed to the maximum value, and the process moves to step S8 to switch to the two-level operation.

[0151] On the other hand, in step S7, when the switching speed does not slow down by more than a certain value ("No"), it is determined that the gate resistance value Rgoff has not yet changed to the maximum value, and the determination of step S7 is continued after a certain delay in step S6 before the gate resistance value Rgoff is transferred to the maximum value.

[0152] Furthermore, when the gate resistance value Rgoff at the time of off is already the maximum in the previous switching operation, the gate resistance value Rgoff cannot be increased further, so the switching speed at off is not compared, and the process moves to step S8 to switch to the two-level operation.

[0153] In addition, in step S7, the completion of the switching of the gate resistance value Rgoff at the time of disconnection is determined based on the change in the switching speed at the time of disconnection, but other methods may be used as long as it can be confirmed that the gate resistance value Rgoff is reliably switched. For example, it may be determined that the switching is reliably performed based on the following situations: the slope of the gate voltage applied to the gate terminal of the switching element changes by a certain value or more after the switching speed change instruction, or the gate current of the switching element changes by a certain value or more, or the maximum value of the surge voltage generated at both ends of the switching element or at both ends of a plurality of capacitors changes by a certain value or more.

[0154] By switching the operation level and the gate resistance value at the time of OFF through the control flow described above, it is possible to achieve control to minimize loss within a range where the maximum surge voltage does not exceed the allowable surge voltage.

[0155] In the above description, a method is described in which the control circuit 8 switches between 2-level operation and 3-level operation in a manner that minimizes the loss of the power conversion device, and switches the gate resistance value when disconnected, but it is also possible to further switch between 2-level operation and 3-level operation in a manner that minimizes the total loss including the power conversion device and the motor, and switch the gate resistance value when disconnected.

[0156] In addition, in addition to switching between 2-level operation and 3-level operation and switching of the gate resistance value when disconnected, the control of the carrier frequency used to control the operation of the inverter circuit can also be changed. As mentioned above, in 3-level operation, the motor iron loss is reduced due to improved current distortion. If the carrier frequency is lowered, although the motor iron loss increases due to increased current distortion, the loss of the power conversion device decreases, so the overall loss can be reduced according to the conditions. Therefore, when the speed command is the same, the carrier frequency during 3-level operation can also be set to be lower than the carrier frequency during 2-level operation. That is, when the carrier frequency during 2-level operation is set to fx_2lv and the carrier frequency during 3-level operation is set to fx_3lv, the carrier frequency is set in a manner that satisfies fx_2lv≥fx_3lv.

[0157] Fig.12 The 2-level operation and 3-level operation of the power conversion device (inverter circuit) and the carrier frequency are schematically mapped to the speed and torque characteristics of the motor. When the speed command of the motor is the same, the control circuit 8 switches to 2-level operation when the torque command (or current command) is above a predetermined threshold, and switches to 3-level operation when it is less than the predetermined threshold. Here, the predetermined threshold is, for example, a threshold determined in advance based on the estimated results of the loss and volume of the power conversion device as described above. In addition, Fig.12 In the example shown, there is one threshold value, but multiple threshold values ​​may be set to perform hysteresis control in a manner that stabilizes the operation. For example, the threshold value for switching between the 2-level operation and the 3-level operation according to the torque command is set to be different between the case where the torque command increases and the case where the torque command decreases. In addition, by making the threshold value in the case of increase higher than the threshold value in the case of decrease, it is possible to prevent unnecessary switching between the 2-level operation and the 3-level operation, and the operation becomes stable.

[0158] In addition, Fig.12 In the action mapping diagram shown, the carrier frequency is also changed according to the motor speed command. Regarding the setting of the carrier frequency, the current distortion of the motor becomes smaller during 3-level operation, so the high-order harmonic iron loss becomes less than during 2-level operation. The switching loss of the inverter circuit is proportional to the switching operation frequency. Therefore, when the frequency is reduced, although it is in a trade-off relationship with the high-frequency iron loss of the motor, it can be used to reduce the inverter loss. In this way, the carrier frequency is an opposite parameter for the inverter circuit and the motor, and it needs to be set to minimize the total loss of the inverter circuit and the motor while ensuring controllability. Usually in the high speed area, the high-order harmonic iron loss of the motor dominates the loss in the motor system, so the carrier frequency can also be increased as the speed increases. Therefore, in Fig.10In the example shown, the carrier frequency is changed in three levels according to the rotation speed, f1_3lv <f2_3lv<f3_3lv。

[0159] Furthermore, the losses of the inverter circuit and the motor in the 2-level operation and the 3-level operation may be calculated using not only the torque command or the speed command but also other parameters. For example, in addition to the torque command or the speed command, an action table corresponding to at least one of the voltage of the DC voltage source and the temperature of the power conversion device may be maintained using the voltage of the DC voltage source and the temperature of the power conversion device, and the losses of the power conversion device and the motor may be calculated based on the action table.

[0160] [Structure of other power conversion devices]

[0161] exist Figure 1 In the power conversion device shown in the figure, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having an anti-parallel diode between the source and the drain is used as the switch circuit 4 provided for performing a three-level operation, but a Fig.13 As shown, a switch circuit 4B has a structure using a reverse blocking type IGBT (Insulated Gate Bipolar Transistor).

[0162] Fig.13 The switching circuit 4B of the power conversion device shown has switching elements 14a, 14b, 14c, 14d, 14e, and 14f which are reverse blocking type IGBTs. Moreover, the switching element 14a and the switching element 14b, the switching element 14c and the switching element 14d, and the switching element 14e and the switching element 14f are respectively connected in reverse parallel. One end of the switching circuit 4B is connected to the first connection point of the capacitor series circuit 2, and the other end is connected to the second, third, and fourth connection points, respectively. In addition, 16a, 16b, 16c, 16d, 16e, and 16f represent the gate input parts of the switching elements 14a, 14b, 14c, 14d, 14e, and 14f. In addition, other structures are the same as Figure 1 The same is true for the power conversion device.

[0163] In such Fig.13 The power conversion device thus constructed can also play a role similar to Figure 1 The same action and effect as the power conversion device.

[0164] [Effects of Embodiment 1]

[0165] As described above, according to the first embodiment, there are:

[0166] A capacitor series circuit has a plurality of capacitors connected in series, with both ends connected to the ends of a DC voltage source;

[0167] An inverter circuit is formed by connecting a plurality of branches formed by connecting a plurality of switching elements in series in parallel, wherein a DC input end is connected to both ends of the capacitor series circuit, and an AC output end is connected to a load;

[0168] a switching circuit having a plurality of switching elements, one end of which is connected to connection points of the plurality of capacitors and the other end of which is connected to a plurality of connection points of the switching elements of the inverter circuit; and

[0169] a control circuit, controlling the inverter circuit and the switch circuit,

[0170] The inverter circuit can perform a two-level operation by turning off the switch element included in the switch circuit, and can perform a three-level operation by turning on / off the switch element included in the switch circuit.

[0171] The control circuit changes the switching speed of the switching element of the inverter circuit and the switching circuit when the operation level is switched between the two-level operation and the three-level operation.

[0172] Therefore, it is possible to provide a power conversion device in which there is no risk of failure of the switching element even when the operation level is switched.

[0173] Furthermore, since the control circuit slows down the switching speed of the switching element when changing from the three-level operation to the two-level operation, the surge voltage can be brought within the allowable range, and there is no risk of failure of the switching element.

[0174] Furthermore, the control circuit changes the switching speed of the switching element before switching the operation level between the three-level operation and the two-level operation, so that the surge voltage can be reliably brought within the allowable range without the possibility of failure of the switching element.

[0175] Furthermore, the control circuit switches the operation level between the 3-level operation and the 2-level operation after waiting for a certain period of time after the switching speed change instruction of the switching element, thereby reliably making the surge voltage converge within the allowable range without worrying about the switching element malfunctioning.

[0176] Furthermore, since the control circuit determines the switching speed change process based on the change in the switching speed of the switching element after the switching speed change instruction of the switching element, the surge voltage can be reliably brought within the allowable range.

[0177] Furthermore, the control circuit determines the switching speed change process based on the change in the slope of the gate voltage applied to the gate terminal of the switching element after the switching speed change instruction of the switching element, and thus the surge voltage can be reliably brought within the allowable range.

[0178] Furthermore, the control circuit determines the switching speed change process based on the fact that the gate current of the switching element changes after the switching speed change instruction of the switching element, so that the surge voltage can be reliably brought within the allowable range.

[0179] Furthermore, the control circuit determines the switching speed change process based on the fact that the surge voltage generated at both ends of the switching element or at both ends of the capacitor series circuit changes after the switching speed change instruction of the switching element, thereby reliably making the surge voltage converge within the allowable range.

[0180] Furthermore, by setting the level switching threshold when changing from the 2-level operation to the 3-level operation and the level switching threshold when changing from the 3-level operation to the 2-level operation to different values ​​to provide hysteresis, frequent operation level changes can be avoided.

[0181] Furthermore, the control circuit changes the switching speed of the switching element based on the detection value of the surge voltage generated at both ends of the switching element or at both ends of the capacitor series circuit, and thus the surge voltage can be reliably brought within the allowable range.

[0182] In addition, the control circuit changes the switching speed of the switching element in such a way that the maximum value of the detected value of the surge voltage generated at both ends of the switching element or at both ends of the capacitor series circuit converges to the target allowable voltage range, thereby reliably making the surge voltage converge within the allowable range.

[0183] Furthermore, since the control circuit changes the switching speed based on a plurality of consecutive detection values ​​of the surge voltage, the surge voltage can be reliably brought within the allowable range.

[0184] Furthermore, the control circuit switches between the two-level operation and the three-level operation based on a comparison between the AC output current value of the power conversion device and a preset current threshold value, and thus the operation level can be switched appropriately.

[0185] Furthermore, the control circuit switches the operating level and changes the switching speed for each fundamental wave period of the AC output current of the power conversion device, and thus can appropriately switch the operating level and change the switching speed.

[0186] Furthermore, since the level switching threshold for switching between the two-level operation and the three-level operation is determined according to the volume of the switch element of the switch circuit, the operation level can be switched appropriately.

[0187] In addition, as the load connected motor, the control circuit determines the switching of the action level and the switching speed based on the command information of the motor and the power conversion device and the detection information of the motor and the power conversion device, according to a pre-prepared table or calculation results, so that the action level can be switched and the switching speed can be changed appropriately.

[0188] In addition, here, "command information of the motor and the power conversion device" refers to "torque command or speed command of the motor, current command of each phase of the power conversion device (Iu (rms) *, Iu *, etc.)", etc. In addition, "detection information of the motor and the power conversion device" refers to "the speed of the motor, the current of each phase of the power conversion device (Iu, etc.), the switching modulation rate of the switching element, the gate voltage of the switching element, the bus voltage of the power conversion device, the surge voltage, the temperature", etc.

[0189] Furthermore, since the control circuit changes the gate resistance value when the switching element is turned off to achieve the change in the switching speed of the switching element, the switching speed of the switching element is appropriately changed.

[0190] Implementation method 2.

[0191] Next, a power conversion device according to Embodiment 2 will be described. The circuit block diagram of the power conversion device according to Embodiment 2 is similar to that of Embodiment 1. Figure 1 , Fig.13 The circuit block diagram of the power conversion device is the same as that of the first embodiment, but the control operation of the control circuit of the power conversion device in the second embodiment is different from that in the first embodiment.

[0192] Fig.14 The operation of the control circuit of the power conversion device according to the second embodiment is shown. The differences from the first embodiment are described below by referring to the control operation ( Figure 8 ) are used for explanation. In addition, the descriptions not specifically recorded are the same as those in Implementation 1.

[0193] In the first embodiment, the switching of the action level and the switching of the gate resistance value when disconnected are implemented at each fundamental wave cycle of the AC output of the power conversion device, but in the second embodiment, the switching of the action level and the switching of the gate resistance value when disconnected are implemented at a time interval shorter than the fundamental wave cycle of the AC output of the power conversion device. That is, the judgment of the action level is implemented in the first embodiment by comparing the AC output current command value (effective value) Iu (rms)* with the level switching threshold, but in the second embodiment, as shown in FIG. Fig.14 As shown in B1 and B2 of FIG. 1 , this is implemented by comparing the AC output current command value (instantaneous value) Iu* with the level switching thresholds Lvth3-2 and Lvth2-3.

[0194] In addition to the comparison between the AC output current command value (instantaneous value) Iu* and the level switching threshold, the detection current value Iu (average of multiple continuous detection values) and the level switching threshold may be used. The detection current value Iu (average of multiple continuous detection values) refers to, for example, the current flowing through the switching element (e.g. Figure 1 The detected value of the U-phase current Iu) is saved in each input cycle, for example, the value obtained by averaging the latest 10 saved values.

[0195] Here, regarding the selection of the action level, in embodiment 1, when the current command value (effective value) Iu (rms)* of the AC output is greater than the level switching threshold, a 2-level action is implemented in the entire area of ​​the AC output (sine wave), but in embodiment 2, it is performed by comparing the current command value (instantaneous value) Iu* of the AC output with the level switching threshold, and thus a 3-level action is implemented in the low current area of ​​the AC output (sine wave), thereby achieving further low loss of the power conversion device.

[0196] In addition, regarding the selection of the gate resistance value at the time of disconnection, in the first embodiment, it is determined in a manner that the surge voltage constraint is satisfied at the maximum current value of the AC output (sine wave), so that a surge voltage margin is generated in the current region other than near the maximum current value, leaving room for further loss reduction. In contrast, in the second embodiment, the gate resistance value at the time of disconnection is changed each time in a manner that the surge voltage constraint is satisfied in the entire region of the AC output (sine wave), so that a surge margin is not generated in the current region other than near the maximum current value, and further loss reduction is achieved. Here, satisfying the surge voltage constraint means that the surge voltage does not exceed the module withstand voltage of the switching element.

[0197] based on Fig.14 The operation for realizing the switching of the operation level and the switching of the gate resistance value at the time of OFF according to the second embodiment will be described.

[0198] like Fig.14 As shown in FIG. 1 , when a 3-level operation is currently being performed, the current command value (instantaneous value) Iu* of the power conversion device is compared with the predetermined level switching threshold Lvth3-2 to determine whether to perform a 2-level operation or a 3-level operation. Fig.14 As shown in B2 of FIG. 1 , when the current command value (instantaneous value) Iu* crosses the level switching threshold Lvth3-2, it is determined that the 3-level operation is to be changed to the 2-level operation (the upward arrow of the solid line D indicates the switching from the 3-level operation to the 2-level operation. In addition, in the solid line D, "low" indicates the 3-level operation and "high" indicates the 2-level operation). Furthermore, when it is determined that the 3-level operation is to be changed to the 2-level operation, first, as shown in FIG. Fig.14 As shown in B4 of FIG. 1 , the relatively small gate resistance value (gate resistance value Rgoff14) used in the 3-level operation is changed to the maximum value in the settable range (in Fig.14 where is the gate resistance value Rgoff1).

[0199] Next, the gate resistance value at the time of off is changed to the maximum value (at Fig.14 After that, by monitoring the gate voltage slope relaxation, gate current reduction, or surge voltage drop when the switching element is turned off, it is confirmed that the gate resistance value Rgoff when turned off actually changes to a large value.

[0200] Next, after confirming the change corresponding to the result of changing the gate resistance value Rgoff when the switching element is turned off to the maximum value (such as the change of the gate voltage slope relaxation), as shown in FIG. Fig.14 As shown in B3 of FIG. 1 , the action level is changed from 3-level action to 2-level action.

[0201] In this way, before the operation level is switched from the 3-level operation to the 2-level operation, the gate resistance value Rgoff at the time of OFF is changed from a small value to a large value.

[0202] Furthermore, in the second embodiment, the maximum surge voltage detection for selecting the gate resistance value at the time of disconnection is determined using the continuous detection values ​​of the surge voltage. Fig.14 As shown in B5, when the surge voltage detection value (maximum voltage between arms) Vmax is less than the allowable surge voltage VX, the surge surplus detection CNT (counter) value is incremented by +1, and when the surge surplus detection CNT value reaches the preset Rgoff switching threshold RZ, the gate resistance value Rgoff at the time of disconnection is changed in sequence. That is, Fig.14In the process, at the time point when the surge margin detection CNT value reaches the Rgoff switching threshold value RZ, for example, the gate resistance value is sequentially changed to Rgoff1, Rgoff2, Rgoff3, Rgoff4, Rgoff5, Rgoff6, etc.

[0203] In addition, Rgoff1>Rgoff2>Rgoff3>Rgoff4>···>Rgoff14>Rgoff15>Rgoff16.

[0204] By changing the gate resistance value Rgoff when the surge margin detection CNT value reaches the preset Rgoff switching threshold value RZ, the gate resistance value when the gate is turned off can be prevented from being frequently changed, thereby suppressing unstable gate resistance value fluctuations.

[0205] The other controls in the second embodiment are the same as those in the first embodiment, and thus the description thereof will be omitted.

[0206] In the second embodiment, based on the detection information of the motor and the power conversion device (phase current, phase current (torque) command value, speed detection value, modulation rate, gate voltage value, surge voltage value, temperature, etc.), the combination of the action level and the gate resistance at the time of disconnection that minimizes the loss while making the surge voltage converge to the allowable range can be calculated for each control cycle, and determined according to a table prepared in advance or loss calculation. In particular, in the second embodiment, the switching of the action level and the switching of the gate resistance value at the time of disconnection are performed at a relatively high speed, so a large effect can be obtained on reducing the loss.

[0207] In implementation mode 2, the switching of the action level and the switching of the gate resistance value when disconnected are implemented according to each AC output current detection cycle that is shorter than the fundamental wave cycle, for example, for controlling the AC output current. As a result, the switching of 2-level action and 3-level action and the switching of the gate resistance value when disconnected can also be implemented in the same cycle, which can achieve more powerful low loss while ensuring safety.

[0208] [Effects of Embodiment 2]

[0209] As described above, according to the second embodiment, the same effects as those of the first embodiment are achieved, and the following effects can be achieved.

[0210] That is, the control circuit implements the switching of the operation level and the change of the switching speed at a time interval shorter than the fundamental wave period of the AC output current of the power conversion device, so that the switching of the operation level and the change of the switching speed can be performed more reliably and appropriately.

[0211] [Hardware structure of control circuit]

[0212] In addition, as an example of hardware, Fig.16 As shown, the control circuit 8 in the first and second embodiments is composed of a processor 100 and a storage device 101. The storage device 101 includes a volatile storage device such as a random access memory (not shown) and a nonvolatile auxiliary storage device such as a flash memory.

[0213] In addition, a hard disk may be provided instead of a flash memory. The processor 100 executes a program input from the storage device 101. In this case, the program is input from the auxiliary storage device to the processor 100 via the volatile storage device. In addition, the processor 100 may output data such as calculation results to the volatile storage device of the storage device 101, or may store data in the auxiliary storage device via the volatile storage device.

[0214] [Other embodiments]

[0215] The present application describes various illustrative embodiments and examples, but various features, methods, and functions described in one or more embodiments are not limited to application in specific embodiments and can be applied to the embodiments alone or in various combinations.

[0216] Therefore, numerous modifications not shown in the examples are conceivable within the technical scope disclosed in the present application, including, for example, modifying, adding or omitting at least one structural element, and extracting at least one structural element and combining it with structural elements of other embodiments.

[0217] (Explanation of Reference Numerals)

[0218] 1: DC voltage source; 2: capacitor series circuit; 2a, 2b: capacitor; 3: inverter circuit; 3a, 3b, 3c, 3d, 3e, 3f: switching element (inverter circuit); 4, 4B: switching circuit; 4a, 4b, 4c, 4d, 4e, 4f: switching element (switch circuit); 14a, 14b, 14c, 14d, 14e, 14f: switching element (switch circuit); 5a, 5b, 5c, 5d, 5e, 5f: gate input part (inverter circuit); 6a, 6b, 6c, 6d, 6e, 6f: gate input part (switching circuit); 16a, 16b, 16c, 16d, 16e, 16f: gate input part (switching circuit); 7: motor (load); 8: control circuit; 9: gate resistance determination part; 10: gate resistance switching circuit; 11: buffer circuit; 12: power on; 15: power off.

Claims

1. A power conversion device, comprising: A capacitor series circuit has a plurality of capacitors connected in series, with both ends connected to the ends of a DC voltage source; An inverter circuit is formed by connecting a plurality of branches formed by connecting a plurality of switching elements in series in parallel, wherein a DC input end is connected to both ends of the capacitor series circuit, and an AC output end is connected to a load; a switching circuit having a plurality of switching elements, one end of which is connected to the connection points of the plurality of capacitors and the other end of which is connected to the plurality of connection points of the switching elements of the inverter circuit; as well as a control circuit, controlling the inverter circuit and the switch circuit, The inverter circuit can perform a two-level operation by turning off the switch element included in the switch circuit, and can perform a three-level operation by turning on / off the switch element included in the switch circuit. The control circuit changes the switching speeds of the switching elements of the inverter circuit and the switching circuit when switching the operation level between the two-level operation and the three-level operation.

2. The power conversion device according to claim 1, wherein: The control circuit reduces the switching speed of the switching element when changing from the three-level operation to the two-level operation.

3. The power conversion device according to claim 1 or 2, wherein: The control circuit changes the switching speed of the switching element before switching the operation level between the three-level operation and the two-level operation.

4. The power conversion device according to any one of claims 1 to 3, wherein: After a command to change the switching speed of the switching element is issued, the control circuit switches the operation level between the three-level operation and the two-level operation after waiting for a certain period of time.

5. The power conversion device according to any one of claims 1 to 3, wherein: After receiving a command to change the switching speed of the switching element, the control circuit determines a switching speed change process based on a change in the switching speed of the switching element.

6. The power conversion device according to any one of claims 1 to 3, wherein: After a command to change the switching speed of the switching element is issued, the control circuit determines a process of changing the switching speed based on a change in a slope of a gate voltage applied to a gate terminal of the switching element.

7. The power conversion device according to any one of claims 1 to 3, wherein: After the instruction to change the switching speed of the switching element is issued, the control circuit determines a process of changing the switching speed based on the fact that the gate current of the switching element has changed.

8. The power conversion device according to any one of claims 1 to 3, wherein: After the switching speed change instruction of the switching element, the control circuit determines the switching speed change process based on the fact that the surge voltage generated at both ends of the switching element or at both ends of the capacitor series circuit has changed.

9. The power conversion device according to any one of claims 1 to 8, wherein: The level switching threshold when changing from the 2-level operation to the 3-level operation and the level switching threshold when changing from the 3-level operation to the 2-level operation are set to different values.

10. The power conversion device according to any one of claims 1 to 9, wherein: The control circuit changes a switching speed of the switching element based on a detection value of a surge voltage generated across both ends of the switching element or across both ends of the capacitor series circuit.

11. The power conversion device according to claim 10, wherein: The control circuit changes the switching speed of the switching element so that the maximum value of the detected value of the surge voltage generated at both ends of the switching element or at both ends of the capacitor series circuit converges within a target allowable voltage range.

12. The power conversion device according to claim 10 or 11, wherein: The control circuit changes the switching speed based on a plurality of consecutive detection values ​​of the surge voltage.

13. The power conversion device according to any one of claims 1 to 12, wherein: The control circuit switches between the two-level operation and the three-level operation based on a comparison between an AC output current value of the power conversion device and a preset current threshold value.

14. The power conversion device according to any one of claims 1 to 13, wherein: The control circuit switches the operation level and changes the switching speed for each fundamental wave cycle of the AC output current of the power conversion device.

15. The power conversion device according to any one of claims 1 to 13, wherein: The control circuit switches the operation level and changes the switching speed at a time interval shorter than a fundamental wave period of the AC output current of the power conversion device.

16. The power conversion device according to any one of claims 1 to 15, wherein: A level switching threshold for switching between the two-level operation and the three-level operation is determined according to the volume of the switch element of the switch circuit.

17. The power conversion device according to any one of claims 1 to 16, wherein: A motor is connected as the load, and the control circuit determines the switching of the action level and the switching speed based on command information from the motor and the power conversion device and detection information from the motor and the power conversion device according to a pre-prepared table or calculation result.

18. The power conversion device according to any one of claims 1 to 17, wherein: The control circuit changes the switching speed of the switching element by changing a gate resistance value when the switching element is turned off.

Images