Field programmable gate array (FPGA) state detection method, system and equipment based on SelectMap interface and medium thereof

Abstract

The invention provides an FPGA (Field Programmable Gate Array) state detection method, system and equipment based on a SelectMap interface and a medium thereof, and the method comprises the steps: periodically reading and detecting a first pin signal and a second pin signal of an FPGA processor through a pin detection module in response to a power-on configuration signal; if it is detected that the first pin signal jumps from the high level to the low level, and it is detected that the second pin signal jumps from the high level to the low level within a preset jumping time and then jumps from the low level to the high level, it is confirmed that the FPGA processor enters a configuration burning state; after the FPGA processor enters the configuration burning state, if it is detected that the first pin signal and the second pin signal are both continuously located at the high level, it is confirmed that the FPGA processor enters the working state; after the FPGA processor enters the working state, if it is detected that the first pin signal or the second pin signal jumps from the high level to the low level, it is confirmed that the FPGA processor is in the hardware abnormal state, and then the error state of the FPGA processor caused by hardware abnormity is accurately detected.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to a method, system, device and medium for detecting FPGA status based on a SelectMap interface. Background Art

[0002] Currently, most scenarios using the SelectMAP interface are as a communication control interface between the radiation-resistant system and the FPGA in a complex space radiation environment. It is used to reload and refresh the target FPGA at a fixed time, clear FPGA configuration data flips and errors caused by particle impacts, and improve the target FPGA's ability to resist radiation.

[0003] However, the existing SelectMAP interface generally lacks real-time and effective detection of the target FPGA. Relatively rigorous detection only reads back and compares the configuration data in the FPGA, and then processes it after the comparison is wrong. Although this type of detection is accurate, it takes a long time to read back and compare all the configuration data of the FPGA.

[0004] Moreover, FPGA anomalies are not just soft errors caused by single-particle effects, but also hard errors caused by FPGA device damage and FPGA peripheral circuit anomalies that lead to errors in the entire FPGA system. Such errors will affect SelectMAP interface communication, causing the readback comparison function to fail to execute. There is currently no systematic detection module and method for comprehensive detection of these errors. Most of them are small logic modules embedded in the entire large system for judgment and detection, which are insufficient in detection and poor in portability. Summary of the invention

[0005] The main purpose of the embodiments of the present application is to propose an FPGA state detection method, system, device and medium based on the SelectMap interface. By detecting the high and low levels of the FPGA pins through the pin detection module, the error state of the FPGA processor due to hardware abnormalities can be accurately detected, thereby improving the accuracy and real-time performance of FPGA processor abnormality error reporting. In addition, the system can be compatible with different operating hosts according to the bus interface, thereby improving the adaptability and portability of FPGA state detection.

[0006] To achieve the above-mentioned purpose, a first aspect of an embodiment of the present application proposes an FPGA state detection method based on a SelectMap interface, which is applied to an FPGA state detection system. The FPGA state detection system includes a bus interface, a control unit, and a SelectMap interface. The control unit includes a pin detection module, and the pin detection module is respectively communicated with the bus interface and the SelectMap interface. The FPGA state detection method includes: The pin detection module responds to the power-on configuration signal sent by the bus interface, and periodically reads and detects the first pin signal and the second pin signal of the FPGA processor from the SelectMap interface; If the pin detection module detects that the first pin signal jumps from a high level to a low level, and detects that the second pin signal jumps from a high level to a low level within a preset jump time, and then jumps from a low level to a high level, it is confirmed that the FPGA processor enters the configuration burning state, and the information that the FPGA processor enters the configuration burning state is fed back to the operating host through the bus interface; After the FPGA processor enters the configuration burning state, if the pin detection module detects that the first pin signal and the second pin signal are both continuously at a high level, it is confirmed that the FPGA processor enters the working state, and the information that the FPGA processor enters the working state is fed back to the operating host through the bus interface; After the FPGA processor enters the working state, if the pin detection module detects that the first pin signal or the second pin signal jumps from a high level to a low level, it confirms that the FPGA processor is in a hardware abnormal state, and feeds back the information that the FPGA processor is in a hardware abnormal state to the operating host through the bus interface.

[0007] Furthermore, in some embodiments, the control unit further includes an access control module, which is respectively connected to the bus interface and the SelectMap interface for communication. Before confirming that the FPGA processor enters the configuration burning state, the FPGA state detection method further includes: If the pin detection module detects that both the first pin signal and the second pin signal jump from a low level to a high level and remain at a high level, it is determined that the FPGA processor is in an idle state, and the information that the FPGA processor is in an idle state is fed back to the operation host through the bus interface; The access control module performs a write operation on the FPGA processor through the SelectMap interface in response to a signal sent by the bus interface indicating that the FPGA processor is in an idle state, so as to write the first data to the target address of the FPGA processor; In response to the completion of the write operation, the access control module performs a read-back operation on the FPGA processor through the SelectMap interface to read the second data from the target address and compare the second data with the first data; When the second data is inconsistent with the first data, the access control module confirms that the FPGA processor is in an abnormal communication state, and feeds back information that the FPGA processor is in an abnormal communication state to the operating host through the bus interface.

[0008] Furthermore, in some embodiments, before confirming that the FPGA processor enters the configuration burning state, the FPGA state detection method further includes: When the second data is consistent with the first data, the access control module reads the third data of the FPGA processor and outputs the third data to the operating host through the bus interface, wherein the third data is the status data stored in the status register in the FPGA processor.

[0009] Furthermore, in some embodiments, before determining that the FPGA processor is in an idle state, the FPGA state detection method further includes: If the pin detection module detects that the first pin signal and the second pin signal are both continuously at a low level, it is determined that the FPGA processor is in an unpowered state, and the information that the FPGA processor is in an unpowered state is fed back to the operating host through the bus interface.

[0010] Furthermore, in some embodiments, in the process of confirming that the FPGA processor enters the configuration burning state, the FPGA state detection method further includes: If the pin detection module detects that the second pin signal has an abnormal high-low level jump during the non-jump period, it is determined that the FPGA processor is in an abnormal configuration state, and the information that the FPGA processor is in an abnormal configuration state is fed back to the operating host through the bus interface.

[0011] Furthermore, in some embodiments, in the process of confirming that the FPGA processor enters the configuration burning state, the FPGA state detection method further includes: If the pin detection module detects that the second pin signal is at a low level for a period of time exceeding the preset transition time during the transition period, it determines that the FPGA processor is in an abnormal configuration state, and feeds back the information that the FPGA processor is in an abnormal configuration state to the operating host through the bus interface.

[0012] To achieve the above-mentioned purpose, a second aspect of an embodiment of the present application proposes an FPGA state detection system, comprising: Bus interface, which is used to communicate and interact with the operating host; SelectMap interface, which is used to communicate and interact with the FPGA processor; A control unit, the control unit includes a pin detection module, and the pin detection module is respectively communicated with the bus interface and the SelectMap interface; wherein the pin detection module is used to execute the FPGA state detection method of the first aspect embodiment mentioned above.

[0013] Further, in some embodiments, the control unit also includes an access control module, which is respectively communicated with the bus interface and the SelectMap interface; wherein the access control module is used in the FPGA state detection method of the first aspect embodiment.

[0014] To achieve the above-mentioned purpose, the third aspect of the embodiments of the present application proposes an electronic device, the electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the FPGA status detection method of the above-mentioned first aspect embodiment when executing the computer program.

[0015] To achieve the above-mentioned purpose, the fourth aspect of the embodiment of the present application proposes a storage medium, which is a computer-readable storage medium. The storage medium stores a computer program, and when the computer program is executed by the processor, the PGA status detection method of the above-mentioned first aspect embodiment is implemented.

[0016] The embodiments of the present application have the following beneficial effects: the present application periodically reads and detects the first pin signal and the second pin signal of the FPGA processor from the SelectMap interface in response to the power-on configuration signal sent by the bus interface through the pin detection module; wherein, if the pin detection module detects that the first pin signal jumps from a high level to a low level, and detects that the second pin signal jumps from a high level to a low level within a preset jump time, and then jumps from a low level to a high level, then it is confirmed that the FPGA processor enters the configuration burning state, and the information that the FPGA processor enters the configuration burning state is fed back to the operating host through the bus interface; after the FPGA processor enters the configuration burning state, if the pin detection module detects that the first pin signal and the second pin signal are both continuously at a high level, then it is confirmed that The FPGA processor is confirmed to enter the working state, and the information that the FPGA processor enters the working state is fed back to the operation host through the bus interface; after the FPGA processor enters the working state, if the pin detection module detects that the first pin signal or the second pin signal jumps from a high level to a low level, it is confirmed that the FPGA processor is in a hardware abnormal state, and the information that the FPGA processor is in the hardware abnormal state is fed back to the operation host through the bus interface, and then based on the high and low level detection of the FPGA pin by the pin detection module, the error state of the FPGA processor due to the hardware abnormality can be accurately detected, thereby improving the accuracy and real-time performance of the FPGA processor abnormal error reporting, and can also be compatible with different operation hosts according to the bus interface, thereby improving the adaptability and portability of FPGA state detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a flow chart of an FPGA state detection method provided by some embodiments of the present application; Figure 2It is a flowchart provided by some embodiments of the present application for confirming that the FPGA processor enters the configuration burning state; Figure 3 It is a flowchart for confirming that the FPGA processor enters the configuration burning state provided by other embodiments of the present application; Figure 4 is a flowchart provided by some embodiments of the present application before determining that the FPGA processor is in an idle state; Figure 5 It is a flowchart of the process of confirming that the FPGA processor enters the configuration burning state provided by some embodiments of the present application; Figure 6 is a flowchart of determining the general direction of data interaction according to a target instruction provided in some embodiments of the present application; Figure 7 It is a flowchart of a process of confirming that an FPGA processor enters a configuration burning state provided by other embodiments of the present application; Figure 8 It is a schematic diagram of the hardware structure of an electronic device provided in some embodiments of the present application. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0019] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0020] It should also be noted that in the description of this application, "several" means more than one, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used to distinguish the technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0022] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0023] First, some nouns involved in this application are analyzed: SelectMAP interface is a parallel communication interface designed by Xilinx, which is used for configuration and register access of all its SRAM-type FPGAs. And because Xilinx's FPGAs are widely used and the technology is relatively open, many domestic manufacturers have also added compatibility with SelectMAP interface in their FPGA designs.

[0024] In the existing SelectMAP interface, there is a general lack of real-time and effective detection of the target FPGA. Relatively rigorous detection only reads back and compares the configuration data in the FPGA, and then processes it after the comparison is wrong. Although this type of detection is accurate, it takes a long time to read back and compare all the configuration data of the FPGA.

[0025] Moreover, FPGA anomalies are not just soft errors caused by single-particle effects, but also hard errors caused by FPGA device damage and FPGA peripheral circuit anomalies that lead to errors in the entire FPGA system. Such errors will affect SelectMAP interface communication, causing the readback comparison function to fail to execute. There is currently no systematic detection module and method for comprehensive detection of these errors. Most of them are small logic modules embedded in the entire large system for judgment and detection, which are insufficient in detection and poor in portability.

[0026] Based on this, the present application periodically reads and detects the first pin signal and the second pin signal of the FPGA processor from the SelectMap interface in response to the power-on configuration signal sent by the bus interface through the pin detection module; wherein, if the pin detection module detects that the first pin signal jumps from a high level to a low level, and detects that the second pin signal jumps from a high level to a low level within a preset jump time, and then jumps from a low level to a high level, it is confirmed that the FPGA processor enters the configuration burning state, and the information that the FPGA processor enters the configuration burning state is fed back to the operating host through the bus interface; after the FPGA processor enters the configuration burning state, if the pin detection module detects that the first pin signal and the second pin signal are both continuously at a high level, it is confirmed that the FPGA processor enters the configuration burning state. The FPGA processor enters a working state, and feeds back information about the FPGA processor entering the working state to the operating host through the bus interface; after the FPGA processor enters the working state, if the pin detection module detects that the first pin signal or the second pin signal jumps from a high level to a low level, it is confirmed that the FPGA processor is in a hardware abnormal state, and the information that the FPGA processor is in a hardware abnormal state is fed back to the operating host through the bus interface, thereby accurately detecting the error state of the FPGA processor due to hardware abnormality based on the high and low level detection of the FPGA pin by the pin detection module, thereby improving the accuracy and real-time performance of the FPGA processor abnormal error reporting, and can also be compatible with different operating hosts according to the bus interface, thereby improving the adaptability and portability of FPGA state detection.

[0027] The embodiments of the present application provide a method, system and storage medium for FPGA state detection based on SelectMap interface, which are specifically described through the following embodiments.

[0028] In the first aspect, an FPGA state detection method based on the SelectMap interface in an embodiment of the present application is first described. The FPGA state detection method is applied to an FPGA state detection system. The FPGA state detection system includes a bus interface, a control unit, and a SelectMap interface. The control unit includes a pin detection module. The pin detection module is respectively communicated with the bus interface and the SelectMap interface. The bus interface is used to communicate and interact with the operating host, and the SelectMap interface is used to communicate and interact with the FPGA processor.

[0029] Reference Figure 1 As shown, Figure 1 is a flowchart of an FPGA state detection method provided in some embodiments of the present application. The FPGA state detection method may include but is not limited to steps S101 to S104.

[0030] Step S101: the pin detection module periodically reads and detects the first pin signal and the second pin signal of the FPGA processor from the SelectMap interface in response to the power-on configuration signal sent by the bus interface.

[0031] The power-on configuration signal is a configuration signal sent by the operating host to the pin detection module through the bus interface.

[0032] It should be noted that the first pin signal is the electrical signal of the DONE pin in the FPGA processor, and the second pin signal is the electrical signal of the INIT pin in the FPGA processor. The level of the first pin signal is the level output to the pin detection module after the SelectMap interface filters and synchronizes the DONE pin electrical signal, and the level of the second pin signal is the level output to the pin detection module after the SelectMap interface filters and synchronizes the INIT pin electrical signal. The level of the first pin signal and the level of the second pin signal directly reflect the status of the DONE pin and the INIT pin in the FPGA processor.

[0033] Specifically, the pin detection module responds to the power-on configuration signal sent by the bus interface, and periodically reads and detects the first pin signal and the second pin signal of the FPGA processor from the SelectMap interface, so that the pin detection module can detect the status information of the DONE pin and the INIT pin at each stage of the FPGA processor in real time.

[0034] Step S102: If the pin detection module detects that the first pin signal jumps from a high level to a low level, and detects that the second pin signal jumps from a high level to a low level within a preset jump time, and then jumps from a low level to a high level, it is confirmed that the FPGA processor enters the configuration burning state, and the information that the FPGA processor enters the configuration burning state is fed back to the operating host through the bus interface.

[0035] Specifically, when the pin detection module detects that both the first pin signal and the second pin signal are in a high level state, and then the first pin signal (i.e., the electrical signal of the DONE pin) jumps from a high level to a low level, and at the same time detects that the second pin signal (i.e., the electrical signal of the INIT pin) jumps from a high level to a low level within a preset jump time, and then jumps from a low level to a high level, it is confirmed that the FPGA processor enters the configuration burning state, and the information that the FPGA processor enters the configuration burning state is fed back to the operating host through the bus interface.

[0036] Step S103: After the FPGA processor enters the configuration burning state, if the pin detection module detects that the first pin signal and the second pin signal are both continuously at a high level, it confirms that the FPGA processor enters the working state, and feeds back the information that the FPGA processor enters the working state to the operating host through the bus interface.

[0037] Specifically, after the FPGA processor enters the configuration burning state, that is, after the second pin signal enters the non-transition period from the transition period, if the pin detection module detects that the first pin signal and the second pin signal are both continuously at a high level, it confirms that the FPGA processor enters the working state of running the logic program, and feeds back the information that the FPGA processor enters the working state to the operating host through the bus interface.

[0038] Step S104: After the FPGA processor enters the working state, if the pin detection module detects that the first pin signal or the second pin signal jumps from a high level to a low level, it is confirmed that the FPGA processor is in a hardware abnormal state, and the information that the FPGA processor is in a hardware abnormal state is fed back to the operating host through the bus interface.

[0039] The hardware exception status is used to indicate that an exception has occurred in the internal hardware of the FPGA processor.

[0040] Specifically, after the FPGA processor enters the working state of running the logic program, if the pin detection module detects that the first pin signal or the second pin signal jumps from a high level to a low level, it confirms that the FPGA processor is in a hardware abnormal state, and feeds back the information that the FPGA processor is in a hardware abnormal state to the operating host through the bus interface.

[0041] It should be noted that, through steps S101 to S104 shown in the embodiment of the present application, the high and low level detection of the FPGA pins can be based on the pin detection module, and the error state of the FPGA processor due to hardware abnormalities can be accurately detected, thereby improving the accuracy and real-time performance of FPGA processor abnormality error reporting, and can also be compatible with different operating hosts according to the bus interface, thereby improving the adaptability and portability of FPGA status detection.

[0042] Further, refer to Figure 2 As shown, Figure 2 This is a flowchart provided by some embodiments of the present application for confirming that the FPGA processor enters the configuration burning state. The FPGA state detection method may include but is not limited to steps S201 to S203.

[0043] Step S201: If the pin detection module detects that both the first pin signal and the second pin signal jump from a low level to a high level and remain at a high level, it is determined that the FPGA processor is in an idle state, and the information that the FPGA processor is in an idle state is fed back to the operating host through the bus interface.

[0044] Specifically, before confirming that the FPGA processor enters the configuration burning state, when the pin detection module detects that the first pin signal and the second pin signal both jump from a low level to a high level and remain at a high level, it is determined that the FPGA processor has been powered on and is in an idle state, and then the information that the FPGA processor is in an idle state is fed back to the operating host through the bus interface.

[0045] It should be noted that the above process of determining whether the first pin signal and the second pin signal are continuously at a high level is as follows: the number of read cycles in which the first pin signal and the second pin signal are respectively at a high level is accumulated. When the number of read cycles is equal to the number of configuration cycles set by the above power-on configuration signal, it is determined that the first pin signal and the second pin signal are continuously at a high level. Finally, it is determined that the FPGA processor has been powered on and is in an idle state. Then, the detection frequency of the pin detection module can be adjusted by operating the parameter configuration of the host, thereby improving the flexibility of detecting the FPGA processor.

[0046] Step S202: In response to the signal sent by the bus interface that the FPGA processor is in an idle state, the access control module performs a write operation on the FPGA processor through the SelectMap interface to write the first data to the target address of the FPGA processor.

[0047] The first data is data of the FPGA processor designated to be written by the operating host.

[0048] Specifically, after the operating host receives the information that the FPGA processor is in an idle state, it sends a signal that the FPGA processor is in an idle state to the access control module through the bus interface. In response to the signal that the FPGA processor is in an idle state sent by the bus interface, the access control module performs a write operation on the FPGA processor through the SelectMap interface to write the first data to the target address of the FPGA processor.

[0049] Step S203: In response to the completion of the write operation, the access control module performs a read-back operation on the FPGA processor through the SelectMap interface to read the second data from the target address and compare the second data with the first data.

[0050] The second data is the data written into the target address of the FPGA processor.

[0051] Specifically, in response to the completion of the write operation, the access control module performs a read-back operation on the FPGA processor through the SelectMap interface to read the second data from the target address and compare the second data with the first data.

[0052] Step S204: When the second data is inconsistent with the first data, the access control module confirms that the FPGA processor is in an abnormal communication state, and feeds back information that the FPGA processor is in an abnormal communication state to the operating host through the bus interface.

[0053] The communication abnormality state is used to indicate that the data communication between the FPGA processor and the SelectMap interface is abnormal.

[0054] Specifically, when the second data is inconsistent with the first data, the access control module confirms that the FPGA processor is in an abnormal communication state, and feeds back information that the FPGA processor is in an abnormal communication state to the operating host through the bus interface.

[0055] It should be noted that, through steps S201 to S204 shown in the embodiment of the present application, it is possible to perform read and write tests between the FPGA processor and the SelectMap interface based on the access control module, accurately detect soft errors caused by interface communication abnormalities in the FPGA processor, and further improve the accuracy and real-time performance of FPGA processor abnormal error reporting.

[0056] Reference Figure 3 As shown, Figure 3 This is a flowchart provided by other embodiments of the present application for confirming that the FPGA processor enters the configuration burning state. The FPGA state detection method may include but is not limited to step S301.

[0057] Step S301: When the second data is consistent with the first data, the access control module reads the third data of the FPGA processor and outputs the third data to the operating host through the bus interface.

[0058] The third data is status data stored in a status register in the FPGA processor.

[0059] Specifically, when the second data is inconsistent with the first data, the access control module confirms that the communication between the FPGA processor and the SelectMap interface is normal, and then the access control module reads the third data of the status register in the FPGA processor and outputs the third data to the operating host through the bus interface.

[0060] In one possible implementation, refer to Figure 4 As shown, Figure 4This is a flowchart provided by some embodiments of the present application before determining that the FPGA processor is in an idle state. The FPGA state detection method may include but is not limited to step S401.

[0061] Step S401: If the pin detection module detects that the first pin signal and the second pin signal are both continuously at a low level, it is determined that the FPGA processor is in an unpowered state, and the information that the FPGA processor is in an unpowered state is fed back to the operating host through the bus interface.

[0062] Among them, before determining that the FPGA processor is in an idle state, if the pin detection module detects that the first pin signal and the second pin signal are both continuously at a low level, it is determined that the FPGA processor is in an unpowered state, and the information that the FPGA processor is in an unpowered state is fed back to the operating host through the bus interface.

[0063] It should be noted that the above process of determining whether the first pin signal and the second pin signal are continuously at a low level is as follows: the number of read cycles in which the first pin signal and the second pin signal are respectively at a low level is accumulated. When the number of read cycles is equal to the number of configuration cycles set by the above power-on configuration signal, it is determined that the first pin signal and the second pin signal are continuously at a low level. Finally, it is determined that the FPGA processor is in an unpowered state, and the detection frequency of the pin detection module can be adjusted by operating the parameter configuration of the host, thereby improving the flexibility of detecting the FPGA processor.

[0064] Reference Figure 5 As shown, Figure 5 This is a flowchart of the process of confirming that the FPGA processor enters the configuration burning state provided by some embodiments of the present application. The FPGA state detection method may include but is not limited to step S501.

[0065] Step S501: If the pin detection module detects that the second pin signal has an abnormal high-low level jump during the non-jump period, it is determined that the FPGA processor is in an abnormal configuration state, and the information that the FPGA processor is in an abnormal configuration state is fed back to the operating host through the bus interface.

[0066] The configuration exception state is used to indicate that an exception occurs during the process of burning configuration data in the FPGA processor.

[0067] In one possible implementation, in the process of confirming that the FPGA processor has entered the configuration burning state, if the pin detection module detects that the second pin signal has an abnormal high-low level jump during the non-transition period, it is determined that the FPGA processor is in an abnormal configuration state, and the information that the FPGA processor is in an abnormal configuration state is fed back to the operating host through the bus interface.

[0068] It should be noted that, through step S501 shown in the embodiment of the present application, high and low level detection can be performed on the FPGA processor burning process based on the pin detection module, and soft errors caused by abnormal burning of the FPGA processor can be accurately detected, further improving the accuracy and real-time performance of abnormal error reporting of the FPGA processor.

[0069] Reference Figure 6 As shown, Figure 6 It is a flowchart of the process of confirming that the FPGA processor enters the configuration burning state provided by other embodiments of the present application. The FPGA state detection method may include but is not limited to step S601.

[0070] Step S601: If the pin detection module detects that the second pin signal is at a low level for a period of time exceeding the preset transition time during the transition period, it is determined that the FPGA processor is in an abnormal configuration state, and the information that the FPGA processor is in an abnormal configuration state is fed back to the operating host through the bus interface.

[0071] Specifically, in the process of confirming that the FPGA processor has entered the configuration burning state, if the pin detection module detects that the second pin signal is at a low level during the transition period for a time that exceeds the preset transition time, it is determined that the FPGA processor is in an abnormal configuration state, and the information that the FPGA processor is in an abnormal configuration state is fed back to the operating host through the bus interface.

[0072] It should be noted that, through step S601 shown in the embodiment of the present application, the level signal detection can be performed on the FPGA processor burning process based on the pin detection module, and the soft errors caused by abnormal burning of the FPGA processor can be accurately detected, thereby further improving the accuracy and real-time performance of the FPGA processor abnormal error reporting.

[0073] In general, through the embodiment of the present application, the pin detection module detects high and low level signals of the FPGA processor, and the access control module performs read and write tests between the FPGA processor and the SelectMap interface, thereby being able to detect errors caused by hardware abnormalities in the FPGA processor, and soft errors caused by communication abnormalities in the FPGA processor, and soft errors caused by burning abnormalities in the FPGA processor, thereby improving the diversity and accuracy of FPGA processor abnormality detection.

[0074] In a second aspect, the present application embodiment also provides an FPGA state detection system, referring to Figure 7 , Figure 7 This is a schematic diagram of the structure of an FPGA state detection system provided in some embodiments of the present application. The FPGA state detection system 700 includes: The bus interface 710 is used to communicate with the operating host; SelectMap interface 720, the SelectMap interface 720 is used to communicate and interact with the FPGA processor; The control unit 730 includes a pin detection module 731, which is respectively connected to the bus interface 710 and the SelectMap interface 720 for communication; wherein the pin detection module 731 is used to execute the FPGA state detection method of the first embodiment.

[0075] The above-mentioned FPGA state detection system 700 and the above-mentioned FPGA state detection method are based on the same inventive concept. The above-mentioned process describes the FPGA state detection system 700 of the embodiment of the present application. The pin detection module 731 responds to the power-on configuration signal sent by the bus interface 710, and periodically reads and detects the first pin signal and the second pin signal of the FPGA processor from the SelectMap interface 720; wherein, if the pin detection module 731 detects that the first pin signal jumps from a high level to a low level, and detects that the second pin signal jumps from a high level to a low level within a preset jump time, and then jumps from a low level to a high level, it is confirmed that the FPGA processor enters the configuration burning state, and the information that the FPGA processor enters the configuration burning state is fed back to the operating host through the bus interface 710; after the FPGA processor enters the configuration burning state, if the pin detection module 731 detects that When both the first pin signal and the second pin signal are continuously at a high level, it is confirmed that the FPGA processor has entered the working state, and the information that the FPGA processor has entered the working state is fed back to the operating host through the bus interface 710; after the FPGA processor enters the working state, if the pin detection module 731 detects that the first pin signal or the second pin signal jumps from a high level to a low level, it is confirmed that the FPGA processor is in a hardware abnormal state, and the information that the FPGA processor is in a hardware abnormal state is fed back to the operating host through the bus interface 710, thereby accurately detecting the error state of the FPGA processor due to hardware abnormality based on the high and low level detection of the FPGA pin by the pin detection module 731, thereby improving the accuracy and real-time performance of the FPGA processor abnormal error reporting, and can also be compatible with different operating hosts according to the bus interface 710, thereby improving the adaptability and portability of FPGA state detection.

[0076] Further, refer again Figure 7 As shown, the control unit 730 also includes an access control module 732, which is respectively communicated with the bus interface 710 and the SelectMap interface 720; wherein the access control module 732 is used in the FPGA state detection method of the first aspect embodiment.

[0077] It should be noted that, in response to the signal sent by the bus interface that the FPGA processor is in an idle state, the access control module performs a write operation on the FPGA processor through the SelectMap interface to write the first data to the target address of the FPGA processor. Then, in response to the completion of the write operation, the access control module performs a read back operation on the FPGA processor through the SelectMap interface to read the second data from the target address and compare the second data with the first data. When the second data is inconsistent with the first data, the access control module confirms that the FPGA processor is in an abnormal communication state, and feeds back the information that the FPGA processor is in an abnormal communication state to the operating host through the bus interface, thereby being able to perform high and low level detection on the FPGA processor burning process based on the pin detection module, accurately detect soft errors caused by abnormal burning of the FPGA processor, and further improve the accuracy and real-time performance of abnormal error reporting of the FPGA processor.

[0078] The embodiment of the present application also provides an electronic device, the electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the above FPGA state detection method when executing the computer program. The electronic device can be any smart terminal including a mobile phone, a tablet computer, a car computer, etc.

[0079] See also Figure 8 , Figure 8 : is a schematic diagram of the hardware structure of an electronic device provided in some embodiments of the present application, and the electronic device includes: The processor 801 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the QSPI serial port transfer method and / or cache data reading method provided in the embodiments of the present application; The memory 802 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 802 can store an operating system and other application programs. When the technical solution provided in the embodiments of this specification is implemented by software or firmware, the relevant program code is stored in the memory 802, and the processor 801 calls and executes the QSPI serial port transfer method and / or cache data reading method provided in the embodiments of this application; Input / output interface 803, used to implement information input and output; The communication interface 804 is used to realize the communication interaction between the device and other devices. The communication can be realized through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.); A bus 805 that transmits information between various components of the device (e.g., the processor 801, the memory 802, the input / output interface 803, and the communication interface 804); The processor 801 , the memory 802 , the input / output interface 803 and the communication interface 804 are connected to each other in communication within the device via a bus 805 .

[0080] The embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the FPGA state detection method provided in the embodiment of the present application is implemented.

[0081] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0082] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0083] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0084] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0085] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0086] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0087] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0088] In the several embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0089] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0090] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0091] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-accessible storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0092] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A FPGA state detection method based on SelectMap interface, characterized in that: Applied to an FPGA state detection system, the FPGA state detection system includes a bus interface, a control unit, and a SelectMap interface, the control unit includes a pin detection module and an access control module, the pin detection module is respectively connected to the bus interface and the SelectMap interface for communication, the access control module is respectively connected to the bus interface and the SelectMap interface for communication, and the FPGA state detection method includes: The pin detection module periodically reads and detects a first pin signal and a second pin signal of the FPGA processor from the SelectMap interface in response to a power-on configuration signal sent by the bus interface; If the pin detection module detects that the first pin signal jumps from a high level to a low level, and detects that the second pin signal jumps from a high level to a low level within a preset jump time, and then jumps from a low level to a high level, it is confirmed that the FPGA processor enters a configuration burning state, and the information that the FPGA processor enters a configuration burning state is fed back to the operating host through the bus interface; After the FPGA processor enters the configuration burning state, if the pin detection module detects that both the first pin signal and the second pin signal are continuously at a high level, it is confirmed that the FPGA processor enters the working state, and the information that the FPGA processor enters the working state is fed back to the operation host through the bus interface; After the FPGA processor enters the working state, if the pin detection module detects that the first pin signal or the second pin signal jumps from a high level to a low level, it is confirmed that the FPGA processor is in a hardware abnormal state, and the information that the FPGA processor is in a hardware abnormal state is fed back to the operation host through the bus interface; Before confirming that the FPGA processor enters the configuration burning state, the FPGA state detection method further includes the following steps: If the pin detection module detects that both the first pin signal and the second pin signal jump from a low level to a high level and remain at a high level, it is determined that the FPGA processor is in an idle state, and information that the FPGA processor is in an idle state is fed back to the operation host through the bus interface; The access control module performs a write operation on the FPGA processor through the SelectMap interface in response to a signal sent by the bus interface indicating that the FPGA processor is in an idle state, so as to write first data to a target address of the FPGA processor; In response to the completion of the write operation, the access control module performs a read-back operation on the FPGA processor through the SelectMap interface to read second data from the target address and compare the second data with the first data; When the second data is inconsistent with the first data, the access control module confirms that the FPGA processor is in an abnormal communication state, and feeds back information that the FPGA processor is in an abnormal communication state to the operation host through the bus interface; Furthermore, when the pin detection module detects that both the first pin signal and the second pin signal jump from a low level to a high level and remain at a high level, the following steps are included: accumulating the number of read cycles in which the first pin signal and the second pin signal are respectively at a high level, and when the number of read cycles of the first pin signal and the second pin signal is equal to the number of configuration cycles set in the power-on configuration signal, it is determined that the first pin signal and the second pin signal are continuously at a high level.

2. The FPGA state detection method according to claim 1, characterized in that: Before confirming that the FPGA processor enters the configuration burning state, the FPGA state detection method further includes: When the second data is consistent with the first data, the access control module reads the third data in the FPGA processor and outputs the third data to the operation host through the bus interface, wherein the third data is the status data stored in the status register in the FPGA processor.

3. The FPGA state detection method according to claim 1, characterized in that: Before determining that the FPGA processor is in an idle state, the FPGA state detection method further includes: If the pin detection module detects that the first pin signal and the second pin signal are both continuously at a low level, it determines that the FPGA processor is in an unpowered state, and feeds back the information that the FPGA processor is in an unpowered state to the operating host through the bus interface.

4. The FPGA state detection method according to claim 1, characterized in that: In the process of confirming that the FPGA processor enters the configuration burning state, the FPGA state detection method further includes: If the pin detection module detects that the second pin signal has an abnormal high-low level jump during the non-jump period, it is determined that the FPGA processor is in an abnormal configuration state, and the information that the FPGA processor is in an abnormal configuration state is fed back to the operating host through the bus interface.

5. The FPGA state detection method according to claim 1, characterized in that: In the process of confirming that the FPGA processor enters the configuration burning state, the FPGA state detection method further includes: If the pin detection module detects that the time when the second pin signal is at a low level during the transition period exceeds the preset transition time, it determines that the FPGA processor is in an abnormal configuration state, and feeds back the information that the FPGA processor is in an abnormal configuration state to the operating host through the bus interface.

6. An FPGA state detection system, characterized in that: include: A bus interface, the bus interface is used to communicate and interact with an operating host; SelectMap interface, the SelectMap interface is used to communicate and interact with the FPGA processor; A control unit, the control unit comprising a pin detection module and an access control module, the pin detection module is respectively connected to the bus interface and the SelectMap interface for communication, and the access control module is respectively connected to the bus interface and the SelectMap interface for communication; The access control module is used for the FPGA state detection method as described in any one of claims 1 to 2, and the pin detection module is used for executing the FPGA state detection method as described in any one of claims 1, 3, 4, and 5.

7. An electronic device, characterized in that: The electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the FPGA state detection method according to any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the FPGA state detection method according to any one of claims 1 to 5 is implemented.

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