Memory controller, operating method thereof and memory system

Abstract

The embodiment of the invention provides a memory controller, an operation method thereof and a memory system. The memory controller comprises a buffer and a processor coupled with the buffer; the cache is configured to cache the first logical address group; wherein the first logic address group is used for indicating continuous N first logic addresses, and N is an integer greater than 1; the data types of the N first data corresponding to the N first logic addresses are the same; the processor is configured to generate a first identification code based on the first logic address group and cache the first identification code into the cache; wherein the first identification code is used for indicating the data type of the N first data.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a memory controller and an operating method thereof, and a memory system. Background Art

[0002] In recent years, the semiconductor integrated circuit industry has experienced rapid development. With the continuous advancement of semiconductor manufacturing processes, the feature size of semiconductor devices has continued to shrink, the integration density of memory has become higher and higher, and its performance has become more and more powerful. Among them, volatile memory requires power to maintain its data, while non-volatile memory can retain the stored data when there is no power supply.

[0003] Although smaller device sizes have significantly increased memory capacity, it has also made it increasingly challenging to increase memory space utilization and improve memory reliability. Summary of the invention

[0004] The present disclosure provides a memory controller and an operating method thereof, and a memory system.

[0005] In a first aspect, the present disclosure provides a memory controller, the memory controller comprising a cache and a processor coupled to the cache;

[0006] The buffer is configured to cache a first logical address group; wherein the first logical address group is used to indicate N consecutive first logical addresses, N is an integer greater than 1; the data types of N first data corresponding to the N first logical addresses are the same;

[0007] The processor is configured to generate a first identification code based on the first logical address group, and cache the first identification code in the buffer; wherein the first identification code is used to indicate the data type of N pieces of the first data.

[0008] In some embodiments, the first logical address group includes a starting logical address and a logical address length; wherein the starting logical address is the first first logical address or the Nth first logical address among the consecutive N first logical addresses; and the processor is specifically configured to:

[0009] The start logical address and the logical address length are determined based on the consecutive N first logical addresses.

[0010] In some embodiments, the buffer is further configured to cache a second logical address group; wherein the second logical address group is used to indicate M consecutive second logical addresses, where M is an integer greater than 1; the data types of the M second data corresponding to the M second logical addresses are the same; and the data type of the second data is different from the data type of the first data;

[0011] The processor is also configured to generate a second identification code based on the second logical address group and cache the second identification code in the buffer; wherein the second identification code is used to indicate the data type of the second data of the M pen; the second identification code is different from the first identification code.

[0012] In some embodiments, the cache is further configured to cache P third logical addresses, where P is an integer greater than 0; wherein the P third logical addresses are not consecutive;

[0013] The processor is further configured to generate corresponding P third identification codes based on the P third logical addresses, respectively, and cache the third identification codes in the buffer; wherein the third identification code is used to indicate a data type of the third data corresponding to the third logical address.

[0014] In some embodiments, the memory controller is configured to: receive a plurality of logical addresses and data corresponding to the plurality of logical addresses; wherein the logical addresses include the first logical address and / or the third logical address;

[0015] The processor is further configured to:

[0016] Determine whether the received multiple logical addresses are continuous and whether the data types of the data corresponding to the multiple logical addresses are the same, and generate a determination result;

[0017] When the judgment result indicates that the plurality of logical addresses are continuous and the data types of the data corresponding to the plurality of logical addresses are the same, the first identification code is generated based on the judgment result.

[0018] In some embodiments, the processor is further configured to:

[0019] When the judgment result indicates that the plurality of logical addresses are not continuous, a plurality of the third identification codes are generated based on the judgment result.

[0020] In some embodiments, the processor is further configured to:

[0021] Based on the sum of the capacity of the first identification code and the N pieces of the first data reaching a preset capacity, storing the first identification code and the N pieces of the first data in the buffer into a memory device;

[0022] or,

[0023] Based on a power-off command from a host and / or detection of abnormal power-off, the first identification code and N pieces of the first data in the buffer are stored in a memory device.

[0024] In a second aspect, the present disclosure provides an operating method of a memory controller, the memory controller comprising a cache and a processor coupled to the cache, the operating method comprising:

[0025] The buffer caches a first logical address group; wherein the first logical address group is used to indicate N consecutive first logical addresses, N is an integer greater than 1; the data types of N first data corresponding to the N first logical addresses are the same;

[0026] The processor generates a first identification code based on the first logical address group, and caches the first identification code in the buffer; wherein the first identification code is used to indicate the data type of N pieces of the first data.

[0027] In some embodiments, the first logical address group includes a starting logical address and a logical address length; wherein the starting logical address is the first first logical address or the Nth first logical address among the consecutive N first logical addresses; and the operation method further includes:

[0028] The processor determines the start logical address and the logical address length based on consecutive N first logical addresses.

[0029] In some embodiments, the operating method further includes:

[0030] The buffer caches a second logical address group; wherein the second logical address group is used to indicate M consecutive second logical addresses, where M is an integer greater than 1; the data types of the M pieces of second data corresponding to the M second logical addresses are the same; and the data type of the second data is different from the data type of the first data;

[0031] The processor generates a second identification code based on the second logical address group and caches the second identification code in the cache; wherein the second identification code is used to indicate the data type of the second data of the M pen; the second identification code is different from the first identification code.

[0032] In some embodiments, the operating method further includes:

[0033] The buffer caches P third logical addresses, where P is an integer greater than 0; wherein the P third logical addresses are not continuous;

[0034] The processor generates corresponding P third identification codes based on the P third logical addresses respectively, and caches the third identification codes in the cache; wherein the third identification code is used to indicate the data type of the third data corresponding to the third logical address.

[0035] In some embodiments, the operating method further includes:

[0036] Receiving a plurality of logical addresses and data corresponding to the plurality of logical addresses; wherein the logical addresses include the first logical address and / or the third logical address;

[0037] The processor determines whether the received multiple logical addresses are continuous and whether the data types of the data corresponding to the multiple logical addresses are the same, and generates a determination result;

[0038] When the judgment result indicates that the plurality of logical addresses are continuous and the data types of the data corresponding to the plurality of logical addresses are the same, the processor generates the first identification code based on the judgment result.

[0039] In some embodiments, the operating method further includes:

[0040] When the determination result indicates that the plurality of logical addresses are not continuous, the processor generates a plurality of the third identification codes based on the determination result.

[0041] In some embodiments, the operating method further includes:

[0042] The processor stores the first identification code and the N pieces of the first data in the buffer into a memory device based on the sum of the capacities of the first identification code and the N pieces of the first data reaching a preset capacity;

[0043] or,

[0044] The processor stores the first identification code and N pieces of the first data in the buffer to the memory device based on a power-off command from the host and / or detecting an abnormal power-off.

[0045] In a third aspect, the present disclosure provides a memory system, the memory system comprising: a memory device and a memory controller coupled to the memory device; the memory controller comprising a cache and a processor coupled to the cache;

[0046] The buffer is configured to cache a first logical address group; wherein the first logical address group is used to indicate N consecutive first logical addresses, N is an integer greater than 1; the data types of N first data corresponding to the N first logical addresses are the same;

[0047] The processor is configured to generate a first identification code based on the first logical address group, and cache the first identification code in the buffer; wherein the first identification code is used to indicate the data type of N pieces of the first data;

[0048] The processor is further configured to store the first identification code and N pieces of the first data in the buffer to the memory device.

[0049] In some embodiments, the first logical address group includes a starting logical address and a logical address length; wherein the starting logical address is the first first logical address or the Nth first logical address among the consecutive N first logical addresses; and the processor is specifically configured to:

[0050] The start logical address and the logical address length are determined based on the consecutive N first logical addresses.

[0051] In some embodiments, the cache is further configured to cache P third logical addresses, where P is an integer greater than 0; wherein the P third logical addresses are not consecutive;

[0052] The processor is also configured to generate corresponding P third identification codes based on the P third logical addresses, respectively, and cache the third identification codes in the corresponding buffers; wherein the third identification codes are used to indicate the data type of the third data corresponding to the third logical address.

[0053] In some embodiments, the memory controller is configured to: receive a plurality of logical addresses and data corresponding to the plurality of logical addresses; wherein the logical addresses include the first logical address and / or the third logical address;

[0054] The processor is further configured to:

[0055] Determine whether the received multiple logical addresses are continuous and whether the data types of the data corresponding to the multiple logical addresses are the same, and generate a determination result;

[0056] When the judgment result indicates that the plurality of logical addresses are continuous and the data types of the data corresponding to the plurality of logical addresses are the same, the first identification code is generated based on the judgment result.

[0057] In some embodiments, the processor is further configured to:

[0058] When the judgment result indicates that the plurality of logical addresses are not continuous, a plurality of the third identification codes are generated based on the judgment result.

[0059] In some embodiments, the processor is further configured to:

[0060] Based on the sum of the capacity of the first identification code and the N pieces of the first data reaching a preset capacity, storing the first identification code and the N pieces of the first data in the buffer into a memory device;

[0061] or,

[0062] Based on a power-off command from a host and / or detection of abnormal power-off, the first identification code and N pieces of the first data in the buffer are stored in a memory device.

[0063] In the disclosed embodiment, N first logical addresses are continuous, and the data types of the N first data corresponding to the N first logical addresses are the same, and the processor is configured to generate a first identification code based on the first logical address group, and cache the first identification code in the buffer. In this way, only one first identification code is needed to indicate the data type of the N first data. On the one hand, the storage capacity occupied by the identification code in the buffer can be reduced, and the storage space utilization rate of the buffer can be improved; on the other hand, when a power failure occurs, the memory controller can quickly store the data and identification code in the buffer into the non-volatile memory device, reducing the risk of data error and loss, thereby improving the reliability of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 A schematic diagram of a system with a memory provided in an embodiment of the present disclosure;

[0065] Figure 2a A schematic diagram of a memory card provided by an embodiment of the present disclosure;

[0066] Figure 2b A schematic diagram of a solid state drive (SSD) provided in an embodiment of the present disclosure;

[0067] Figure 3 A schematic diagram of a memory system provided in an embodiment of the present disclosure;

[0068] Figure 4 A schematic diagram of an identification code and a logical address stored in a buffer and a memory device provided by an embodiment of the present disclosure;

[0069] Figure 5 A schematic diagram of a first identification code and a first logical address group stored in a buffer and a memory device provided by an embodiment of the present disclosure;

[0070] Figure 6 A schematic diagram of a second identification code and a second logical address group stored in a buffer and a memory device provided by an embodiment of the present disclosure;

[0071] Figure 7 A schematic diagram of a third identification code and a third logical address stored in a cache and a memory device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0072] In order to facilitate the understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0073] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0074] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0075] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0076] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0077] Figure 1 A schematic diagram of a system 100 having a memory according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein.

[0078] like Figure 1 As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0079] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital Memory Card (SD Card), a Compact Flash Card (CF Card), a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment solid state drive or embedded Multi Media Card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0080] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and write (also known as programming) operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with a host (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the host 108 through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCIE) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced System Device Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0081] The memory controller 106 and the one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2aIn one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card International Association, PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (Smart Media, SM) card, a memory stick, a Multi Media Card (Multi Media Card, MMC), a Reduced-Size MMC (RS-MMC), a Micro Multi Media Card (Multi Media Card Micro, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a Universal Flash Storage (Univeral Flash Storage, UFS), etc. The memory card 202 may also include a method for connecting the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0082] In an embodiment of the present disclosure, each of the memory chips (Die) may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), tri-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC) may store multiple bits per cell. In some embodiments, each of the memory devices may include one or more memory cell arrays, such as an SLC array, an MLC array, a TLC array, a QLC array, or any combination of such memory cell arrays.

[0083] Figure 3A schematic diagram of a memory system 300 provided in an embodiment of the present disclosure, wherein the memory system 300 includes a memory controller 310 and at least one memory device 320 coupled to the memory controller 310, and the memory controller 310 includes a processor 311 and a cache 312. The memory system 300 includes, but is not limited to, a solid-state drive, such as an enterprise solid-state drive (Enterprise SSD, eSSD), etc. The memory device 320 may be a non-volatile storage device, such as a NAND memory, a NOR memory, etc. The memory controller 310 may include one or more integrated circuits and / or discrete components, a cache, or hardware of a combination thereof. The memory controller 310 may be configured to receive data and commands from a host 400, and to operate the memory device 320, such as read, erase, and write operations, etc. The processor 311 in the memory controller 310 may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.). The buffer 312 may be a static random access memory (SRAM), a dynamic random access memory (DRAM), etc. The following description will be made by taking the buffer 312 as an SRAM as an example.

[0084] Figure 4 Schematic diagram of an identification code and a logical address in a buffer 312 and a memory device 320 provided in an embodiment of the present disclosure. The buffer 312 can be used to buffer multiple data (not shown in FIG. Figure 4 ), and logical-to-physical mapping table (L2P) mapping information corresponding to multiple data, where each data corresponds to a logical address and a physical address. The logical addresses of the multiple data can be continuous, i.e., sequential data, or discontinuous, i.e., random data. For example, the Q logical addresses Ltu1 to Ltu2 in the buffer 312 are Q Each logical address in is respectively associated with Q physical addresses Fla1 to Fla QEach physical address in corresponds to Q one by one, and Q is an integer greater than 0. The buffer 312 can also store Q identification codes Opcode, each identification code Opcode is used to indicate the data type of a data corresponding to a logical address, so as to track the source of each data, where the data type includes but is not limited to trim data, host data, garbage collection (Garbage Collection, GC) data or wear leveling (WL) data. It can be understood that the data types indicated by any two identification codes Opcode can be the same or different, that is, the data types of any two data can be the same or different. In some embodiments, the storage space occupied by each identification code is 4 bytes, the storage space occupied by each logical address is 4 bytes, and the storage space occupied by each physical address is also 4 bytes.

[0085] Since the buffer 312 is generally a volatile memory with a relatively small storage capacity, the mapping information from the logical address to the physical address in the buffer 312 and the multiple identification codes corresponding to the multiple data can be transferred to the memory device 320 when certain conditions are met. Exemplarily, when the sum of the capacity of the storage identification code, the logical address, the physical address and the data (or any one or more of the four) in the buffer 312 reaches a preset capacity, the processor 311 can transfer the identification code, the logical address, the physical address and the data in the buffer 312 to the memory device 320; in addition, the processor 311 can also transfer the identification code, the logical address, the physical address and the data in the buffer 312 to the memory device 320 based on a power-off command from the host 400 and / or detection of an abnormal power-off.

[0086] It is understandable that each piece of data requires an identification code Opcode to mark its data type, and each piece of data also requires a corresponding logical address to establish a mapping relationship from the logical address to the physical address. Exemplarily, Q pieces of data require 4Q bytes of storage space for storing Q identification codes, and also require 4Q bytes of storage space for storing Q logical addresses. This makes the storage space of the buffer 312 occupied by the identification code and the logical address larger, and the storage space of the memory device 320 occupied is also larger, and the storage space utilization rate of the buffer 312 and the memory device 320 is low. In addition, due to the large storage space occupied by the identification code and the logical address, when the processor 311 receives the power-off command of the host 400, the speed of transferring the identification code and the logical address from the buffer 312 to the memory device 320 is slow, thereby affecting the working efficiency of the memory system 300; and in the case of abnormal power failure, due to the slow speed of transferring the identification code and the logical address from the buffer 312 to the memory device 320, data errors and data loss may occur, affecting the reliability of the memory system 300.

[0087] Based on this, in order to solve one or more of the above technical problems, an embodiment of the present disclosure provides a memory.

[0088] like Figure 3 As shown, the present disclosure provides a memory controller 310, the memory controller 310 includes a buffer 312 and a processor 311 coupled to the buffer 312;

[0089] The buffer 312 is configured to cache a first logical address group; wherein the first logical address group is used to indicate N consecutive first logical addresses, where N is an integer greater than 1; and the data types of the N first data corresponding to the N first logical addresses are the same;

[0090] The processor 311 is configured to generate a first identification code based on the first logical address group, and cache the first identification code in the buffer 312; wherein the first identification code is used to indicate the data type of N pieces of the first data.

[0091] In the embodiments of the present disclosure, reference Figure 5, the first logical address group Ltulist1 indicates N consecutive first logical addresses, the processor 311 can generate a first identification code Opcode1 based on the N consecutive first data with the same data type and the first logical address group Ltulist1, and cache the first identification code Opcode1 in the buffer 312. It can be understood that the N first data here are sequential data. Exemplarily, the data type represented by the first identification code Opcode1 includes but is not limited to one of trimming data, host data, garbage collection data or wear leveling data.

[0092] Thus, N pieces of first data only need to be marked with one first identification code Opcode1 to indicate their data type. Figure 4 The embodiment shown in (each data requires an identification code to mark the data type) can greatly reduce the storage space occupied by the identification code, so that the storage space utilization rate of the buffer 312 and the memory device 320 is higher; in addition, when the processor 311 receives the power-off command from the host 400 (that is, the memory system is powered off normally), the first identification code Opcode1 is transferred from the buffer 312 to the memory device 320 at a faster speed, and the operation time required for normal power off is shorter, thereby improving the working efficiency of the memory system 300; and in the event of an abnormal power off, since the first identification code Opcode1 is transferred from the buffer 312 to the memory device 320 at a faster speed, the possibility of data error and data loss is lower, thereby improving the reliability of the memory system 300.

[0093] It should be noted that the first logical address group Ltulist1 stored in the buffer 312 may also be generated by the processor 311, and the specific method may refer to the subsequent embodiments.

[0094] In addition, for random data (i.e., multiple data with discontinuous logical addresses), or when the data types of any two data with adjacent logical addresses in multiple sequential data are different (e.g., although Ltu1 and Ltu2 are continuous, the corresponding two data have different data types), the processor 311 can still use Figure 4 In the embodiment shown, a corresponding identification code is generated for each piece of data, thereby achieving the purpose of compatibility between sequential data and random data.

[0095] In some embodiments, Figure 5 As shown, the first logical address group Ltulist1 includes a starting logical address StartLtu1 and a logical address length LtuCnt1; wherein the starting logical address is the first first logical address or the Nth first logical address among the consecutive N first logical addresses; the processor is specifically configured as follows:

[0096] The start logical address StartLtu1 and the logical address length LtuCnt1 are determined based on the consecutive N first logical addresses.

[0097] In the embodiment of the present disclosure, the processor may also determine the starting logical address StartLtu1 and the logical address length LtuCnt1 based on the N consecutive first logical addresses. For example, the N consecutive first logical addresses are Ltu1, Ltu2, ..., LtuCnt1. N-1 , Ltu N , the processor can Ltu1 or Ltu N The starting logical address StartLtu (i.e., the first or last first logical address) is determined, and N is determined as the logical address length LtuCnt1. In this way, the starting logical address StartLtu1 and the logical address length LtuCnt1 constitute the first logical address group Ltulist1, and the starting logical address StartLtu1 and the logical address length LtuCnt1 can be used to represent N consecutive first logical addresses. It can be understood that compared to Figure 4 Each piece of data needs a corresponding logical address to establish an L2P mapping relationship. Here, N pieces of first data only need a starting logical address StartLtu1 and a logical address length LtuCnt1 to establish an L2P mapping relationship, so that the storage space occupied by the logical address in the buffer is further compressed. While improving the storage space utilization of the buffer and the memory device, the processor can also quickly store the identification code and logical address (L2P mapping information) in the buffer to the non-volatile memory device, reducing the risk of data error and loss, thereby improving the reliability of the memory system.

[0098] In some embodiments, Figure 6 As shown, the buffer 312 is further configured to cache a second logical address group Ltulist2; wherein the second logical address group Ltulist2 is used to indicate M consecutive second logical addresses, where M is an integer greater than 1; the data types of the M second data corresponding to the M second logical addresses are the same; the data type of the second data is different from the data type of the first data;

[0099] The processor is also configured to generate a second identification code Opcode2 based on the second logical address group Ltulist2, and cache the second identification code Opcode2 in the buffer 312; wherein the second identification code Opcode2 is used to indicate the data type of the second data of the M pen; the second identification code Opcode2 is different from the first identification code Opcode1.

[0100] In the disclosed embodiment, the processor may also generate a plurality of different identification codes according to sequential data of different data types, that is, a corresponding identification code is generated for sequential data of the same data type. Exemplarily, the processor may generate a first logical address group Ltulist1 based on N consecutive first data of logical addresses, and generate a first identification code Opcode1 based on the first logical address group Ltulist1, and the processor may also generate a second logical address group Ltulist2 based on M consecutive second data of logical addresses, and generate a second identification code Opcode2 based on the second logical address group Ltulist2, where the data types indicated by the first identification code Opcode1 and the second identification code Opcode2 are different.

[0101] It is understandable that, in addition to the first identification code Opcode1 and the second identification code Opcode2, other identification codes may be stored in the buffer 312, one of which may be used to indicate the data type of multiple data of the same data type and continuous logical addresses (one identification code may also indicate the data type of a random data), and the number of identification codes is not limited here. In other words, the buffer 312 may store multiple logical address groups, and each logical address group is configured with a corresponding identification code.

[0102] For example, k records of data correspond to k consecutive logical addresses Ltu1, Ltu2, ..., Ltu k-1 , Ltu k , k>M+N and k is an integer, where the data types of the first to Nth data are the same and the logical addresses Ltu1 to Ltu N Continuous (i.e. the N first data), the data types of the N+1th data to the N+Mth data are the same and the logical address Ltu N+1 To Ltu N+M Continuous (i.e. the M second data), the data types of the N+M+1th data to the kth data are the same and the logical address Ltu N+M+1 To Ltu kContinuous (referred to as the fourth data for ease of understanding), the data types of the first data, the second data and the fourth data are different here. In this way, the processor can generate the corresponding first identification code, the second identification code and the fourth identification code respectively, and cache the first identification code, the second identification code and the fourth identification code in the buffer 312. It is worth noting that the data types of the first data and the fourth data here can also be the same, but the processor will still generate the first identification code and the fourth identification code (the storage position of the identification code in the buffer or memory device can be adjacent to the corresponding logical address group, so as to distinguish when the data type is the same). In this way, multiple data and the corresponding L2P information and identification codes can be flexibly stored, so as to compress the storage space of the identification code and the logical address as much as possible, so as to improve the storage space utilization of the buffer and the memory device, and enhance the stability of the memory system.

[0103] In some embodiments, Figure 6 As shown, the buffer 312 is further configured to cache P third logical addresses, where P is an integer greater than 0; wherein the P third logical addresses are not continuous;

[0104] The processor is further configured to generate corresponding P third identification codes Opcode3 based on the P third logical addresses respectively, and cache the third identification codes Opcode3 in the buffer 312; wherein the third identification code Opcode3 is used to indicate the data type of the third data corresponding to the third logical address.

[0105] In the disclosed embodiment, the processor may also generate corresponding P third identification codes Opcode3 based on P discontinuous third data of logical addresses and corresponding P discontinuous third logical addresses, and cache the third identification codes Opcode3 in the buffer 312. It is understandable that each third identification code Opcode3 is used to indicate the data type of a third data, so the data types indicated by any two third identification codes Opcode3 may be the same or different.

[0106] It should be noted that the buffer 312 may include one or more of the first identification code, the second identification code and the third identification code. That is, for sequential data, the processor can determine whether the data types are the same, and then choose whether to compress the identification code and the logical address group, thereby improving the storage space utilization of the buffer and the memory device; while for random data, the processor can use Figure 4 In the embodiment shown, a corresponding identification code is generated for each piece of data, thereby achieving the purpose of compatibility between sequential data and random data.

[0107] In some embodiments, the memory controller 310 is configured to: receive a plurality of logical addresses and data corresponding to the plurality of logical addresses; wherein the logical addresses include the first logical address and / or the third logical address;

[0108] The processor 311 is further configured to:

[0109] Determine whether the received multiple logical addresses are continuous and whether the data types of the data corresponding to the multiple logical addresses are the same, and generate a determination result;

[0110] When the judgment result indicates that the plurality of logical addresses are continuous and the data types of the data corresponding to the plurality of logical addresses are the same, the first identification code is generated based on the judgment result.

[0111] In some embodiments, the processor 311 is further configured to:

[0112] When the judgment result indicates that the plurality of logical addresses are not continuous, a plurality of the third identification codes are generated based on the judgment result.

[0113] In the disclosed embodiment, the processor 311 can detect and judge the continuity of multiple logical addresses corresponding to multiple data and the data types of the multiple data, and generate a judgment result, and then generate a first identification code (sequential data with the same data type) or multiple third identification codes (random data, or different data types for any two data with adjacent logical addresses in the multiple sequential data) based on the judgment result. The processor 311 may include an arbitrator circuit to perform the above judgment operation to generate a judgment result. It should be noted that there are no excessive restrictions on the order of judging whether the logical addresses of multiple data are continuous and whether the data types of multiple data are the same. The specific judgment order can be determined according to actual design requirements.

[0114] Exemplarily, the memory controller 310 receives k pieces of data and corresponding k logical addresses, where the first to the (i - 1)-th logical addresses are discontinuous, the i-th to the j-th logical addresses are continuous, the (j + 1)-th to the k-th logical addresses are discontinuous, i, j, and k are all positive integers, and i > 2, i < j, j + 1 < k; the data types of the i-th to the t-th pieces of data are the same, i < t and t + 2 < j, the data type of the (t + 1)-th piece of data is different from the data types of the i-th to the t-th pieces of data, the data types of the (t + 2)-th to the j-th pieces of data are the same, and the data types of the (t + 2)-th to the j-th pieces of data are different from the data type of the (t + 1)-th piece of data. Thus, the processor 311 can generate corresponding (i - 1) identification codes based on the first to the (i - 1)-th pieces of data, generate corresponding 1 identification code based on the i-th to the t-th pieces of data, generate corresponding 1 identification code based on the (t + 1)-th piece of data, generate corresponding 1 identification code based on the (t + 2)-th to the j-th pieces of data, and generate corresponding (k - j) identification codes based on the (j + 1)-th to the k-th pieces of data.

[0115] In some embodiments, the processor 311 is further configured to:

[0116] Based on the sum of the first identification code and the capacities of N pieces of the first data reaching a preset capacity, store the first identification code and N pieces of the first data in the buffer 312 into the memory device 320;

[0117] Or,

[0118] Based on a power-off command from the host 400 and / or detecting an abnormal power-off, store the first identification code and N pieces of the first data in the buffer 312 into the memory device 320.

[0119] In the embodiments of the present disclosure, since the buffer 312 is generally a volatile memory with a small storage capacity, the logical address to physical address mapping information in the buffer 312, and multiple identification codes corresponding to multiple pieces of data can be transferred to the memory device 320 under certain conditions. Exemplarily, when the sum of the storage capacities of the identification codes, logical addresses, physical addresses, and data (or any combination of one or more of the four) in the buffer 312 reaches a preset capacity, the processor 311 can transfer the identification codes, logical addresses, physical addresses, and data in the buffer 312 to the memory device 320. Here, the preset capacity is less than or equal to the total capacity of the buffer 312, and the preset capacity can be determined according to the total capacity of the buffer 312 and the read / write performance requirements for the memory system 300.

[0120] In addition, the processor 311 can also transfer the identification code, logical address, physical address and data in the buffer 312 to the memory device 320 based on the power-off command from the host 400 and / or the detection of abnormal power-off. In this way, the storage space occupied by the identification code and the logical address can be greatly reduced, so that the storage space utilization rate of the buffer 312 and the memory device 320 is higher; in addition, since the storage space occupied by the identification code and the logical address is reduced, when the processor 311 receives the power-off command from the host 400 (that is, the memory system is normally powered off), the speed of transferring the identification code and the logical address from the buffer 312 to the memory device 320 is faster, and the operation time required for normal power-off is shorter, thereby improving the working efficiency of the memory system 300; and in the event of abnormal power-off, since the speed of transferring the identification code from the buffer 312 to the memory device 320 is faster, the possibility of data error and data loss is lower, thereby improving the reliability of the memory system 300.

[0121] The present disclosure provides an operating method of a memory controller, wherein the memory controller includes a buffer and a processor coupled to the buffer, and the operating method includes:

[0122] The buffer caches a first logical address group; wherein the first logical address group is used to indicate N consecutive first logical addresses, N is an integer greater than 1; the data types of N first data corresponding to the N first logical addresses are the same;

[0123] The processor generates a first identification code based on the first logical address group, and caches the first identification code in the buffer; wherein the first identification code is used to indicate the data type of N pieces of the first data.

[0124] In some embodiments, the first logical address group includes a starting logical address and a logical address length; wherein the starting logical address is the first first logical address or the Nth first logical address among the consecutive N first logical addresses; and the operation method further includes:

[0125] The processor determines the start logical address and the logical address length based on consecutive N first logical addresses.

[0126] In some embodiments, the operating method further includes:

[0127] The buffer caches a second logical address group; wherein the second logical address group is used to indicate M consecutive second logical addresses, where M is an integer greater than 1; the data types of the M pieces of second data corresponding to the M second logical addresses are the same; and the data type of the second data is different from the data type of the first data;

[0128] The processor generates a second identification code based on the second logical address group and caches the second identification code in the cache; wherein the second identification code is used to indicate the data type of the second data of the M pen; the second identification code is different from the first identification code.

[0129] In some embodiments, the operating method further includes:

[0130] The buffer caches P third logical addresses, where P is an integer greater than 0; wherein the P third logical addresses are not consecutive;

[0131] The processor generates corresponding P third identification codes based on the P third logical addresses respectively, and caches the third identification codes in the cache; wherein the third identification code is used to indicate the data type of the third data corresponding to the third logical address.

[0132] In some embodiments, the operating method further includes:

[0133] Receiving a plurality of logical addresses and data corresponding to the plurality of logical addresses; wherein the logical addresses include the first logical address and / or the third logical address;

[0134] The processor determines whether the received multiple logical addresses are continuous and whether the data types of the data corresponding to the multiple logical addresses are the same, and generates a determination result;

[0135] When the judgment result indicates that the plurality of logical addresses are continuous and the data types of the data corresponding to the plurality of logical addresses are the same, the processor generates the first identification code based on the judgment result.

[0136] In some embodiments, the operating method further includes:

[0137] When the determination result indicates that the plurality of logical addresses are not continuous, the processor generates a plurality of the third identification codes based on the determination result.

[0138] In some embodiments, the operating method further includes:

[0139] The processor stores the first identification code and the N pieces of first data in the buffer into a memory device based on the sum of the capacity of the first identification code and the N pieces of first data reaching a preset capacity;

[0140] or,

[0141] The processor stores the first identification code and N pieces of the first data in the buffer to the memory device based on a power-off command from the host and / or detecting an abnormal power-off.

[0142] The embodiment of the present disclosure also provides a computer-readable storage medium, on which executable instructions are stored. When the executable instructions are executed, the method described in any one of the above embodiments is implemented. Exemplarily, the executable instructions can be stored in the memory device 320 and can be executed by the processor 311. Specifically, the executable instructions can be instructions related to the Flash Translation Layer (FTL). The executable instructions can also be referred to as firmware.

[0143] like Figure 3 As shown, the present disclosure provides a memory system 300, the memory system 300 comprising: a memory device 320 and a memory controller 310 coupled to the memory device 320; the memory controller 310 comprising a buffer 312 and a processor 311 coupled to the buffer 312;

[0144] The buffer 312 is configured to cache a first logical address group; wherein the first logical address group is used to indicate N consecutive first logical addresses, where N is an integer greater than 1; and the data types of the N first data corresponding to the N first logical addresses are the same;

[0145] The processor 311 is configured to generate a first identification code based on the first logical address group, and cache the first identification code in the buffer 312; wherein the first identification code is used to indicate the data type of the N first data;

[0146] The processor 311 is further configured to store the first identification code and N pieces of first data in the buffer 312 to the memory device 320 .

[0147] In the disclosed embodiment, the memory controller 310 may be configured to receive data and commands from the host 400, and perform operations on the memory device 320, such as read, erase and write operations. The processor 311 in the memory controller 310 may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array, an application-specific integrated circuit), etc. The buffer 312 may be a static random access memory, a dynamic random access memory, etc. The buffer 312 may be used to cache multiple data, and the logical address to physical address mapping information corresponding to the multiple data, wherein each data corresponds to a logical address and a physical address. Here, the logical addresses of the multiple data may be continuous, i.e., sequential data, and the logical addresses of the multiple data may also be discontinuous, i.e., random data.

[0148] The processor 311 can generate a first identification code based on N first data with consecutive logical addresses and the same data type and the first logical address group, and cache the first identification code in the buffer 312. It can be understood that the N first data here are sequential data. Exemplarily, the data type represented by the first identification code includes but is not limited to one of trimming data, host data, garbage collection data, or wear leveling data.

[0149] Since the buffer 312 is generally a volatile memory with a relatively small storage capacity, the mapping information of the logical address to the physical address in the buffer 312 and the multiple identification codes corresponding to the multiple data can be transferred to the memory device 320 when certain conditions are met. Exemplarily, when the sum of the capacity of storing the first identification code, the first logical address, the physical address and the first data (or any one or more of the four) in the buffer 312 reaches the preset capacity, the processor 311 can transfer the first identification code, the first logical address, the physical address and the first data in the buffer 312 to the memory device 320. Here, the preset capacity can be determined according to the total capacity of the buffer 312 and the read and write performance requirements for the memory system 300. In addition, the processor 311 can also transfer the first identification code, the first logical address, the physical address and the first data in the buffer 312 to the memory device 320 based on the power-off command from the host 400 and / or the detection of abnormal power off.

[0150] Thus, N pieces of first data only need to be marked with one first identification code to identify their data types. Figure 4 The embodiment shown in (each data requires an identification code to mark the data type) can greatly reduce the storage space occupied by the identification code, so that the storage space utilization rate of the buffer 312 and the memory device 320 is higher; in addition, when the processor 311 receives a power-off command from the host 400, the first identification code is transferred from the buffer 312 to the memory device 320 at a faster speed, thereby improving the working efficiency of the memory system 300; and in the event of an abnormal power outage, since the first identification code is transferred from the buffer 312 to the memory device 320 at a faster speed, the possibility of data error and data loss is lower, thereby improving the reliability of the memory system 300.

[0151] It should be noted that the first logical address group stored in the buffer 312 may also be generated by the processor 311. The specific method is referred to the above embodiment and will not be described again here.

[0152] In some embodiments, the first logical address group includes a starting logical address and a logical address length; wherein the starting logical address is the first first logical address or the Nth first logical address among the consecutive N first logical addresses; and the processor is specifically configured to:

[0153] The start logical address and the logical address length are determined based on the consecutive N first logical addresses.

[0154] In some embodiments, the cache is further configured to cache P third logical addresses, where P is an integer greater than 0; wherein the P third logical addresses are not consecutive;

[0155] The processor is also configured to generate corresponding P third identification codes based on the P third logical addresses, respectively, and cache the third identification codes in the corresponding buffers; wherein the third identification codes are used to indicate the data type of the third data corresponding to the third logical address.

[0156] In some embodiments, the memory controller is configured to: receive a plurality of logical addresses and data corresponding to the plurality of logical addresses; wherein the logical addresses include the first logical address and / or the third logical address;

[0157] The processor is further configured to:

[0158] Determine whether the received multiple logical addresses are continuous and whether the data types of the data corresponding to the multiple logical addresses are the same, and generate a determination result;

[0159] When the judgment result indicates that the plurality of logical addresses are continuous and the data types of the data corresponding to the plurality of logical addresses are the same, the first identification code is generated based on the judgment result.

[0160] In some embodiments, the processor is further configured to:

[0161] When the judgment result indicates that the plurality of logical addresses are not continuous, a plurality of the third identification codes are generated based on the judgment result.

[0162] In some embodiments, the processor is further configured to:

[0163] Based on the sum of the capacity of the first identification code and the N pieces of the first data reaching a preset capacity, storing the first identification code and the N pieces of the first data in the buffer into a memory device;

[0164] or,

[0165] Based on a power-off command from a host and / or detection of abnormal power-off, the first identification code and N pieces of the first data in the buffer are stored in a memory device.

[0166] In some embodiments, the processor generates an identification code, a starting logical address, and a logical address length based on multiple data with consecutive logical addresses and the same data type, thereby greatly reducing the storage space occupied by the identification code and the logical address. This operation can be implemented by the processor executing executable instructions. It is understandable that by detecting the source code, it can be found that the data structure of the identification code and the logical address after optimization in the present disclosure has changed.

[0167] Table 1

[0168]

[0169] In some embodiments, the memory system may be an enterprise-level solid-state drive. Since the processor can compress the identification code and the logical address of the sequential data, the storage space of the buffer and the memory device occupied by the identification code and the logical address is small, so the full-disk sequential writing capability of the enterprise-level solid-state drive is improved. Exemplarily, referring to Table 1, for writing 1024 sequential data of the same data type, if the processor does not compress the identification code and the logical address, the storage space occupied by the identification code and the logical address is 8K (the identification code and the logical address corresponding to each data occupy 8 bytes); if the processor compresses the identification code and the logical address, that is, only one identification code, one starting logical address and one logical address length are generated for 1024 sequential data of the same data type, then the storage space occupied by the identification code and the logical address is 8 bytes, which is only 1 / 1024 of the above-mentioned uncompressed case.

[0170] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0171] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A memory controller, characterized in that: The memory controller includes a buffer and a processor coupled to the buffer; The buffer is configured to cache a first logical address group; wherein the first logical address group is used to indicate N consecutive first logical addresses, N is an integer greater than 1; the data types of N first data corresponding to the N first logical addresses are the same; The processor is configured to generate a first identification code based on the first logical address group, and cache the first identification code in the buffer; wherein the first identification code is used to indicate the data type of N pieces of the first data.

2. The memory controller according to claim 1, wherein: The first logical address group includes a starting logical address and a logical address length; wherein the starting logical address is the first first logical address or the Nth first logical address among the consecutive N first logical addresses; and the processor is specifically configured to: The start logical address and the logical address length are determined based on the consecutive N first logical addresses.

3. The memory controller according to claim 1 or 2, characterized in that: The buffer is further configured to cache a second logical address group; wherein the second logical address group is used to indicate M consecutive second logical addresses, where M is an integer greater than 1; the data types of the M pieces of second data corresponding to the M second logical addresses are the same; and the data type of the second data is different from the data type of the first data; The processor is also configured to generate a second identification code based on the second logical address group and cache the second identification code in the buffer; wherein the second identification code is used to indicate the data type of the second data of the M pen; the second identification code is different from the first identification code.

4. The memory controller according to claim 1, wherein: The buffer is further configured to cache P third logical addresses, where P is an integer greater than 0; wherein the P third logical addresses are not consecutive; The processor is further configured to generate corresponding P third identification codes based on the P third logical addresses, respectively, and cache the third identification codes in the buffer; wherein the third identification code is used to indicate a data type of the third data corresponding to the third logical address.

5. The memory controller according to claim 4, characterized in that: The memory controller is configured to: receive a plurality of logical addresses and data corresponding to the plurality of logical addresses; wherein the logical addresses include the first logical address and / or the third logical address; The processor is further configured to: Determine whether the received multiple logical addresses are continuous and whether the data types of the data corresponding to the multiple logical addresses are the same, and generate a determination result; When the judgment result indicates that the plurality of logical addresses are continuous and the data types of the data corresponding to the plurality of logical addresses are the same, the first identification code is generated based on the judgment result.

6. The memory controller according to claim 5, characterized in that: The processor is further configured to: When the judgment result indicates that the plurality of logical addresses are not continuous, a plurality of the third identification codes are generated based on the judgment result.

7. The memory controller according to claim 1, wherein: The processor is further configured to: Based on the sum of the capacity of the first identification code and the N pieces of the first data reaching a preset capacity, storing the first identification code and the N pieces of the first data in the buffer into a memory device; or, Based on a power-off command from a host and / or detection of abnormal power-off, the first identification code and N pieces of the first data in the buffer are stored in a memory device.

8. A method for operating a memory controller, characterized in that: The memory controller includes a buffer and a processor coupled to the buffer, and the operating method includes: The buffer caches a first logical address group; wherein the first logical address group is used to indicate N consecutive first logical addresses, N is an integer greater than 1; the data types of N first data corresponding to the N first logical addresses are the same; The processor generates a first identification code based on the first logical address group, and caches the first identification code in the buffer; wherein the first identification code is used to indicate the data type of N pieces of the first data.

9. The operating method according to claim 8, characterized in that: The first logical address group includes a starting logical address and a logical address length; wherein the starting logical address is the first first logical address or the Nth first logical address among the consecutive N first logical addresses; the operation method further includes: The processor determines the start logical address and the logical address length based on consecutive N first logical addresses.

10. The operating method according to claim 8 or 9, characterized in that: The operation method also includes: The buffer caches a second logical address group; wherein the second logical address group is used to indicate M consecutive second logical addresses, where M is an integer greater than 1; the data types of the M pieces of second data corresponding to the M second logical addresses are the same; and the data type of the second data is different from the data type of the first data; The processor generates a second identification code based on the second logical address group and caches the second identification code in the cache; wherein the second identification code is used to indicate the data type of the second data of the M pen; the second identification code is different from the first identification code.

11. The operating method according to claim 8, characterized in that: The operation method also includes: The buffer caches P third logical addresses, where P is an integer greater than 0; wherein the P third logical addresses are not continuous; The processor generates corresponding P third identification codes based on the P third logical addresses respectively, and caches the third identification codes in the cache; wherein the third identification code is used to indicate the data type of the third data corresponding to the third logical address.

12. The operating method according to claim 11, characterized in that: The operation method also includes: Receiving a plurality of logical addresses and data corresponding to the plurality of logical addresses; wherein the logical addresses include the first logical address and / or the third logical address; The processor determines whether the received multiple logical addresses are continuous and whether the data types of the data corresponding to the multiple logical addresses are the same, and generates a determination result; When the judgment result indicates that the plurality of logical addresses are continuous and the data types of the data corresponding to the plurality of logical addresses are the same, the processor generates the first identification code based on the judgment result.

13. The operating method according to claim 12, characterized in that: The operation method also includes: When the determination result indicates that the plurality of logical addresses are not continuous, the processor generates a plurality of the third identification codes based on the determination result.

14. The operating method according to claim 8, characterized in that: The operation method also includes: The processor stores the first identification code and the N pieces of the first data in the buffer into a memory device based on the sum of the capacities of the first identification code and the N pieces of the first data reaching a preset capacity; or, The processor stores the first identification code and N pieces of the first data in the buffer to the memory device based on a power-off command from the host and / or detecting an abnormal power-off.

15. A memory system, characterized in that: The memory system comprises: a memory device and a memory controller coupled to the memory device; the memory controller comprises a buffer and a processor coupled to the buffer; The buffer is configured to cache a first logical address group; wherein the first logical address group is used to indicate N consecutive first logical addresses, N is an integer greater than 1; the data types of N first data corresponding to the N first logical addresses are the same; The processor is configured to generate a first identification code based on the first logical address group, and cache the first identification code in the buffer; wherein the first identification code is used to indicate the data type of N pieces of the first data; The processor is further configured to store the first identification code and N pieces of the first data in the buffer to the memory device.

16. The memory system according to claim 15, characterized in that: The first logical address group includes a starting logical address and a logical address length; wherein the starting logical address is the first first logical address or the Nth first logical address among the consecutive N first logical addresses; and the processor is specifically configured to: The start logical address and the logical address length are determined based on the consecutive N first logical addresses.

17. The memory system according to claim 15, characterized in that: The buffer is further configured to cache P third logical addresses, where P is an integer greater than 0; wherein the P third logical addresses are not consecutive; The processor is also configured to generate corresponding P third identification codes based on the P third logical addresses, respectively, and cache the third identification codes in the corresponding buffers; wherein the third identification codes are used to indicate the data type of the third data corresponding to the third logical address.

18. The memory system according to claim 17, wherein: The memory controller is configured to: receive a plurality of logical addresses and data corresponding to the plurality of logical addresses; wherein the logical addresses include the first logical address and / or the third logical address; The processor is further configured to: Determine whether the received multiple logical addresses are continuous and whether the data types of the data corresponding to the multiple logical addresses are the same, and generate a determination result; When the judgment result indicates that the plurality of logical addresses are continuous and the data types of the data corresponding to the plurality of logical addresses are the same, the first identification code is generated based on the judgment result.

19. The memory system according to claim 18, characterized in that: The processor is further configured to: When the judgment result indicates that the plurality of logical addresses are not continuous, a plurality of the third identification codes are generated based on the judgment result.

20. The memory system according to claim 15, wherein: The processor is further configured to: Based on the sum of the capacity of the first identification code and the N pieces of the first data reaching a preset capacity, storing the first identification code and the N pieces of the first data in the buffer into a memory device; or, Based on a power-off command from a host and / or detection of abnormal power-off, the first identification code and N pieces of the first data in the buffer are stored in a memory device.

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